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Features

2100AI PCIe NVMe NAND Flash SSD

MTFDHBL064, MTFDHBL128, MTFDHBL256, MTFDHBL512, MTFDHBM1T0,
MTFDHBK128, MTFDHBK256, MTFDHBK512, MTFDHBK1T0

Features • Reliability
– MTTF: 3 million hours4
• Micron® 3D TLC NAND Flash – Static and dynamic wear leveling
• PCIe Express base specification Rev 3.0 – Uncorrectable bit error rate (UBER): <1 sector
– Gen3 x4 lanes per 1016 bits read
– Backward Compatibility • Micron redundant array of independent NAND
• NVMe Express Rev 1.3c compliant (RAIN) technology
– Number of namespaces supported: Up to 4
– Round robin arbitration: weighted Options Marking
– Autonomous power state transitions • Form Factor
– Host memory buffer (HMB) – BGA type 1620, 16mm x 20mm x BL
– Boot partitions and RPMB 1.2mm
– End-to-end data protection – BGA type 1620, 16mm x 20mm x BM
• Retention JESD47 compliant: 1.6mm
– 5 years @55°C at 10% of TBW – M.2 type 2230, 22mm x 30mm BK
– 1 year @55°C at max TBW • Density
• Package compliance: – 64GB
– RoHS certification – 128GB 128
– BGA, MSL3 – 256GB 256
• Capacity (unformatted)1: 64GB, 128GB, 256GB, – 512GB 512
512GB, 1024GB – 1TB 1T0
• Physical capacity management (SLC mode) • Product Family
• Endurance: Total bytes written (TBW) – 2100AI DP
– Up to 480TB for 1024GB • BOM
• Security – 1st Generation 1
– TCG/Opal 2.0 compliant self-encrypting drive – Engineering Samples A
(SED) • Operating Temperature 5
– Hardware-based AES-256 encryption engine – Grade 3 extended (–40°C to +95°C) IT
– Digitally signed firmware • Customer Designator
– Firmware secure boot – Standard YY
• Self-monitoring, analysis, and reporting technology
(SMART) command set Notes: 1. User capacity: 1GB = 1 billion bytes.
• Power loss protection for data-at-rest 2. Typical I/O performance numbers as meas-
• Performance2 ured fresh-out-of-box (FOB) with HMB ena-
– Sequential 128KB READ: Up to 2000 MB/s bled.
– Sequential 128KB WRITE: Up to 1800 MB/s 3. 4KB, queue depth 1 transfers used for
– Random 4KB READ: Up to 200,000 IOPS READ/WRITE latency values.
– Random 4KB WRITE: Up to 130,000 IOPS 4. Mean Time To Failure (MTTF) based on pop-
• Latency3 ulation statistics not relevant to individual
– Read (TYP): 85µs units.
– Write (TYP): 40µs 5. Case surface temperature.
• Host-controlled thermal management
• Low power consumption
– Sleep: 3mW/5mW (PS4 & L1.2) BGA/M.2

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Features

Part Number Ordering

Verify valid part numbers by using Micron’s part catalog search at www.micron.com. To compare features and
specifications by device type, visit www.micron.com/products. Contact the factory for devices not found.

Figure 1: Part Number Ordering Information

MT FD H XX XXX T XX - X AT 1 2 XX YY ES

Micron Technology Production Status

ES = Engineering samples
Product Family Blank = Production
FD = Flash drive (SSD)
Customer Designator
Drive Interface YY = Standard
H = PCIe Gen3
Operating Temperature
Drive Form Factor AI = Automotive support,
BL = BGA, 16 x 20 x 1.2mm Industrial (–40°C to 95°C)
BM = BGA, 16 x 20 x 1.6mm AT = Automotive (–40°C to 105°C)
BK = M.2, 22 x 30mm
Extended Firmware Features
Drive Density 2 = Self-encrypting drive (SED)
064 = 64GB
128 = 128GB Sector Size
256 = 256GB
1 = 512 bytes
512 = 512GB
1T0 = 1024GB
NAND Component
NAND Type AT = 512Gb, TLC, x8, 3.3V (3D)
T = TLC
BOM
Product Family A = Engineering samples
DP = 2100AI 1 = 1st Generation
DQ = 2100AT

Table 1: Part Number Ordering Information

Base Part Number Density Package

MTFDHBL064TDP-1AT12AIYY 64GB BGA type 1620, 16mm x 20mm x 1.2mm
MTFDHBL128TDP-1AT12AIYY 128GB BGA type 1620, 16mm x 20mm x 1.2mm
MTFDHBL256TDP-1AT12AIYY 256GB BGA type 1620, 16mm x 20mm x 1.2mm
MTFDHBL512TDP-1AT12AIYY 512GB BGA type 1620, 16mm x 20mm x 1.2mm
MTFDHBM1T0TDP-1AT12AIYY 1TB BGA type 1620, 16mm x 20mm x 1.6mm
MTFDHBK128TDP-1AT12AIYY 128GB M.2 Type 2230 M-key, 22mm x 30mm x 2.0mm
MTFDHBK256TDP-1AT12AIYY 256GB M.2 Type 2230 M-key, 22mm x 30mm x 2.0mm
MTFDHBK512TDP-1AT12AIYY 512GB M.2 Type 2230 M-key, 22mm x 30mm x 2.0mm
MTFDHBK1T0TDP-1AT12AIYY 1TB M.2 Type 2230 M-key, 22mm x 30mm x 2.4mm

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Important Notes and Warnings

Important Notes and Warnings

Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this docu-
ment if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifi-
cally designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distrib-
utor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of non-
automotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and con-
ditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to in-
demnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron compo-
nent could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environ-
mental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Mi-
cron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAIL-
URE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or en-
vironmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.

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General Description

General Description
Micron’s 2100AI solid state drive (SSD) uses a single-chip controller with a PCIe Gen3
interface connecting up to four PCIe lanes to Micron’s 3D TLC NAND Flash.
The SSD is designed to use the PCIe interface efficiently during both READs and
WRITEs while delivering bandwidth-focused, low latency performance through the in-
novative Nonvolatile Memory Express protocol. SSD technology enables enhanced boot
times, faster application load times, reduced power consumption, and extended relia-
bility.
The 2100AI is ideally suited for industrial applications, which require mass storage in a
very small footprint.

Figure 2: Functional Block Diagram

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Performance

Performance
Measured performance can vary for a number of reasons. The major factors affecting
drive performance are the capacity of the drive and the interface of the host. Addition-
ally, overall system performance can affect the measured drive performance. When
comparing drives, it is recommended that all system variables are the same, and only
the drive being tested varies.
Performance numbers vary depending on the host system configuration.
For SSDs designed for the client and cloud computing markets, Micron specifies per-
formance in fresh-out-of-box (FOB) state and steady state. Data throughput measured
in steady state may be lower than FOB state, depending on the nature of the data work-
load.
For a description of these performance states and of Micron's best practices for per-
formance measurement, refer to Micron's technical marketing brief Best Practices for
SSD Performance Measurement.

Table 2: Drive Performance With/Without HMB Enabled – Fresh Out of Box

64GB 128GB 256GB 512GB 1024GB

Parameter HMB HMB HMB HMB HMB HMB HMB HMB HMB HMB Unit
Off On Off On Off On Off On Off On
Sequential read
550 550 1100 1100 2000 2000 2000 2000 2000 2000 MB/s
(128KB transfer)
Sequential write
250 250 500 500 1000 1000 1700 1700 1800 1800 MB/s
(128KB transfer)
Random read
12K 25K 20K 50K 38K 100K 65K 170K 105K 200K IOPS
(4KB transfer)
Random write
40K 50K 60K 85K 80K 110K 90K 120K 100K 130K IOPS
(4KB transfer)
READ latency
85 85 85 85 85 85 85 85 85 85 µs
(TYP)
WRITE latency
40 40 40 40 40 40 40 40 40 40 µs
(TYP)

Notes: 1. Performance values measured in fresh-out-of-box (FOB) state using FIO with a queue
depth of 32.
2. Drive write cache enabled.
3. NVMe power state 0.
4. 4KB transfers with a queue depth of 1 are used to measure READ/WRITE latency values.
5. 4KB transfers can be further improved with the support of HMB by the host.
6. System variations will affect measured results.

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Logical Block Address Configuration

Logical Block Address Configuration

The drive is set to report the number of logical block addresses (LBA) that will ensure
sufficient storage space for the specified capacity. Standard LBA settings (100% TLC),
based on the IDEMA standard (LBA1-03), are shown below.

Table 3: Standard LBA Settings (100% TLC)

Total 512 - Byte LBA Max 512 - Byte LBA

Capacity Decimal Hexadecimal Decimal Hexadecimal
64GB 125,045,424 7740AB0 125,045,423 7740AAF
128GB 250,069,680 EE7C2B0 250,069,679 EE7C2AF
256GB 500,118,192 1DCF32B0 500,118,191 1DCF32AF
512GB 1,000,215,216 3B9E12B0 1,000,215,215 3B9E12AF
1024GB 2,000,409,264 773BD2B0 2,000,409,265 773BD2AF

Note: Look at Physical Capacity Management (page 9) Section for more options rela-
ted to SLC Vs. TLC configurations

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Reliability

Reliability
Micron’s SSDs incorporate advanced technology for defect and error management. We
use various combinations of hardware-based error correction algorithms and firmware-
based static and dynamic wear-leveling algorithms.
Over the life of the SSD, uncorrectable errors may occur. An uncorrectable error is de-
fined as data that is reported as successfully programmed to the SSD but when it is read
out of the SSD, the data differs from what was programmed.

Table 4: Uncorrectable Bit Error Rate

Uncorrectable Bit Error Rate Operation

<1 sector per 1016 bits read READ

Mean Time To Failure

Mean time to failure (MTTF) for the SSD can be predicted based on the component reli-
ability data using the methods referenced in the Telcordia SR-332 reliability prediction
procedures for electronic equipment.

Table 5: MTTF

Capacity MTTF (Operating Hours)

All capacities 3 million

Note: 1. The mean time to failure (MTTF) reported in the above table is based on population sta-
tistics. Therefore, it is not relevant to individual unit.

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Reliability

Endurance
Endurance for the SSD can be predicted based on the usage conditions applied to the
device. The table shows the minimum drive lifetime for each SSD capacity based on
predefined usage conditions noted below.

Table 6: Total Bytes Written

Capacity Total Bytes Written

64GB 30TB
128GB 60TB
256GB 120TB
512GB 240TB
1024GB 480TB

Notes: 1. Total bytes written validated with the drive 90% full.
2. SSD volatile write cache is enabled.
3. Access patterns used during reliability testing are 25% sequential and 75% random and
consist of the following: 1% are 512B; 44% are 4 KiB; 35% are 64 KiB; and 20% are
128 KiB.
4. Host workload parameters, including write cache settings, I/O alignment, transfer sizes,
randomness, and percent full, that are substantially different than the described notes
may result in varied endurance results.
5. GB/day can be calculated by dividing the total bytes written value by (365 × number of
years). For example: 100TB/5 years/365 days = 54GB/day for 5 years.

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Physical Capacity Management

Physical Capacity Management

At least one of the user configurable namespaces (up to four) can be configured in “SLC
mode” to meet the most demanding endurance requirements. This is the case of write
intensive applications or applications requiring long retention with limited writes. SLC
mode also ensures higher performance.
Micron has defined the vendor specific Physical Capacity Management command to
perform physical space configuration. The Physical Capacity Management command is
a vendor-specific NVMe Admin command. This command provides operations which
are outside the scope of the NVMe standard and which, to date, have been implemen-
ted by multiple companies in vendor-specific manners. This command makes use of
concepts defined in the NVMe standard.
Search for TN-FD-49: 2100AI/AT Physical Capacity Management Technical Note at
http://www.micron.com . Alternatively, consult your sales representative for more in-
formation.

Endurance

Table 7: Bytes Written

SLC Mode Total Bytes Written (in Terabytes)

Size [%] 64GB 128GB 256GB 512GB 1024GB
0% (Default) 30 60 120 240 480
10% 77 154 308 616 1232
20% 124 248 496 992 1984
30% 171 342 684 1368 2736
40% 218 436 872 1744 3488
50% 265 530 1060 2120 4240
100% 500 1000 2000 4000 8000

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Physical Capacity Management

Logical Block Address Configuration

Table 8: SLC LBA Settings

SLC Mode Total 512 - Byte LBA

Size [%] 64GB 128GB 256GB 512GB 1024GB
0% (Default) 0 0 0 0 0
10% 4,182,136 8,343,096 16,684,564 33,347,950 66,694,264
20% 8,343,096 16,684,564 33,347,950 66,694,264 133,367,352
30% 12,523,596 25,026,024 50,030,878 100,040,578 200,059,980
40% 16,684,564 33,347,950 66,694,264 133,367,352 266,733,076
50% 20,845,522 41,689,410 83,357,650 166,713,666 333,406,162
100% 41,689,410 83,357,650 166,713,666 333,406,162 666,810,690

Table 9: TLC LBA Settings

SLC Mode Total 512 - Byte LBA

Size [%] 64GB 128GB 256GB 512GB 1024GB
0% (Default) 125,045,424 250,069,680 500,118,192 1,000,215,216 2,000,409,264
10% 112,543,006 225,064,834 450,108,492 900,195,816 1,800,370,462
20% 100,040,578 200,059,980 400,098,792 800,176,414 1,600,331,650
30% 87,538,152 175,055,134 350,089,090 700,157,004 1,400,292,840
40% 75,035,724 150,050,280 300,079,390 600,137,602 1,200,254,028
50% 62,533,296 125,045,424 250,069,680 500,118,192 1,000,215,216
100% 0 0 0 0 0

Table 10: Total LBA Settings

SLC Mode Total 512 - Byte LBA

Size [%] 64GB 128GB 256GB 512GB 1024GB
0% (Default) 125,045,424 250,069,680 500,118,192 1,000,215,216 2,000,409,264
10% 116,725,142 233,407,930 466,793,056 933,543,766 1,867,064,726
20% 108,383,674 216,744,544 433,446,742 866,870,678 1,733,699,002
30% 100,061,748 200,081,158 400,119,968 800,197,582 1,600,352,820
40% 91,720,288 183,398,230 366,773,654 733,504,954 1,466,987,104
50% 83,378,818 166,734,834 333,427,330 666,831,858 1,333,621,378
100% 41,689,410 83,357,650 166,713,666 333,406,162 666,810,690

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Physical Capacity Management

Performance
For SSDs designed for the client and cloud computing markets, Micron specifies per-
formance in fresh-out-of-box (FOB) state and steady state. Data throughput measured
in steady state may be lower than FOB state, depending on the nature of the data work-
load.
For a description of these performance states and of Micron's best practices for per-
formance measurement, refer to Micron's technical marketing brief Best Practices for
SSD Performance Measurement.

Table 11: Drive Performance With/Without HMB Enabled (SLC Mode=100%) – Fresh Out of Box

Capacity 64GB 128GB 256GB 512GB 1024GB

Actual Capacity 21GB 42GB 85GB 170GB 341GB
Unit
HMB HMB HMB HMB HMB HMB HMB HMB HMB HMB
Parameter
Off On Off On Off On Off On Off On
Sequential read
550 550 1100 1100 2000 2000 2000 2000 2000 2000 MB/s
(128KB transfer)
Sequential write
250 250 500 500 1000 1000 1700 1700 1800 1800 MB/s
(128KB transfer)
Random read
12K 25K 20K 50K 38K 100K 65K 170K 105K 200K IOPS
(4KB transfer)
Random write
48K 48K 90K 100K 160K 185K 170K 190K 189K 210K IOPS
(4KB transfer)
READ latency
85 85 85 85 85 85 85 85 85 85 µs
(TYP)
WRITE latency
40 40 40 40 40 40 40 40 40 40 µs
(TYP)

Notes: 1. Performance values measured in fresh-out-of-box (FOB) state using FIO with a queue
depth of 32.
2. Drive write cache enabled.
3. NVMe power state 0.
4. 4KB transfers with a queue depth of 1 are used to measure READ/WRITE latency values.
5. 4KB transfers can be further improved with the support of HMB by the host.
6. System variations will affect measured results.

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Component Electrical Characteristics

Component Electrical Characteristics

Environmental conditions beyond those listed may cause permanent damage to the de-
vice. This is a stress rating only, and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.

BGA Type

Table 12: Power Consumption

NVMe Power NVMe Power NVMe Power State 0

State 4 State 3 Idle Power
Capacity Sleep Slumber (IDLP) Active Reads Active Writes Unit
64GB 3 <80 <100 <3000 <3000 mW
128GB 3 <80 <100 <3000 <3000 mW
256GB 3 <80 <100 <3000 <3000 mW
512GB 3 <80 <150 <3000 <4000 mW
1024GB 3 <80 <200 <3000 <5000 mW

Notes: 1. Active reads/actives write power is an average power measurement performed using FIO
with 128KB sequential read/write transfers respectively.
2. For power states 3 and power state 4 average power measurements, the PCIe state is set
to L1.2 link state.

Table 13: Maximum Current per Power Rail

Parameter 64GB 128GB 256GB 512GB 1024GB Unit

Symbol/ Active Active Active Active Active Active Active Active Active Active
Capacity Read Write Read Write Read Write Read Write Read Write
PWR_1 75 75 115 115 170 165 175 290 195 290 mA
PWR_2 130 110 160 125 240 150 405 295 420 330 mA
PWR_3 1555 1295 1475 1220 1575 1320 1535 1280 1600 1345 mA

Notes: 1. The data is obtained from limited samples.

2. Average maximum current over any 8ms time interval.

Table 14: Operating Ratings

Parameter Symbol/Condition Nominal Min Max Unit

PWR_1 3.3 2.97 3.63 V
PWR_2 1.2 1.14 1.26 V
PWR_3 0.9 0.86 0.945 V
Delay in between the power-off and power-on (all PWRs) 1 s
Operating temperature1,4 TC -40 95 °C
Sensor temperature2, 3 TS -55 135 °C

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Component Electrical Characteristics

Table 14: Operating Ratings (Continued)

Parameter Symbol/Condition Nominal Min Max Unit

Non-operating ambient temperature - -40 105 °C
Rate of temperature change(both operating & unbiased) - - 90 °C/hour
Relative humidity (non-condensing) - 5 95 %

Notes: 1. Operating temperature is the case surface temperature at the center of the top side of
the device.
2. Temperature is measured by SMART. Sensor temperature represents the TJ of the SSD
micro-controller. The reported temperature is expected to be sightly greater than Oper-
ating temperature TC. The temperature difference will be highest at heavy workload
and without air-flow.
3. If SMART temperature (Log Identifier 02h) exceeds 115°C, performance will be throttled.
Sensor temperature range has been characterised on limited samples.
4. Refer to TN-00-08 for method and the criteria to ensure that the memory operates be-
low its maximum allowable temperature.
5. Refer to TN-FD-50: 2100AT Power Supply Electrical Requirements for further information
about power on/off and power cycle requirements.

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Modules Electrical Characteristics

Modules Electrical Characteristics

Environmental conditions beyond those listed may cause permanent damage to the de-
vice. This is a stress rating only, and functional operation of the device at these or any
other conditions above those indicated in the operational sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect reliability.

M.2 Type

Table 15: Power Consumption

NVMe Power NVMe Power NVMe Power State 0

State 4 State 3 Idle Power
Capacity Sleep Slumber (IDLP) Active Reads Active Writes Unit
128GB 5 <80 <100 <3000 <3000 mW
256GB 5 <80 <100 <3000 <3000 mW
512GB 5 <80 <150 <3000 <4000 mW
1024GB 5 <80 <200 <3000 <5000 mW

Notes: 1. Active reads/active writes power is an average power measurement performed using FIO
with 128KB sequential read/write transfers.
2. For Power States 3 and 4 average power measurements, the PCIe is set to L1.2 link state.

Table 16: Operating Ratings

Signal Name/Condition Nominal Min Max Unit

3.3V 3.3V 3.135 3.465 V
Delay in between the power-off and power-on (3.3V) 1 s
Operating temperature1 TC -40 95 °C
Sensor temperature2, 3 TS -55 135 °C
Non-operating ambient temperature - -40 105 °C
Rate of temperature change (both operating & unbiased) - - 90 °C/hour
Relative humidity (non-condensing) - 5 95 %

Notes: 1. Operating temperature is the case surface temperature at the center of the top side of
the device.
2. If SMART temperature (log identifier 02h) exceeds 115°C, performance will be throttled.
3. Temperature is measured by SMART. Sensor temperature range has been characterised
on limited samples.

Table 17: Shock and Vibration

Parameter/Condition Specification
Non-operating shock 1500G @ 0.5ms half sine
Non-operating vibration Random vibration 7-2000Hz

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Identify – Identify Controller Data Structure

Identify – Identify Controller Data Structure

Table 18: Identify – Identify Controller Data Structure

Bytes Default Value Description

01:00 1344h PCI Vendor ID (VID): Contains the Micron identifier assigned by the PCI SIG.
03:02 1344h PCI Subsystem Vendor ID (SSVID): Contains the Micron identifier assigned by
the PCI SIG for the subsystem.
23:04 Variable Serial Number (SN): Contains the serial number for the NVM subsystem as an
ASCII string.
63:24 Variable Model Number (MN): Contains the model number for the NVM subsystem as an
ASCII string.
71:64 Variable Firmware Revision (FR): Contains the currently active firmware revision for the
NVM subsystem.
72 06 Recommended Arbitration Burst (RAB): This is the recommended arbitration
burst size.
75:73 00h-A0h-75h IEEE OUI Identifier (IEEE): Contains the organization unique identifier (24bit
OUI MA-L Format).
76 0 Controller Multi-Path I/O and Namespace Sharing Capabilities (CMIC): This
field specifies multi-path I/O and namespace sharing capabilities of the controller
and NVM subsystem.
Bits 7:3 are reserved
Bit 2 = 0 the controller is associated with a PCI function
Bit 1 = 0 the NVM subsystem contains only a single controller
Bit 0 = 0 the NVM subsystem contains only a single PCI Express port
77 6 Maximum Data Transfer Size (MDTS): This field indicates the maximum data
transfer size between the host and the controller. The host should not submit a
command that exceeds this transfer size. If a command is submitted that exceeds
the transfer size, then the command is aborted with a status of Invalid Field in
command. The value is in units of the minimum memory page size (4096 bytes)
and is reported as a power of two (2n ).
79:78 0001 Controller ID (CNTLID): Contains the NVM subsystem unique controller identifi-
er associated with the controller.
83:80 10300h Version (VER): This register indicates the major and minor version of the NVM
Express specification that the controller implementation supports.
87:84 000249F0h RTD3 Resume Latency (RTD3R): This field indicates the typical latency in micro-
seconds resuming from Runtime D3 (RTD3).
91:88 00013880h RTD3 Entry Latency (RTD3E): This field indicates the typical latency in microsec-
onds to enter Runtime D3 (RTD3).
95:92 00000200h Optional Asynchronous Events Supported (OAES): This field indicates the op-
tional asynchronous events supported by the controller. A controller shall not
send optional asynchronous events before they are enabled by host software.
Bits 31:10 are reserved
Bit 9 = 1 the controller support sending Firmware Activation Notices
Bit 8 = 0 the controller does not support the Namespace Attribute Changed event
Bits 7:0 are reserved
239:96 – Reserved

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Identify – Identify Controller Data Structure

Table 18: Identify – Identify Controller Data Structure (Continued)

Bytes Default Value Description

239:100 – Reserved
255:240 – Reserved
257:256 0000000000011111b Optional Admin Command Support (OACS): This field indicates the optional
Admin commands supported by the controller.
Bits 15:5 are reserved.
Bit 4 = 1 the controller supports the DEVICE SELF TEST (DST) command
Bit 3 = 1 the controller support the NAMESPACE MANAGEMENT and NAMESPACE
ATTACHMENT commands
Bit 2 = 1 the controller supports the FIRMWARE COMMIT and FIRMWARE IMAGE
DOWNLOAD commands
Bit 1 = 1 the controller supports the FORMAT NVM command
Bit 0 = 1 the controller supports the SECURITY SEND and SECURITY RECEIVE com-
mands
258 04h Abort Command Limit (ACL): This field is used to convey the maximum number
of concurrently outstanding ABORT commands supported by the controller. This is
a 0's based value.
259 07h Asynchronous Event Request Limit (AERL): This field is used to convey the
maximum number of concurrently outstanding ASYNCHRONOUS EVENT REQUEST
commands supported by the controller. This is a 0's based value.
260 000010110b Firmware Updates (FRMW): This field indicates capabilities regarding firmware
updates.
Bits 7:5 are reserved.
Bit 4 = 1 the controller does not support firmware activation without a reset
Bits 3:1 = up to 3 the number of firmware slots that the controller supports (de-
pending on OEM)
Bit 0 = 0 the first firmware slot (slot 1) is read/write
261 00000111b Log Page Attributes (LPA): This field indicates optional attributes for log pages
that are accessed via the GET LOG PAGE command.
Bits 7:4 are reserved.
Bit 3 = 0 "Telemetry Host/Controller-Initiated Log Pages" not supported
Bit 2 = 1 the controller supports get log page
Bit 1 = 1 the controller supports the Command Effects log page
Bit 0 = 1 the controller supports the SMART/Health Information log page on a per
namespace basis
262 3Fh Error Log Page Entries (ELPE): This field indicates the number of Error Informa-
tion log entries that are stored by the controller. This field is a 0's based value.
263 4h Number of Power States Support (NPSS): This field indicates the number of
NVM Express power states supported by the controller. This is a 0's based value.
264 1 Reserved
265 00000001b Autonomous Power State Transition Attributes (APSTA): This field indicates
the attributes of the autonomous power state transition feature.
Bits 7:1 are reserved.
Bit 0 = 1 the controller supports autonomous power state transitions

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Identify – Identify Controller Data Structure

Table 18: Identify – Identify Controller Data Structure (Continued)

Bytes Default Value Description

267:266 184h Warning Composite Temperature Threshold (WCTEMP): This field indicates
the minimum Composite Temperature field value (Temperature value reported in
the SMART/Health Information log) that indicates an overheating condition dur-
ing which controller operation continues. Immediate remediation is recommen-
ded (for example, additional cooling or workload reduction). The platform should
strive to maintain a composite temperature below this value.
269:268 18Ch Critical Composite Temperature Threshold (CCTEMP): This field indicates the
minimum Composite Temperature field value (Temperature value reported in the
SMART/Health Information log) that indicates a critical overheating condition (for
example, automatic device shutdown).
271:270 32h Maximum Time for Firmware Activation (MTFA): Indicates the maximum
time the controller temporarily stops processing commands to activate the firm-
ware image. This field is specified in 100 millisecond units.
275:272 4000h Host Memory Buffer Preferred Size (HMPRE): Host Memory Buffer Preferred
Size.
279:276 2000h Host Memory Buffer Minimum Size (HMMIN): Host Memory Buffer Minimum
Size.
295:280 Density Specific Total NVM Capacity (TNVMCAP): Total NVM capacity depends on density:
0xEE8156000 (64GB), 0x1DCF856000 (128GB), 0x3B9E656000 (256GB),
0x773C256000 (512GB), 0xEE77A56000 (1024GB)
311:296 Density Specific Unallocated NVM Capacity (UNVMCAP): Unallocated NVM Capacity is suppor-
ted. Value change runtime depending on SSD usage,
315:312 00000001h Replay Protected Memory Block Support (RPMBS): One single Replay Protec-
ted Memory Blocks is supported.
317:316 000Ah Extended Device Self-test Time (EDSTT): This field indicates the nominal
amount of time in one minute units that the controller takes to complete an ex-
tended DEVICE SELF TEST operation when in power state 0.
318 1 Device Self-test Options (DSTO): This field indicates the controller supports
one DEVICE SELF TEST operation in progress at a time.
319 00h Firmware Update Granularity (FWUG) : This field indicates the controller sup-
ports the Firmware Upgrade Granularity.
321:320 0 Keep Alive Support (KAS): Keep Alive is not supported.
323:322 111h (273K=0°C) Host Controlled Thermal Management Attributes (HCTMA): This field indi-
cates the attributes of the host controlled thermal management feature.
Bits 15:1 are reserved.
Bit 0 = 0 the controller does not support host controlled thermal management
325:324 184h (388K=115°C) Minimum Thermal Management Temperature (MNTMT): This field indicates
the minimum temperature, in degrees Kelvin, that the host may request in the
Thermal Management Temperature 1 field and Thermal Management Tempera-
ture 2 field of a SET FEATURES command.
327:326 0000h Maximum Thermal Management Temperature (MXTMT): This field indicates
the maximum temperature, in degrees Kelvin, that the host may request in the
Thermal Management Temperature 1 field and Thermal Management Tempera-
ture 2 field of a SET FEATURES command.

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Identify – Identify Controller Data Structure

Table 18: Identify – Identify Controller Data Structure (Continued)

Bytes Default Value Description

331:328 0003h Sanitize Capabilities (SANICAP): This field indicates attributes for sanitize op-
erations. If the Sanitize command is supported then this field shall be non-zero
511:332 – Reserved
512 66h Submission Queue Entry Size (SQES): This field defines the required and maxi-
mum submission queue entry size when using the NVM command set.
Bits 7:4 = 6 defines the maximum submission queue entry size when using the
NVM command set. The value is in bytes and is reported as a power of two (2n )
Bits 3:0 = 6 defines the required submission queue entry size when using the NVM
command set. The value is in bytes and is reported as a power of two (2n )
513 44h Completion Queue Entry Size (CQES): This field defines the required and max-
imum completion queue entry size when using the NVM command set.
Bits 7:4 = 4 defines the maximum completion queue entry size when using the
NVM command set. The value is in bytes and is reported as a power of two (2n )
Bits 3:0 = 4 defines the required completion queue entry size when using the
NVM command set. The value is in bytes and is reported as a power of two (2n )
515:514 0 Maximum Outstanding Commands (MAXCMD): Maximum Outstanding Com-
mands is not supported.
519:516 4 Number of Namespaces (NN): This field defines the number of valid namespa-
ces present for the controller.
521:520 0000000001010101b Optional NVM Command Support (ONCS): This field indicates the optional
NVM commands and features supported by the controller.
Bits 15:7 are reserved.
Bit 6 = 1 timestamp supported
Bit 5 = 0 the controller does not support reservations
Bit 4 = 1 the controller supports the save field in the SET FEATURES command and
the select field in the GET FEATURES command
Bit 3 = 0 the controller does not support the WRITE ZEROS command
Bit 2 = 1 the controller supports the DATASET MANAGEMENT command
Bit 1 = 0 the controller does not support the WRITE UNCORRECTABLE command
Bit 0 = 1 the controller support the COMPARE command
523:522 0 Fused Operation Support (FUSES): Fused Operation is not supported.
524 00000111b Format NVM Attributes (FNA): This field indicates attributes for the FORMAT
NVM command.
Bits 7:3 are reserved.
Bit 2 = 1 indicates cryptographic erase is supported as part of the secure erase
functionality
Bit 1 = 1 user data erase of a particular namespace as part of a format results in a
user data erase of all namespaces
Bit 0 = 1 all namespaces shall be configured with the same attributes and a for-
mat of any namespace results in a format of all namespaces

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Identify – Identify Controller Data Structure

Table 18: Identify – Identify Controller Data Structure (Continued)

Bytes Default Value Description

525 00000001b Volatile Write Cache (VWC): This field indicates attributes related to the pres-
ence of a volatile write cache in the implementation.
Bits 7:1 are reserved.
Bit 0 = 1 volatile write cache is present. The host may issue FLUSH commands and
control whether the volatile write cache is enabled with SET FEATURES specifying
the volatile write cache feature identifier.
527:526 0 Atomic Write Unit Normal (AWUN) is not supported.
529:528 0 Atomic Write Unit Power Fail (AWUPF) is not supported.
530 1 NVM Vendor Specific Command Configuration (NVSCC)
531 – Reserved.
533:532 0 Atomic Compare & Write Unit (ACWU): Atomic Compare & Write Unit is not
supported.
535:534 – Reserved
539:536 0 SGL Support (SGLS): SGL is not supported.
767:540 – Reserved.
1023:768 Variable NVM Subsystem NVMe Qualified Name (SUBNQN): This field specifies the
NVM Subsystem NVMe Qualified Name as a UTF-8 null-terminated string.
2047:1024 – Reserved
2079:2048 Density Specific Power State 0 Descriptor (PSD0): This field indicates the characteristics of
power state 0. The format of this field is defined in Table 19.
2111:2080 Density Specific Power State 1 Descriptor (PSD1): This field indicates the characteristics of
power state 1. The format of this field is defined in Table 19.
2143:2112 Density Specific Power State 2 Descriptor (PSD2): This field indicates the characteristics of
power state 2. The format of this field is defined in Table 19.
2175:2144 303030300003A9800001 Power State 3 Descriptor (PSD3): This field indicates the characteristics of
F40030008DEh power state 3. The format of this field is defined in Table 19.
2207:2176 40404040000C35000002 Power State 4 Descriptor (PSD4): This field indicates the characteristics of
71003000082h power state 4. The format of this field is defined in Table 19.
327F:2208 - Reserved.
3280 Variable Physical Capacity Management Attribute (PCMA): This field indicates the at-
tributes and support of the Physical Capacity Management feature.
3281 Variable Maximum Namespaces in SLC Physical Configuration (MNSPC): This field
indicates the maximum amount of namespaces the SLC physical space can support
in the current physical configuration.
3282 Variable Maximum Namespace in TLC Physical Configuration (MNTPC): This field in-
dicates the maximum amount of namespaces the TLC physical space can support
in the current physical configuration.
3298:3283 Variable Total SLC NVM Capacity (TSNCAP):This field indicates the total SLC NVM ca-
pacity in the NVM subsystem for the current physical configuration. The value is in
bytes.

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Identify – Identify Controller Data Structure

Table 18: Identify – Identify Controller Data Structure (Continued)

Bytes Default Value Description

3314 : 3299 Variable Total TLC NVM Capacity (TTNCAP):This field indicates the total TLC NVM ca-
pacity in the NVM subsystem for the current physical configuration. The value is in
bytes.
4095:3315 – Reserved.

Table 19: Power State Descriptor Data Structure

Bits Description
15:0 Maximum Power (MP): This field indicates the maximum power consumed by the NVM subsystem in this
power state. The power in Watts is equal to the value in this field multiplied by the scale specified in the
Maximum Power Scale field.
23:16 Reserved
24 Max Power Scale (MPS): This field indicates the scale for the Maximum Power field. If this field is cleared
to 0, then the scale of the Maximum Power field is in 0.01 Watts. If this field is set to 1, then the scale of the
Maximum Power field is in 0.0001 Watts.
25 Non-Operational State (NOPS): This field indicates whether the controller processes I/O commands in this
power state. If this field is cleared to 0, then the controller processes I/O commands in this power state. If
this field is set to 1, then the controller does not process I/O commands in this power state.
31:26 Reserved
63:32 Entry Latency (ENLAT): This field indicates the maximum entry latency in microseconds associated with
entering this power state.
95:64 Exit Latency (EXLAT): This field indicates the maximum exit latency in microseconds associated with exit-
ing this power state.
100:96 Relative Read Throughput (RRT): This field indicates the relative read throughput associated with this
power state. A lower value means higher read throughput.
103:101 Reserved
108:104 Relative Read Latency (RRL): This field indicates the relative READ latency associated with this power
state. A lower value means lower READ latency.
111:109 Reserved
116:112 Relative Write Throughput (RWT): This field indicates the relative write throughput associated with this
power state. A lower value means higher write throughput.
119:117 Reserved
124:120 Relative Write Latency (RWL): This field indicates the relative WRITE latency associated with this power
state. A lower value means lower WRITE latency.
127:125 Reserved
143:128 Idle Power (IDLP): This field indicates the typical power consumed by the NVM subsystem over 30 seconds
in this power state when idle. The measurement starts after the NVM subsystem has been idle for 10 sec-
onds. The power in Watts is equal to the value in this field multiplied by the scale indicated in the Idle Pow-
er Scale field.
149:144 Reserved
151:150 Idle Power Scale (IPS): This field indicates the scale for the Idle Power field.

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Identify – Identify Controller Data Structure

Table 19: Power State Descriptor Data Structure (Continued)

Bits Description
159:152 Reserved
175:160 Active Power (ACTP): This field indicates the largest average power consumed by the NVM subsystem over
a 10 second period in this power state with the workload indicated in the Active Power Workload field. The
power in Watts is equal to the value in this field multiplied by the scale indicated in the Active Power Scale
field.
178:176 Active Power Workload (APW): This field indicates the workload used to calculate maximum power for
this power state.
181:179 Reserved
183:182 Active Power Scale (APS): This field indicates the scale for the Active Power field.
255:184 Reserved

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Identify – Identify Namespace Data Structure

Identify – Identify Namespace Data Structure

Table 20: Identify – Identify Namespace Data Structure

Byte Default Value Description

07:00 Variable Namespace Size (NSZE): This field indicates the total size of the namespace in logical
blocks. A namespace of size n consists of LBA 0 through (n - 1). The number of logical blocks
is based on the formatted LBA size.
15:08 Variable Namespace Capacity (NCAP): This field indicates the maximum number of logical blocks
that may be allocated in the namespace at any point in time. The number of logical blocks is
based on the formatted LBA size. A logical block is allocated when it is written with a WRITE
or WRITE UNCORRECTABLE command. A logical block may be deallocated using the DATA-
SET MANAGEMENT command.
23:16 Variable Namespace Utilization (NUSE): This field indicates the current number of logical blocks
allocated in the namespace. This field is equal to the Namespace Capacity. The number of
logical blocks is based on the formatted LBA size. When using the NVM command set: A log-
ical block is allocated when it is written with a WRITE or WRITE UNCORRECTABLE command.
A logical block may be deallocated using the DATASET MANAGEMENT command.
24 00000100b Namespace Features (NSFEAT): This field defines features of the namespace.
Bits 7:4 are reserved
Bit 3 = 0 the NGUID and EUI64 fields for this namespace are reused by the controller
Bit 2 = 1 the controller does support the Deallocated or Unwritten Logical Block error
Bit 1 = 0 the controller does not support the fields NAWUN, NAWUPF, and NACWU for the
namespace
Bit 0 = 0 thin provisioning is not supported, the Namespace Size and Namespace Capacity
fields report the same value
25 0 Number of LBA Formats (NLBAF):

This field defines the number of supported LBA data sizes supported by the namespace. This
is a 0's based value.
26 00000000b Formatted LBA Size (FLBAS): This field indicates the LBA data size that the namespace
has been formatted with.
Bits 7:5 are reserved
Bit 4 = 0 the controller does not support metadata
Bits 3:0 = 0. Indicates one of the 2 supported LBA formats indicated in this data structure.
27 0 Metadata Capabilities (MC): Metadata Capabilities is not supported.
28 0 End-to-end Data Protection Capabilities (DPC): End-to-end Data Protection Capabilities
is not supported.
29 0 End-to-end Data Protection Type Settings (DPS): End-to-end Data Protection Type Set-
tings is not supported.
30 0 Namespace Multi-path I/O and Namespace Sharing Capabilities (NMIC): Namespace
Multi-path I/O and Namespace Sharing Capabilities is not supported.
31 0 Reservation Capabilities (RESCAP): Reservation Capabilities field is not supported.

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Identify – Identify Namespace Data Structure

Table 20: Identify – Identify Namespace Data Structure (Continued)

Byte Default Value Description

32 1VVVVVVVb Format Progress Indicator (FPI): If a format operation is in progress, this field indicates
the percentage of the namespace that remains to be formatted.
Bit 7 = 1 the namespace supports the Format Progress Indicator defined by bits 6:0 in this
field
Bits 6:0 = Variable. Indicates the percentage of the namespace that remains to be formatted
(For example, a value of 25 indicates that 75% of the namespace has been formatted and
25% remains to be formatted). A value of 0 indicates that the namespace is formatted with
the format specified by the FLBAS field in this data structure.
33 – Reserved
35:34 0 Namespace Atomic Write Unit Normal (NAWUN): Namespace Atomic Write Unit Nor-
mal is not supported.
37:36 0 Namespace Atomic Write Unit Power Fail (NAWUPF): Namespace Atomic Write Unit
Power Fail is not supported.
39:38 0 Namespace Atomic Compare & Write Unit (NACWU): Namespace Atomic Compare &
Write Unit is not supported.
41:40 0 Namespace Atomic Boundary Size Normal (NABSN): Namespace Atomic Boundary Size
Normal is not supported.
43:42 0 Namespace Atomic Boundary Offset (NABO): Namespace Atomic Boundary Offset is not
supported.
45:44 0 Namespace Atomic Boundary Size Power Fail (NABSPF): Namespace Atomic Boundary
Size Power Fail is not supported.
47:46 – Reserved
63:48 0 NVM Capacity (NVMCAP): This field indicates the total size of the NVM allocated to this
namespace. The value is in bytes.
103:64 – Reserved
119:104 Variable Namespace Globally Unique Identifier (NGUID): This field contains the 128-bit Name-
space Globally Unique Identifier value.
127:120 Variable IEEE Extended Unique Identifier (EUI64): This field contains the 64-bit IEEE Extended
Unique Identifier value.
131:128 90000 LBA Format 0 Support (LBAF0)
135:132 – LBA Format 1 Support (LBAF1): not supported
139:136 – LBA Format 2 Support (LBAF2): not supported
... – ... – ...
191:188 – LBA Format 15 Support (LBAF15): not supported
383:192 – Reserved
384 – Namespace Physical NAND Configuration (NPNC):
Bits 7:2 are reserved
Bit 1 = 1 for TLC operation
Bit 0 = 1 for SLC operation of the Namespace
4095:385 – Vendor Specific (VS)

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Interface Signals

Interface Signals
BGA Type

Figure 3: Ballmap - BGA Type (Top View)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

A DNU DNU DNU DNU DNU DNU DNU DNU DNU DNU

B DNU DNU DNU DNU DNU DNU DNU DNU DNU DNU

C GND GND GND GND GND DNU DNU

DNU DNU DNU DNU DNU DNU RFU RFU GND DNU DNU DNU

UART_
D REFCLKp REFCLKn DNU
GND PERST# CLKREQ# PWR_1 PWR_1 GND DNU RFU RFU
DLorem ipsum RX
UART_
E GND GND GND GND GND GND GND DNU PWR_1 PWR_1 GND DNU GND GND DNU DNU DNU
TX

F PERp0 PERn0 GND DNU RFU

G GND GND GND GND GND PWR_3 PWR_3 GND GND PWR_3 PWR_3 GND GND DNU DNU DNU

H PETp0 PETn0 PWR_3 PWR_3 GND GND PWR_3 PWR_3 RFU PLN#

J GND GND GND GND GND PWR_3 PWR_3 GND GND PWR_3 PWR_3 GND GND DNU DNU DNU

K PERp1 PERn1 GND GND GND GND GND GND RFU PLA#

JTAG_
L GND GND GND GND GND RFU RFU RFU RFU RFU RFU GND GND DNU DNU
TRST#

M PETp1 PETn1 RFU RFU GND GND RFU RFU RFU RFU

JTAG_ JTAG_
N GND GND GND GND GND RFU RFU RFU RFU RFU RFU GND GND DNU
TCK TMS

P PERp2 PERn2 GND GND GND GND GND GND RFU RFU

JTAG_ JTAG_
R GND GND GND GND GND PWR_2 PWR_2 GND GND PWR_2 PWR_2 GND GND DNU
TDI TDO

T PETp2 PETn2 PWR_2 PWR_2 GND GND PWR_2 PWR_2 RFU RFU

U GND GND GND GND GND PWR_2 PWR_2 GND GND PWR_2 PWR_2 GND GND DNU DNU DNU

V PERp3 PERn3 RFU RFU

W GND GND GND GND GND GND LED_1# RFU PWR_1 PWR_1 GND RFU RFU GND GND DNU DNU DNU

Y PETp3 PETn3 GND DNU DNU PWR_1 PWR_1 GND DNU GND DNU DNU

AA GND GND GND GND GND DNU DNU DNU DNU DNU DNU DNU DNU GND GND DNU DNU DNU

AB DNU DNU DNU DNU DNU DNU DNU DNU DNU DNU

AC DNU DNU DNU DNU DNU DNU DNU DNU DNU DNU

Note: 1. Preliminary ballmap. Available signals are subject to change.

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Interface Signals

Table 21: BGA Signal Descriptions

Name Type Power Domain Description

PETp0, PETn0 O PCIe TX+ Lane 0, PCIe TX- Lane 0
PERp0, PERn0 I PCIe RX+ Lane 0, PCIe RX- Lane 0
PETp1, PETn1 O PCIe TX+ Lane 1, PCIe TX- Lane 1. It can be left floating
PERp1, PERn1 I PCIe RX+ Lane 1, PCIe RX- Lane 1. It can be left floating
PETp2, PETn2 O PCIe TX+ Lane 2, PCIe TX- Lane 2. It can be left floating
PERp2, PERn2 I PCIe RX+ Lane 2, PCIe RX- Lane 2. It can be left floating
PETp3, PETn3 O PCIe TX+ Lane 3, PCIe TX- Lane 3. It can be left floating
PERp3, PERn3 I PCIe RX+ Lane 3, PCIe RX- Lane 3. It can be left floating
REFCLKp, REFCLKn I 100 MHz reference clock+, 100 MHz reference clock–
CLKREQ# OD (1.8V) Clock request
PERST# I (1.8V) PCIe Fundamental Reset
LED_1# OD 3.3V Status indicator for system LED; Optional for customer. It
can use 100 ohms to LED tied to 3.3V
UART_RX I 3.3V Engineering test. It can be left floating1
UART_TX O 3.3V Engineering test. It can be left floating1
JTAG_TRST# I 3.3V Engineering test. It can be left floating1
JTAG__TDI I 3.3V Engineering test. It can be left floating1
JTAG__TDO O 3.3V Engineering test. It can be left floating1
JTAG__TCK I 3.3V Engineering test. It can be left floating1
JTAG__TMS I 3.3V Engineering test. It can be left floating1
PLN# I 3.3V6 Power Loss Notification. Pull-up when not driven.
PLA# O 3.3V6 Power Loss Acknowledgement (default high).
PWR_1 I 3.3V power 7
PWR_2 I 1.2V power
PWR_3 I 0.9V power
RFU NA NA Reserved for future use2
DNU NA NA Do not use3

Notes: 1. Engineering test signal should be routed to a test point pad. They are not intended for
customer use since they have controlled access to insure security of data
2. RFU signals are reserved for future use. These balls shall be soldered to a platform
board, but shall be electrically no-connect on the host or the module
3. DNU signals are for manufacturing only. These balls shall be soldered to a platform
board, but shall be electrically no-connect on the host or the module
4. Power domain (1.8V) is internally generated by an LDO
5. Each PCIe in-band signal (PETxy/PERxy) requires AC coupling capacitance (75nF–500nF)
close to the transmitter
6. We recommend to make a design compatible with both 3.3V and 1.8V.
7. We recommend to make a design compatible with 2.5V for next generation SSD.

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Interface Connectors

Interface Connectors
M.2 Type

Figure 4: Connector - M.2 Type

Top side Bottom side

P75 P57 P1 P2 P58 P74

P67 P68

Table 22: Signal Assignments

Top Side Bottom Side

Pin # Signal Name Description Pin # Signal Name Description
1 GND Ground 2 3.3V +3.3V
3 GND Ground 4 3.3V +3.3V
5 PETn3 PCIe TX– Lane 3 6 NC6 No connect
7 PETp3 PCIe TX+ Lane 3 8 PLN# Power Loss Notification
9 GND Ground 10 LED_1# LED Activity Indicator
11 PERn3 PCIe RX– Lane 3 12 3.3V +3.3V
13 PERp3 PCIe RX+ Lane 3 14 3.3V +3.3V
15 GND Ground 16 3.3V +3.3V
17 PETn2 PCIe TX– Lane 2 18 3.3V +3.3V
19 PETp2 PCIe TX+ Lane 2 20 NC20 No connect
21 GND Ground 22 NC22 No connect
23 PERn2 PCIe RX– Lane 2 24 NC24 No connect
25 PERp2 PCIe RX+ Lane 2 26 NC26 No connect
27 GND Ground 28 NC28 No connect
29 PETn1 PCIe TX– Lane 1 30 PLA# Power Loss Acknowl-
edge
31 PETp1 PCIe TX+ Lane 1 32 NC32 No connect
33 GND Ground 34 NC34 No connect
35 PERn1 PCIe RX– Lane 1 36 NC36 No connect
37 PERp1 PCIe RX+ Lane 1 38 NC38 No connect
39 GND Ground 40 NC40 No connect
41 PETn0 PCIe TX– Lane 0 42 NC42 No connect
43 PETp0 PCIe TX+ Lane 0 44 NC44 No connect

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Interface Connectors

Table 22: Signal Assignments (Continued)

Top Side Bottom Side

Pin # Signal Name Description Pin # Signal Name Description
45 GND Ground 46 NC46 No connect
47 PERn0 PCIe RX– Lane 0 48 NC48 No connect
49 PERp0 PCIe RX+ Lane 0 50 PERST# PERST#
51 GND Ground 52 CLKREQ# CLKREQ#
53 REFCLKn PCIe REFCLK– 54 PEWAKE# No connect
55 REFCLKp PCIe REFCLK+ 56 UART_RX Reserved - Engineering
test
57 GND Ground 58 UART_TX Reserved - Engineering
test
Mechanical M Key Mechanical M Key
67 NC67 No connect 68 SUSCLK No connect
69 PEDET No connect 70 3.3V +3.3V
71 GND Ground 72 3.3V +3.3V
73 GND Ground 74 3.3V +3.3V
75 GND Ground – – –

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Commands

Commands

Table 23: Op Codes for Admin Commands

Codes not listed are reserved. All commands in the table are supported.
Command Name Op Code (hex)
DELETE I/O SUBMISSION QUEUE 00h
CREATE I/O SUBMISSION QUEUE 01h
GET LOG PAGE 02h
DELETE I/O COMPLETION QUEUE 04h
CREATE I/O COMPLETION QUEUE 05h
IDENTIFY 06h
ABORT 08h
SET FEATURES – SET ARBITRATION 09h - 01h
SET FEATURES – SET POWER MANAGEMENT 09h - 02h
SET FEATURES – SET LBA RANGE TYPE 09h - 03h
SET FEATURES – SET TEMPERATURE THRESHOLD 09h - 04h
SET FEATURES – SET ERROR RECOVERY 09h - 05h
SET FEATURES – SET VOLATILE WRITE CACHE 09h - 06h
SET FEATURES – SET NUMBER OF QUEUES 09h - 07h
SET FEATURES – SET INTERRUPT COALESCE 09h - 08h
SET FEATURES – SET INTERRUPT VECTOR CONFIGURATION 09h - 09h
SET FEATURES – SET WRITE ATOMICITY 09h - 0Ah (Not Supported)
SET FEATURES – SET ASYNC EVENT CONFIGURATION 09h - 0Bh
SET FEATURES – SET AUTONOMOUS POWER STATE TRANSITION 09h - 0Ch
SET FEATURES – SET HOST MEMORY BUFFER 09h - 0Dh
SET FEATURES - TIMESTAMP 09h - 0Eh
SET FEATURES - KEEP ALIVE TIMER 09h - 0Fh (Not Supported)
SET FEATURES – HOST CONTROLLED THERMAL MANAGEMENT 09h - 10h
SET FEATURES – NON OPERATIONAL POWER STATE CONFIG 09h - 11h
SET FEATURES – SW PROGRESS MARKER 09h - 80h
SET FEATURES - RESERVATION PERSISTENCE 09h - 83h (Not Supported)
SET FEATURES - RESERVATION PERSISTENCE 09h - 83h (Not Supported)
SET FEATURES - RESERVATION PERSISTENCE 09h - 83h (Not Supported)
SET FEATURES – SET PLN/PLA FEATURES 09h - CAh
SET FEATURES – SLC REFLOW MFG STATE 09h - C6h
GET FEATURES – GET ARBITRATION 0Ah - 01h
GET FEATURES – GET POWER MANAGEMENT 0Ah - 02h
GET FEATURES – GET LBA RANGE TYPE 0Ah - 03h
GET FEATURES – GET TEMPERATURE THRESHOLD 0Ah - 04h
GET FEATURES – GET ERROR RECOVERY 0Ah - 05h
GET FEATURES – GET VOLATILE WRITE CACHE 0Ah - 06h

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Commands

Table 23: Op Codes for Admin Commands (Continued)

Codes not listed are reserved. All commands in the table are supported.
Command Name Op Code (hex)
GET FEATURES – GET NUMBER OF QUEUES 0Ah - 07h
GET FEATURES – GET INTERRUPT COALESCE 0Ah - 08h
GET FEATURES – GET INTERRUPT VECTOR CONFIGURATION 0Ah - 09h
GET FEATURES – HOST CONTROLLED THERMAL MANAGEMENT 0Ah - 10h
GET FEATURES – GET WRITE ATOMICITY 0Ah - 0Ah (Not Supported)
GET FEATURES – GET ASYNC EVENT CONFIGURATION 0Ah - 0Bh
GET FEATURES – GET AUTONOMOUS POWER STATE TRANSITION 0Ah - 0Ch
GET FEATURES – GET HOST MEMORY BUFFER 0Ah - 0Dh
GET FEATURES - TIMESTAMP 0Ah - 0Eh
GET FEATURES – HOST CONTROLLED THERMAL MANAGEMENT OAh - 10h
GET FEATURES – SW PROGRESS MARKER 0Ah - 80h (Not Supported)
GET FEATURES – HOST IDENTIFIER 0Ah - 81h (Not Supported)
GET FEATURES – RESERVATION NOTIFICATION MASK 0Ah - 82h (Not Supported)
GET FEATURES – RESERVATION PERSISTENCE 0Ah - 83h (Not Supported)
GET FEATURES – SLC REFLOW MFG STATE 0Ah - C6h
GET FEATURES – ACCL. PROGRAM MFG STATE 0Ah - C9h (Not Supported)
ASYNCHRONOUS EVENT REQUEST 0Ch (Not Supported)
NAMESPACE MANAGEMENT 0Dh
FIRMWARE COMMIT / ACTIVATE 10h
FIRMWARE IMAGE DOWNLOAD 11h
DEVICE SELF TEST (DST) 14h
DIRECTIVE SEND 19h (Not Supported)
KEEP ALIVE 18h
DIRECTIVE RECEIVE 1Ah (Not Supported)
PHYSICAL CAPACITY MANAGEMENT (Vendor Specific) C0h
LOCK PHYSICAL CONFIGURATION (Vendor Specific) C4h
FORMAT NVM 80h
SECURITY SEND 81h
SECURITY RECEIVE 82h
SANITIZE - BLOCK ERASE 84h - 01h
SANITIZE - OVERWRITE 84h - 02h
SANITIZE - CRYPTO ERASE 84h - 03h

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Commands

Table 24: Op Codes for NVMe Commands

Codes not listed are reserved. All commands in the table are supported.
Command Name Op Code (hex)
FLUSH 00h
WRITE 01h
READ 02h
WRITE UNCORRECTABLE 04h1 (Not Supported)
COMPARE ZEROs 05h1
WRITE ZEROs 08h1 (Not Supported)
DATASET MANAGEMENT – DEALLOCATE (AD) 09h1
DATASET MANAGEMENT – INTEGRAL DATA SET FOR WRITE (IDW) 09h1
DATASET MANAGEMENT – INTEGRAL DATA SET FOR READ (IDR) 09h1
RESERVATION REGISTER 0Dh (Not Supported)
RESERVATION REPORT 0Eh (Not Supported)
RESERVATION ACQUIRE 11h (Not Supported)
RESERVATION RELEASE 15h (Not Supported)

Note: 1. 4KB LBA alignment is mandatory.

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Log Pages

Log Pages
The SSD supports log information as defined in the NVMe specification. Supported in-
formation is shown in the following tables:
• Error Information (Log Identifier 01h)
• SMART/Health Information (Log Identifier 02h)
• Firmware Slot Information (Log Identifier 03h)
• Commands Supported and Effects (Log Identifier 05h)
• Device Self-Test Log (Log Identifier 06h)

Table 25: Error Information Log Entry (Log Identifier 01h)

Bytes Name Description

7:0 Error count This is a 64-bit incrementing error count, indicating a unique identifier for this error. The
error count starts at 1h, is incremented for each unique error log entry, and is retained
across power off conditions. A value of 0h indicates an invalid entry; this value may be
used when there are lost entries or when there are fewer errors than the maximum
number of entries the controller supports.
9:8 Submission queue ID This field indicates the submission queue Identifier of the command that the error infor-
mation is associated with. If the error is not specific to a particular command then this
field shall be set to FFFFh.
11:10 Command ID This field indicates the command Identifier of the command that the error is associated
with. If the error is not specific to a particular command then this field shall be set to
FFFFh.
13:12 Status field This field indicates the status field for the command that completed. The status field is
located in bits 15:01, bit 00 corresponds to the phase tag posted for the command. If the
error is not specific to a particular command then this field reports the most applicable
status value.
15:14 Parameter error loca- This field indicates the byte and bit of the command parameter that the error is associ-
tion ated with, if applicable. If the parameter spans multiple bytes or bits, then the location
indicates the first byte and bit of the parameter.
Bit 7:0; Byte in command that contained the error. Valid values are 0 to 63.
Bit 10:8; Bit in command that contained the error. Valid values are 0 to 7.
Bit 15:11; Reserved.
If the error is not specific to a particular command then this field shall be set to FFFFh.
23:16 LBA This field indicates the first LBA that experienced the error condition, if applicable.
27:24 Namespace This field indicates the namespace that the error is associated with, if applicable.
31:28 Reserved Reserved
39:32 Command specific in- This field contains command specific information. If used, the command definition speci-
formation fies the information returned.
63:40 Reserved Reserved

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Log Pages

Table 26: SMART/Health Information (Log Identifier 02h)

Bytes Name Description

0 Critical warning Indicates critical warnings for the state of the controller. Each bit corresponds to a criti-
cal warning type; multiple bits may be set. If a bit is cleared to 0, the critical warning
does not apply. Critical warnings may result in an asynchronous event notification to the
host.
Bit 0; If set to 1, the available spare space has fallen below the threshold.
Bit 1; If set to 1, the temperature has exceeded a critical threshold.
Bit 2; If set to 1, the device reliability has been degraded due to significant media-rela-
ted errors or any internal error that degrades device reliability.
Bit 3; If set to 1, the media has been placed in read-only mode.
Bit 4; If set to 1, the volatile memory backup device has failed.
Bits 7:5; Reserved.
2:1 Temperature Contains the temperature of the controller in units of Kelvin. If it exceeds the tempera-
ture threshold, an asynchronous event may be issued to the host.
3 Available spare Contains a normalized percentage (0–100%) of the remaining available spare capacity.
4 Available spare When the available spare falls below the threshold indicated in this field, an asynchro-
threshold nous event may be issued to the host. The value is indicated as a normalized percentage
(0–100%).
5　 Percentage used 　 Contains an estimate of the percentage of the device life used based on the actual de-
vice usage and prediction of device life. A value of 100 indicates that the estimated en-
durance of the device has been consumed, but may not indicate a device failure. The
value is allowed to exceed 100.
Percentages greater than 254 shall be represented as 255. This value shall be updated
once per power-on hour (when the controller is not in a sleep state).
31:6 Reserved Reserved
47:32 Data units read Contains the number of 512-byte data units the host has read from the controller; this
value does not include metadata. This value is reported in thousands (that is, a value of
1 corresponds to 1000 units of 512 bytes read) and is rounded up. For the NVM com-
mand set, logical blocks read as part of COMPARE and READ operations shall be inclu-
ded in this value.
63:48 Data units written Contains the number of 512-byte data units the host has written to the controller; this
value does not include metadata. This value is reported in thousands (that is, a value of
1 corresponds to 1000 units of 512 bytes written) and is rounded up. For the NVM com-
mand set, logical blocks written as part of WRITE operations shall be included in this val-
ue.
79:64 Host READ com- Contains the number of READ commands completed by the controller. For the NVM
mands command set, this is the number of COMPARE and READ commands.
95:80 Host WRITE com- Contains the number of WRITE commands completed by the controller. For the NVM
mands command set, this is the number of WRITE commands.
111:96 Controller busy time Contains the amount of time the controller is busy with I/O commands. The controller is
busy when there is a command outstanding to an I/O queue (specifically, a command
was issued via an I/O submission queue tail doorbell write and the corresponding com-
pletion queue entry has not been posted yet to the associated I/O completion queue.
This value is reported in minutes.

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Log Pages

Table 26: SMART/Health Information (Log Identifier 02h) (Continued)

Bytes Name Description

127:112 Power cycles Contains the number of power cycles.
143:128 Power on hours Contains the number of power-on hours. This does not include time that the controller
was powered and in a low-power state condition.
159:144 Unsafe shutdowns Contains the number of unsafe shutdowns. This count is incremented when a shutdown
notification (CC.SHN) is not received prior to loss of power.
175:160 Media and data in- Contains the number of occurrences where the controller detected an unrecovered data
tegrity errors integrity error.
191:176 Number of error info Contains the number of error information log entries over the life of the controller.
log entries
195:192 Warning composite Contains the amount of time in minutes that the controller is operational and the com-
temperature time posite temperature is greater than or equal to the warning composite temperature
threshold (WCTEMP) field and less than the critical composite temperature threshold
(CCTEMP) field in the Identify controller data structure. If the value of the WCTEMP or
CCTEMP field is 0h, then this field is always cleared to 0h regardless of the composite
temperature value.
199:196 Critical composite Contains the amount of time in minutes that the controller is operational and the com-
temperature time posite temperature is greater the critical composite temperature threshold (CCTEMP)
field in the Identify controller data structure. If the value of the CCTEMP field is 0h, then
this field is always cleared to 0h regardless of the composite temperature value.
201:200 Temperature Sensor Contains the highest Nand temperature.
1
215:202 Reserved Reserved
219:216 Thermal Manage- Contains the number of times the controller transitioned to lower power active power
ment Temperature 1 states or performed vendor-specific thermal management actions while minimizing the
transition count impact on performance in order to attempt to reduce the Composite Temperature be-
cause of the host-controlled thermal management feature. This counter shall not wrap
after it reaches its maximum value. A value of zero indicates that this transition has nev-
er occurred.
223:220 Thermal Manage- Contains the number of times the controller transitioned to lower power active power
ment Temperature 2 states or performed vendor-specific thermal management actions regardless of the im-
transition count pact on performance in order to attempt to reduce the Composite Temperature because
of the host-controlled thermal management feature. This counter shall not wrap after it
reaches its maximum value. A value of zero indicates that this transition has never occur-
red.
227:224 Total time for Ther- Contains the number of seconds that the controller transitioned to lower power active
mal Management power states or performed vendor-specific thermal management actions while minimiz-
Temperature 1 ing the impact on performance in order to attempt to reduce the Composite Tempera-
ture because of the host-controlled thermal management feature. This counter shall not
wrap after it reaches its maximum value. A value of zero indicates that this transition
has never occurred.

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Log Pages

Table 26: SMART/Health Information (Log Identifier 02h) (Continued)

Bytes Name Description

231:228 Total time for Ther- Contains the number of seconds that the controller transitioned to lower power active
mal Management power states or performed vendor-specific thermal management actions regardless of
Temperature 2 the impact on performance in order to attempt to reduce the Composite Temperature
because of the host controlled thermal management feature. This counter shall not
wrap after it reaches its maximum value. A value of zero indicates that this transition
has never occurred.
511:232 Reserved Reserved

Table 27: Firmware Slot Information (Log Identifier 03h)

Bytes Name Description

0 Active Firmware Info Specifies information about the active firmware revision.
(AFI) Bit 7 is reserved.
Bits 6:4 indicates the firmware slot that is going to be activated at the next controller
reset.
Bit 3 is reserved.
Bits 2:0 indicates the firmware slot from which the actively running firmware revision
was loaded.
7:1 Reserved Reserved
15:08 Firmware Revision Contains the revision of the firmware downloaded to firmware slot 1.
for Slot 1 (FRS1)
511:16 Reserved Reserved

Table 28: Commands Supported and Effects (Log Identifier 05h)

Bytes Name Description

3:0 Admin Command Contains the Command Effect data structure for the Admin command with an opcode
Supported 0 (ACS0) value of 0h. The format of this field is defined by the NVM Express specification.
… … …
1023:1020 Admin Command Contains the Command Effect data structure for the Admin command with an opcode
Supported 255 value of 255. The format of this field is defined by the NVM Express specification.
(ACS255)
1027:1024 I/O Command Sup- Contains the Command Effect data structure for the I/O command with an opcode val-
ported 0 (IOCS0) ue of 0h. The format of this field is defined by the NVM Express specification.
… … …
2047:2044 I/O Command Sup- Contains the Command Effect data structure for the I/O command with an opcode val-
ported 255 (IOCS255) ue of 255. The format of this field is defined by the NVM Express specification.
4095:2048 Reserved Reserved

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Log Pages

Table 29: Device Self-Test Log (Log Identifier 06h)

Bytes Name Description

0 Current Device Self- Defines the current device self-test operation.
Test Operation Bits 7:4 are reserved.
Bits 3:0 Value indicates the status of the current device self-test operation.
Value 0h = No device self-test operation in progress.
Value 1h = Short device self-test operation in progress.
Value 2h = Extended device self-test operation in progress.
Value Fh:3h = Reserved.
1 Current Device Self- Defines the completion status of the current device self-test.
Test Completion Bit 7 is reserved.
Bits 6:0 indicates the percentage of the device self-test operation that is complete.
3:2 Reserved Reserved
31:4 Newest Device Self- The format of this field is defined by the NVM Express specification.
Test Result Data
Structure
… … …
563:536 20th Newest Device The format of this field is defined by the NVM Express specification.
Self-Test Result Data
Structure

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TCG/Opal Support

TCG/Opal Support

Table 30: TCG/Opal Support Parameters

Property Supported? Comments

TCG Storage Specifications
OPAL: TCG Storage Security SubSystem Specification 2.00 Revision 1.00, Feb 24, 2012
Class
TCG Core Specification Specification 2.00 Revision 2.00, Nov 4, 2011
TCG Storage Interface Interactions Specifi- TCG Reference Specification Version 1.02 Revision 1.00 30 Decem-
cation Specification ber, 2011
OPAL SSC 1.00 (backward compatibility) Not supported –
OPAL SSC Additional Feature Set Specification
Additional DataStore Table Supported Specification 1.00 Revision 1.00, Feb 24, 2012
Single User Mode Supported Specification 1.00 Revision 1.00, Feb 24, 2012
TCG Storage Protection Mechanisms for Supported Specification Version 1.00 Revision 1.07 17 August,
Secrets 2011
PSID – Physical Presence SID Supported Specification Version 1.00 Committee Draft Revi-
sion 1.05 February 9, 2011
GUDID (Globally Unique Serial Number) Supported Mandatory GUDID Proposal 11/03/2011 (Microsoft)
SID Authority Disable Supported SID Authority Disable Proposal 9/26/2011 (Micro-
soft)
Modifiable CommonName Columns Supported Modifiable CommonName Columns Proposal
7/22/2010 (Microsoft)
OPAL SSC Feature Set – Specific List
ALL OPAL Mandatory Features Supported –
Close Session (optional) Supported Allows Tper to notify the host it has aborted a ses-
sion
Restricted Command & Table (optional) Not Supported The interface control template enables TPer control
over selected interface commands; the benefit is
the reduction of undesired side effects
Type Table (not required) Not Supported –
Activate Method Supported –
Revert Method Supported –
Revert SP Method Supported –
Activate Method Within Transactions Not Supported As per OPAL, this behavior is out of the scope
Revert Method within Transactions Not Supported As per OPAL, this behavior is out of the scope
Revert SP Method within Transactions Not Supported As per OPAL, this behavior is out of the scope
Creation/Deletion of Tables/Rows after Not Supported As per OPAL, this behavior is out of the scope
Manufacturing
Tper Feature
COM ID Management Support Not Supported Dynamic COM ID allocation & management not
supported
Buffer Management Support Not Supported Flow control

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TCG/Opal Support

Table 30: TCG/Opal Support Parameters (Continued)

Property Supported? Comments

ACK/NACK Support Not Supported Session reliability
Async Support Not Supported Asynchronous protocol support with multiple com-
mands per session
Geometry Reporting Feature
ALIGN Supported OPAL 2.0 (only)
Logical Block Size 512 bytes Logical block size = 512 Bytes
Alignment Granularity 4096 Bytes Page or Descriptor size <<Minimum AES LU size>>
Lowest Aligned LBA 0 –
OPAL SSC V2.00 Feature Descriptor
Base COM ID 0x1000 0x1000-0xFFFF defined for COM ID management
Number of COM IDs 1 –
Range Crossing Behavior 0 If drive receives a READ or WRITE command that
spans multiple LBA ranges and the LBA ranges are
not locked, then:
1. Process the data transfer, if Range Crossing = 0
2. Terminate the command with “Other Invalid
Command Parameter” if Range Crossing = 1
Number of Locking SP Admin Authorities 4 As per OPAL 2.0, drive should support at least 4 ad-
Supported min
Number of Locking SP User Authorities 16 As per OPAL 2.0, drive should support at least 8
Supported users
Initial C_PIN_SID PIN Indicator 0x00 0x00 = The initial C_PIN_SID PIN value is equal to
the C_PIN_MSID PIN value
0xFF = The initial C_PIN_SID PIN value is VU, and
MAY not be equal to the C_PIN_MSID PIN value
OPAL 2.0 (only)
Customer-specific SID – Configurable
Behavior of C_PIN_SID PIN upon Ter Revert 0x00 0x00 = The C_PIN_SID PIN value becomes the value
of the C_PIN_MSID PIN column after successful in-
vocation of revert on the admin SP’s object in the
SP table
0xFF = The C_PIN_SID PIN value changes to a VU
value after successful invocation of revert on the
admin SP’s object in the SP table and MAY not be
equal to the C_PIN_MSID PIN value OPAL 2.0 (only)
DataStore Table Feature
Maximum number of DataStore Tables 16 The maximum number of the DataStore tables that
the TPer supports, including the DataStore table
defined in OPAL SSC 2.0
Maximum total size of DataStore Tables 90MB Specifies the maximum total size in bytes of all of
the DataStore tables that TPer supports, including
the DataStore table defined in OPAL SSC 2.0
MBR Table 128MB –

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TCG/Opal Support

Table 30: TCG/Opal Support Parameters (Continued)

Property Supported? Comments

Byte Table Access Granularity
Mandatory Write Granularity 1 TPer enforces when the host invokes the set meth-
od on byte tables; it should be less than or equal to
8192; it should be less than or equal to Recommen-
ded Access Granularity, OPAL 2.0 (only)
Recommended Access Granularity 8192 Tper recommends when the host invokes the set or
get method on byte tables; it should be less than or
equal to 8192
Cryptographic Features
AES Key Size 256 Bits AES key is generated by using CTR DRBG algorithm
(FIPS Compliant)
AES Mode CBC IV swapped
Number of Ranges/Band Supported 16 Now supporting 15 LBA ranges; range cross read
(15 user definable, and write allowed if LBA ranges are unlocked
1 global range)
Re-Encryption Not Supported –
Key Management Cryptographic
Crypto Erase Completion Time <1s Yes –
Cryptographic Algorithms are Certified by No Designed to meet, no plans for certification
FIPS-197
AES 256-Bit CBC/ECB Mode Supported ECB mode used only for generating the random
key by CTR DRBG
CTR DRBG Supported –
SHA 256 Supported –
RSA 2048 Signature Verification Supported –
TPer Communication Properties
Max ComPacket Size 32256 in Byte
Max Response ComPacket Size 32256 in Byte
Max Packet Size 32236 in Byte
Max Individual Token Size 32200 in Byte
Max Packets 1 –
Max SubPackets 1 –
Max Sessions 1 Each session requires a set of buffers and variables
Max Transaction Limit 1 Transaction are inside sessions
Max Methods 1 Methods are contained in a transaction
Max Authentications 14 –
Def Session Timeout Yes The session timeout length (in milliseconds) used
by the TPer by default

IEEE1667
Probe Silo Supported –

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TCG/Opal Support

Table 30: TCG/Opal Support Parameters (Continued)

Property Supported? Comments

TCG Storage Silo Supported –
Other than Probe and TCG Storage Silo Not Supported –
IEEE1667 Major Version 2 -
IEEE1667 Minor Version 0 –
Maximum P_OUT Transfer Size 32768 256 sectors (128K)
Others
FDE (ATA Security with Key Management) Yes –
Secure Firmware Download Supported Firmware image is validated by using SHA256 and
RSA2048 algorithm

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PCI Header

PCI Header

Table 31: PCI Header Space Registers

End
Start Ad- Default
Address dress Symbols Register Definition Bits Type Value Description
00h 03h ID Identifiers 31:16 RO 6001h Device ID (DID)
0:15 RO 1344h Vendor ID (VID)
04h 05h CMD Command Register 15:11 RO 0 Reserved
10 RW 0 Interrupt Disable
9 RO 0 Fast Back-to-Back Enable
8 RW 0 SERR# Enable
7 RO 0 IDSEL Stepping/Wait Cycle Control
6 RW 0 Parity Error Response Enable
5 RO 0 VGA Palette Snooping Enable
4 RO 0 Memory Write and Invalidate Enable
3 RO 0 Special Cycle Enable
2 RW 0 Bus Master Enable
1 RW 0 Memory Space Enable
0 RW 0 I/O Space Enable
06h 07h STS Device Status 15 RW1 0 Detected Parity Error
C
14 RW1 0 Signaled System Error
C
13 RW1 0 Received Master Abort
C
12 RW1 0 Received Target Abort
C
11 RW1 0 Signaled Target Abort
C
10:9 RO 0 DEVSEL Timing
7 RO 0 Master Data Parity Error Detected
8 RW1 0 Fast Back-to-Back Transaction Capa-
C ble
6 RO 0 Reserved
5 RO 0 66MHz Capable
4 RO 0 Capabilities List
3 RO 0 Interrupt Status
2:1 RO 0 Reserved
0 RO 0 Reserved
08h 08h RID Revision ID 7:10 RO 0 Controller Hardware Revision ID

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PCI Header

Table 31: PCI Header Space Registers (Continued)

End
Start Ad- Default
Address dress Symbols Register Definition Bits Type Value Description
09h 0Bh CC Class Codes 23:16 RO 1h Base Class Code
15:8 RO 8h Sub Class Code
7:0 RO 2h Programming Interface
0Ch 0Ch CLS Cache Line Size 7:0 RO 0 N/A
0Dh 0Dh MLT Master Latency Timer 7:0 RO 0 N/A
0Eh 0Eh HTYPE Header Type 7 RO 0 Multi-Function Device
6:0 RO 0 Reserved
0Fh 0Fh BIST Built in Self Test 7:0 RO 0 Not Supported
10h 13h MLBAR Memory Register Base 31:14 RW 0 Base Address
(BAR0) Address (lower 32-bit) 13:4 RO 0 Reserved
3 RO 0 Pre-Fetchable
2:1 RO 2h Address Type (64-bit)
0 RO 0 Memory Space Indicator (MEMSI)
14h 17h MUBAR Memory Register Base 31:0 RO 0 Base Address
(BAR1) Address (upper 32-bit)
18h 1Bh IDBAR Index/Data Pair Register 31:0 RO 0 Not Supported
(BAR2) Base Address
1Ch 1Fh BAR3 BAR3 Register 31:0 RO 0 Reserved
20h 23h BAR4 BAR4 Register 31:0 RO 0 Vendor Specific
24h 27h BAR5 Vendor Specific BAR5 31:0 RO 0 Vendor Specific
28h 2Bh CCPTR CardBus CIS Pointer 31:0 RO 0 N/A
2Ch 2Fh SS Subsystem Identifiers 31:16 RO See ta- Subsystem ID (SSID)
ble be-
low
15:0 RO 1344h Subsystem Vendor ID (SSVID)
30h 33h EXPROM Expansion ROM Base Ad- 31:17 RW 0 Expansion ROM Base Address
dress 16:1 RO 0 Reserved
0 RW 0 Expansion ROM Enable/Disable
34h 34h CAP Capabilities Pointer 7:0 RO 0 N/A
35h 3Bh R Reserved
3Ch 3Dh INTR Interrupt Information 15:8 RO 01h Interrupt Pin
7:0 RW FFh Interrupt Line
3Eh 3Eh MGNT Minimum Grant 7:0 RO 0 N/A
3Fh 3Fh MLAT Maximum Latency 7:0 RO 0 N/A

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PCI Header

Table 32: Subsystem ID (SSID)

Package Density (GB) Value

BGA 64 0400h
128 0400h
256 0400h
512 1400h
1024 2400h
M.2 128 0100h
256 0100h
512 1100h
1024 2100h

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Package Physical Configuration

Package Physical Configuration

BGA Type 1620

Figure 5: BGA Type 1620 – 291-Ball 16mm x 20mm x 1.2mm (Package Code BL)

Seating plane

A 0.1 A

291X Ø0.51 ±0.05

Dimensions apply
to solder balls
post-reflow on Ball A1 ID Ball A1 ID
Ø0.50 SMD ball pads. (covered by SR)
18 16 14 12 10 8 6 4 2
17 15 13 11 9 7 5 3 1

A
B
C
D
E
F
G
H
J
K
L
17.6
M
CTR N
P
R
20 ±0.1 T
U
V
W
Y
AA
AB
0.8 TYP
AC

0.8 TYP 1.1 ±0.1

13.6 CTR 0.305 ±0.05

16 ±0.1
44X 0.45X0.45 square test pads.
Ni/Au plated on pitch.
No solder balls.

Notes: 1. All dimensions are in millimeters.

2. Ball diameter before soldering is 0.45mm. The solder ball composition is SAC405.
3. For optimal Solder Join Reliability (SJR) performance refer to CSN33 for recommended
PCB pad dimension to align to the SMD ball pad size of the package.

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Package Physical Configuration

Figure 6: BGA Type 1620 – 291-Ball 16mm x 20mm x 1.6mm (Package Code BM)

Seating plane

A 0.1 A

291X Ø0.510 ±0.05

Dimensions apply
to solder balls
post-reflow on Ball A1 ID Ball A1 ID
Ø0.50 SMD ball pads. (covered by SR)
18 16 14 12 10 8 6 4 2
17 15 13 11 9 7 5 3 1

A
B
C
D
E
F
G
H
J
K
L
17.6
M
CTR N
P
R
20 ±0.1 T
U
V
W
Y
AA
AB
0.8 TYP
AC

0.8 TYP 1.5 ±0.1

13.6 CTR 0.305 ±0.05

16 ±0.1
44X 0.45X0.45 square test pads.
Ni/Au plated on pitch.
No solder balls.

Notes: 1. All dimensions are in millimeters.

2. Ball diameter before soldering is 0.45mm. The solder ball composition is SAC405.
3. For optimal Solder Join Reliability (SJR) performance refer to CSN33 for recommended
PCB pad dimension to align to the SMD ball pad size of the package.

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Modules Physical Configuration

Modules Physical Configuration

M.2 Type 2230 (M-key)

Figure 7: M.2 Type 2230 Form Factor (Package Code BK)

Pin 1

W ±0.15

Pin 75

L ±0.15

A MAX
C MAX
B ±0.08

Note: 1. All dimensions are in millimeters.

Table 33: M.2 Type 2230 Form Factor Dimensions

Capacity Type W L A B C Unit

up to 512GB 2230 22.00 30.00 1.2 0.8 0.0 mm
1TB 2230 22.00 30.00 1.6 0.8 0.0 mm

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Compliance (M.2 only)

Compliance (M.2 only)

The SSDs into M.2 package comply with the following:
• Micron Green Standard
• CE (Europe): EN55032, EN55024 Class B, RoHS
• FCC: CFR Title 47, Part 15, Class B, CNS 15663
• UL/cUL: approval to UL-60950-1, 2nd Edition, IEC 60950-1:2005 (2nd Edition); EN
60950-1 (2006) + A11:2009+ A1:2010 + A12:2011 + A2:2013
• BSMI (Taiwan): approval to CNS 13438 Class B
• RCM (Australia, New Zealand): AS/NZS CISPR32 Class B
• KC RRL (Korea): approval to KN32 Class B, KN 35 Class B

• W.E.E.E.: Compliance with EU WEEE directive 2012/19/EC. Additional obligations

may apply to customers who place these products in the markets where WEEE is en-
forced.
• TUV (Germany): approval to IEC60950/EN60950
• VCCI (Japan): 2015-04 Class B

• IC (Canada): ICES-003 Class B

- This Class B digital apparatus complies with Canadian ICES-003.
- Cet appareil numérique de la classe B est conforme à la norme NMB-003 du Canada.
• Morocco: EN55032, EN55024 Class B

FCC Rules
This equipment has been tested and found to comply with the limits for a Class B digital
device, pursuant to part 15 of the FCC Rules. These limits are designed to provide rea-
sonable protection against harmful interference in a residential installation. This equip-
ment generates, uses, and can radiate radio frequency energy and, if not installed and
used in accordance with the instructions, may cause harmful interference to radio com-
munications. However, there is no guarantee that interference will not occur in a partic-
ular installation. If this equipment does cause harmful interference to radio or televi-
sion reception, which can be determined by turning the equipment off and on, the user
is encouraged to try to correct the interference by one or more of the following meas-
ures:
• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and the receiver.
• Connect the equipment into an outlet on a circuit different from that to which the re-
ceiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.

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References

References
• NVM Express, Revision 1.3
• PCI Express Base Specification, Revision 3.0
• PCI Express Electromechanical Specification, PCI EXpress M.2 Specification Revision
1.1
• PCI-SIG Engineering Change Notice: Power Loss Notification Functions (Mar. 26,
2018)
• PCI-SIG Engineering Change Notice: 1.8V sideband, Power Loss Notification, USB 2.0,
and higher power support (Nov. 28, 2018). To be considered for forward compatibility
• TCG Storage Architecture Core Specification Version 2.01 Revision 1.00
• TCG Storage Security Subsystem Class: Opal Specification Version 2.01 Revision 1.00
• TCG Storage Security Subsystem Class: Pyrite Specification Version 1.00 Revision 1.00
• IDEMA Standard LBA 1-03
• JEDEC Standard, Integrated Circuits Thermal Test Method Environmental Conditions
JESD51-2A
• For further information like technical notes and white papers on automotive and in-
dustrial Micron SSD, periodically check www.micron.com

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Revision History

Revision History
Rev. C - 05/20
• Updated Table: Operating Ratings
– Changed PWR_1 range for BGA
– Specified "Ambient" for "Rate of temperature change" and "Non-operating temper-
ature" for both BGA and M.2 form factor
• Updated Notes in Table: Maximum Current per Power Rail.
• Updated Table: BGA Signal Description. In-Band-Signals type are now specified if
they are Input (I) or Output (O); CLKREQ# type changed from Input/Output (I/O) to
Open Drain (OD)
• Added Table: Drive Performance With/Without HMB Enabled (SLC Mode=100%) –
Fresh Out of Box
• Minor editorial changes

Rev. B - 12/19
• Data Sheet maturity level changed from Preliminary to Production; Preliminary has
been removed on the top right corner of each page
• Added 64GB Micron Part Number for BGA package
• Updated Table: BGA Signal Description. Note no.6 include PWR_1 recommendation
for future SSD (from 3.3V to 2.5V)
• Updated Table: M.2 Signal Assignments. Added LED_1#, UART_RX and UART_TX
• MTTF updated to 3 million.
• Renamed Table: Maximum Ratings into Operating Ratings. Sensor temperature sym-
bol changed
• Removed Table: Drive Performance With/Without HMB Enabled – Steady State. The
server workload condition for performance calculation does not apply to 2100AI/AT
SSD.

Rev. A - 11/19
• Power domain for PLN#/PLA# is changed to 3.3V on BGA. Ensure design correctness
for your board schematics. For further information search for TN-FD-47 2100AI_AT
PCIe Schematics Reference Design Technical Note at http://www.micron.com
• Added a new table for BGA: Maximum Current per Power Rail.
• Updated Section: Identify Controller Data Structure.
• Updated Table: Maximum Ratings.
• Updated Section: Commands.
• Updated Section: Log Pages.
• Updated Section: TCG/Opal Support.
• Updated Section: Identify – Identify Namespace Data Structure.
• Added Section: PCI Header.
• Updated Table: Drive Performance With/Without HMB Enabled – Fresh Out of Box.
• Updated Table: Drive Performance With/Without HMB Enabled – Steady State.

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Revision History

Pre-Release 04/19
• All details subject to change

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000

www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.

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