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The Myth of the Harvard Architecture

Richard Pawson , Naked Objects Group Ltd, RG9 4LZ, Henley-on-Thames, U.K.

The label “Harvard architecture” has been applied to various computing devices
where instructions and data are stored in separate memories. In the Harvard Mark
III/IV the decision to separate the stores was motivated by a desire to optimize each
form of storage, not by Aiken’s oft-quoted antagonism toward “self-modifying code,”
which was anyway not justified even at the time, and would become a liability with
the emergence of operating systems. The term “Harvard architecture” was coined
decades later, in the context of microcontroller design, retrospectively applied to the
Harvard machines, and subsequently applied to RISC microprocessors with
separated caches. The so-called “Harvard” and “von Neumann” architectures are
often portrayed as a dichotomy, but the various devices labeled as the former have
far more in common with the latter than they do with each other.

T
he term “Harvard architecture” appears in many Every mainstream computer designed since 1945
college-level textbooks on computer architecture. stores instructions and data separately at some
For example, in Computer Architecture: A Quanti- point—ultimately in different registers within the
tative Approach, Hennessy and Patterson say this: processor. Within the historical contexts listed ear-
lier, instructions, and data were separated at some
The [Harvard] Mark-III and Mark-IV were being additional level, but both the nature and the motiva-
built after the first stored-program machines. tion of the further separation differed in each case.
Because they had separate memories for Encompassing these separate developments in a
instructions and data, the machines were single term encourages misleading generalizations,
regarded as reactionary by the advocates of such as this:
stored-program computers. The term Harvard
architecture was coined to describe this type of the Harvard architecture . . . allows the CPU to
machine. Though clearly different from the access instruction and data simultaneously [37].
original sense, this term is used today to apply to That was true of the two later developments (micro-
machines with a single main memory but with controllers and RISC processors), but not for any
separate instruction and data caches [21]. Harvard machine.
This is a sound explanation that avoids mistakes In Essentials of Computer Architecture [10], Comer
made in some other sources, cited later. As it sug- positions the “Harvard architecture” as an alternative to
gests, the term “Harvard architecture” has more than the “von Neumann architecture. ” While there is much
one meaning. The term itself was not coined until the dispute both about the exact scope and definition of
1970s in the context of designing the first microcon- the latter and how much of it is legitimately attributed
troller (complete computing device on a single chip) to John von Neumann, few dispute that the primary
and it was only retrospectively applied to the “Harvard source, The First Draft of a Report on the EDVAC [40]
machines”—designed by or for the Harvard Comput- (the “First Draft”) embodies—in today’s terms—an
ing Laboratory (HCL), under the leadership of Howard “architecture” [2], [13]. No definition of the “Harvard
Aiken. Later, it was applied again to RISC processors architecture” provides an equivalent basis to the First
that cached instructions and data separately. Draft for designing a computer. The various historical
developments labeled as “Harvard architecture” have
each resulted in a single design choice that may be
adopted within the von Neumann architecture. The Har-
vard Mark III and IV adopted all the design principles of
1058-6180 ß 2022 IEEE
the latter bar two: representing numbers in binary and
Digital Object Identifier 10.1109/MAHC.2022.3175612
Date of publication 20 May 2022; date of current version 27 treating memory as a flexible resource for storing all
August 2022. forms of data and instructions. And while most modern

July-September 2022 Published by the IEEE Computer Society IEEE Annals of the History of Computing 59
ARTICLE

machines still owe much to the First Draft, none since to diminish Aiken’s reputation for these achievements
the 1950s has followed it in every respect. Only the most one iota, simply to put paid to the persistent myth of
recent interpretation of “Harvard architecture”—storing Aiken the architectural prophet without honor in his
instructions and data in a common memory but caching own time. His concern about program immutability
them separately within the processor—is applicable to was not justified even at the time, and his pattern of
modern general-purpose computing. storing instructions in nonwritable memory would
This terminology might be sloppy, but what rele- prove unworkable with the later introduction of oper-
vance does it have to the formal history of computing? ating systems.
It has encouraged a myth that Aiken invented an Since the “Harvard architecture” has been con-
architecture superior to that commonly attributed to trasted to the “von Neumann architecture,” we start
von Neumann, but that this superiority was not recog- by looking at the meaning of the latter term, identify-
nized until many decades later. Two individuals, who ing the 10 key design principles that it embodies. The
worked with Aiken at the HCL, Peter Calingaert, and Harvard machines are then evaluated against the prin-
Grace Hopper, have implied this: ciples. The article then explores the emergence of the
term “Harvard architecture” during the invention of
Today’s prevailing wisdom praises the separate
the microcontroller, and its subsequent reinterpreta-
storage of instructions and data as the
tion in the context of RISC microprocessors, before
Harvard architecture [4].
concluding with the relevance of this discussion to
the present day.
Aiken always insisted that the data and the
program must be stored independently. We lost
that concept for a while when people came “VON NEUMANN ARCHITECTURE”
along and said “Oh, we want to store the
The validity of the term “von Neumann architecture”
program in the same memory as numbers so
has been widely questioned [17]. It is being used here
that we can alter the program.” . . . In my
only because the term “Harvard architecture” is often
opinion, that put more bugs in programs than
explicitly contrasted to it. There is also no consensus
anything else ever did [24].
on the exact meaning of the former, except that it
Others have amplified these assertions, for emanates from work initiated by the team that
example: designed the ENIAC plus new contributors, including
John von Neumann, to design a successor machine
In hindsight, with knowledge of the
that—even before the ENIAC was running—would use
proliferation of von Neumann architecture-
new technologies and new design principles to over-
enabled security threats, there is reason to
come what were already perceived as limitations of
wonder whether the entire information
the ENIAC’s design. Although, even before any new
technology industry would not have been vastly
machine had been built to use the new ideas, the
better off had there been early agreement to
ENIAC itself was substantially modified to adopt many
embrace the Harvard architecture and its
of them [18].
complete separation of code and data memory
This article reuses a framework set out by
regions, despite the costs involved [29].
Haigh et al. [17], which groups design principles drawn
In this myth, the Harvard and von Neumann archi- from the First Draft under three headings: the “EDVAC
tectures are cast in roles broadly equivalent to Beta- Hardware paradigm,” the “von Neumann architectural
max and VHS in the story of video-tape format paradigm,” and the “Modern Programming Paradigm.”
competition [11], the populist version of which holds The number and wording of the principles listed under
that the earlier-and-superior technology—Betamax— those three headings, given in the following, vary
was eclipsed by the later-and-inferior, but better-mar- slightly from their version, but principally for brevity,
keted, technology—VHS. not to favor any argument being advanced herein. In
Howard Aiken is rightly recognized as a pioneer in designing a computing machine, each of the principles
automated computing: his vision and drive led to the listed in the following could be adopted independently
creation of one of the first large-scale automated of the others—indeed the authors of that framework
computers, completed and applied to real work before have shown that while some were evident in the first
the end of WWII. He also initiated the first comprehen- discussions of the EDVAC, others took time to be
sive postgraduate program in what we today call agreed. For later reference within this article, the prin-
“computer science.” It is not the intent of this article ciples have been numbered: #1 to #10.

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EDVAC HARDWARE PARADIGM be applied for days at a time to a single problem, but
#1 Large addressable read/write memory: Initially would tackle many different problems within one day.
enabled by Eckert’s design for a “delay line store” Therefore, it should be possible to read the program
(derived from the Mercury delay lines used in radar rapidly into memory from some external medium. This
systems) and stretched by von Neumann’s vision that principle is not explicit in the (incomplete) First Draft,
the computer should be applied to different kinds of which does not cover input/output, but was clearly a
mathematical modeling that were far more data-inten- part of the thinking.
sive, the planned EDVAC design would advance the
requirement from tens of numbers stored in working MODERN PROGRAMMING
(writable) memory, to thousands. PARADIGM
#2 Binary number representation: Where the ENIAC #8 Sequential atomic instructions: Programming the
and other early computing devices had stored and proc- ENIAC involved physically configuring the operation of
essed numbers in decimal format, the natural represen- each accumulator and their interconnection, through
tation for the users of the machine, the EDVAC used
plugboards and switches. Thought had been given to
binary, which, to achieve the same precision, was about allowing this physical configuration to be specified “in
25% more efficient in storage, and made for simpler software” (to use a modern term), but by the time of
arithmetical circuits. This gain was felt to outweigh the the First Draft, the concept of a program (as we now
cost of the additional circuits and/or software needed call it) had changed to mean the specification of sepa-
to convert from/to decimal for input and output. rate, atomic, instructions to be processed in a sequence.
#9 Automated jumps: This was probably meant to
VON NEUMANN ARCHITECTURE contrast with paper tape run machines, which had no
PARADIGM automated branching.
#10 Instructions operating on variable addresses:
#3 Separate organs for storage, arithmetic, and control:
The First Draft indicated that it should be possible to
The ENIAC had been built around 20 “accumulators,”
vary the address part of an instruction. One need for
each combining working storage (for one number) with
that was to apply the same code to different data ele-
arithmetic and control circuits. Scaling up the memory
ments successively, which von Neumann demon-
by at least two orders of magnitude meant that it would
strated in his first program [27]. It would also support
not be feasible to repeat this pattern.
subroutines, which upon completion needed to return
#4 Special purpose registers: Inside the processor,
execution to the instruction after the one that had
there would be a few fast storage units, known as regis-
called the subroutine [41]. These requirements can be
ters, each with a dedicated purpose—such as the accu-
realized in different ways: by modifying the address
mulator, instruction register, and program counter (PC)—
portion of an instruction stored in the program mem-
hardwired to different arithmetic and/or control circuits.
ory (the initial idea); by modifying a copy of the instruc-
#5 The program executed from fast memory: Pro-
tion held in a register (von Neumann himself later
gram instructions should be held in numbered mem-
proposed this); or by defining an instruction that reads
ory locations, randomly accessible at high speed.
its address from one or more specialized registers.
(Note that this may be adopted independently from
The third option—which includes what is now known
the next principle.)
as indexed or indirect addressing—was implemented
#6 Fully interchangeable memory: von Neumann’s
by others even before the first machine to adopt the
wording of this principle in the First Draft is surpris-
EDVAC blueprint, for example, in the Manchester
ingly tentative, stating that it is:
Mark I [28]. It is misleading to equate this principle
. . .tempting to treat the entire memory as one with the idea of “self-modifying code,” not only
organ, and to have its parts even as because of the alternative ways in which it could be
interchangeable as possible. [40, Sec. 2.5] implemented but because even the initial idea did not
permit instructions to overwrite other instructions—
In the paragraphs preceding this comment, he had
only the address portion of those instructions.
been talking about the multiple differing needs for data
storage in a program run, so he was making a tentative
case for treating all memory units as interchangeable, HARVARD MACHINES
not just the storage of data and instructions. We can now evaluate the design of the Harvard
#7 Program loadable from external media: von machines against the 10 principles. The results are
Neumann foresaw that future computers would not summarized in Table 1, with more details to follow for

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TABLE 1. Harvard machines evaluated against 10 design principles evident in the First Draft.

each machine. (For comparison, the table also shows rotating counters with 48 faster-operating registers
the original ENIAC, the modified ENIAC, and the built from relays, but stripped of their addition/sub-
EDSAC—the first machine explicitly designed to fol- traction functionality. The latter was now imple-
low the proposed EDVAC design.) mented in a centralized relay-based logic unit. So,
whether consciously or not, Mark II had adopted prin-
ciple #3.
MARK I AND MARK II
The design of the Harvard Mark I [1], [5], [14], originally
known as the Automatic Sequence Controlled Calcu- MARK III AND MARK IV
lator, preceded the conception of the EDVAC and the In the Mark III [16], [30] all logic was implemented
ENIAC. Nonetheless, the Mark I can be said to have using vacuum tube electronics and working data were
anticipated principle #8 because it was programmed stored on eight magnetic drums: two “fast” and six
by defining a sequence of instructions, captured on “slow.” Only the fast ones were directly addressable by
24-channel paper tape. Grace Hopper would later the instruction logic: data could be bulk transferred
argue in [24] that between the fast and slow drums. (While this article
argues that Aiken’s splitting of instruction and data
. . .because it was sequentially programmed . . .
stores was of little lasting significance, he is arguably
Mark I clearly resembled more closely [than the
not given enough credit for pioneering the splitting of
ENIAC] what we have today.
the data store into what we now call “primary” and
Instructions were read and executed one at a time “secondary” online storage.)
in strict sequence; there were no machine-controlled The later Mark IV replaced the “fast” drums with what
jumps, conditional or unconditional, though by 1946 a was referred to at the time as “magnetic delay lines,” but
limited form of what we would today call a “condi- could perhaps be more clearly described as “magnetic
tional expression” had been added. Subroutines core shift registers”: a solid-state electromagnetic form of
involved halting the machine at a defined point and memory, working somewhat like the later “ core memory,”
manually repositioning or switching paper tapes. but with serial rather than random access.
The core of the machine comprised 72 rotating In both the Mark III and IV, instructions were also
mechanical counters, each representing a 23-digit held on magnetic drum memory, thus permitting fast
signed decimal number, and each capable of perform- jumps between instructions. However, in both machines,
ing addition and subtraction. Centralized relay-based the storage of instructions and data was physically sepa-
logic circuits added multiplication and division, as well rated—each element of memory storage was perma-
as the ability to interpolate between successive values nently dedicated either to data or to instructions.
in a “function table”—either one built into the machine Instruction memory could be loaded from external media
or specified as arbitrary function tables on three before a run commenced but could not be written to by
24-channel paper tape readers. other instructions.
The Mark II [6], [15], [25] broadly followed the archi- The Mark III and IV both, therefore, implemented
tecture of the Mark I, replacing the mechanical all the design principles of the EDVAC identified

62 IEEE Annals of the History of Computing July-September 2022

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earlier, with the exception that they stayed with deci- instructions, such as multiply, that had their own dedi-
mal representation and did not store instructions and cated circuits. Mark III’s processing cycle (approx. 4.3
data in common memory space. milliseconds) generally commenced with reading the
next instruction, before (in most cases) going on to
read and write data.
AIKEN’s RATIONALE FOR KEEPING The most likely explanation for the split memories
THE STORES SEPARATE is simply that it allowed the design of the two stores
Given that the Mark III was designed from scratch, to be optimized to the different characteristics—both
that the design did not start until well after the First static and dynamic—of data and instructions. Think-
Draft had been widely circulated, and that it clearly ing of instructions and data as entirely separate things
adopted many principles from the First Draft, it seems had begun with the Mark I. Ceruzzi states:
likely that the idea of fully interchangeable memory
That the [instruction and data tape] units were
was consciously rejected.
physically identical suggests that the Mark I’s
It is well documented that Aiken abhorred the idea
designers might have recognized that in some
of altering code at runtime. In addition to the sources
sense numbers and operations are equivalent.
cited earlier, Fred Brooks recalls that Aiken was
Probably they did not [7].
. . .so adamant about protecting proven
Supporting that argument is the fact that one of
program code that after he had recorded
Mark I’s three data tape readers was subsequently
instructions on the drum on the Mark IV he
converted into a second instruction tape reader to
unplugged the write circuits [3].
facilitate switching between tapes, but there does not
This was almost certainly pure showmanship by appear to have been the idea to make the tape units
Aiken because none of the Harvard machines had dynamically interchangeable.
instructions that could write to the instruction store, By the time of the Mark III, Aiken would have
so unplugging the write circuits after loading the pro- been aware of the proposal to treat data and
gram would have made no difference. instructions at least somewhat interchangeably, but
However, we do not have clear evidence that Aiken he probably still saw greater advantages in keeping
held these strong views at the time the Mark III was them separate. Even von Neumann’s tentative sug-
being designed (commencing January 1948). Indeed, it gestion of interchangeable memory in the First Draft
seems unlikely given that at that time no one yet had (quoted earlier) had been preceded by the
practical experience of running programs where the counterargument:
instructions were being modified at runtime. Further-
While it appeared that various parts of this
more, the Mark III would implement the principle of
memory have to perform functions which differ
“Instructions operating on variable addresses” (#10)
somewhat in their nature and considerably in
via specialized registers: a “delta” register for indexed
their purpose. . . [40 Sec. 2.5].
addressing, and a register to store the previous value
of the “line number” (program counter) for returning The strongest evidence for this claim lies in Mark
from subroutines. So, there would have been no III’s specifications for the instruction and data drums.
need—identified at that time—to modify instructions While all drums use the same recording technology,
on the fly on the Mark III. every other aspect of the specifications is different
Aiken’s fear of the consequences was, arguably, (see Table 2).
misplaced. For though it is true that the nonwritable Aiken’s preferred representation of numbers (16-digit
(at runtime) instruction store prevented corruption decimal, each digit encoded to 4 bits, using an unusual
of code, having variable addressing implemented via representation [16, p. 8]), and of instructions (a 38-bit for-
registers does not reduce the likelihood of acciden- mat that facilitated the design of a radical and effective
tal corruption to data, as any programmer who has keyboard, closely matching the instruction semantics, to
ever made an “off by one error” in their indexing will punch the tape) were very different. To implement a sin-
testify. gle shared store would have required the adoption of a
Another possible argument for the separated larger address range (pushing up the number of bits
stores and access circuits is that it could permit the needed for each of the three addresses in the instruction
next instruction to be read while the current one is format), as well as a fixed word-length for both data and
being decoded and/or executed. However, this was instructions. Nor would it have been possible to load the
not possible on any Harvard machine—except for whole instruction in parallel, while loading the data

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TABLE 2. Summary of the drum memory specifications on slow-speed data stores onto a single drum. However,
the Harvard Mark III. they were still allocated physically separate channels,
accessed via separate circuits.
Instruction “Fast” data “Slow” data
store storage storage
No. of 1 2 6
END OF THE HARVARD MACHINES
drums The Mark IV was the last of the Harvard machines.
Drum 16 inches 8 inches 8 inches
With the emergence of commercially manufactured
diameter computers, military funding for expensive one off com-
puting machines was less available. In 1956, the HCL
Rotation 1725 RPM 6900 RPM 6900 RPM
speed installed a UNIVAC I [8], the first commercially pro-
duced electronic computer—a gift from Remington
Pulse 20 per inch 10 per inch 10 per inch
Rand.1 We can only imagine Aiken’s reaction to the
density
fact that this machine relied on modifying instructions
Parallel 152 x 1 bit 36 x 4 bit in 400 x 4 bit in in situ to implement subroutines [36].
channels total total
Another factor in the demise may have been, as
Bits per 28,776 28,903 28,903 Calingaert recalls in [4], that Aiken kept the HCL team
second
largely isolated from developments elsewhere. This
(per
channel) isolation cuts both ways: in the words of Aiken’s biog-
rapher, friend, and colleague at Harvard, I. Bernard
38-bit 16-digit, 16-digit,
Cohen, Aiken’s machines had little influence on the
instruction signed signed
accessed in decimal decimal main line of the rapidly developing design of com-
parallel format format puters [9].
Format
across 38 accessed accessed Had the HCL continued to develop its own range of
channels serially from serially from machines, Aiken’s insistence that program code should
a (4 bit) a (4 bit)
be immutable would have proven to be a huge liability
channel channel
with the emergence of operating systems. In the era of
4000 200 working 4000
instructions numbers þ numbers the Harvard machines, the user had been in complete
10 charge of a machine. If their program contained errors,
configurable these could impact only that user’s run; the machine
Capacity
constants þ would then be reset, and control of the machine passed
150
to the next user. Batch processing changed that, to be
permanent
constants followed later by time-sharing [42]. Both relied on a
“supervisor” program, responsible for loading, running,
and unloading the user program and data, and for inter-
serially by decimal digit and parallel within each digit, vening to cancel a program that failed to terminate
which suited his decimal processing circuits. within a time limit or attempted an illegal action. The
From this starting point, it seems likely that the supervisor program had to be able to write instructions
design of Mark III’s two stores proceeded indepen- into memory that would then be executed.
dently. Ultimately, successive instructions had to be With the new need, however, came new forms of
recorded 125 rows apart on the drum, to put the next protection against corruption—accidental or inten-
instruction close to where the read head would be by tional—by the user programs. A hardware mechanism
the end of the processing cycle. And while the eight limited the memory address range accessible to a
data storage drums were all driven from a single motor user program, with the supervisor running in a privi-
via a gearbox (the Mark III must surely be the only leged mode that gave it access to the full memory.
computer where the operator panel included a “Gear- Neither the Harvard machines nor the EDVAC
box low oil pressure” warning light), the instruction design—at least had it followed von Neumann’s idea
drum was driven by its own motor—a far from an opti- that only the address portion of an instruction could
mal arrangement that required sophisticated elec- be overwritten—could have made the transition to
tronic speed control circuitry to keep the instruction this new world of supervisory programs or operating
and data drums in synch. Unsurprisingly, the Mark
IV—having moved the high-speed data memory to 1
Based on an email to the author from Peter Calingaert, who
solid-state technology—merged the instruction and worked in the HCL at that time.

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FIGURE 1. In the early microcontrollers, the processor’s PC was hard-wired to the address inputs to the ROM, and the data out-
put from the ROM was hard-wired to the IR. This specific design was the first use of the term “Harvard architecture.”

systems. The difference is that the EDVAC design address and data bus, but the ROM is hardwired to
could evolve without anyone having to recant a the PC and the instruction register (IR)—see Figure 1.
strongly espoused principle of doctrine. The main motivations for this new arrangement in
The final irony is that while Aiken might have been microcontrollers were simplicity (it needed less multi-
gratified to learn that—50 years after his death—dynamic plexing on the buses), which translated into lower
mutation of code is typically prevented (in user pro- cost, and that the ROM and RAM could have different
grams), he would surely have been astonished to learn data widths and different addresses widths. TI’s first
that an increasing number of computer scientists, espe- microcontroller, for example, had 1024  8 bits of
cially those favoring functional programming languages, ROM and 64  4 bits of RAM.
now advocate the runtime immutability of data [20]. This new configuration also meant that fetching an
instruction could overlap with reading or writing data.
As soon as the value in the PC is incremented, or over-
COINING OF “HARVARD written (for a jump), the next instruction automatically
ARCHITECTURE” IN THE FIRST appears on the input to the IR—without having to
MICROCONTROLLERS wait for the current instruction to finish using the
The term “Harvard architecture” did not exist in the address/data buses for accessing data. The next clock
era of the Harvard machines. Even the word ‘‘architec- pulse merely latches the instruction into the IR.
ture” was not applied to the context of computing The new arrangement was not designed to prevent
until the early 1960s [19]. References may be found to writing to the program store: it was dependent on the
the ‘‘Harvard class” (of computers) [23], or to the lack of need for it. And it was suited only to microcon-
‘‘Aiken architecture” [39] in the 1970s, though the trollers because it depended upon either the ROM or
meaning given to these terms is not consistent. The RAM (or both) being on the same chip as the proces-
term ‘‘Harvard architecture” does not appear in print sor: there was not enough space at the edge of a chip
until 1982 [26]—and it was given a specific meaning to permit two data buses plus two address buses to
that would not have applied to the Harvard machines. be exposed as “tabs,” and hence as pins on the pack-
In 1971, the same year that Intel had announced age. (Chip and package sizes have increased over
the first 4-bit microprocessor, Texas Instruments (TI) time, but so have an address and data bus widths.)
had developed the first complete computing device This arrangement became known as the “Harvard
on a single chip: microprocessor, memory, and I/O. architecture.” When the term was coined is unclear2
These devices eventually became known as ‘‘micro- but the 1982 publication [26] clearly implies that the
controllers”; they were used in embedded applications term had been in use within the microcontroller
such as industrial controllers, domestic appliances, design community for some time. The name is widely
calculators, and electronic toys. Instructions and data assumed to be a nod to the Harvard machines but, if
were stored in separate memories. This was not a
design choice: it was dictated by requirements. For
2
most embedded applications, the program had to be The author believes that the term was most likely coined by
persistent, and the device had to boot up automati- Gary Boone, or by one of his team, at TI working on single-
chip microcomputing devices in the early 1970s. The author
cally from power-ON, so instructions were stored in managed to locate one surviving member of that original
ROM, while variable data had to be stored in the (typi- team, Charles Brixey, in April 2021, who recalled that the term
cally smaller) RAM. However, this starting point sug- “Harvard architecture” was in use within the team from early
on, but did not know its origin. Surendar Magar (see [28]),
gested a new possibility for connecting the on-chip who later worked closely with that team, gave a similar
components, where the RAM is connected to an recollection.

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so, the connection is tenuous at best. Where the Har-

vard Mark III/IV had separated the stores by choice,
on the microcontrollers it was not a choice. And the
only beneficial side effect gained from the split that
microcontrollers had in common with the Harvard
machines, was the possibility of different address and
word sizes for instructions and data. It is quite possi-
ble that whoever coined the term wrongly believed FIGURE 2. In the 1990s, the term “Harvard architecture”
that the Mark III/IV designs had also enabled overlap- appeared again, to describe processors that cache both
ping instruction and data fetches. Possibly they just instructions and data, but separately.
wanted a name for the new pattern, and “Harvard
architecture” offered a certain cachet.
By 1982, it was already being argued that advances
in silicon manufacture made the shared memory example, unlike the data cache, the instruction cache
address space—as used on most microprocessors—a does not have to worry about instructions becoming
valid option for microcontrollers [26]. However, the “stale,” because the instructions do not change
“Harvard architecture”—as defined for microcontrol- dynamically (the latter was enforced by the memory
lers—would continue to be used in some digital signal management unit). It would also permit simultaneous
processor chips, a specialized development from the instruction and data fetch, provided that the fetch
original microcontrollers, where the speed advantage was from the cache.
carries a greater significance [31]. It has also been The actual performance gain attributable specifi-
used in several more recent “retro-computing” proj- cally to splitting the caches was quite small compared
ects where the aim is to build a complete computer to that delivered by caching in general. The evolution
from scratch using only technology that existed of the ARM—the family of RISC processors found in
before the first microprocessors.3 most mobile phones—provides a benchmark [12, pp.
269–283]. In the ARM1 there was no separation of
instructions and data; “pipelining” (overlapping of
instruction and data fetches) was achieved by a differ-
SPLIT CACHES IN RISC ent mechanism. Caching was introduced with ARM3.
MICROPROCESSORS The simulation had shown that a “perfect” caching
The third historical context to which the term “Harvard mechanism (one where every item happens to be in
architecture” is now commonly attached is the emer- the cache when it is needed) would deliver a 1.13 per-
gence of a new generation of microprocessors arising formance improvement if data were cached, a 1.95
from three research projects in the early 1980s—the improvement if instructions were cached, and a 2.5
IBM 801 minicomputer [35], the MIPS project at Stan- improvement if both data and instructions were
ford [22], and the Reduced Instruction Set Computing cached. As implemented in ARM3, a single on-chip
(RISC) project at Berkeley [33]—for which RISC , would cache was used for both data and instructions, and
later become the generic name. “Harvard architecture” the measured performance improvement came sur-
does not appear in any of the original research project prisingly close to the perfect ideal. The ratio of cached
reports, but external commentators had started to add instructions to data was not fixed: it would vary
this label by the late 1980s [34] and it was being used in dynamically during operation.
product documentation by 1990 [32]. The StrongARM CPU [12, pp. 327–335] developed by
Although various approaches to splitting instruc- Digital Equipment Corporation and derived from extant
tions from data were explored in these projects, the ARM designs, was the first to feature separate caches
one that stuck was to keep them together in the main for instructions and data, and this pattern was subse-
memory, but cache them separately within the proces- quently adopted in the ARM9 and most subsequent
sor (see Figure 2). One motivation for that split was implementations. The ARM9 got close to the ideal nett
that from the perspective of caching, the characteris- throughput of one instruction per clock cycle, but prior
tics of the two things were different, allowing the hard- versions of ARM were already delivering better than
ware cache logic to be optimized for each. For 80% of this goal by other means. So, the gain from split-
ting the cache was at most 1.25, and probably rather
3 less since it was introduced at the same time as multi-
One of the best-known of these is the Gigatron: htt_ps://
gigatron.io/ ple other performance-enhancing tweaks.

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 ARTICLE

TABLE 3. Summary of the three distinct meanings of the term “Harvard Architecture” in relation to three historical
developments.

Period Devices Design Possible benefits Limitations Applicability

Late Harvard Mark Physically separate - Optimization of each - Program loaded Not viable for
1940s to III/IV instruction and data store design to manually modern
early stores characteristics of - Memory allocation computing
1950s instructions or data fixed
1970s Microcontrollers Instructions in ROM, - Simpler design - Program must be Embedded
onward and Digital Signal hardwired to - Supports different word/ in ROM computing
Processors Program Counter address sizes -ROM or RAM must applications
and Instruction - Instruction/data fetches be small enough to only
Register in parallel be on-chip
1990s Microprocessors Instructions and - Modest gain in General
onwards with split on-chip data held in performance though cache purpose
caches common RAM, but design optimisation, and by computing
cached separately permitting instruction/data
on the processor fetches in parallel (when
from cache)

This split-cache design is, today, the most widely of which were not recognized until after his passing,
used meaning for the term “Harvard architecture.” It is the continuing use of the term “Harvard architecture”
sometimes labeled as “modified Harvard architecture,” reinforces the idea that there is a dichotomy between
though that term had been coined back in 1982, with a that and the “von Neumann architecture.’’ The author
different meaning.4 has seen the negative consequences of this in an edu-
cational context, where students come away with the
impression that modern computers are either “von
CONCLUSION Neumann’’ or “Harvard.” One question in a high-school
The three historical developments that have been computer science exam set by a public exam board
labeled as “Harvard architecture” are summarized in asked for advice to be made to a business whose sys-
Table 3. All adopted most of the principles associated tems were running too slowly. Included in the official
with the term “von Neumann architecture,” including Mark Scheme’s examples of creditable points that
the fact that they ultimately stored instructions and might be made in the short-essay response, alongside
data in dedicated registers. All three additionally split such valid points as “replace HDDs with SSDs” and
instructions and data earlier in the process, but in dif- “install more RAM,” was “use the Harvard architec-
ferent ways, to achieve different benefits, and with dif- ture.” The exam board’s decision to cite such a sug-
ferent limitations. gestion as valid is perhaps understandable when an
Only the third development is relevant to modern otherwise respectable textbook implies that Harvard
general-purpose computing because it is the only one versus von Neumann is just another buyer’s choice,
that will work with an operating system. The perfor- such as Linux or Windows:
mance advantage (relative to having a unified cache
for data and instructions) is modest. And it would be The chief disadvantage [of the Harvard
more accurately described as a “modified von Neu- architecture] arises from inflexibility: when
mann architecture” than a “modified Harvard architec- purchasing a computer, an owner must choose
ture.” In short, it is not architecture, and it did not the size of the instruction memory and the size
derive from work at Harvard. of data memory. Once the computer has been
As well as perpetuating the myth that Howard purchased, an owner cannot use part of the
Aiken developed a better architecture, the advantages instruction memory to store data nor can he or
she use part of the data memory to store
programs [10].
4
Surendar Magar had used the term “modified Harvard archi-
tecture” in his 1982 patent application, [28] where it referred
Research for this article stopped short of asking
to the fact that the processor could load instructions from
the data memory for debugging purposes. for such a machine at the local computer store.

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ARTICLE

ACKNOWLEDGMENTS [9] I. B. Cohen, “Howard Aiken and the dawn of the

computer age,” in The First Computers, History and
The author would like to thank many people who pro-
Architectures, R. Rojas and U. Hashagen Eds.,
vided help to the author in the form of pointers to use-
Cambridge, MA, USA: MIT Press, 2002, pp. 107–120.
ful sources, personal recollections, feedback on early
[10] D. Comer, Essentials of Computer Architecture.
ideas or drafts, or patient explanations of complex
London, U.K.: Chapman & Hall, 2017, pp. 70–71.
technical ideas. Notwithstanding which, the author
[11] M. Cusumano, Y. Mylonadis, and R. S. Rosenbloom,
takes full responsibility for any remaining errors or
“Strategic maneuvering and mass-market dynamics:
misunderstandings. Nor does inclusion in these
The triumph of VHS over beta,” Bus. Hist. Rev., vol. 66,
acknowledgements imply endorsement for any argu-
no. 1, pp. 51–94, Mar. 1992.
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to (in alphabetical order): Penny Ahlstrand, Walter
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Belgers, Gordon Bell, Charles Brixey, Fred Brooks,
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Peter Calingaert, Martin Campbell-Kelly, Paul Ceruzzi,
Neumann planned it,” IEEE Ann. Hist. Comput., vol. 15,
Steve Furber, Steve Golson, Tom Haigh, John Hen-
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