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Junction Temperature Extraction Approach with Turn-Off Delay Time for

High-Voltage High-Power IGBT Modules

Article  in  IEEE Transactions on Power Electronics · January 2015

DOI: 10.1109/TPEL.2015.2481465

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5122 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 7, JULY 2016

Junction Temperature Extraction Approach

With Turn-Off Delay Time for High-Voltage
High-Power IGBT Modules
Haoze Luo, Yuxiang Chen, Pengfei Sun, Wuhua Li, Member, IEEE, and Xiangning He, Fellow, IEEE

Abstract—Thermo-sensitive electrical parameter (TSEP) ap- junction and case temperature fluctuations may deteriorate the
proaches are widely employed in the junction temperature ex- electrical specifications, such as resulting in higher leakage cur-
traction and prediction of power semiconductor devices. In this rents and smaller safe operation areas, etc. Since the enclosed
paper, the turn-off delay time is explored as an indicator of a TSEP
to extract the junction temperature from high-power insulated semiconductor packaging consists of several materials with dif-
gate bipolar transistor (IGBT) modules. The parasitic inductor ferent thermal expansion coefficients, power and thermal cy-
Le E between the Kelvin and power emitter terminals of an IGBT cling under complex working conditions can lead to different
module is utilized to extract the turn-off delay time. Furthermore, degrees of thermo-mechanical failure.
the monotonic dependence between the junction temperature and Consequently, the junction temperature monitoring is a key
turn-off delay time is investigated. The beginning and end point
of the turn-off delay time can be determined by monitoring the factor in failure mechanism analysis and lifetime prediction of
induced voltage ve E across the inductor Le E . A dynamic switch- IGBT modules. Junction temperature monitoring provides an
ing characteristic test platform for high-power IGBT modules is efficient way to realize active thermal control for high-power
used to experimentally verify the theoretical analysis. The experi- converters, hence is a potential approach to strengthen sys-
mental results show that the dependency between IGBT junction
tem reliability [9], [10]. Consequently online junction tempera-
temperature and turn-off delay time is near linear. It is established
that the turn-off delay time is a viable TSEP with good linearity, ture detection methods have aroused interest from both device
fixed sensitivity, and offers nondestruction on-line IGBT junction manufacturers and users. Existing IGBT junction temperature
temperature extraction. measurement approaches can be categorized into the optical-
Index Terms—High-power insulated gate bipolar transistors based, physical contact-based, and thermo-sensitive electrical
(IGBTs), online junction temperature extraction, thermo-sensitive parameter (TSEP)-based solutions [11]–[13]. An infrared cam-
electrical parameter, turn-off delay time. era is representative of an optical-based method, but is expensive
and restricted in practical applications [14]. The thermocouple
I. INTRODUCTION and build-in thermistor are the typical physical contact-based
methods, examples, and are cost-effective and widely applied
ITH high switching speeds, low conduction losses, and
W high over-current capacity, high-power IGBT modules
are widely employed in voltage-source-converter-based high-
in industrial applications. But their dynamic response are rela-
tively slow, thus, cannot detect the dynamic junction temperature
fluctuations. It is, therefore, concluded that a TSEP extraction
voltage direct current transmission, megawatt-level renewable method affords the most promising and feasible way to attain fast
energy generation plants, and high-speed traction systems [1], temperature measurement from high-power IGBT modules [11].
[2]. As a core component in the high-power conversion systems, By using the die itself as a thermal sensor, the TSEP method
high-power IGBT module reliability is an important issue in the can establish correspondence between the external observable
power electronics applications [3], [4]. Research has shown that electrical parameters and junction temperature. This makes it
31% of power electronic conversion system breakdowns are at- possible for the online IGBT module junction temperature mon-
tributable to the power device failure, and nearly 60% of device itoring. In the literature, the common TSEPs are divided into the
failures are thermally induced [5]. In addition, failure rate dou- static parameters and dynamic parameters [9]. Static TSEPs are
bles for every 10 °C junction temperature increase [6]. It has defined as the parameters extracted during the onstate or offs-
been concluded that power device failures are mostly triggered tate, whilst dynamic TSEPs are extracted during the turn-on or
by the thermo-electrical breakdown, local thermal runaway, and turn-off transitions, where both category parameter possibilities
thermo-mechanical failure [7], [8]. In practical applications, are classified in Fig. 1.
An auxiliary current source injection circuit is required to
Manuscript received April 10, 2015; revised July 7, 2015; accepted Septem-
ber 17, 2015. Date of publication September 23, 2015; date of current version ensure the current is low enough to avoid self-heating effects in
January 28, 2016. This work was supported by the National Basic Research Pro- TSEP Vsat based methods [15]. In the case of the TSEP Isc , a
gram of China (973 Program 2014CB247400) and the National Nature Science bypass power device is introduced under the test to produce the
Foundations of China (51490682). Recommended for publication by Associate
Editor J. Wang short current [16]. When these limited conditions for the TSEP
The authors are with the College of Electrical Engineering, Zhejiang Univer- Isat and Vf methods are reached in a deteriorated device, the
sity, Hangzhou 310027, China (e-mail: [email protected]). power module is susceptible to catastrophic.
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. Dynamic TSEPs include threshold voltage vth , Miller-plateau
Digital Object Identifier 10.1109/TPEL.2015.2481465 voltage vgp , the maximum voltage slope dv/dt(m ax) , current

0885-8993 © 2015 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
LUO et al.: JUNCTION TEMPERATURE EXTRACTION APPROACH WITH TURN-OFF DELAY TIME FOR HIGH-VOLTAGE 5123

Fig. 1. Classification of thermo-sensitive electrical parameters.

slope di/dt(m ax) , and turn-on/off delay time (tdon /tdoff ) [13].
In terms of TSEPs vth and vgp , they are unlikely for the online
extraction because of their low sensitivity (About few millivolts
per degree [11]) and sensitive sensing circuit requirements. Ad-
ditional components are needed to convert dynamic dv/dt and
di/dt to an observable signal, like RC circuitry or a PCB Ro-
gowski coil, which affect IGBT switching characteristics [17],
[18]. Particularly, the turn-on current of IGBT intertwined with
the reverse recovery current of corresponding diode in the com- Fig. 2. High-power IGBT module package structure and equivalent circuit in
mutation circuits, thus di/dt(m ax) , during the turn-on interval terms of parasitic inductors.
may not reflect the IGBT junction temperature accurately. In the
case of di/dt(m ax) during the turn-off interval, the difficulty is
determination of time base in the sensing process, which relies dynamic switching characteristic testing platform, the turn-off
on the accurate measurement of a variable high collector current. switching transitions, accounting for the internal parasitic in-
In general, the TSEP extraction methods with only low-voltage ductors is discussed. Then the tdoff measurement method using
sampling circuits, comparators, and logic circuits are ideal can- the parasitic inductor LeE is outlined.
didates, which can simplify the test procedures and achieve high
integration. A. Internal Parasitic Inductors in High-Power IGBT Modules
In this paper, a junction temperature extraction approach
based on turn-off delay time tdoff is proposed for high-power Parallel operation of multichip devices is the direct and ef-
IGBT modules. Benefitting from the specific package of high- fective way to enhance the capacity of a single module. The
voltage and high-power IGBT modules, tdoff can be extracted Infineon high-power multichip IGBT module FZ1500R33HE3
by using the parasitic inductor LeE between the Kelvin emitter rated at 3.3 kV/1.5 kA, is taken as an example to evaluate mod-
and power emitter terminals. The information of the induced ule inherent characteristics, as shown in Fig. 2. The multichip
voltage on LeE provides a cost-effective solution to measure the IGBT module consists of three parallel-connected IGBT de-
turn-off delay time tdoff . Previous research has examined the vices. Moreover, the power emitters of three IGBT devices are
physical mechanisms behind dv/dt or di/dt during the turn-off connected together inside and share a common gate driver. Con-
process [19], [20]. In this paper, tdoff is divided into three parts nected by aluminum bond wires, copper layers, power connec-
according to the operation state of the turn-off collector voltage tion terminals, and direct copper bonded, the parasitic inductors
vce . Then tdoff measuring method and the dependences among are inevitably in the current flow path.
junction temperature, load current, and bus voltage at each stage Accordingly, as in Fig. 2, LAC , LcA , Lg , Lek , and LkE rep-
of tdoff are analyzed. resent the parasitic inductors between the external terminals
(including power terminals C and E; control terminals c, g, and
e) and internal chips, Rin is the internal gate driver resistor which
II. SWITCHING CHARACTERISTICS ANALYSIS CONSIDERING increases driver loop damping; the parasitic inductor LeE be-
INTERNAL PARASITIC INDUCTOR
tween the Kelvin and power emitters is the sum of Lek and LkE .
In this section, the specifics of modern high-voltage and Cge is gate capacitor. The gate collector capacitor Cgc consists
high-power IGBT modules are demonstrated. On the basis of a of the variable depletion layer capacitor Cdep and fixed oxide
5124 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 7, JULY 2016

Fig. 4. IGBT turn-off process with module parasitic inductors.

[21]. In Fig. 3(a), the platform consists of a freewheel diode

DM , an inspected IGBT module SM with its antiparallel diode
and a load inductor Lload . Ls1 is parasitic inductor from dc-link
positive voltage to Lload , Ls2 is the combination of the series
parasitic inductors in the positive bus bar and in the DM mod-
ule, Ls3 is the series parasitic inductors between power emitter
E and ground, and Ls4 is parasitic between ground and negative
bus bar. The total gate resistor Rg is defined as the sum of Rin
and Rg o . The double-pulse test sequence is plotted in Fig. 3(b).
During the first pulse, Lload is energized through SM to the
desired load current IL at a preset bus voltage Vdc , and then
IL freewheels when SM is turned OFF. In the second turn-on
pulse, the key switching waveforms, such as the induced volt-
age veE on LeE , gate driver voltage vge , collector voltage vce ,
and collector current ic , are captured at time tb and tc transition
separately for the switching performance evaluation.
From the changes of turn-off collector voltage vce , the whole
Fig. 3. Double-pulse test circuit considering parasitic parameters and main turn-off process can be divided into four stages as plotted in
waveforms. Fig. 4 [22]. Before time t0 , IL flows though SM , Lload , and
Ls2 . The inspected IGBT is in the forward conduction mode
capacitor Cox . The value of Cgc is related to the turn-off tran- with a low-forward voltage drop. The freewheel diode DM is
sition stages. Cce is the parasitic capacitor across collector and reverse biased, by a voltage Vdc .
emitter. As far as auxiliary emitter and power emitter are con- Stage 1 [t0 –t1 ]: The gating delay time from t0 to t1 is defined
cerned, the internal parasitic inductor LeE provides a poten- as Δt1 . At t0 , the voltage drop of vge leads to a decreasing elec-
tial intermediary for the junction temperature extraction. The tron concentration in the accumulation layer. The gate voltage
switching-related dic /dt and dig e /dt can produce different vge decreases exponentially due to the gate capacitor discharg-
induced voltages veE across LeE . Hence, any temperature in- ing via gate resistor Rg with gate current ig . An induced voltage
duced veE affected can be measured for the junction temperature vek occurs across Lek due to the gate current ig variation.
extraction. Accordingly, vge , veE , and vek during this stage can be deter-
mined from
B. Switching Characteristics Analysis Considering Internal ⎧ t

Parasitic Inductors ⎪
⎨ vge = (vgon − vgoff )e −R g ( C g c + C g e ) + vgoff
(1)
The high-power IGBT switching performance testing plat- ⎪
⎩ veE =vek = Lek dige
form based on the double-pulse principle, is illustrated in Fig. 3 dt
LUO et al.: JUNCTION TEMPERATURE EXTRACTION APPROACH WITH TURN-OFF DELAY TIME FOR HIGH-VOLTAGE 5125

C. Feasibility of Measuring veE -Based TSEP Extraction

The turn-off delay time tdoff is defined as the period from t0
to t3 in Fig. 4. During the IGBT turn-off process, an induced
voltage veE occurs across LeE by dig e /dt and dic /dt. This
induced voltage veE consists of vek introduced by dig e /dt at
the beginning of stage 1 and vkE introduced by dic /dt at the
beginning of stage 4. As a result, the start point (SP) of tdoff
can be determined by Lek · dig /dt, and the ending point (EP) is
triggered by LkE · dic /dt
dige dic
veE = vek +vkE = Lek + LkE . (4)
dt
   dt
Trigger of S P Trigger of E P

The induced voltage veE is affected by variations of vge and

ic . Therefore, tdoff can be extracted from veE , which is linked
to the IGBT junction temperature. Consequently, the turn-off
delay time tdoff can be used as an effective TSEP.
Fig. 5. Structure of planar IGBT and charge profiles during inductive turn-off
process.
III. TEMPERATURE DEPENDENCE CHARACTERIZATION OF
TURN-OFF DELAY TIME
where vg on and vg of f are the steady state turn-on and off gate
voltages, respectively. The whole turn-off delay time tdoff can be divided into three
Stage 2 [t1 –t2 ]: The depletion layer expansion under the gate parts according to the changes of vce , in terms of Δt1 , Δt2 , and
region begins at t1 when vge reduces to be the Miller plateau Δt3 . The turn-off delay time tdoff is essentially related to the
voltage vgp . vce rises slightly and IL remains constant. Since rate the stored charge is swept away, for given operation con-
vge is constant, all the gate current ig is supplied by igc during ditions. In this section, the time dependency of each stage on
this stage. The gate current is given by IL , Vdc , and junction temperature Tj are studied. The planar gate
IGBT structure and relevant charge profiles during the inductive
dvce
ig = igc = Cgc . (2) turn-off process are shown in Fig. 5 [19], [23]. With high-level
dt injection of the n− base during the onstate, the hole concentra-
With constant IL , the induced voltage veE is zero. The spe- tion equals to the electron concentration in n− base region at
cific value can be defined as the knee voltage Vknee of turn-off t0 . The n− base carrier distribution under the gate involves a
voltage vce and the corresponding time instant is t2 [19]. For par- high-concentration accumulation layer. vce can increase as the
ticular high-power IGBT modules, Vknee is usually around tens carrier storage region starts to contract from the Emitter (E) to
of volts and can be neglected when compared with the high bus Collector (C). And WB is the physical length of drift region of
voltage Vdc . IGBT, LM is half physical length under gate region.
Stage 3 [t2 –t3 ]: Once the accumulation layer under the gate
region is fully depleted by the space charge region (SCR), the
A. Duration Δt1 Dependence Analysis
gate collector capacitance Cgc decreases quickly due to the
depletion capacitor component Cdep as vce increases rapidly. The duration Δt1 is the time for the gate voltage fall to the
There is a negative feedback from the rising collector voltage to Miller plateau voltage vgp . This gating delay duration Δt1 is
the gate voltage. An extra current caused by the rising collector expressed by
voltage will flow into the gate through Cgc , preventing the re-

vgon − vgoff
duction of vge [19]. Both the gate voltage vge and gate current Δt1 = Rg (Cgc + Cge ) ln . (5)
ig decrease slightly. Essentially the gate current ig is provided vgp − vgoff
by the discharging of Cgc , and the turn-off collector voltage vce In (5), gate capacitance Cge , oxide capacitance Cox , and turn-
increases near linearly. The induced voltage vek across Lek can off vgp are the main impact factors. During this stage, Cgc and
be neglected due to the small gate current variation. Cge are constant and Tj independent. At the active region of
Stage 4 [t3 –t4 ]: At t3 , when vce reaches the bus voltage Vdc , IGBT output characteristic curve, the relationships between vgp
the diode DM becomes forward biased, so begins to conduct and the relevant trans-conductance gm are given by [24]
the load current. The load current IL in the collector current ic
decreases rapidly. The collector current dic /dt induces voltage IL
vgp = vth + (6)
vkE across LkE and the overshoot voltage Δvce across the loop gm
parasitic inductors in the current commutation loop. The induced
where gm is the IGBT trans-conductance. Usually, gm at the
voltage veE is given by
specific Tj can be deduced from the transfer characteristic in
dic the datasheet. The Infineon IGBT module FZ1500R33HE3 used
veE =vkE = LeE . (3)
dt as an example, with a transfer characteristic is shown in Fig. 6.
5126 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 7, JULY 2016

Fig. 8. Shrink process of accumulation layer under gate region at Δt2 stage.

B. Duration Δt2 Dependence Analysis

This stage involves development of the base region depletion
layer under the gate region. Due to the slight reduction of the
Fig. 6. IGBT transfer characteristic variation with junction temperature. gate plateau voltage, the MOS channel electron current starts
to decrease. The carriers swept out of two base regions: the ac-
cumulation layer under the gate region and the carrier storage
region under the P+ base, where the first is much larger than
the second [22]–[25]. Consequently, under the same extraction
velocity, the extraction current from the accumulation layer ac-
counts for the majority of the total carrier extraction. With a
decreasing MOS channel electron current, the carrier extraction
from the n− drift region is needed to maintain the constant IL .
Then, the depletion layer under gate region begins to widen and
the collector voltage vce starts to rise.
At t1 , a significantly high-density accumulation layer still ex-
ists. Hence, the collector-emitter capacitance Cce remains high,
decreasing until the depletion layer under the gate region is fully
formed. During this process, the collector voltage vce rises but
Fig. 7. High-power IGBT module trans-conductance with +15 V/−10 V drive
voltages.
is low compared with bus voltage Vdc . The feedback effect of
dvce /dt on the gate collector capacitor Cgc represses reduc-
tion of the gate voltage vge [19]. Therefore, the turn-off Miller
Threshold voltage vth monotonically decreases with increas- plateau voltage vgp is maintained as a plateau.
ing junction temperature [27]. On the basis of inspected IGBT The shrinking accumulation layer width under gate region
model, the threshold voltage variation with junction tempera- Δt2 is shown in Fig. 8. wcd is the depletion layer length under the
ture, for the Infineon FZ1500R33HE3, can be measured with gate region. Based on the charge control principle, the carriers
the semiconductor parameter analyzer HP4155b from Agilent removed by the depletion layer expansion equal the carriers
Corporation. The measured results are approximated by removed to maintain constant IL during Δt2 .
Provided the load current IL is constant, the widening of
vth (T ) = vth (Ta ) − 9 × 10−3 (T − Ta ) (7) wcd is directly related to the MOS channel current reduction
under the gate region. Assuming a uniform carrier concentration
where vth (Ta ) is the threshold voltage at temperature Ta = distribution nac in the accumulation layer, the rate of length wcd
25 °C and vth (25 °C) = 6.47 V. It should be pointed out that (7) change during Δt2 can be expressed by
is a fitting equation from the measured data.
dwcd (t) ΔIch
From (6) and (7), the temperature dependence of Miller qnac = ΔJch ≈ (8)
plateau voltage vgp under different load currents IL is presented dt Ac
in Fig. 7. From Fig. 7, the Miller plateau voltage vgp has a neg- where q is the unit charge, ΔJch is the electron current density
ative temperature coefficient. Therefore, duration Δt1 increases reduction in the MOS channel under the gate region, and Ac is
with the junction temperature. Also the higher IL , the higher the active area of IGBT chip.
vgp . This means duration Δt1 decreases with increased IL at a At t2 , assuming the depletion layer under gate area is fully
given junction temperature and bus voltage Vdc . established. The length of wcd can be approximated to LM .
LUO et al.: JUNCTION TEMPERATURE EXTRACTION APPROACH WITH TURN-OFF DELAY TIME FOR HIGH-VOLTAGE 5127

assumption, the effecting doping Neff is given by [19]

Jc
Neff ≈ NB + (12)
qvsat
The electrical field gradient in the depletion layer, accounting
for the effecting doping Neff is expressed by
Jc
dE qNeff q(NB + q vsa t )
= = (13)
dx ε ε
where ND is the doping concentration in the n− base region,
ε is the silicon dielectric coefficient. Then, the bias voltage vce
related to wsc can be computed by


1 q Jc 2
vce = Em wsc = NB + wsc (14)
Fig. 9. Expanding process of the depletion layer during Δt3 stage. 2 2ε qvsat
where wsc is the length of depletion layer in this stage. Accord-
Integrating function (8) gives expression (9) ing to the charge control principle, the depletion layer expansion
dwsc /dt is related to the electron concentration in the n− drift
t 2 L M region ndrl
qnac
dt = dwcd (t). (9)
ΔJch dwsc ΔJch ΔJch ΔJch
t1 0 = ⇒ ndr l dwsc = dt ⇒ wsc = t
dt qndr l q qndr l
So the expression for Δt2 can be deduced as (15)
From (14) and (15), the collector voltage vce can be repre-
LM qnac
Δt2 = . (10) sented by
ΔJch


2
As carrier lifetime τHL increases with Tj [11], the carrier q Jc ΔJch
vce = NB + t . (16)
concentration in the base region has an overall increase with Tj 2ε qvsat qndrl
rise, as well as nac . This prolongs Δt2 . However, for fixed Tj , When vce reaches bus voltage Vdc , with the relatively small knee
the carrier concentration in accumulation layer under the gate voltage Vknee ignored, the duration Δt3 can be obtained from
region is near independent of load current IL [22]. As a result,
the relationship between IL and Δt2 is determined by ΔJch , 2εqVdc
(Δt3 )2 =  2 . (17)
which is discussed in the next part. Jc Δ Jch
NB + q vsa t qnd rl

C. Duration Δt3 Dependence Analysis The duration Δt3 becomes

After t2 , the depletion region under the gate region starts 
2εqVdc 1
to widen toward the collector, where the depletion capacitance Δt3 = Jc
· . (18)
Cdep appears as shown in Fig. 9. The accumulation layer un- NB + q v s a t Δ Jch
qnd rl
der the gate region has disappeared, and the gate collector ca-
pacitance Cgc is reduced by two orders of magnitude as the Therefore, the voltage level Vdc dominates Δt3 under fixed
collector voltage vce increases rapidly [25]. Cgc at this stage IL and Tj , which is directly proportional to Vdc .
is series connected with the oxide capacitor Cox and depletion In order to analyze the interdependences of IL , Tj and Δt3 ,
capacitor Cdep . the relationships among ΔJn , IL , and Tj should be considered.
Since the gate voltage and MOS current continues to decrease, According to the square-law characteristic for the MOS struc-
one depletion layer boundary expands toward the collector with ture at this stage, the saturated MOS channel current is given
a reduced current density Jch . With n− base high-level injection, by [27]
ΔJch in the MOS channel may cause a decrease in the coupled
Ich = Kc (vge − vth )2 (19)
hole current density ΔJp . But the carrier extraction current
component maintains the current flowing through the SCR at IL where Kc is a constant coefficient associated with channel di-
level. In general, the effective doping Neff can be expressed by mensions and electron mobility in the inversion layer. In the
Jpsc Jnsc saturated current regime of operation, the trans-conductance is
Neff = NB + − . (11) given by [27]
qvsat qvsat
When accounting for the carrier mobility difference be- dIch dKc (vge − vth )2
gm = = = 2Kc (vge − vth ). (20)
tween holes and electrons, with a similar saturation velocity dvge dvge
5128 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 7, JULY 2016

TABLE I
TURN-OFF DELAY TIME TRENDS OVER OPERATION CONDITIONS

Δ t1 Trend Δ t2 Trend Δ t3 Trend Δ td o f f

Trend

Operation Tj ↑ ↑ ↑ ↑ ↑
condition Vd c ↑ — — ↑ ↑
trends IL ↑ ↓ ↓ ↓ ↓

TABLE II
EXPERIMENT PARAMETERS

Parameter Value Parameter Value

IGBT module Infineon Drive voltage v g e +15 V/−10 V

FZ1500R33HE3
Bus capacitor C b u s 1000 μF Turn-on/off gate 2.7 Ω/3.75 Ω
resistor
R g o n /R g o f f
Load inductor L l o a d 400 μH Junction temperature 25 ° C, 50 ° C,
Tj 75 ° C, 100 ° C,
Fig. 10. Experimental waveforms of turn-off ic , v g e and v e E , for
125° C
different T j .
Switching voltage 1400–1600 V Lek ࣈ6.5 nH
Vd c
Load current I L 200–1200 A Lk E ࣈ4 nH
as the Tj increases under fixed Vdc and IL . Consequently, Δt3
in (19) increases as Tj increases.
The relationship between the MOS channel current Ich and Table I summarizes the relationships among Tj , Vdc , IL and
load current IL is expressed by each period comprising tdoff . As Tj increases, the durations of
Δt1 , Δt2 , and Δt3 all increases. For a fixed Tj , the Δt2 and
Ich = (1 − αpnp )IE = (1 − αpnp )IL . (21)
Δt3 increase with higher Vdc . However, the voltage level Vdc is
The change of channel current ΔIch can be obtained by (6), not related to Δt1 and Δt2 . Conversely, each duration decreases
(19)–(21) with higher IL at the same Tj and Vdc . Generally, tdoff increases
 monotonically with both Tj and Vdc . With increasing IL , tdoff
ΔIch = ΔJch Ac = 2Δvge (1 − αpnp )Kc IL . (22) decreases monotonically. As a result, tdoff is an effective TSEP
owing to the monotonicity of Tj variation, Vdc and IL .
The electron concentration ndrl in the carrier storage region
is approximated by
x IV. EXPERIMENTAL INVESTIGATION
ndrl = ndrl0 (1 − ) (23)
WB In order to verify the relationship between tdoff and junction
where x is the distance between the collector of the planar IGBT temperature during the turn-off process, a high-voltage high-
structure and boundary of carrier storage region as shown in power IGBT module (rated at 3.3 kV/1.5 kA) is assessed with
Fig. 5. an inductive load. The IGBT and its environment are uniformly
The initial electron concentration ndrl0 can be obtained heated to the required junction temperature via its heat-sink
from [19] in the sealed box over a long period before experimental data
 are taken. The associated experimental parameters are given in
μn IL Table II. A 1000-μF bus capacitor bank maintains the dc rail
ndrl 0 ≈ . (24)
qAc hp (μn + μp ) voltage constant during the double-pulse testing process. The
values of Rgon and Rgoff are selected from the recommendation
According to (23) and (24), the initial electron concentration of datasheet. The internal parasitic inductors Lek and LkE are
ndrl0 and ΔJch are √ both proportional to
√ the square root of load about 6.5 and 4 nH, respectively.
current IL :ndrl0 ∝ IL and ΔJch ∝ IL . Since the collector The experimental waveforms of IGBT turn-off ic , vce , vg e ,
current density Jc is directly proportional to the load current IL , and induced veE are shown in Fig. 10. The IGBT junction tem-
the duration Δt3 increase with IL is revealed by (18). While a perature is controlled at 25 °C, and Vdc and IL are maintained at
Δt2 decreases with the IL for fixed Vdc and Tj is revealed by 1600 V/1200 A. tdoff is defined as the time gate voltage falls to
(10) and (22). From (8) and (18), ΔJch is 90% until the collector current rises 10%. When induced volt-
Ich age veE is utilized to extract tdoff , the time base of vge and IL
= IL = gm (vge − vth ) (25)
1 − αpnp decrease is reflected by a synchronous jump of veE . tdoff can be
extracted by confirming the start and end point of tdoff in stage
ΔJch = (1 − αpnp )gm Δvge /Ac . (26)
2 and stage 4, respectively.
As junction temperature Tj increases, the trans-conductance In Fig. 11, the experimental waveforms of vce and related
gm decreases, while the resultant current gain αpnp [28] and veE at 25 and 125 °C are separately plotted (Vdc = 1600 V,
electron concentration ndrl increase [29]. Further, ΔJch reduces IL = 1200 A). In the case of fixed Vd and IL , Δt1 +Δt2 is
LUO et al.: JUNCTION TEMPERATURE EXTRACTION APPROACH WITH TURN-OFF DELAY TIME FOR HIGH-VOLTAGE 5129

Fig. 12. Experimental waveforms of ic and related v e E at V d c = 1600 V,

T j = 25 °C, for different load currents.

make tdoff an excellent TSEP candidate for evaluating the Tj of

Fig. 11. Experimental waveforms of v c e and related v e E at V d c = 1600 V,
IL = 1200 A, for different junction temperatures. high-power IGBT modules.

V. COMPARISON AND EVALUATION OF STATE-OF-THE-ART

TSEPS
3.6 μs and Δt3 is 1.33 μs at 25 °C, while Δt1 +Δt2 and Δt3
at 125 °C are 3.87 and 1.42 μs, respectively. With increasing The comparison among the voltage at low-current injection
junction temperature, Δt3 and Δt1 +Δt2 are prolonged, which Vsat [14], voltage at high-current injection Vf [30], and turn-off
is consistent with the presented theoretical analysis. delay time tdoff are summarized by three radar graphs, which
The induced veE at Vdc = 1600 V and Tj = 25 °C for dif- are plotted in Fig. 15.
ferent load currents are plotted in Fig. 12. The measured tdoff In the radar graphs, a point near the outer periphery means
at IL = 400 A is about 5.09 μs while tdoff is about 4.82 μs at that the TSEP candidate has excellent performance under the
IL = 800 A. As shown in Table I, the trend of tdoff decreases specific comparison criterion [11]. The linearity, sensitivity, cal-
with increased IL under fixed Vdc and Tj . ibration, online implementation, and generalization are adopted
Experimentally, tdoff not only depends on junction temper- as the comparison criterion to explore and compare the detailed
ature but also on Vdc and IL . The measured tdoff at different performance of TSEP candidates [11]. From Fig. 15, it can be
IGBT junction temperatures and IL are illustrated in Fig. 13. seen that the selected three TSEPs have good linearity with junc-
With fixed Tj , the measured tdoff decreases as the load current tion temperature. This means the calibration and data process
IL increases. For fixed IL and Vdc test conditions, tdoff is pro- can be simplified due to the high linearity. For the voltage at
portional to the junction temperature, as analyzed. In Fig. 13(a), high-current injection Vf , the sensitivity is from 3.5 mV/°C at
the sensitivity at IL = 800 A is about 4 ns/°C (Vdc = 1400 V). IL = 1200 A to 0.5 mV/°C at IL = 200 A for the tested IGBT
In Fig. 13(b), when the bus voltage is increased to 1600 V, the modules, which can be derived from the datasheet. This indi-
sensitivity ratio at IL = 800 A is also about 4 ns/°C. As Tj cates that the sensitivity of Vf -based TSEP is determined by
increases, the measured tdoff under different IL has the same the current levels. Consequently, it is difficult to determinate
sensitivity. This fixed sensitivity and linearity make the proposed the junction temperature under low-load current levels. Fortu-
tdoff a viable TSEP candidate. nately, the turn-off delay time tdoff -based TSEP has a relatively
The variation of tdoff with IGBT Tj at different Vdc and IL fixed sensitivity. Therefore, tdoff -based TSEP can be applied
are illustrated in Fig. 14. As the bus voltage Vdc increases for to a wide range of load current, particularly to low-load cur-
the same Tj , the depletion layer in the SCR needs to extend to rent levels. Compared with Vsat -based TSEP, benefitting from
support Vdc . Thus, the measured tdoff increases with increasing the transferring effect of the auxiliary inductor LeE , the turn-
of Vdc . For fixed IL and Vdc , tdoff tends to increase with rising off delay time tdoff can be extracted effectively and feasibly
Tj . In Fig. 14(a), the sensitivity at IL = 1000 A is about 4 ns/°C for the online implementation. From the generalization point
(Vdc = 1600 V), which is the same as the sensitivity at IL = of view, the voltage at low-current injection Vsat and voltage
1200 A in Fig. 14(b). at high-current injection Vf -based TSEPs can be used for all
The start and end points of tdoff are easily extracted from power semiconductor devices. However, the turn-off delay time
the induced voltage veE across the parasitic inductor LeE , with- tdoff -based TSEP cannot be applicable for the power diodes.
out influencing IGBT switching performance. High linearity In general, the turn-off delay time tdoff -based TSEP con-
and relatively fixed sensitivity and simple sensing requirements tains the feature of fixed sensitivity, high linearity, and feasible
5130 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 7, JULY 2016

Fig. 13. Correlation and linear-fitted curves between td o ff time extracted by v e E , IGBT junction temperature and load current: (a) V d c = 1400 V and
(b) V d c = 1600 V.

Fig. 14. Variation of td o ff with T j and V d c and linear fitted curves: (a) load current IL = 1000 A and (b) load current IL = 1200 A.

Fig. 15. Comparison of three state-of-the-art TSEPs: (a) Voltage at low current injection V sa t , (b) Voltage at high-current injection V f , and (c) Turn-off delay
time td o ff .

online implementation. For the existing assembled converters, VI. CONCLUSION

the power module and external circuit parameters are usually This paper proposed a junction temperature extraction ap-
fixed. The corresponding IGBT junction temperature can be esti- proach, for high-power IGBT modules, that utilizes turn-off de-
mated from a look-up table, which is drawn from the calibration lay time. Only the voltage sampling circuits, comparators, and
process in advance. logic circuits are required with the proposed extraction method,
LUO et al.: JUNCTION TEMPERATURE EXTRACTION APPROACH WITH TURN-OFF DELAY TIME FOR HIGH-VOLTAGE 5131

because the high current information has been changed to the [15] Z. Khatir, L. Dupont, and A. Ibrahim, “Investigations on junction temper-
low voltage information by the inherent parasitic inductor LeE ature estimation based on junction voltage measurements,” Microelectron.
Rel., vol. 50, pp. 1506–1510, 2010.
in high-power IGBT modules. The junction temperature charac- [16] Z. Xu, F. Xu, and F. Wang, “Junction temperature measurement of IGBTs
teristic and impact factors on turn-off delay time were discussed, using short circuit current as a temperature sensitive electrical parameter
and were verified experimentally on a high power IGBT module for converter prototype evaluation,” IEEE Trans. Ind. Electron., vol. 62,
no. 6, pp. 3419–3429, Jun. 2015.
test system. Experimental results have shown that measuring the [17] Y. Lobsiger and J. W. Kolar, “Closed-Loop di/dt and dv/dt IGBT gate
voltage veE across the parasitic inductor between the Kelvin and driver,” IEEE Trans. Power Electron., vol. 30, no. 6, pp. 3402–3417, Jun.
power emitter terminals provides a practical approach to moni- 2015.
[18] M. H. Samimi, A. Mahari, M. A. Farahnakian, and H. Mohseni,
tor turn-off delay time. A positive near-linear dependency exists “The Rogowski coil principles and applications: A review,” IEEE Sens.
between turn-off delay time and junction temperature. With a J., vol. 15, no. 2, pp. 651–658, Feb. 2015.
database of turn-off delay with junction temperature, bus volt- [19] A. Bryant, S. Yang, P. Mawby, D. Xiang, L. Ran, P. Tavner, and P. Palmer,
“Investigation into IGBT dV/dt during turn-off and its temperature depen-
age and load current, IGBT junction temperature can be online dence,” IEEE Trans. Power Electron., vol. 26, no. 10, pp. 3019–3031, Oct.
monitored. With fixed sensitivity and good linearity, it can be 2011.
concluded that turn-off delay time is a practical TSEP for on- [20] M. Trivedi and K. Shenai, “Modeling the turn-off of IGBT’s in hard-
and soft-switching applications,” IEEE Trans. Electron Devices, vol. 44,
line junction temperature monitoring. This monitoring method no. 5, pp. 887–893, May 1997.
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602, Feb. 2015. neering, Zhejiang University, Zhejiang, China.
[11] Y. Avenas, L. Dupont, and Z. Khatir, “Temperature measurement of power From January to April 2015, he was a Visiting
semiconductor devices by thermo-sensitive electrical parameters—A re- Researcher at Newcastle University, Newcastle upon
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2012. converters and reliability of high-power modules.
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IGBTs based on temperature sensitive electrical parameters,” in Proc. 13th
Eur. Conf. Power Electron. Appl., 2009, pp. 1–10. Yuxiang Chen received the B.Sc. and M.Sc. degrees
[13] B. J. Alexander, S. Bastian, M. Gerhard, and L. Andreas, “Investigation from the Department of Information and Electrical
of temperature sensitive electrical parameters for power semiconductors Engineering, China University of Mining and Tech-
(IGBT) in real-time applications,” in Proc. Int. Exhib. Conf. Power Elec- nology, Xuzhou, China, in 2011 and 2014, respec-
tron., Intell. Motion, Renewable Energy Energy Manage. Eur. Conf. Appl., tively. She is currently working toward the Ph.D.
2014, pp. 1–9. degree in the College of Electrical Engineering,
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vol. 49, no. 4, pp. 1599–1608, Jul./Aug. 2013.
5132 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 31, NO. 7, JULY 2016

Pengfei Sun received the B.Sc. degree in electronics Xiangning He (M’95–SM’96–F’10) received the
from the Department of Electrical Engineering, Yan- B.Sc. and M.Sc. degrees from the Nanjing Univer-
shan University, Qinhuangdao, China, in 2012, and sity of Aeronautics and Astronautics, Nanjing, China,
the M.Sc. degree from the Department of Electrical in 1982 and 1985, respectively, and the Ph.D. degree
Engineering, Zhejiang University, Hangzhou, China, from Zhejiang University, Hangzhou, China, in 1989.
in 2015. From 1985 to 1986, he was an Assistant Engineer
His research interests include high-power IGBT at the 608 Institute of Aeronautical Industrial General
module reliability and modeling. Company, Zhuzhou, China. From 1989 to 1991, he
was a Lecturer at Zhejiang University. In 1991, he ob-
tained a Fellowship from the Royal Society of U.K.,
and conducted research in the Department of Com-
puting and Electrical Engineering, Heriot-Watt University, Edinburgh, U.K., as
Wuhua Li (M’09) received the B.Sc. and Ph.D. de- a Postdoctoral Research Fellow for two years. In 1994, he joined Zhejiang Uni-
grees in applied power electronics and electrical engi- versity as an Associate Professor. Since 1996, he has been a Full Professor in
neering from Zhejiang University, Hangzhou, China, the College of Electrical Engineering, Zhejiang University. He was the Director
in 2002 and 2008, respectively. of the Power Electronics Research Institute and the Head of the Department of
From 2004 to 2005, he was a Research Intern, Applied Electronics, and he is currently the Vice Dean of the College of Elec-
and from 2007 to 2008, a Research Assistant in GE trical Engineering, Zhejiang University. His research interests include power
Global Research Center, Shanghai, China. From 2008 electronics and their industrial applications. He is the author or coauthor of
to 2010, he joined the College of Electrical Engineer- more than 280 papers and one book Theory and Applications of Multi-Level
ing, Zhejiang University as a Post doctor. In 2010, Converters (Beijing, China: China Machine Press, 2006). He holds 22 patents.
he was promoted as an Associate Professor. Since Dr. He received the 1989 Excellent Ph.D. Graduate Award, the 1995 Elite
2013, he has been a Full Professor at Zhejiang Uni- Prize Excellence Award, the 1996 Outstanding Young Staff Member Award,
versity. From 2010 to 2011, he was a Ryerson University Postdoctoral Fellow and 2006 Excellent Staff Award from Zhejiang University for his teaching and
with the Department of Electrical and Computer Engineering, Ryerson Univer- research contributions. He received seven Scientific and Technological Achieve-
sity, Toronto, ON, Canada. His research interests include high-power devices, ments Awards from Zhejiang Provincial Government and the State Educational
advanced power converters, and operation optimization for renewable energy- Ministry of China in 1998, 2002, 2009, and 2011 respectively, and six Excellent
based power systems. Paper Awards. Dr. He is a Fellow of The Institute of Electrical and Electronics
Dr. Li has published more than 100 peer-reviewed technical papers and holds Engineers (IEEE) and has been appointed as IEEE Distinguished Lecturer by
more than 30 issued/pending patents. Due to his excellent teaching and research the IEEE Power Electronics Society in 2011. He is also a Fellow of the Institu-
contributions, Dr. Li received the 2011 Top Ten Excellent Young Staff Award tion of Engineering and Technology (formerly IEE), U.K.
and the 2012 Distinguished Young Scholar from Zhejiang University, the 2012
Outstanding Young Researcher Award from Zhejiang Province, the 2012 Delta
Young Scholar from Delta Environmental & Educational Foundation and the
2012 National Outstanding Young Scholar. He received four Scientific and Tech-
nological Achievements Awards from Zhejiang Provincial Government and the
State Educational Ministry of China in 2009, 2011, and 2014, respectively.

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