// fpga4student.
com FPGA projects, VHDL projects, Verilog
projects
// Verilog project: Verilog code for traffic light
controller
module traffic_light(light_highway, light_farm, C, clk,
rst_n);
parameter HGRE_FRED=2'b00, // Highway green and farm red
HYEL_FRED = 2'b01,// Highway yellow and farm red
HRED_FGRE=2'b10,// Highway red and farm green
HRED_FYEL=2'b11;// Highway red and farm yellow
input C, // sensor
clk, // clock = 50 MHz
rst_n; // reset active low
output reg[2:0] light_highway, light_farm; // output of
lights
// fpga4student.com FPGA projects, VHDL projects, Verilog
projects
reg[27:0] count=0,count_delay=0;
reg delay10s=0,
delay3s1=0,delay3s2=0,RED_count_en=0,YELLOW_count_en1=0,YELL
OW_count_en2=0;
wire clk_enable; // clock enable signal for 1s
reg[1:0] state, next_state;
// next state
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
state <= 2'b00;
else
state <= next_state;
end
// FSM
always @(*)
begin
case(state)
HGRE_FRED: begin // Green on highway and red on farm way
RED_count_en=0;
YELLOW_count_en1=0;
YELLOW_count_en2=0;
light_highway = 3'b001;
light_farm = 3'b100;
if(C) next_state = HYEL_FRED;
// if sensor detects vehicles on farm road,
// turn highway to yellow -> green
else next_state =HGRE_FRED;
end
HYEL_FRED: begin// yellow on highway and red on farm way
light_highway = 3'b010;
light_farm = 3'b100;
RED_count_en=0;
YELLOW_count_en1=1;
YELLOW_count_en2=0;
if(delay3s1) next_state = HRED_FGRE;
// yellow for 3s, then red
else next_state = HYEL_FRED;
end
HRED_FGRE: begin// red on highway and green on farm way
light_highway = 3'b100;
light_farm = 3'b001;
RED_count_en=1;
YELLOW_count_en1=0;
YELLOW_count_en2=0;
if(delay10s) next_state = HRED_FYEL;
// red in 10s then turn to yello -> green again for high
way
else next_state =HRED_FGRE;
end
HRED_FYEL:begin// red on highway and yellow on farm way
light_highway = 3'b100;
light_farm = 3'b010;
RED_count_en=0;
YELLOW_count_en1=0;
YELLOW_count_en2=1;
if(delay3s2) next_state = HGRE_FRED;
// turn green for highway, red for farm road
else next_state =HRED_FYEL;
end
default: next_state = HGRE_FRED;
endcase
end
// fpga4student.com FPGA projects, VHDL projects, Verilog
projects
// create red and yellow delay counts
always @(posedge clk)
begin
if(clk_enable==1) begin
if(RED_count_en||YELLOW_count_en1||YELLOW_count_en2)
count_delay <=count_delay + 1;
if((count_delay == 9)&&RED_count_en)
begin
delay10s=1;
delay3s1=0;
delay3s2=0;
count_delay<=0;
end
else if((count_delay == 2)&&YELLOW_count_en1)
begin
delay10s=0;
delay3s1=1;
delay3s2=0;
count_delay<=0;
end
else if((count_delay == 2)&&YELLOW_count_en2)
begin
delay10s=0;
delay3s1=0;
delay3s2=1;
count_delay<=0;
end
else
begin
delay10s=0;
delay3s1=0;
delay3s2=0;
end
end
end
// create 1s clock enable
always @(posedge clk)
begin
count <=count + 1;
//if(count == 50000000) // 50,000,000 for 50 MHz clock
running on real FPGA
if(count == 3) // for testbench
count <= 0;
end
assign clk_enable = count==3 ? 1: 0; // 50,000,000 for
50MHz running on FPGA
endmodule
// fpga4student.com FPGA projects, VHDL projects,
Verilog projects
// Verilog project: Verilog code for traffic light
controller
module traffic_light(light_highway, light_farm, C,
clk, rst_n);
parameter HGRE_FRED=2'b00, // Highway green and farm
red
HYEL_FRED = 2'b01,// Highway yellow and farm red
HRED_FGRE=2'b10,// Highway red and farm green
HRED_FYEL=2'b11;// Highway red and farm yellow
input C, // sensor
clk, // clock = 50 MHz
rst_n; // reset active low
output reg[2:0] light_highway, light_farm; // output
of lights
// fpga4student.com FPGA projects, VHDL projects,
Verilog projects
reg[27:0] count=0,count_delay=0;
reg delay10s=0,
delay3s1=0,delay3s2=0,RED_count_en=0,YELLOW_count_en1
=0,YELLOW_count_en2=0;
wire clk_enable; // clock enable signal for 1s
reg[1:0] state, next_state;
// next state
always @(posedge clk or negedge rst_n)
begin
if(~rst_n)
state <= 2'b00;
else
state <= next_state;
end
// FSM
always @(*)
begin
case(state)
HGRE_FRED: begin // Green on highway and red on farm
way
RED_count_en=0;
YELLOW_count_en1=0;
YELLOW_count_en2=0;
light_highway = 3'b001;
light_farm = 3'b100;
if(C) next_state = HYEL_FRED;
// if sensor detects vehicles on farm road,
// turn highway to yellow -> green
else next_state =HGRE_FRED;
end
HYEL_FRED: begin// yellow on highway and red on farm
way
light_highway = 3'b010;
light_farm = 3'b100;
RED_count_en=0;
YELLOW_count_en1=1;
YELLOW_count_en2=0;
if(delay3s1) next_state = HRED_FGRE;
// yellow for 3s, then red
else next_state = HYEL_FRED;
end
HRED_FGRE: begin// red on highway and green on farm
way
light_highway = 3'b100;
light_farm = 3'b001;
RED_count_en=1;
YELLOW_count_en1=0;
YELLOW_count_en2=0;
if(delay10s) next_state = HRED_FYEL;
// red in 10s then turn to yello -> green again for
high way
else next_state =HRED_FGRE;
end
HRED_FYEL:begin// red on highway and yellow on farm
way
light_highway = 3'b100;
light_farm = 3'b010;
RED_count_en=0;
YELLOW_count_en1=0;
YELLOW_count_en2=1;
if(delay3s2) next_state = HGRE_FRED;
// turn green for highway, red for farm road
else next_state =HRED_FYEL;
end
default: next_state = HGRE_FRED;
endcase
end
// fpga4student.com FPGA projects, VHDL projects,
Verilog projects
// create red and yellow delay counts
always @(posedge clk)
begin
if(clk_enable==1) begin
if(RED_count_en||YELLOW_count_en1||YELLOW_count_en2)
count_delay <=count_delay + 1;
if((count_delay == 9)&&RED_count_en)
begin
delay10s=1;
delay3s1=0;
delay3s2=0;
count_delay<=0;
end
else if((count_delay == 2)&&YELLOW_count_en1)
begin
delay10s=0;
delay3s1=1;
delay3s2=0;
count_delay<=0;
end
else if((count_delay == 2)&&YELLOW_count_en2)
begin
delay10s=0;
delay3s1=0;
delay3s2=1;
count_delay<=0;
end
else
begin
delay10s=0;
delay3s1=0;
delay3s2=0;
end
end
end
// create 1s clock enable
always @(posedge clk)
begin
count <=count + 1;
//if(count == 50000000) // 50,000,000 for 50 MHz
clock running on real FPGA
if(count == 3) // for testbench
count <= 0;
end
assign clk_enable = count==3 ? 1: 0; // 50,000,000
for 50MHz running on FPGA
endmodule
The Verilog code developed for the principle operation
of an elevator with any number of floors is given below.
Module chk2(reset,clk,PROX,HBTNS_U,HBTNS_D,
CBTNS,INV1F,INV1R,BRAKE,HLBTNS_D,HLBTNS_U,
CLBTNS);
parameter N=3;
input clk;
input reset;
input[N-1:0] PROX;
input[N-2:0] HBTNS_U;
input[N-2:0] HBTNS_D;
input[N-1:0]CBTNS;
output INV1F;
output INV1R;
output BRAKE;
output [N-2:0]HLBTNS_U;
output [N-2:0]HLBTNS_D;
output [N-1:0]CLBTNS;
reg [N-1:0] status;
integer i;
reg[N-1:0]BTNS;
reg[N-1:0]HBTNS_in;
reg[N-2:0]HBTNS_U_in;
reg[N-2:0]HBTNS_D_in;
reg[N-1:0]CBTNS_in;
reg[N-1:0]BTNS_in;
reg[N-1:0]PROX_in;
reg INV1F,INV1R,BRAKE;
reg [N-2:0]HLBTNS_U;
reg [N-2:0]HLBTNS_D;
reg [N-1:0]CLBTNS;
always @(posedge clk)
if (!reset) begin
HBTNS_U_in=HBTNS_U;
HBTNS_D_in=HBTNS_D;
HBTNS_in = HBTNS_D_in*2 + HBTNS_U_in ;
CBTNS_in = CBTNS ;
if(status==1) begin
BTNS_in <=0;
CLBTNS <=0;
HLBTNS_D <=0;
HLBTNS_U <=0;
end
else begin
BTNS_in<= BTNS;
end
if(HBTNS_in> 0 || CBTNS_in> 0 ) begin
for (i = 0 ; i < N; i=i+1) begin
BTNS[i] <= HBTNS_in[i] | CBTNS_in[i] ;
HLBTNS_U <= HBTNS_U_in;
HLBTNS_D <= HBTNS_D_in ;
CLBTNS <= CBTNS_in;
end
end
end
always @(posedge clk)
if (!reset) begin
PROX_in<= PROX ;
if (PROX_in>0) begin
if (PROX_in==BTNS_in) begin
status<= 1;
end
else if (BTNS_in>PROX_in ) begin
status<= 2;
end
else if (BTNS_in<PROX_in&&BTNS_in!=0)
begin
status<= 3;
end
else begin
status<=0;
end
end
end
always @(posedge clk)
if (!reset) begin
case(status)
1: begin
INV1F_ins <=0;
INV1R_ins <=0;
BRAKE_ins<=0;
end
2: begin
INV1F_ins <=1;
BRAKE_ins<=1;
end
3: begin
INV1R_ins <=1;
BRAKE_ins<=1;
end
default: begin
INV1F_ins <=0;
INV1R_ins <=0;
BRAKE_ins<=0;
end
end case
end
end module
//----------------------------------------------------
// A four level, round-robin arbiter. This was
// orginally coded by WD Peterson in VHDL.
//----------------------------------------------------
module arbiter (
clk,
rst,
req3,
req2,
req1,
req0,
gnt3,
gnt2,
gnt1,
gnt0
);
// --------------Port Declaration-----------------------
input clk;
input rst;
input req3;
input req2;
input req1;
input req0;
output gnt3;
output gnt2;
output gnt1;
output gnt0;
//--------------Internal Registers----------------------
wire [1:0] gnt ;
wire comreq ;
wire beg ;
wire [1:0] lgnt ;
wire lcomreq ;
reg lgnt0 ;
reg lgnt1 ;
reg lgnt2 ;
reg lgnt3 ;
reg lasmask ;
reg lmask0 ;
reg lmask1 ;
reg ledge ;
//--------------Code Starts Here-----------------------
always @ (posedge clk)
if (rst) begin
lgnt0 <= 0;
lgnt1 <= 0;
lgnt2 <= 0;
lgnt3 <= 0;
end else begin
lgnt0 <=(~lcomreq & ~lmask1 & ~lmask0 & ~req3 & ~req2 & ~req1 & req0)
| (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req0)
| (~lcomreq & lmask1 & ~lmask0 & ~req3 & req0)
| (~lcomreq & lmask1 & lmask0 & req0 )
| ( lcomreq & lgnt0 );
lgnt1 <=(~lcomreq & ~lmask1 & ~lmask0 & req1)
| (~lcomreq & ~lmask1 & lmask0 & ~req3 & ~req2 & req1 & ~req0)
| (~lcomreq & lmask1 & ~lmask0 & ~req3 & req1 & ~req0)
| (~lcomreq & lmask1 & lmask0 & req1 & ~req0)
| ( lcomreq & lgnt1);
lgnt2 <=(~lcomreq & ~lmask1 & ~lmask0 & req2 & ~req1)
| (~lcomreq & ~lmask1 & lmask0 & req2)
| (~lcomreq & lmask1 & ~lmask0 & ~req3 & req2 & ~req1 & ~req0)
| (~lcomreq & lmask1 & lmask0 & req2 & ~req1 & ~req0)
| ( lcomreq & lgnt2);
lgnt3 <=(~lcomreq & ~lmask1 & ~lmask0 & req3 & ~req2 & ~req1)
| (~lcomreq & ~lmask1 & lmask0 & req3 & ~req2)
| (~lcomreq & lmask1 & ~lmask0 & req3)
| (~lcomreq & lmask1 & lmask0 & req3 & ~req2 & ~req1 & ~req0)
| ( lcomreq & lgnt3);
end
//----------------------------------------------------
// lasmask state machine.
//----------------------------------------------------
assign beg = (req3 | req2 | req1 | req0) & ~lcomreq;
always @ (posedge clk)
begin
lasmask <= (beg & ~ledge & ~lasmask);
ledge <= (beg & ~ledge & lasmask)
| (beg & ledge & ~lasmask);
end
//----------------------------------------------------
// comreq logic.
//----------------------------------------------------
assign lcomreq = ( req3 & lgnt3 )
| ( req2 & lgnt2 )
| ( req1 & lgnt1 )
| ( req0 & lgnt0 );
//----------------------------------------------------
// Encoder logic.
//----------------------------------------------------
assign lgnt = {(lgnt3 | lgnt2),(lgnt3 | lgnt1)};
//----------------------------------------------------
// lmask register.
//----------------------------------------------------
always @ (posedge clk )
if( rst ) begin
lmask1 <= 0;
lmask0 <= 0;
end else if(lasmask) begin
lmask1 <= lgnt[1];
lmask0 <= lgnt[0];
end else begin
lmask1 <= lmask1;
lmask0 <= lmask0;
end
assign comreq = lcomreq;
assign gnt = lgnt;
//----------------------------------------------------
// Drive the outputs
//----------------------------------------------------
assign gnt3 = lgnt3;
assign gnt2 = lgnt2;
assign gnt1 = lgnt1;
assign gnt0 = lgnt0;
endmodule
module uart_rx
#(parameter CLKS_PER_BIT)
(
input i_Clock,
input i_Rx_Serial,
output o_Rx_DV,
output [7:0] o_Rx_Byte
);
parameter s_IDLE = 3'b000;
parameter s_RX_START_BIT = 3'b001;
parameter s_RX_DATA_BITS = 3'b010;
parameter s_RX_STOP_BIT = 3'b011;
parameter s_CLEANUP = 3'b100;
reg r_Rx_Data_R = 1'b1;
reg r_Rx_Data = 1'b1;
reg [7:0] r_Clock_Count = 0;
reg [2:0] r_Bit_Index = 0; //8 bits total
reg [7:0] r_Rx_Byte = 0;
reg r_Rx_DV = 0;
reg [2:0] r_SM_Main = 0;
// Purpose: Double-register the incoming data.
// This allows it to be used in the UART RX Clock Domain.
// (It removes problems caused by metastability)
always @(posedge i_Clock)
begin
r_Rx_Data_R <= i_Rx_Serial;
r_Rx_Data <= r_Rx_Data_R;
end
// Purpose: Control RX state machine
always @(posedge i_Clock)
begin
case (r_SM_Main)
s_IDLE :
begin
r_Rx_DV <= 1'b0;
r_Clock_Count <= 0;
r_Bit_Index <= 0;
if (r_Rx_Data == 1'b0) // Start bit detected
r_SM_Main <= s_RX_START_BIT;
else
r_SM_Main <= s_IDLE;
end
// Check middle of start bit to make sure it's still low
s_RX_START_BIT :
begin
if (r_Clock_Count == (CLKS_PER_BIT-1)/2)
begin
if (r_Rx_Data == 1'b0)
begin
r_Clock_Count <= 0; // reset counter, found the middle
r_SM_Main <= s_RX_DATA_BITS;
end
else
r_SM_Main <= s_IDLE;
end
else
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= s_RX_START_BIT;
end
end // case: s_RX_START_BIT
// Wait CLKS_PER_BIT-1 clock cycles to sample serial data
s_RX_DATA_BITS :
begin
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= s_RX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;
r_Rx_Byte[r_Bit_Index] <= r_Rx_Data;
// Check if we have received all bits
if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= s_RX_DATA_BITS;
end
else
begin
r_Bit_Index <= 0;
r_SM_Main <= s_RX_STOP_BIT;
end
end
end // case: s_RX_DATA_BITS
// Receive Stop bit. Stop bit = 1
s_RX_STOP_BIT :
begin
// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= s_RX_STOP_BIT;
end
else
begin
r_Rx_DV <= 1'b1;
r_Clock_Count <= 0;
r_SM_Main <= s_CLEANUP;
end
end // case: s_RX_STOP_BIT
// Stay here 1 clock
s_CLEANUP :
begin
r_SM_Main <= s_IDLE;
r_Rx_DV <= 1'b0;
end
default :
r_SM_Main <= s_IDLE;
endcase
end
assign o_Rx_DV = r_Rx_DV;
assign o_Rx_Byte = r_Rx_Byte;
endmodule // uart_rx
rec
module uart_tx
#(parameter CLKS_PER_BIT)
(
input i_Clock,
input i_Tx_DV,
input [7:0] i_Tx_Byte,
output o_Tx_Active,
output reg o_Tx_Serial,
output o_Tx_Done
);
parameter s_IDLE = 3'b000;
parameter s_TX_START_BIT = 3'b001;
parameter s_TX_DATA_BITS = 3'b010;
parameter s_TX_STOP_BIT = 3'b011;
parameter s_CLEANUP = 3'b100;
reg [2:0] r_SM_Main = 0;
reg [7:0] r_Clock_Count = 0;
reg [2:0] r_Bit_Index = 0;
reg [7:0] r_Tx_Data = 0;
reg r_Tx_Done = 0;
reg r_Tx_Active = 0;
always @(posedge i_Clock)
begin
case (r_SM_Main)
s_IDLE :
begin
o_Tx_Serial <= 1'b1; // Drive Line High for Idle
r_Tx_Done <= 1'b0;
r_Clock_Count <= 0;
r_Bit_Index <= 0;
if (i_Tx_DV == 1'b1)
begin
r_Tx_Active <= 1'b1;
r_Tx_Data <= i_Tx_Byte;
r_SM_Main <= s_TX_START_BIT;
end
else
r_SM_Main <= s_IDLE;
end // case: s_IDLE
// Send out Start Bit. Start bit = 0
s_TX_START_BIT :
begin
o_Tx_Serial <= 1'b0;
// Wait CLKS_PER_BIT-1 clock cycles for start bit to finish
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= s_TX_START_BIT;
end
else
begin
r_Clock_Count <= 0;
r_SM_Main <= s_TX_DATA_BITS;
end
end // case: s_TX_START_BIT
// Wait CLKS_PER_BIT-1 clock cycles for data bits to finish
s_TX_DATA_BITS :
begin
o_Tx_Serial <= r_Tx_Data[r_Bit_Index];
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= s_TX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;
// Check if we have sent out all bits
if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= s_TX_DATA_BITS;
end
else
begin
r_Bit_Index <= 0;
r_SM_Main <= s_TX_STOP_BIT;
end
end
end // case: s_TX_DATA_BITS
// Send out Stop bit. Stop bit = 1
s_TX_STOP_BIT :
begin
o_Tx_Serial <= 1'b1;
// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= s_TX_STOP_BIT;
end
else
begin
r_Tx_Done <= 1'b1;
r_Clock_Count <= 0;
r_SM_Main <= s_CLEANUP;
r_Tx_Active <= 1'b0;
end
end // case: s_Tx_STOP_BIT
// Stay here 1 clock
s_CLEANUP :
begin
r_Tx_Done <= 1'b1;
r_SM_Main <= s_IDLE;
end
default :
r_SM_Main <= s_IDLE;
endcase
end
assign o_Tx_Active = r_Tx_Active;
assign o_Tx_Done = r_Tx_Done;
endmodule
module single_port_sync_ram
# (parameter ADDR_WIDTH = 4,
parameter DATA_WIDTH = 32,
parameter DEPTH = 16
)
( input clk,
input [ADDR_WIDTH-1:0] addr,
inout [DATA_WIDTH-1:0] data,
input cs,
input we,
input oe
);
reg [DATA_WIDTH-1:0] tmp_data;
reg [DATA_WIDTH-1:0] mem [DEPTH];
always @ (posedge clk) begin
if (cs & we)
mem[addr] <= data;
end
always @ (posedge clk) begin
if (cs & !we)
tmp_data <= mem[addr];
end
assign data = cs & oe & !wr ? tmp_data : 'hz;
endmodule
test bench
module tb;
parameter ADDR_WIDTH = 4;
parameter DATA_WIDTH = 16;
parameter DEPTH = 16;
reg clk;
reg cs;
reg we;
reg oe;
reg [ADDR_WIDTH-1:0] addr;
wire [DATA_WIDTH-1:0] data;
reg [DATA_WIDTH-1:0] tb_data;
single_port_sync_ram #(.DATA_WIDTH(DATA_WIDTH)) u0
( .clk(clk),
.addr(addr),
.data(data),
.cs(cs),
.we(we),
.oe(oe)
);
always #10 clk = ~clk;
assign data = !oe ? tb_data : 'hz;
initial begin
{clk, cs, we, addr, tb_data, oe} <= 0;
repeat (2) @ (posedge clk);
for (integer i = 0; i < 2**ADDR_WIDTH; i= i+1) begin
repeat (1) @(posedge clk) addr <= i; we <= 1; cs <=1; oe <= 0; tb_data <=
$random;
end
for (integer i = 0; i < 2**ADDR_WIDTH; i= i+1) begin
repeat (1) @(posedge clk) addr <= i; we <= 0; cs <= 1; oe <= 1;
end
#20 $finish;
end
endmodule
module serial_adder
( input clk,reset, //clock and reset
input a,b,cin, //note that cin is used for only first iteration.
output reg s,cout //note that s comes out at every clock cycle and cout is
valid only for last clock cycle.
);
reg c,flag;
always@(posedge clk or posedge reset)
begin
if(reset == 1) begin //active high reset
s = 0;
cout = c;
flag = 0;
end else begin
if(flag == 0) begin
c = cin; //on first iteration after reset, assign cin to c.
flag = 1; //then make flag 1, so that this if statement isnt executed
any more.
end
cout = 0;
s = a ^ b ^ c; //SUM
c = (a & b) | (c & b) | (a & c); //CARRY
end
end
endmodule
module add_sub_4 (A, B, In, Res, Out);
input [3:0] A, B;
input In;
output [3:0] Res;
output Out;
wire t1,t2,t3,t4,t5,t6,t7;
xor x3(t3,B[0],In);
xor x4(t4,B[1],In);
xor x5(t5,B[2],In);
xor x6(t6,B[3],In);
fadder f5(A[0],t3,In,Res[0],t1);
fadder f6(A[1],t4,t1,Res[1],t2);
fadder f7(A[2],t5,t2,Res[2],t3);
fadder f8(A[3],t6,t3,Res[3],Out);
endmodule
module fadder (A, B, Cin, Sum, Cout);
input A, B;
input Cin;
output Sum;
output Cout;
wire t1,t2,t3,t4;
xor x1(t1,A,B);
xor x2(Sum,t1,Cin);
and g1(t2,A,B);
and g2(t3,B,Cin);
and g3(t4,Cin,A);
or g4(Cout,t2,t3,t4);
endmodule
VHDL Program for BCD Adder using Parallel Adder.
1 module bcdas(s,c,a,b);
2 output [3:0]s;
3 output c;
4 input [3:0]a,b;
5 wire [3:0]x;
6 wire z,y,co,c1,k;
7 parad4 u1(x,c1,a,b);
8 and1 u2(y,x[3],x[2]);
9 and1 u3(z,x[1],x[3]);
10 or1 u4(k,z,y);
11 or1 u5(c,k,c1);
12 parad4 u6(s,co,x,{1'b0,c,c,1'b0});
13 endmodule
Verilog HDL Program for Serial Parallel Multiplier.
module spm(s,m,q);
1
output [7:0]s;
2
input [3:0]m,q;
3
and1 u1(s[0],m[0],q[0]);
4
and1 u2(s1,m[0],q[1]);
5
and1 u3(s2,m[0],q[2]);
6
and1 u4(s3,m[0],q[3]);
7
and1 u5(s4,m[1],q[0]);
8
and1 u6(s5,m[1],q[1]);
9
and1 u7(s6,m[1],q[2]);
10
and1 u8(s7,m[1],q[3]);
11
and1 u9(s8,m[2],q[0]);
12
and1 u10(s9,m[2],q[1]);
13
and1 u11(s10,m[2],q[2]);
14
and1 u12(s11,m[2],q[3]);
15
and1 u13(s12,m[3],q[0]);
16
and1 u14(s13,m[3],q[1]);
17
and1 u15(s14,m[3],q[2]);
18
and1 u16(s15,m[3],q[3]);
19
parad4 u21({s18,s17,s16,s[1]},c3,{s7,s6,s5,s4},{1'b0,s3,s2,s1});
20
parad4 u22({s21,s20,s19,s[2]},c7,{c3,s18,s17,s16},{s11,s10,s9,s8});
21
parad4 u23({s[6],s[5],s[4],s[3]},s[7],{c7,s21,s20,s19},
22
{s15,s14,s13,s12});
23
endmodule
24
25
module parad4(a,c,p,q); // Parallel Adder Module
26
output [3:0]a; output c; input [3:0]p,q; wire c1,c2,c3;
27
ha u1(a[0],c1,p[0],q[0]);
28
fa u2(a[1],c2,p[1],q[1],c1);
29
fa u3(a[2],c3,p[2],q[2],c2);
30
fa u4(a[3],c,p[3],q[3],c3);
31
endmodule
Verilog HDL Program for Serial Parallel Multiplier.
1 module spm(s,m,q);
2 output [7:0]s;
3 input [3:0]m,q;
4 and1 u1(s[0],m[0],q[0]);
5 and1 u2(s1,m[0],q[1]);
6 and1 u3(s2,m[0],q[2]);
7 and1 u4(s3,m[0],q[3]);
8 and1 u5(s4,m[1],q[0]);
9 and1 u6(s5,m[1],q[1]);
10 and1 u7(s6,m[1],q[2]);
11 and1 u8(s7,m[1],q[3]);
12 and1 u9(s8,m[2],q[0]);
13 and1 u10(s9,m[2],q[1]);
14 and1 u11(s10,m[2],q[2]);
15 and1 u12(s11,m[2],q[3]);
16 and1 u13(s12,m[3],q[0]);
17 and1 u14(s13,m[3],q[1]);
18 and1 u15(s14,m[3],q[2]);
19 and1 u16(s15,m[3],q[3]);
20 parad4 u21({s18,s17,s16,s[1]},c3,{s7,s6,s5,s4},{1'b0,s3,s2,s1});
21 parad4 u22({s21,s20,s19,s[2]},c7,{c3,s18,s17,s16},{s11,s10,s9,s8});
22 parad4 u23({s[6],s[5],s[4],s[3]},s[7],{c7,s21,s20,s19},{s15,s14,s13,s12});
23 endmodule
24
25 module parad4(a,c,p,q); // Parallel Adder Module
26 output [3:0]a; output c; input [3:0]p,q; wire c1,c2,c3;
27 ha u1(a[0],c1,p[0],q[0]);
28 fa u2(a[1],c2,p[1],q[1],c1);
29 fa u3(a[2],c3,p[2],q[2],c2);
30 fa u4(a[3],c,p[3],q[3],c3);
31 endmodule
module fsm(clock,reset,coin,vend,state,change);
\\these are the inputs and the outputs.
input clock;
input reset;
input [2:0]coin;
output vend;
output [2:0]state;
output [2:0]change;
\\i need to define the registers as change,coin and vend
reg vend;
reg [2:0]change;
wire [2:0]coin;
\\my coins are declared as parameters to make reading better.
parameter [2:0]NICKEL=3’b001;
parameter [2:0]DIME=3’b010;
parameter [2:0]NICKEL_DIME=3’b011;
parameter [2:0]DIME_DIME=3’b100;
parameter [2:0]QUARTER=3’b101;
\\MY STATES ARE ALSO PARAMETERS . I DONT WANT TO MAKE YOU READ
\\IN MACHINE LANGUAGE
parameter [2:0]IDLE=3’b000;
parameter [2:0]FIVE=3’b001;
parameter [2:0]TEN=3’b010;
parameter [2:0]FIFTEEN=3’b011;
parameter [2:0]TWENTY=3’b100;
parameter [2:0]TWENTYFIVE=3’b101;
\\AS ALWAYS THE STATES ARE DEFINED AS REG
reg [2:0]state,next_state;
\\MY MACHINE WORKS ON STATE AND COIN
always @(state or coin)
begin
next_state=0; \\VERYFIRST NEXT STATE IS GIVEN ZERO
case(state)
IDLE: case(coin) \\THIS IS THE IDLE STATE
NICKEL: next_state=FIVE;
DIME: next_state=TEN;
QUARTER: next_state=TWENTYFIVE;
default: next_state=IDLE;
endcase
FIVE: case(coin) \\THIS IS THE SECOND STATE
NICKEL: next_state=TEN;
DIME: next_state=FIFTEEN;
QUARTER: next_state=TWENTYFIVE; //change=NICKEL
default: next_state=FIVE;
endcase
TEN: case(coin) \\THIS IS THE THIRD STATE
NICKEL: next_state=FIFTEEN;
DIME: next_state=TWENTY;
QUARTER: next_state=TWENTYFIVE; //change=DIME
default: next_state=TEN;
endcase
FIFTEEN: case(coin) \\THIS IS THE FOURTH STATE
NICKEL: next_state=TWENTY;
DIME: next_state=TWENTYFIVE;
QUARTER: next_state=TWENTYFIVE; //change==NICKEL_DIME
default: next_state=FIFTEEN;
endcase
TWENTY: case(coin) \\THIS IS THE FIFTH STATE
NICKEL: next_state=TWENTYFIVE;
DIME: next_state=TWENTYFIVE; //change=NICKEL
QUARTER: next_state=TWENTYFIVE; //change==DIME_DIME
default: next_state=TWENTY;
endcase
TWENTYFIVE: next_state=IDLE; \\THE NEXT STATE HERE IS THE RESET
default : next_state=IDLE;
endcase
end
always @(clock)
begin \\WHENEVER I GIVE A RESET I HAVE TO MAKE THE STATE TO IDLE AND
VEND TO 1
if(reset) begin
state <= IDLE;
vend <= 1’b0;
// change <= 3’b000;
end \\THE CHANGE ALSO HAS TO BECOME NONE
else state <= next_state; case (state) \\HERE WE DECIDE THE NEXT STATE
\\ALL THE STATES ARE DEFINED HERE AND THE OUTPUT IS ALSO GIVEN
IDLE: begin vend <= 1’b0; change <=3’d0; end
FIVE: begin vend <= 1’b0; if (coin==QUARTER) change <=NICKEL; else change <=3’d0;
TEN: begin vend <= 1’b0; if (coin==QUARTER) change <=DIME; else change <= 3’d0;
FIFTEEN : begin vend <= 1’b0; if (coin==QUARTER) change <=NICKEL_DIME; else
change TWENTY : begin vend <= 1’b0; if (coin==DIME) change <=NICKEL; else if
(coin==QUARTER) TWENTYFIVE : begin vend <= 1’b1; change <=3’d0; end
default: state <= IDLE;
endcase
end
endmodule
