Tpa 3100 D 2

TPA3100D2
QFN HTQFP
www.ti.com SLOS469F – OCTOBER 2005 – REVISED AUGUST 2010
20-W STEREO CLASS-D AUDIO POWER AMPLIFIER

Check for Samples: TPA3100D2
1FEATURES APPLICATIONS
• 20-W/ch into an 8-Ω Load From a 18-V Supply • Televisions
• 10-W/ch into an 8-Ω Load From a 12-V Supply
• 15-W/ch into an 4-Ω Load From a 12-V Supply
DESCRIPTION
• Operates from 10 V to 26 V The TPA3100D2 is a 20-W (per channel) efficient,
Class-D audio power amplifier for driving bridged-tied
• 92% Efficient Class-D Operation Eliminates stereo speakers. The TPA3100D2 can drive stereo
Need for Heat Sinks speakers as low as 4 Ω. The high efficiency of the
• Four Selectable, Fixed Gain Settings TPA3100D2, 92%, eliminates the need for an
• Differential Inputs external heat sink when playing music.
• Thermal and Short-Circuit Protection With The gain of the amplifier is controlled by two gain
Auto Recovery Feature select pins. The gain selections are 20, 26, 32,
36 dB.
• Clock Output for Synchronization With
Multiple Class-D Devices The outputs are fully protected against shorts to
• Surface Mount 7 mm × 7 mm, 48-pin QFN GND, VCC, and output-to-output shorts with an auto
Package recovery feature and monitor output.
• Surface Mount 9 mm × 9 mm, 48-pin HTQFP
Package
Simplified Application Circuit

1 mF
TPA3100D2 0.22 mF
RINP BSRN
1 mF
ROUTN
TV Audio RINN
ROUTP
Processor 1 mF
LINN BSRP
1 mF 0.22 mF
VCLAMPR
LINP 1 mF
PGNDR
Shutdown SHUTDOWN 10 nF
Control
VREG
1 mF
Mute Control MUTE
VBYP
GAIN0 ROSC
Gain Select
GAIN1 100 kW
MSTR/SLV BSLN
Sync Control 0.22 mF
SYNC LOUTN
LOUTP
Fault Flag FAULT
PVCCR BSLP
0.22 mF
10 V to 26 V PVCCL VCLAMPL
AVCC 1 mF
PGNDL
AGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright © 2005–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPA3100D2
SLOS469F – OCTOBER 2005 – REVISED AUGUST 2010 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted) (1)
UNIT
VCC Supply voltage AVCC, PVCC –0.3 V to 30 V
SHUTDOWN, MUTE –0.3 V to VCC + 0.3 V
VI Input voltage GAIN0, GAIN1, RINN, RINP, LINN, LINP, MSTR/SLV,
–0.3 V to VREG + 0.5 V
SYNC
Continuous total power dissipation See Thermal Information Table
TA Operating free-air temperature range –40°C to 85°C
TJ Operating junction temperature range (2) –40°C to 150°C
Tstg Storage temperature range –65°C to 150°C
RLoad Load Resistance 3.2 Ω Minimum
(3)
Human body model (all pins) ±2 kV
(4)
Electrostatic discharge Machine model (all pins) ±200 V
(5)
Charged-device model (all pins) ±500 V
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operations of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The TPA3100D2 incorporates an exposed thermal pad on the underside of the chip. This acts as a heatsink, and it must be connected
to a thermally dissipating plane for proper power dissipation. Failure to do so may result in the device going into thermal protection
shutdown. See TI Technical Briefs SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical
Briefs SLMA002 for more information about using the HTQFP thermal pad.
(3) In accordance with JEDEC Standard 22, Test Method A114-B.
(4) In accordance with JEDEC Standard 22, Test Method A115-A
(5) In accordance with JEDEC Standard 22, Test Method C101-A
THERMAL INFORMATION
TPA3100D2
THERMAL METRIC (1) (2)
UNITS
RGZ (48 PINS) PHP (48 PINS)
qJA Junction-to-ambient thermal resistance 25 28.7
qJCtop Junction-to-case (top) thermal resistance 16.5 19.2
qJB Junction-to-board thermal resistance 12.8 12.4
°C/W
yJT Junction-to-top characterization parameter 0.2 0.2
yJB Junction-to-board characterization parameter 4.9 6.6
qJCbot Junction-to-case (bottom) thermal resistance 1.0 0.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
VCC Supply voltage PVCC, AVCC 10 26 V
SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV,
VIH High-level input voltage 2 V
SYNC
SHUTDOWN, MUTE, GAIN0, GAIN1, MSTR/SLV,
VIL Low-level input voltage 0.8 V
SYNC
2 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated
Product Folder Link(s): TPA3100D2

TPA3100D2
RECOMMENDED OPERATING CONDITIONS (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
SHUTDOWN, VI = VCC, VCC = 24 V 125
MUTE, VI = VCC, VCC = 24 V 75
IIH High-level input current µA
GAIN0, GAIN1, MSTR/SLV, SYNC, VI = VREG,
2
VCC = 24 V
SHUTDOWN, VI = 0, VCC = 24 V 2
IIL Low-level input current SYNC, MUTE, GAIN0, GAIN1, MSTR/SLV, VI = 0 1 µA
V, VCC = 24 V
VOH High-level output voltage FAULT, IOH = 1 mA VREG - 0.6 V
VOL Low-level output voltage FAULT, IOL = -1 mA AGND + 0.4 V
fOSC Oscillator frequency Rosc Resistor = 100 kΩ, MSTR/SLV = 2 V 200 300 kHz
TA Operating free-air temperature –40 85 °C
DC CHARACTERISTICS
TA = 25°C, VCC = 24 V, RL = 8 Ω (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Class-D output offset voltage (measured
| VOS | VI = 0 V, Gain = 36 dB 5 50 mV
differentially)
Bypass reference for input amplifier VBYP, no load 1.1 1.25 1.45 V
4-V internal supply voltage VREG, no load, VCC = 10 V to 26 V 3.75 4 4.25 V
VCC = 12 V to 24 V, inputs ac coupled to AGND,
PSRR DC Power supply rejection ratio -70 dB
Gain = 36 dB
ICC Quiescent supply current SHUTDOWN = 2 V, MUTE = 0 V, no load, filter, 22 26.5 mA
or snubber
ICC(SD) Quiescent supply current in shutdown mode SHUTDOWN = 0.8 V, no load, filter, or snubber 180 250 µA
ICC(MUTE) Quiescent supply current in mute mode MUTE = 2 V, no load, filter, or snubber 8 10 mA
High Side 200
VCC = 12 V, IO = 500 mA,
rDS(on) Drain-source on-state resistance Low side 200 mΩ
TJ = 25°C
Total 400 500
GAIN0 = 0.8 V 19 20 21
GAIN1 = 0.8 V dB
GAIN0 = 2 V 25 26 27
G Gain
GAIN0 = 0.8 V 31 32 33
GAIN1 = 2 V dB
GAIN0 = 2 V 35 36 37
Gain matching Between channels 2%
tON Turn-on time C(VBYP) = 1 µF, SHUTDOWN = 2 V 25 ms
tOFF Turn-off time C(VBYP) = 1 µF, SHUTDOWN = 0.8 V 0.1 ms
DC CHARACTERISTICS
Class-D output offset voltage (measured
| VOS | VI = 0 V, Gain = 36 dB 5 50 mV
differentially)
Bypass reference for input amplifier VBYP, no load 1.1 1.25 1.45 V
4-V internal supply voltage VREG, no load 3.75 4 4.25 V
VCC = 12 V to 24 V, Inputs ac coupled to AGND,
PSRR DC Power supply rejection ratio -70 dB
Gain = 36 dB
ICC Quiescent supply current SHUTDOWN = 2 V, MUTE = 0 V, no load, filter, 18 22.5 mA
or snubber
ICC(SD) Quiescent supply current in shutdown mode SHUTDOWN = 0.8 V, no load, filter, or snubber 80 200 µA
ICC(MUTE) Quiescent supply current in mute mode MUTE = 2 V, no load, filter, or snubber 7 9 mA
Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 3

TPA3100D2
DC CHARACTERISTICS (continued)
High Side 200
VCC = 12 V, IO = 500 mA,
rDS(on) Drain-source on-state resistance Low side 200 mΩ
TJ = 25°C
Total 400 500
GAIN0 = 0.8 V 19 20 21
GAIN1 = 0.8 V dB
GAIN0 = 2 V 25 26 27
G Gain
GAIN0 = 0.8 V 31 32 33
GAIN1 = 2 V dB
GAIN0 = 2 V 35 36 37
tON Turn-on time C(VBYP) = 1 µF, SHUTDOWN = 2 V 25 ms
tOFF Turn-off time C(VBYP) = 1 µF, SHUTDOWN = 0.8 V 0.1 ms
AC CHARACTERISTICS
200 mVPP ripple from 20 Hz–1 kHz,
KSVR Supply ripple rejection –70 dB
Gain = 20 dB, Inputs ac-coupled to AGND
THD+N = 7%, f = 1 kHz, VCC = 18 V 20.6 W
PO Continuous output power
THD+N = 10%, f = 1 kHz, VCC = 18 V 21.8 W
THD+N Total harmonic distortion + noise VCC = 18 V, f = 1 kHz, PO = 10 W (half-power) 0.11%
100 µV
Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
–80 dBV
Crosstalk VO = 1 Vrms, Gain = 20 dB, f = 1 kHz –92 dB
Maximum output at THD+N < 1%, f = 1 kHz,
SNR Signal-to-noise ratio 102 dB
Gain = 20 dB, A-weighted
Thermal trip point 150 °C
Thermal hysteresis 30 °C
AC CHARACTERISTICS
200 mVPP ripple from 20 Hz–1 kHz,
KSVR Supply ripple rejection –70 dB
Gain = 20 dB, Inputs ac-coupled to AGND
THD+N = 7%, f = 1 kHz 9.4
THD+N = 10%, f = 1 kHz 10
PO Continuous output power W
THD+N = 7%, f = 1 kHz, RL = 4 Ω 15.6
THD+N = 10%, f = 1 kHz, RL = 4 Ω 16.4
THD+N Total harmonic distortion + noise RL = 8 Ω, f = 1 kHz, PO = 5 W (half-power) 0.11%
RL = 4 Ω, f = 1 kHz, PO = 8 W (half-power) 0.15%
100 µV
Vn Output integrated noise 20 Hz to 22 kHz, A-weighted filter, Gain = 20 dB
–80 dBV
Crosstalk Po = 1 W, Gain = 20 dB, f = 1 kHz –94 dB
Maximum output at THD+N < 1%, f = 1 kHz,
SNR Signal-to-noise ratio 98 dB
Gain = 20 dB, A-weighted
Thermal trip point 150 °C
Thermal hysteresis 30 °C

TPA3100D2
48 PIN, QFN PACKAGE 48 PIN, HTQFP PACKAGE

(TOP VIEW) (TOP VIEW)
SHUTDOWN
SHUTDOWN
ROUTN
ROUTN
ROUTP
ROUTP
ROUTN
ROUTN
ROUTP
ROUTP
FAULT
FAULT
MUTE
BSRN
BSRP
AVCC
AVCC
MUTE
BSRN
BSRP
AVCC
GND
NC
NC
48 47 46 45 44 43 42 41 40 39 38 37 48 47 46 45 44 43 42 41 40 39 38 37
NC 1 36 NC GND 1 36 GND
RINN 2 35 PVCCR RINN 2 35 PVCCR
RINP 3 34 PVCCR RINP 3 34 PVCCR
AGND 4 33 PGNDR AGND 4 33 PGNDR
LINP 5 32 PGNDR LINP 5 32 PGNDR
LINN 6 Exposed 31 VCLAMPR
Thermal Pad LINN 6 Exposed 31 VCLAMPR
NC 7 30 VCLAMPL Thermal Pad
GAIN0 7 30 VCLAMPL
GAIN0 8 29 PGNDL
GAIN0 8 29 PGNDL
GAIN1 9 28 PGNDL
GAIN1 9 28 PGNDL
MSTR/SLV 10 27 PVCCL
MSTR/SLV 10 27 PVCCL
SYNC 11 26 PVCCL
SYNC 11 26 PVCCL
NC 12 25 NC
GND 12 25 GND
13 14 15 16 17 18 19 20 21 22 23 24
13 14 15 16 17 18 19 20 21 22 23 24
LOUTN
LOUTN
BSLN
VREG
NC
ROSC
NC
AGND
VBYP
BSLP
LOUTP
LOUTP
LOUTN
LOUTN
LOUTP
LOUTP
GND
GND
BSLN
AGND
VREG
ROSC
VBYP
BSLP
TERMINAL FUNCTIONS
TERMINAL
QFN HTQFP I/O DESCRIPTION
NAME
NO. NO.
Shutdown signal for IC (LOW = disabled, HIGH = operational). TTL logic
SHUTDOWN 44 44 I
levels with compliance to AVCC.
RINN 2 2 I Negative audio input for right channel. Biased at VREG/2.
RINP 3 3 I Positive audio input for right channel. Biased at VREG/2.
LINN 6 6 I Negative audio input for left channel. Biased at VREG/2.
LINP 5 5 I Positive audio input for left channel. Biased at VREG/2.
GAIN0 8 7, 8 I Gain select least significant bit. TTL logic levels with compliance to VREG.
GAIN1 9 9 I Gain select most significant bit. TTL logic levels with compliance to VREG.
1, 12, 13,
GND 24, 25, 36, Connect to the thermal pad.
37
Mute signal for quick disable/enable of outputs (HIGH = outputs high-Z,
MUTE 45 45 I
LOW = outputs enabled). TTL logic levels with compliance to AVCC.
TTL compatible output. HIGH = short-circuit fault. LOW = no fault. Only
FAULT 46 46 O
reports short-circuit faults. Thermal faults are not reported on this terminal.
BSLP 18 18 I/O Bootstrap I/O for left channel, positive high-side FET.
Power supply for left channel H-bridge, not internally connected to PVCCR
PVCCL 26, 27 26, 27
or AVCC.
LOUTP 19, 20 19, 20 O Class-D 1/2-H-bridge positive output for left channel.
PGNDL 28, 29 28, 29 Power ground for left channel H-bridge.
LOUTN 21, 22 21, 22 O Class-D 1/2-H-bridge negative output for left channel.
BSLN 23 23 I/O Bootstrap I/O for left channel, negative high-side FET.
VCLAMPL 30 30 Internally generated voltage supply for left channel bootstrap capacitor.
VCLAMPR 31 31 Internally generated voltage supply for right channel bootstrap capacitor.
BSRN 38 38 I/O Bootstrap I/O for right channel, negative high-side FET.
ROUTN 39, 40 39, 40 O Class-D 1/2-H-bridge negative output for right channel.
PGNDR 32, 33 32, 33 Power ground for right channel H-bridge.

TPA3100D2
TERMINAL FUNCTIONS (continued)

TERMINAL
QFN HTQFP I/O DESCRIPTION
NAME
NO. NO.
ROUTP 41, 42 41, 42 O Class-D 1/2-H-bridge positive output for right channel.
PVCCR 34, 35 34, 35 Power supply for right channel H-bridge, not connected to PVCCL or AVCC.
BSRP 43 43 I/O Bootstrap I/O for right channel, positive high-side FET.
AGND 4, 17 4, 17 Analog ground for digital/analog cells in core.
ROSC 14 14 I/O I/O for current setting resistor of ramp generator.
Master/Slave select for determining direction of SYNC terminal.
HIGH=Master mode, SYNC terminal is an output; LOW = slave mode,
MSTR/SLV 10 10 I
SYNC terminal accepts a clock input. TTL logic levels with compliance to
VREG.
Clock input/output for synchronizing multiple class-D devices. Direction
SYNC 11 11 I/O
determined by MSTR/SLV terminal. Input signal not to exceed VREG.
Reference for preamplifier. Nominally equal to 1.25 V. Also controls start-up
VBYP 16 16 O
time via external capacitor sizing.
4-V regulated output for use by internal cells, GAINx, MUTE, and
VREG 15 15 O
MSTR/SLV pins only. Not specified for driving other external circuitry.
High-voltage analog power supply. Not internally connected to PVCCR or
AVCC 48 47, 48
PVCCL.
1, 7, 12,
NC 13, 24, 25, Not internally connected.
36, 37, 47
Connect to AGND and PGND – should be star point for both grounds.
Internal resistive connection to AGND and PGND. Thermal vias on the PCB
Thermal Pad - - - should connect this pad to a large copper area on an internal or bottom
layer for the best thermal performance. The Thermal Pad must be soldered
to the PCB for mechanical reliability.

TPA3100D2
FUNCTIONAL BLOCK DIAGRAM
PVCCR
PVCCR
VCLAMPR
PVCCR
VBYP
BSRN
VBYP
AVCC
AVCC
Gain
Gate
Drive ROUTN
RINN VClamp
Gain PWM Gen
Control Logic PVCCR
RINP
VBYP
BSRP
Gate
To Gain Adj. Drive
GAIN0 Gain ROUTP
GAIN1 Control Blocks and
8 Startup Logic Gain
FAULT SC PGNDR
Detect
VBYP AVCC Thermal

ROSC VREG
Ramp Startup
SYNC Biases VREGok
Generator Protection PVCCL
and AVCC
Logic
MSTR/SLV References VCCok PVCCL
VREG
VREG 4V Reg
VCLAMPL
PVCCL
TLL Input
SHUTDOWN Buffer BSLN
(VCC Compliant)
TLL Input
MUTE Buffer Gate
Drive LOUTN
(VCC Compliant) Gain
VBYP VClamp
Gen PVCCL
LINN
Gain PWM BSLP
Control Logic
LINP
Gate
Drive LOUTP
Gain PGNDL
AGND
TYPICAL CHARACTERISTICS
Table 1. TABLE OF GRAPHS (1)

FIGURE
THD+N Total harmonic distortion + noise vs Frequency 1, 2, 3, 4
THD+N Total harmonic distortion + noise vs Output power 5, 6, 7, 8
Closed-loop response vs Frequency 9, 10
Output power vs Supply voltage 11. 12
Efficiency vs Output power 13, 14
VCC Supply current vs Total output power 15, 16
Crosstalk vs Frequency 17, 18
kSVR Supply ripple rejection ratio vs Frequency 19, 20
(1) All graphs were measured using the TPA3100D2 EVM.

TPA3100D2
TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

vs vs
FREQUENCY FREQUENCY
10 10
VCC = 12 V, VCC = 18 V,
THD+N - Total Harmonic Distortion + Noise - %

RL = 8 W, RL = 8 W,
Gain = 20 dB Gain = 20 dB
1 1
PO = 10 W
PO = 5 W
0.1 0.1
PO = 5 W
PO = 2.5 W
0.01 PO = 0.5 W 0.01 PO = 1 W
0.005 0.005
0.003 0.003
20 100 1k 10k 20k 20 100 1k 10k 20k
f - Frequency - Hz f - Frequency - Hz
Figure 1. Figure 2.

vs vs
FREQUENCY FREQUENCY
10 10
VCC = 24 V, VCC = 12 V,
RL = 8 W, RL = 4 W,
1 1 PO = 5 W
PO = 10 W
PO = 10 W
0.1 0.1
PO = 1 W
PO = 5 W
PO = 1 W
0.01 0.01
0.005 0.005
0.003 0.003
20 100 1k 10k 20k 20 100 1k 10k 20k
f - Frequency - Hz f - Frequency - Hz
Figure 3. Figure 4.

TPA3100D2

vs vs
OUTPUT POWER OUTPUT POWER
10 10 V = 18 V,

VCC = 12 V, CC
RL = 8 W, RL = 8 W,
1 1
10 kHz 10 kHz
0.1 0.1
0.05 0.05 1 kHz

1 kHz
20 Hz
0.02 20 Hz 0.02
0.01 0.01
10m 100m 200m 1 10 20 40 10m 100m 200m 1 10 20 40
PO - Output Power - W PO - Output Power - W
Figure 5. Figure 6.

vs vs
10 10
VCC = 12 V,
VCC = 24 V,
RL = 8 W, RL = 4 W,
1 1
10 kHz
10 kHz
0.1 0.1
0.05 0.05 1 kHz

1 kHz
0.02 20 Hz 0.02 20 kHz
0.01 0.01
10m 100m 200m 1 10 20 40 10m 100m 200m 1 10 20 40
PO - Output Power - W PO - Output Power - W
Figure 7. Figure 8.

TPA3100D2
CLOSED LOOP RESPONSE CLOSED LOOP RESPONSE

vs vs
FREQUENCY FREQUENCY
40 200 40 200
35 Gain 150 35 Gain 150
30 100 30 100
25 50 25 50
Gain − dB
Gain − dB
Phase − °
Phase − °
Phase Phase
20 0 20 0
15 VCC = 12 V −50 15 VCC = 24 V −50

RL = 8 W RL = 8 W
10 −100 10 −100
VI = 0.1 Vrms VI = 0.1 Vrms
CI = 10 mF CI = 10 mF
5 −150 5 −150
RC Filter = 100 W, 10 nF RC Filter = 100 W, 10 nF
0 −200 0 −200
10 100 1k 10k 100k 10 100 1k 10k 100k
f − Frequency − Hz f − Frequency − Hz
Figure 9. Figure 10.

vs vs
SUPPLY VOLTAGE SUPPLY VOLTAGE
50 35
RL = 8 W RL = 4 W
45
Gain = 20 dB 30 Gain = 20 dB
40
PO − Output Power − W
PO − Output Power − W
35 25
THD+N = 10%
30
20
25
THD+N = 10%
15
20
THD+N = 1%
THD+N = 1%
15 10
10 Power Represented by
Power Represented by 5 Dash Lines May Require
5 Dash Lines May Require More Heatsinking.
More Heatsinking.
0 0
10 12 14 16 18 20 22 24 26 28 10 11 12 13 14 15 16
VCC - Supply Voltage - V VCC − Supply Voltage − V

TPA3100D2
EFFICIENCY EFFICIENCY
vs vs
100 100
VCC = 12 V
90 90 VCC = 12 V
80 80
VCC = 18 V
70 70
Efficiency − %
Efficiency − %
60 60
VCC = 24 V
50 50
40 40
30 30
20 20
RL = 8 W RL = 4 Ω
10 Gain = 32 dB 10 Gain = 32 dB
0 0
0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 15
PO − Output Power (Per Channel) − W PO − Output Power (Per Channel) − W
SUPPLY CURRENT SUPPLY CURRENT

vs vs
TOTAL OUTPUT POWER TOTAL OUTPUT POWER
2.5 3.5
RL = 8 Ω RL = 4 Ω
Gain = 20 dB VCC = 18 V Gain = 20 dB
3
2
ICC − Supply Current − A
ICC − Supply Current − A
2.5
VCC = 12 V VCC = 12 V
1.5
2
VCC = 24 V 1.5
1
1
0.5
Power Represented by Power Represented by
0.5 Dash Lines May Require
Dash Lines May Require
More Heatsinking. More Heatsinking.
0 0
0 10 20 30 40 0 10 20 30 40
PO − Total Output Power − W PO − Total Output Power − W

TPA3100D2
CROSSTALK CROSSTALK
vs vs
FREQUENCY FREQUENCY
-40 -40
VCC = 12 V VCC = 24 V
RL = 8 Ω RL = 8 Ω
−60 −60
VO = 1 Vrms VO = 1 Vrms
L to R L to R
Crosstalk − dB
Crosstalk − dB
−80 −80
R to L R to L
−100 −100
−120 −120
−140 −140
20 100 1k 10k 20k 20 100 1k 10k 20k
SUPPLY RIPPLE REJECTION RATIO SUPPLY RIPPLE REJECTION RATIO

vs vs
FREQUENCY FREQUENCY
0 0
VCC = 12 V VCC = 18 V
kSVR − Supply Ripple Rejection Ratio − dB
kSVR − Supply Ripple Rejection Ratio − dB
−10 RL = 8 Ω −10 RL = 8 Ω
−20 −20
V(RIPPLE) = 200 mVPP V(RIPPLE) = 200 mVPP
−30 −30
−40 −40
−50 −50
−60 −60
−70 −70
−80 −80
−90 −90
−100 −100
20 100 1k 10k 20k 20 100 1k 10k 20k

TPA3100D2
APPLICATION INFORMATION
Shutdown
Fault Output
and Mute
Control
1 nF 33 mH
1 mF
20 W 8W
1 nF 1 mF
33 mH
20 W
10 V - 26 V
220nF 220nF
10 mF
1 mF
SHUTDOWN
FAULT
ROUTN
ROUTN
BSRN
MUTE
ROUTP
ROUTP
AVCC
BSRP
NC
NC
10 V - 26 V
NC NC
1 mF
RINN PVCCR
1 mF
220 mF
RINP PVCCR
Differential 1 mF
Analog AGND PGNDR
Inputs 1 mF
LINP PGNDR
1 mF
VCLAMPR
LINN
1 mF TPA3100D2 1 mF
NC VCLAMPL
GAIN0 PGNDL
4-Step
Gain Control
GAIN1 PGNDL
220 mF
MSTR/SLV PVCCL
Synchronize Multiple
Class-D Devices SYNC PVCCL
LOUTN
LOUTN
LOUTP
LOUTP
1 mF
AGND
ROSC
VREG
VBYP
BSLN
BSLP
NC NC
NC
NC 10 V - 26 V
100 kW 220nF 220nF
1 nF
10 nF
20 W
1 mF
1 nF 33 mH 1 mF
20 W 8W
1 mF
33 mH
Figure 21. Stereo Class-D With Differential Inputs (QFN)

TPA3100D2
Shutdown
Fault Output
and Mute
Control
1 nF 33 mH
1 mF
20 W 8W
1 nF 1 mF
33 mH
20 W
10 V - 26 V
220nF 220nF
10 mF
1 mF
SHUTDOWN
FAULT
ROUTN
ROUTN
BSRN
MUTE
ROUTP
ROUTP
AVCC
BSRP
NC
NC
10 V - 26 V
NC NC
1 mF
RINN PVCCR
1 mF
220 mF
RINP PVCCR
Single-Ended 1 mF
Analog AGND PGNDR
Inputs 1 mF
LINP PGNDR
1 mF
VCLAMPR
LINN
1 mF TPA3100D2 1 mF
NC VCLAMPL
GAIN0 PGNDL
4-Step
Gain Control
GAIN1 PGNDL
220 mF
MSTR/SLV PVCCL
Class-D Devices SYNC PVCCL
LOUTN
LOUTN
LOUTP
LOUTP
1 mF
AGND
ROSC
VREG
VBYP
BSLN
BSLP
NC NC
NC
NC
10 V - 26 V
100 kW
220nF 220nF
10 nF 1 nF
20 W
1 mF
1 nF 33 mH 1 mF
20 W 8W
1 mF
33 mH
Figure 22. Stereo Class-D With Single-Ended Inputs (QFN)

TPA3100D2
Shutdown
Fault Output
and Mute
Control
1 nF 33 mH
1 mF
20 W 8W
1 nF 1 mF
33 mH
20 W
10 V - 26 V
220nF 220nF
10 mF
1 mF
SHUTDOWN
FAULT
ROUTN
ROUTN
GND
BSRN
MUTE
ROUTP
ROUTP
AVCC
AVCC
BSRP
10 V - 26 V
GND GND
1 mF
RINN PVCCR
1 mF
220 mF
RINP PVCCR
Differential 1 mF
Analog AGND PGNDR
Inputs 1 mF
LINP PGNDR
1 mF
LINN
TPA3100D2 VCLAMPR
1 mF 1 mF
GAIN0 VCLAMPL
GAIN0 PGNDL
4-Step
Gain Control
GAIN1 PGNDL
220 mF
MSTR/SLV PVCCL
Class-D Devices SYNC
LOUTN
PVCCL
LOUTN
LOUTP
LOUTP
1 mF
AGND
ROSC
VREG
VBYP
BSLN
BSLP
GND
GND
GND GND
10 V - 26 V
100 kW
220nF 220nF
10 nF 1 nF
20 W
1 mF
1 nF 33 mH 1 mF
20 W 8W
1 mF
33 mH
Figure 23. Stereo Class-D With Differential Inputs (HTQFP)

TPA3100D2
Shutdown
Fault Output
and Mute
Control
1 nF 33 mH
1 mF
20 W 8W
1 nF 1 mF
33 mH
20 W
10 V - 26 V
220nF 220nF
10 mF
1 mF
SHUTDOWN
FAULT
ROUTN
ROUTN
GND
BSRN
MUTE
ROUTP
ROUTP
AVCC
AVCC
BSRP
10 V - 26 V
GND GND
1 mF
RINN PVCCR
1 mF
220 mF
RINP PVCCR
Single-Ended 1 mF
Analog AGND PGNDR
Inputs 1 mF
LINP PGNDR
1 mF
LINN
TPA3100D2 VCLAMPR
1 mF 1 mF
GAIN0 VCLAMPL
GAIN0 PGNDL
4-Step
Gain Control
GAIN1 PGNDL
220 mF
MSTR/SLV PVCCL
Class-D Devices SYNC
LOUTN
PVCCL
LOUTN
LOUTP
LOUTP
1 mF
AGND
ROSC
VREG
VBYP
BSLN
BSLP
GND
GND
GND GND
10 V - 26 V
100 kW
220nF 220nF
10 nF 1 nF
20 W
1 mF
1 nF 33 mH 1 mF
20 W 8W
1 mF
33 mH
Figure 24. Stereo Class-D With Single-Ended Inputs (HTQFP)

TPA3100D2
CLASS-D OPERATION
This section focuses on the class-D operation of the TPA3100D2.
Traditional Class-D Modulation Scheme

The traditional class-D modulation scheme, which is used in the TPA032D0x family, has a differential output
where each output is 180 degrees out of phase and changes from ground to the supply voltage, VCC. Therefore,
the differential prefiltered output varies between positive and negative VCC, where filtered 50% duty cycle yields
0 V across the load. The traditional class-D modulation scheme with voltage and current waveforms is shown in
Figure 25. Note that even at an average of 0 V across the load (50% duty cycle), the current to the load is high,
causing high loss and thus causing a high supply current.
OUTP
OUTN
+12 V
Differential Voltage
0V
Across Load
-12 V
Current
Figure 25. Traditional Class-D Modulation Scheme's Output Voltage and Current Waveforms into an
Inductive Load With No Input
TPA3100D2 Modulation Scheme

The TPA3100D2 uses a modulation scheme that still has each output switching from 0 to the supply voltage.
However, OUTP and OUTN are now in phase with each other with no input. The duty cycle of OUTP is greater
than 50% and OUTN is less than 50% for positive output voltages. The duty cycle of OUTP is less than 50% and
OUTN is greater than 50% for negative output voltages. The voltage across the load sits at 0 V throughout most
of the switching period, greatly reducing the switching current, which reduces any I2R losses in the load.

TPA3100D2
OUTP
OUTN
Output = 0 V
Differential +12 V
Voltage
0V
Across
Load -12 V
Current
OUTP
OUTN Output > 0 V
Differential +12 V
Voltage
0V
Across
-12 V
Load
Current
Figure 26. The TPA3100D2 Output Voltage and Current Waveforms Into an Inductive Load
Efficiency: LC Filter Required With the Traditional Class-D Modulation Scheme

The main reason that the traditional class-D amplifier needs an output filter is that the switching waveform results
in maximum current flow. This causes more loss in the load, which causes lower efficiency. The ripple current is
large for the traditional modulation scheme, because the ripple current is proportional to voltage multiplied by the
time at that voltage. The differential voltage swing is 2 x VCC, and the time at each voltage is half the period for
the traditional modulation scheme. An ideal LC filter is needed to store the ripple current from each half cycle for
the next half cycle, while any resistance causes power dissipation. The speaker is both resistive and reactive,
whereas an LC filter is almost purely reactive.
The TPA3100D2 modulation scheme has little loss in the load without a filter because the pulses are short and
the change in voltage is VCC instead of 2 x VCC. As the output power increases, the pulses widen, making the
ripple current larger. Ripple current could be filtered with an LC filter for increased efficiency, but for most
applications the filter is not needed.
An LC filter with a cutoff frequency less than the class-D switching frequency allows the switching current to flow
through the filter instead of the load. The filter has less resistance but higher impedance at the switching
frequency than the speaker, which results in less power dissipation, therefore increasing efficiency.
When to Use an Output Filter for EMI Suppression

Design the TPA3100D2 without the filter if the traces from amplifier to speaker are short (< 10 cm). Powered
speakers, where the speaker is in the same enclosure as the amplifier, is a typical application for class-D without
a filter.

TPA3100D2
Most applications require a ferrite bead filter. The ferrite filter reduces EMI around 1 MHz and higher (FCC and
CE only test radiated emissions greater than 30 MHz). When selecting a ferrite bead, choose one with high
impedance at high frequencies, but low impedance at low frequencies.
Use an LC output filter if there are low frequency (<1 MHz) EMI-sensitive circuits and/or there are long wires
from the amplifier to the speaker.
When both an LC filter and a ferrite bead filter are used, the LC filter should be placed as close as possible to
the IC followed by the ferrite bead filter.
33 mH
OUTP
C2
L1
1 mF
33 mH
OUTN
C3
L2
1 mF
Figure 27. Typical LC Output Filter, Cutoff Frequency of 28 kHz, Speaker Impedance = 8 Ω
15 mH
OUTP
L1 C2
2.2 mF
15 mH
OUTN
L2 C3
2.2 mF
Figure 28. Typical LC Output Filter, Cutoff Frequency of 28 kHz, Speaker Impedance = 4 Ω
Ferrite
Chip Bead
OUTP
1 nF
Ferrite
Chip Bead
OUTN
1 nF
Figure 29. Typical Ferrite Chip Bead Filter (Chip Bead Example: Fair-Rite 2512067007Y3)

TPA3100D2
Using the LC filter in Figure 27, the TPA3100D2 EMI EVM passed the FCC Part 15 Class B radiated emissions
with 21-inch speaker wires. Quasi-peak measurements were taken for the 4 standard test configurations, and the
TPA3100D2 EVM passed with at least 17-dB margin. A plot of the peak measurement for the horizontal rear
configuration is shown in Figure 30.
National Technical Systems, Plano TX
Radiated Emissions 30 MHz - 1000 MHz
FCC B
70
60
FCC B Limit
Limit Level - dB(mV/m)
50
40
30
Peak dB
20
20
0
30 M 230 M 430 M 630 M 830 M
f - Frequency - Hz
Figure 30. Radiated Emissions Prescan 30 MHz - 1000 MHz
Inductors used in LC filters must be chosen carefully. A significant change in inductance at the peak output
current of the TPA3100D2 will cause increased distortion. The change of inductance at currents up to the peak
output current must be less than 0.1 mH per amp to avoid this distortion. Also note that smaller inductors than 33
mH may cause an increase in distortion above what is shown in the preceding graphs of THD versus frequency
and output power.
Capacitors used in LC filters must also be chosen carefully. A significant change in capacitance at the peak
output voltage of the TPA3100D2 will cause increased distortion. LC filter capacitors should have DC voltage
ratings at least twice the peak application voltage (the power supply voltage) and should be made of X5R or
better material. In all cases avoid using capacitors with loose temperature ratings, like Y5V.

TPA3100D2
Adaptive Dynamic Range Control
TPA3100D2 TPA3100D2
V - Voltage = 10 V/div
V - Voltage = 1 V/div
Closest Competitor Closest Competitor
t - Time = 100 ms/div t - Time = 20 ms/div
Figure 31. 1-kHz Sine Output at 10% THD+N Figure 32. 8-kHz Sine Output at 10% THD+N
The Texas Instruments patent-pending adaptive dynamic range control (ADRC) technology removes the notch
inherent in class-D audio power amplifiers when they come out of clipping. This effect is more severe at higher
frequencies as shown in Figure 32.
Gain setting via GAIN0 and GAIN1 inputs

The gain of the TPA3100D2 is set by two input terminals, GAIN0 and GAIN1.
The gains listed in Table 2 are realized by changing the taps on the input resistors and feedback resistors inside
the amplifier. This causes the input impedance (ZI) to be dependent on the gain setting. The actual gain settings
are controlled by ratios of resistors, so the gain variation from part-to-part is small. However, the input impedance
from part-to-part at the same gain may shift by ±20% due to shifts in the actual resistance of the input resistors.
For design purposes, the input network (discussed in the next section) should be designed assuming an input
impedance of 12.8 kΩ, which is the absolute minimum input impedance of the TPA3100D2. At the lower gain
settings, the input impedance could increase as high as 38.4 kΩ
Table 2. Gain Setting

INPUT IMPEDANCE
AMPLIFIER GAIN (dB)
GAIN1 GAIN0 (kΩ)
TYP TYP
0 0 20 32
0 1 26 16
1 0 32 16
1 1 36 16
INPUT RESISTANCE
Changing the gain setting can vary the input resistance of the amplifier from its smallest value, 16 kΩ ±20%, to
the largest value, 32 kΩ ±20%. As a result, if a single capacitor is used in the input high-pass filter, the -3 dB or
cutoff frequency may change when changing gain steps.

TPA3100D2
Zf
Ci
Zi
Input IN
Signal
The -3-dB frequency can be calculated using Equation 1. Use the ZI values given in Table 2.
1
f =
2p Zi Ci (1)
INPUT CAPACITOR, CI
In the typical application, an input capacitor (CI) is required to allow the amplifier to bias the input signal to the
proper dc level for optimum operation. In this case, CI and the input impedance of the amplifier (ZI) form a
high-pass filter with the corner frequency determined in Equation 2.
-3 dB
1
fc =
2p Zi Ci
fc (2)
The value of CI is important, as it directly affects the bass (low-frequency) performance of the circuit. Consider
the example where ZI is 20 kΩ and the specification calls for a flat bass response down to 20 Hz. Equation 2 is
reconfigured as Equation 3.
1
Ci =
2p Zi fc (3)
In this example, CI is 0.4 µF; so, one would likely choose a value of 0.47 mF as this value is commonly used. If
the gain is known and is constant, use ZI from Table 2 to calculate CI. A further consideration for this capacitor is
the leakage path from the input source through the input network (CI) and the feedback network to the load. This
leakage current creates a dc offset voltage at the input to the amplifier that reduces useful headroom, especially
in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When
polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most
applications as the dc level there is held at 2 V, which is likely higher than the source dc level. Note that it is
important to confirm the capacitor polarity in the application. Additionally, lead-free solder can create dc offset
voltages and it is important to ensure that boards are cleaned properly.
Power Supply Decoupling, CS

The TPA3100D2 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling
to ensure that the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also
prevents oscillations for long lead lengths between the amplifier and the speaker. The optimum decoupling is
achieved by using two capacitors of different types that target different types of noise on the power supply leads.
For higher frequency transients, spikes, or digital hash on the line, a good low equivalent-series-resistance (ESR)
ceramic capacitor, typically 0.1 mF to 1 µF placed as close as possible to the device VCC lead works best. For
filtering lower frequency noise signals, a larger aluminum electrolytic capacitor of 220 mF or greater placed near
the audio power amplifier is recommended. The 220 mF capacitor also serves as local storage capacitor for
supplying current during large signal transients on the amplifier outputs. The PVCC terminals provide the power
to the output transistors, so a 220 µF or larger capacitor should be placed on each PVCC terminal. A 10 µF
capacitor on the AVCC terminal is adequate.

TPA3100D2
IC Output Snubbers
1-nF capacitors in series with 20-Ω resistors from the outputs of the TPA3100D2 IC to ground are switching
snubbers. These are illustrated in Figure 33. They linearize switching transitions and reduce overshoot and
ringing. By doing so they improve THD+N, reducing it by a factor near 3 at 1kHz, 1W; and they improve EMC by
2 to 6 dB at middle frequencies. They increase quiescent current by 5 to 15 mA depending on power supply
voltage.
OUTP
OUTN
1 nF 1 nF
20 W 20 W
Figure 33. IC Output Snubbers
BSN and BSP Capacitors

The full H-bridge output stages use only NMOS transistors. Therefore, they require bootstrap capacitors for the
high side of each output to turn on correctly. A 220-nF ceramic capacitor, rated for at least 25 V, must be
connected from each output to its corresponding bootstrap input. Specifically, one 220-nF capacitor must be
connected from xOUTP to BSxx, and one 220-nF capacitor must be connected from xOUTN to BSxx. (See the
application circuit diagram in Figure 21.)
The bootstrap capacitors connected between the BSxx pins and corresponding output function as a floating
power supply for the high-side N-channel power MOSFET gate drive circuitry. During each high-side switching
cycle, the bootstrap capacitors hold the gate-to-source voltage high enough to keep the high-side MOSFETs
turned on.
VCLAMP Capacitors
To ensure that the maximum gate-to-source voltage for the NMOS output transistors is not exceeded, two
internal regulators clamp the gate voltage. Two 1-mF capacitors must be connected from VCLAMPL (pin 30) and
VCLAMPR (pin 31) to ground and must be rated for at least 16 V. The voltages at the VCLAMP terminals may
vary with VCC and may not be used for powering any other circuitry.
Internal Regulated 4-V Supply (VREG)

The VREG terminal (pin 15) is the output of an internally generated 4-V supply, used for the oscillator,
preamplifier, and gain control circuitry. It requires a 10-nF capacitor, placed close to the pin, to keep the regulator
stable.
This regulated voltage can be used to control GAIN0, GAIN1, MSTR/SLV, and MUTE terminals, but should not
be used to drive external circuitry.
VBYP Capacitor Selection

The internal bias generator (VBYP) nominally provides a 1.25-V internal bias for the preamplifier stages. The
external input capacitors and this internal reference allow the inputs to be biased within the optimal
common-mode range of the input preamplifiers.
The selection of the capacitor value on the VBYP terminal is critical for achieving the best device performance.
During power up or recovery from the shutdown state, the VBYP capacitor determines the rate at which the
amplifier starts up. When the voltage on the VBYP capacitor equals VBYP, the device starts a 16.4-ms timer.
When this timer completes, the outputs start switching. The charge rate of the capacitor is calculated using the
standard charging formula for a capacitor, I = C x dV/dT. The charge current is nominally equal to 250µA and dV
is equal to VBYP. For example, a 1-µF capacitor on VBYP would take 5 ms to reach the value of VBYP and
begin a 16.4-ms count before the outputs turn on. This equates to a turn-on time of <30 ms for a 1-µF capacitor
on the VBYP terminal.
TPA3100D2
A secondary function of the VBYP capacitor is to filter high-frequency noise on the internal 1.25-V bias generator.
A value of at least 0.47µF is recommended for the VBYP capacitor. For the best power-up and shutdown pop
performance, the VBYP capacitor should be greater than or equal to the input capacitors.
ROSC Resistor Selection

The resistor connected to the ROSC terminal controls the class-D output switching frequency using Equation 4:
1
FOSC =
2 x ROSC x COSC (4)
COSC is an internal capacitor that is nominally equal to 20 pF. Variation over process and temperature can
result in a ±15% change in this capacitor value.
For example, if ROSC is fixed at 100 kΩ, the frequency from device to device with this fixed resistance could
vary from 217 kHz to 294 kHz with a 15% variation in the internal COSC capacitor. The tolerance of the ROSC
resistor should also be considered to determine the range of expected switching frequencies from device to
device. It is recommended that 1% tolerance resistors be used.
Differential Input
The differential input stage of the amplifier cancels any noise that appears on both input lines of the channel. To
use the TPA3100D2 with a differential source, connect the positive lead of the audio source to the INP input and
the negative lead from the audio source to the INN input. To use the TPA3100D2 with a single-ended source, ac
ground the INP or INN input through a capacitor equal in value to the input capacitor on INN or INP and apply
the audio source to either input. In a single-ended input application, the unused input should be ac grounded at
the audio source instead of at the device input for best noise performance.
SHUTDOWN OPERATION
The TPA3100D2 employs a shutdown mode of operation designed to reduce supply current (ICC) to the absolute
minimum level during periods of nonuse for power conservation. The SHUTDOWN input terminal should be held
high (see specification table for trip point) during normal operation when the amplifier is in use. Pulling
SHUTDOWN low causes the outputs to mute and the amplifier to enter a low-current state. Never leave
SHUTDOWN unconnected, because amplifier operation would be unpredictable.
For the best power-off pop performance, place the amplifier in the shutdown or mute mode prior to removing the
power supply voltage.
MUTE Operation
The MUTE pin is an input for controlling the output state of the TPA3100D2. A logic high on this terminal
disables the outputs. A logic low on this pin enables the outputs. This terminal may be used as a quick
disable/enable of outputs when changing channels on a television or transitioning between different audio
sources.
The MUTE terminal should never be left floating. For power conservation, the SHUTDOWN terminal should be
used to reduce the quiescent current to the absolute minimum level.
The MUTE terminal can also be used with the FAULT output to automatically recover from a short-circuit event.
When a short-circuit event occurs, the FAULT terminal transitions high indicating a short-circuit has been
detected. When directly connected to MUTE, the MUTE terminal transitions high, and clears the internal fault
flag. This causes the FAULT terminal to cycle low, and normal device operation resumes if the short-circuit is
removed from the output. If a short remains at the output, the cycle continues until the short is removed.
If external MUTE control is desired, and automatic recovery from a short-circuit event is also desired, an OR gate
can be used to combine the functionality of the FAULT output and external MUTE control, see Figure 34.

TPA3100D2
TPA3100D2
External GPIO
Control
MUTE
FAULT
Figure 34. External MUTE Control
MSTR/SLV and SYNC operation

The MSTR/SLV and SYNC terminals can be used to synchronize the frequency of the class-D output switching.
When the MSTR/SLV terminal is high, the output switching frequency is determined by the selection of the
resistor connected to the ROSC terminal (see ROSC Resistor Selection). The SYNC terminal becomes an output
in this mode, and the frequency of this output is also determined by the selection of the ROSC resistor. This TTL
compatible, push-pull output can be connected to another TPA3100D2, configured in the slave mode. The output
switching is synchronized to avoid any beat frequencies that could occur in the audio band when two class-D
amplifiers in the same system are switching at slightly different frequencies.
When the MSTR/SLV terminal is low, the output switching frequency is determined by the incoming square wave
on the SYNC input. The SYNC terminal becomes an input in this mode and accepts a TTL compatible square
wave from another TPA3100D2 configured in the master mode or from an external GPIO. If connecting to an
external GPIO, recommended frequencies are 200 kHz to 300 kHz for proper device operation, and the
maximum amplitude is 4 V.
USING LOW-ESR CAPACITORS

Low-ESR capacitors are recommended throughout this application section. A real (as opposed to ideal) capacitor
can be modeled simply as a resistor in series with an ideal capacitor. The voltage drop across this resistor
minimizes the beneficial effects of the capacitor in the circuit. The lower the equivalent value of this resistance,
the more the real capacitor behaves like an ideal capacitor.
SHORT-CIRCUIT PROTECTION AND AUTOMATIC RECOVERY FEATURE

The TPA3100D2 has short-circuit protection circuitry on the outputs that prevents damage to the device during
output-to-output shorts, output-to-GND shorts, and output-to-VCC shorts. When a short circuit is detected on the
outputs, the part immediately disables the output drive. This is a latched fault and must be reset by cycling the
voltage on the SHUTDOWN pin or MUTE pin. This clears the short-circuit flag and allows for normal operation if
the short was removed. If the short was not removed, the protection circuitry again activates.
The FAULT terminal can be used for automatic recovery from a short-circuit event, or used to monitor the status
with an external GPIO. For automatic recovery from a short-circuit event, connect the FAULT terminal directly to
the MUTE terminal. When a short-circuit event occurs, the FAULT terminal transitions high indicating a
short-circuit has been detected. When directly connected to MUTE, the MUTE terminal transitions high, and
clears the internal fault flag. This causes the FAULT terminal to cycle low, and normal device operation resumes
if the short-circuit is removed from the output. If a short remains at the output, the cycle continues until the short
is removed. If external MUTE control is desired, and automatic recovery from a short-circuit event is also desired,
an OR gate can be used to combine the functionality of the FAULT output and external MUTE control, see
Figure 34.

TPA3100D2
THERMAL PROTECTION
Thermal protection on the TPA3100D2 prevents damage to the device when the internal die temperature
exceeds 150°C. There is a ±15°C tolerance on this trip point from device to device. Once the die temperature
exceeds the thermal set point, the device enters into the shutdown state and the outputs are disabled. This is not
a latched fault. The thermal fault is cleared once the temperature of the die is reduced by 30°C. The device
begins normal operation at this point with no external system interaction.
PRINTED-CIRCUIT BOARD (PCB) LAYOUT

Because the TPA3100D2 is a class-D amplifier that switches at a high frequency, the layout of the printed-circuit
board (PCB) should be optimized according to the following guidelines for the best possible performance.
• Decoupling capacitors—The high-frequency 1µF decoupling capacitors should be placed as close to the
PVCC (pins 26, 27, 34, and 35) and AVCC (pin 48) terminals as possible. The VBYP (pin 16) capacitor,
VREG (pin 15) capacitor, and VCLAMP (pins 30 and 31) capacitor should also be placed as close to the
device as possible. Large (220 µF or greater) bulk power supply decoupling capacitors should be placed near
the TPA3100D2 on the PVCCL, PVCCR, and AVCC terminals.
• Grounding—The AVCC (pin 48) decoupling capacitor, VREG (pin 15) capacitor, VBYP (pin 16) capacitor, and
ROSC (pin 14) resistor should each be grounded to analog ground (AGND, pin 17). The PVCC decoupling
capacitors and VCLAMP capacitors should each be grounded to power ground (PGND, pins 28, 29, 32, and
33). Analog ground and power ground should be connected at the thermal pad, which should be used as a
central ground connection or star ground for the TPA3100D2.
• Output filter—The ferrite EMI filter (Figure 29) should be placed as close to the output terminals as possible
for the best EMI performance. The LC filter (Figure 27 and Figure 28) should be placed close to the outputs.
The capacitors used in both the ferrite and LC filters should be grounded to power ground. If both filters are
used, the LC filter should be placed first, following the outputs.
• Thermal Pad—The thermal pad must be soldered to the PCB for proper thermal performance and optimal
reliability. The dimensions of the thermal pad and thermal land should be 5,1 mm by 5,1 mm. Five rows of
solid vias (five vias per row, 0,3302 mm or 13 mils diameter) should be equally spaced underneath the
thermal land. The vias should connect to a solid copper plane, either on an internal layer or on the bottom
layer of the PCB. The vias must be solid vias, not thermal relief or webbed vias. See TI Technical Briefs
SCBA017D and SLUA271 for more information about using the QFN thermal pad. See TI Technical Briefs
SLMA002 for more information about using the HTQFP thermal pad. For recommended PCB footprints, see
figures at the end of this data sheet.
For an example layout, see the TPA3100D2 Evaluation Module (TPA3100D2EVM) User Manual, (SLOU179).
Both the EVM user manual and the thermal pad application note are available on the TI Web site at
http://www.ti.com.
BASIC MEASUREMENT SYSTEM

This application note focuses on methods that use the basic equipment listed below:
• Audio analyzer or spectrum analyzer
• Digital multimeter (DMM)
• Oscilloscope
• Twisted-pair wires
• Signal generator
• Power resistor(s)
• Linear regulated power supply
• Filter components
• EVM or other complete audio circuit
Figure 35 shows the block diagrams of basic measurement systems for class-AB and class-D amplifiers. A sine
wave is normally used as the input signal because it consists of the fundamental frequency only (no other
harmonics are present). An analyzer is then connected to the APA output to measure the voltage output. The
analyzer must be capable of measuring the entire audio bandwidth. A regulated dc power supply is used to
reduce the noise and distortion injected into the APA through the power pins. A System Two audio measurement
system (AP-II) (Reference 1) by Audio Precision includes the signal generator and analyzer in one package.

TPA3100D2
The generator output and amplifier input must be ac-coupled. However, the EVMs already have the ac-coupling
capacitors, (CIN), so no additional coupling is required. The generator output impedance should be low to avoid
attenuating the test signal, and is important because the input resistance of APAs is not high. Conversely, the
analyzer-input impedance should be high. The output resistance, ROUT, of the APA is normally in the hundreds of
milliohms and can be ignored for all but the power-related calculations.
Figure 35(a) shows a class-AB amplifier system. It takes an analog signal input and produces an analog signal
output. This amplifier circuit can be directly connected to the AP-II or other analyzer input.
This is not true of the class-D amplifier system shown in Figure 35(b), which requires low-pass filters in most
cases in order to measure the audio output waveforms. This is because it takes an analog input signal and
converts it into a pulse-width modulated (PWM) output signal that is not accurately processed by some
analyzers.
Power Supply
Signal APA RL Analyzer

Generator 20 Hz - 20 kHz
(a) Basic Class-AB
Power Supply
Low-Pass RC
Filter
Signal Class-D APA RL Analyzer
Generator (See note A) 20 Hz - 20 kHz
Low-Pass RC
Filter
(b) Filter-Free and Traditional Class-D

A. For efficiency measurements with filter-free Class-D, RL should be an inductive load like a speaker.
Figure 35. Audio Measurement Systems
The TPA3100D2 uses a modulation scheme that does not require an output filter for operation, but they do
sometimes require an RC low-pass filter when making measurements. This is because some analyzer inputs
cannot accurately process the rapidly changing square-wave output and therefore record an extremely high level
of distortion. The RC low-pass measurement filter is used to remove the modulated waveforms so the analyzer
can measure the output sine wave.

TPA3100D2
DIFFERENTIAL INPUT AND BTL OUTPUT

All of the class-D APAs and many class-AB APAs have differential inputs and bridge-tied load (BTL) outputs.
Differential inputs have two input pins per channel and amplify the difference in voltage between the pins.
Differential inputs reduce the common-mode noise and distortion of the input circuit. BTL is a term commonly
used in audio to describe differential outputs. BTL outputs have two output pins providing voltages that are 180
degrees out of phase. The load is connected between these pins. This has the added benefits of quadrupling the
output power to the load and eliminating a dc blocking capacitor.
A block diagram of the measurement circuit is shown in Figure 36. The differential input is a balanced input,
meaning the positive (+) and negative (-) pins have the same impedance to ground. Similarly, the BTL output
equates to a balanced output.
Evaluation Module
Audio Power
Generator Analyzer
Amplifier
CIN Low-Pass
RC Filter
RGEN RIN ROUT RANA CANA
VGEN RL
CIN
Low-Pass
RGEN RIN ROUT RC Filter RANA CANA
Twisted-Pair Wire Twisted-Pair Wire
Figure 36. Differential Input, BTL Output Measurement Circuit
The generator should have balanced outputs, and the signal should be balanced for best results. An unbalanced
output can be used, but it may create a ground loop that affects the measurement accuracy. The analyzer must
also have balanced inputs for the system to be fully balanced, thereby cancelling out any common-mode noise in
the circuit and providing the most accurate measurement.
The following general rules should be followed when connecting to APAs with differential inputs and BTL outputs:
• Use a balanced source to supply the input signal.
• Use an analyzer with balanced inputs.
• Use twisted-pair wire for all connections.
• Use shielding when the system environment is noisy.
• Ensure that the cables from the power supply to the APA, and from the APA to the load, can handle the large
currents (see Table 3).
Table 3 shows the recommended wire size for the power supply and load cables of the APA system. The real
concern is the dc or ac power loss that occurs as the current flows through the cable. These recommendations
are based on 12-inch long wire with a 20-kHz sine-wave signal at 25°C.
Table 3. Recommended Minimum Wire Size for Power Cables

DC POWER LOSS AC POWER LOSS
POUT (W) RL(Ω) AWG Size
(MW) (MW)
10 4 18 22 16 40 18 42
2 4 18 22 3.2 8 3.7 8.5
1 8 22 28 2 8 2.1 8.1
< 0.75 8 22 28 1.5 6.1 1.6 6.2

TPA3100D2
CLASS-D RC LOW-PASS FILTER

An RC filter is used to reduce the square-wave output when the analyzer inputs cannot process the pulse-width
modulated class-D output waveform. This filter has little effect on the measurement accuracy because the cutoff
frequency is set above the audio band. The high frequency of the square wave has negligible impact on
measurement accuracy because it is well above the audible frequency range, and the speaker cone cannot
respond at such a fast rate. The RC filter is not required when an LC low-pass filter is used, such as with the
class-D APAs that employ the traditional modulation scheme (TPA032D0x, TPA005Dxx).
The component values of the RC filter are selected using the equivalent output circuit as shown in Figure 37. RL
is the load impedance that the APA is driving for the test. The analyzer input impedance specifications should be
available and substituted for RANA and CANA. The filter components, RFILT and CFILT, can then be derived for the
system. The filter should be grounded to the APA near the output ground pins or at the power supply ground pin
to minimize ground loops.
Load RC Low-Pass Filters AP Analyzer Input

RFILT
CFILT CANA RANA
RL VL= VIN
VOUT
RFILT
CFILT CANA RANA
To APA
GND
Figure 37. Measurement Low-Pass Filter Derivation Circuit-Class-D APAs
The transfer function for this circuit is shown in Equation 5 where wO = REQCEQ, REQ = RFILT || RANA and
CEQ = (CFILT + CANA). The filter frequency should be set above fMAX, the highest frequency of the measurement
bandwidth, to avoid attenuating the audio signal. Equation 6 provides this cutoff frequency, fC. The value of RFILT
must be chosen large enough to minimize current that is shunted from the load, yet small enough to minimize the
attenuation of the analyzer-input voltage through the voltage divider formed by RFILT and RANA. A general rule is
that RFILT should be small (~100 Ω) for most measurements. This reduces the measurement error to less than
1% for RANA ≥ 10 kΩ.
( RANA
)
( )
VOUT
VIN
=
RANA + RFILT
1 + j ( )w
wO
(5)
fc = Ö2 x fmax (6)
An exception occurs with the efficiency measurements, where RFILT must be increased by a factor of ten to
reduce the current shunted through the filter. CFILT must be decreased by a factor of ten to maintain the same
cutoff frequency. See Table 4 for the recommended filter component values.
Once fC is determined and RFILT is selected, the filter capacitance is calculated using Equation 7. When the
calculated value is not available, it is better to choose a smaller capacitance value to keep fC above the minimum
desired value calculated in Equation 7.
1
CFILT =
2p x fc x RFILT (7)

TPA3100D2
Table 4 shows recommended values of RFILT and CFILT based on common component values. The value of fC
was originally calculated to be 28 kHz for an fMAX of 20 kHz. CFILT, however, was calculated to be 57,000 pF, but
the nearest values of 56,000 pF and 51,000 pF were not available. A 47,000-pF capacitor was used instead, and
fC is 34 kHz, which is above the desired value of 28 kHz.
Table 4. Typical RC Measurement Filter Values

MEASUREMENT RFILT CFILT
Efficiency 1000 Ω 5,600 pF
All other measurements 100 Ω 56,000 pF
spacer
REVISION HISTORY
Changes from Revision E (May 2007) to Revision F Page
• Replaced the TYPICAL DISSIPATION RATINGS table with the Thermal Inforamtion table ............................................... 2

PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2022
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
TPA3100D2PHP ACTIVE HTQFP PHP 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 TPA3100D2 Samples
TPA3100D2PHPG4 ACTIVE HTQFP PHP 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 TPA3100D2 Samples
TPA3100D2PHPR ACTIVE HTQFP PHP 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 TPA3100D2 Samples
TPA3100D2PHPRG4 ACTIVE HTQFP PHP 48 1000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 TPA3100D2 Samples
TPA3100D2RGZR ACTIVE VQFN RGZ 48 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 TPA Samples
3100D2
TPA3100D2RGZT ACTIVE VQFN RGZ 48 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 TPA Samples
3100D2
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 14-Oct-2022
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPA3100D2 :
• Automotive : TPA3100D2-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Feb-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPA3100D2PHPR HTQFP PHP 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
TPA3100D2RGZR VQFN RGZ 48 2500 330.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
TPA3100D2RGZT VQFN RGZ 48 250 180.0 16.4 7.3 7.3 1.5 12.0 16.0 Q2
Pack Materials-Page 1
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPA3100D2PHPR HTQFP PHP 48 1000 350.0 350.0 43.0
TPA3100D2RGZR VQFN RGZ 48 2500 356.0 356.0 35.0
TPA3100D2RGZT VQFN RGZ 48 250 210.0 185.0 35.0
TRAY
L - Outer tray length without tabs KO -

Outer
tray
height
W-
Outer
tray
width
Text
P1 - Tray unit pocket pitch

CW - Measurement for tray edge (Y direction) to corner pocket center
CL - Measurement for tray edge (X direction) to corner pocket center
Chamfer on Tray corner indicates Pin 1 orientation of packed units.

Device Package Package Pins SPQ Unit array Max L (mm) W K0 P1 CL CW
Name Type matrix temperature (mm) (µm) (mm) (mm) (mm)
(°C)
TPA3100D2PHP PHP HTQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
TPA3100D2PHPG4 PHP HTQFP 48 250 10 x 25 150 315 135.9 7620 12.2 11.1 11.25
GENERIC PACKAGE VIEW
RGZ 48 VQFN - 1 mm max height
7 x 7, 0.5 mm pitch PLASTIC QUADFLAT PACK- NO LEAD
Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4224671/A
www.ti.com
PACKAGE OUTLINE
RGZ0048A VQFN - 1 mm max height
PLASTIC QUADFLAT PACK- NO LEAD
7.1 A
B 6.9
(0.1) TYP
7.1 SIDE WALL DETAIL

PIN 1 INDEX AREA 6.9 OPTIONAL METAL THICKNESS
(0.45) TYP
CHAMFERED LEAD
CORNER LEAD OPTION
1 MAX
C
SEATING PLANE
0.05 0.08 C
0.00
2X 5.5
5.15±0.1 (0.2) TYP

13 24
44X 0.5
12
25
SEE SIDE WALL
DETAIL
2X SYMM
5.5
1 36
PIN1 ID 48X 0.30
0.18
48 37
(OPTIONAL)
SYMM 0.1 C A B
48X 0.5
0.3 0.05 C
SEE LEAD OPTION
4219044/D 02/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
2X (6.8)
( 5.15)
SYMM
48X (0.6) 48 37
48X (0.24)
44X (0.5) 1
36
2X SYMM 2X
(5.5) (6.8)
2X
(1.26)
2X
(1.065)
(R0.05)
TYP
25
12
21X (Ø0.2) VIA
TYP
13 24
2X (1.26) 2X (1.065)
2X (5.5)
LAND PATTERN EXAMPLE
SCALE: 15X
0.07 MAX 0.07 MIN SOLDER MASK

ALL AROUND ALL AROUND OPENING
EXPOSED METAL EXPOSED METAL

METAL
SOLDER MASK METAL UNDER
OPENING NON SOLDER MASK SOLDER MASK
SOLDER MASK
DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS 4219044/D 02/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
2X (6.8)
SYMM ( 1.06)
48X (0.6) 48 37
48X (0.24)
44X (0.5) 1
36
2X SYMM 2X
(5.5) 2X (6.8)
(0.63)
2X
(1.26)
(R0.05)
TYP
25
12
13 2X 24
2X (0.63)
(1.26)
2X (5.5)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
67% PRINTED COVERAGE BY AREA
SCALE: 15X
4219044/D 02/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
GENERIC PACKAGE VIEW
PHP 48 TQFP - 1.2 mm max height
7 x 7, 0.5 mm pitch QUAD FLATPACK
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226443/A
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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TPA3100D2

www.ti.com SLOS469F – OCTOBER 2005 – REVISED AUGUST 2010

20-W STEREO CLASS-D AUDIO POWER AMPLIFIER

Simplified Application Circuit

ABSOLUTE MAXIMUM RATINGS

RECOMMENDED OPERATING CONDITIONS

2 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated

Product Folder Link(s): TPA3100D2

RECOMMENDED OPERATING CONDITIONS (continued)

Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 3

4 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated

Product Folder Link(s): TPA3100D2

48 PIN, QFN PACKAGE 48 PIN, HTQFP PACKAGE

Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 5

TERMINAL FUNCTIONS (continued)

6 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated

Product Folder Link(s): TPA3100D2

FUNCTIONAL BLOCK DIAGRAM

VBYP AVCC Thermal

Table 1. TABLE OF GRAPHS (1)

(1) All graphs were measured using the TPA3100D2 EVM.

Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 7

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

THD+N - Total Harmonic Distortion + Noise - %

0.01 PO = 0.5 W 0.01 PO = 1 W

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

THD+N - Total Harmonic Distortion + Noise - %

8 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated

Product Folder Link(s): TPA3100D2

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

THD+N - Total Harmonic Distortion + Noise - %

0.05 0.05 1 kHz

TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE

0.05 0.05 1 kHz

0.02 20 Hz 0.02 20 kHz

Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 9

CLOSED LOOP RESPONSE CLOSED LOOP RESPONSE

35 Gain 150 35 Gain 150

15 VCC = 12 V −50 15 VCC = 24 V −50

OUTPUT POWER OUTPUT POWER

10 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated

Product Folder Link(s): TPA3100D2

SUPPLY CURRENT SUPPLY CURRENT

ICC − Supply Current − A

Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 11

SUPPLY RIPPLE REJECTION RATIO SUPPLY RIPPLE REJECTION RATIO

kSVR − Supply Ripple Rejection Ratio − dB

12 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated

Product Folder Link(s): TPA3100D2

100 kW 220nF 220nF

Figure 21. Stereo Class-D With Differential Inputs (QFN)

Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 13

Figure 22. Stereo Class-D With Single-Ended Inputs (QFN)

14 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated

Product Folder Link(s): TPA3100D2

Figure 23. Stereo Class-D With Differential Inputs (HTQFP)

Copyright © 2005–2010, Texas Instruments Incorporated Submit Documentation Feedback 15

Figure 24. Stereo Class-D With Single-Ended Inputs (HTQFP)

16 Submit Documentation Feedback Copyright © 2005–2010, Texas Instruments Incorporated