Scribd Logo
Upload

Welcome to Scribd!

  • 20 views

    Design Code For Counter

    Uploaded by

    Pranita Bhosale
    This document contains VHDL code for a counter design and testbench. The counter design entity defines a generic width and ports for a clock, reset, preset, direction, data input, and output. The architecture contains a process that resets the counter signal based on preset and direction, and increments or decrements the counter signal on each clock edge based on the direction. The testbench instantiates the counter design and generates a clock signal. It contains test cases that initialize and reset the counter, preset the counter value from the data input, and test incrementing and decrementing the counter in both directions.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd

    Design Code For Counter

    Uploaded by

    Pranita Bhosale
    20 views6 pages
    This document contains VHDL code for a counter design and testbench. The counter design entity defines a generic width and ports for a clock, reset, preset, direction, data input, and output. The architecture contains a process that resets the counter signal based on preset and direction, and increments or decrements the counter signal on each clock edge based on the direction. The testbench instantiates the counter design and generates a clock signal. It contains test cases that initialize and reset the counter, preset the counter value from the data input, and test incrementing and decrementing the counter in both directions.

    Original Title

    Design code for counter (1)

    Copyright

    © © All Rights Reserved

    Available Formats

    DOCX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    This document contains VHDL code for a counter design and testbench. The counter design entity defines a generic width and ports for a clock, reset, preset, direction, data input, and output. The architecture contains a process that resets the counter signal based on preset and direction, and increments or decrements the counter signal on each clock edge based on the direction. The testbench instantiates the counter design and generates a clock signal. It contains test cases that initialize and reset the counter, preset the counter value from the data input, and test incrementing and decrementing the counter in both directions.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    20 views6 pages

    Design Code For Counter

    Uploaded by

    Pranita Bhosale
    This document contains VHDL code for a counter design and testbench. The counter design entity defines a generic width and ports for a clock, reset, preset, direction, data input, and output. The architecture contains a process that resets the counter signal based on preset and direction, and increments or decrements the counter signal on each clock edge based on the direction. The testbench instantiates the counter design and generates a clock signal. It contains test cases that initialize and reset the counter, preset the counter value from the data input, and test incrementing and decrementing the counter in both directions.

    Copyright:

    © All Rights Reserved
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 6

    Design code for counter:

    library IEEE;

    use IEEE.std_logic_1164.all;

    use IEEE.numeric_std.all;

    entity design is

    generic(

    constant WIDTH : integer := 4);

    port(

    clk, reset, preset, direction : in STD_LOGIC;

    d : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);

    q : out STD_LOGIC_VECTOR(WIDTH-1 downto 0));

    end design;

    architecture rtl of design is

    signal cnt : STD_LOGIC_VECTOR(WIDTH-1 downto 0);

    begin

    process(clk, reset)

    begin

    if reset = '0' then

    if (direction = '1') then

    cnt <= (others => '1');

    elsif (direction = '0') then

    cnt <= (others => '0');

    end if;

    elsif falling_edge(clk) then

    if preset = '0' then

    cnt <= d;

    elsif direction = '1' then -- counting down

    cnt <= STD_LOGIC_VECTOR(unsigned(cnt) - 1);


    elsif direction = '0' then -- counting up

    cnt <= STD_LOGIC_VECTOR(unsigned(cnt) + 2);

    end if;

    end if;

    q <= cnt;

    end process;

    end rtl;

    Testbench counter:

    library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_std.all;

    entity testbench is
    generic(
    constant WIDTH : integer := 4);
    end testbench;

    architecture behave of testbench is


    component design is
    generic(
    constant WIDTH : integer);
    port(
    clk, reset, preset, direction: in STD_LOGIC;
    d : in STD_LOGIC_VECTOR(WIDTH-1 downto 0);
    q : out STD_LOGIC_VECTOR(WIDTH-1 downto 0));
    end component;

    shared variable done : boolean := false;


    signal clk : STD_LOGIC := '0';
    signal reset : STD_LOGIC := '0';
    signal preset : STD_LOGIC := '0';
    signal direction : STD_LOGIC := '0';
    signal d : STD_LOGIC_VECTOR(WIDTH-1 downto 0);
    signal q : STD_LOGIC_VECTOR(WIDTH-1 downto 0);

    begin
    UUT: design
    generic map(
    WIDTH => WIDTH)
    port map(
    clk => clk,
    reset => reset,
    preset => preset,
    direction => direction,
    d => d,
    q => q);

    generate_clk : process
    begin
    while done = false loop
    clk <= not clk;
    wait for 50 ns;
    end loop;
    wait;
    end process;
    process
    begin
    -- CASE 0: INITIALIZE
    d <= "1111";
    reset <= '1';
    preset <= '1';
    direction <= '1';

    wait for 100 ns;


    assert (q = "0000") report "Test 0 FAILURE" severity error;

    -- CASE 1: RESET
    d <= "XXXX";
    reset <= '0';
    preset <= 'X';
    direction <= '1';

    wait for 100 ns;


    assert (q = "1111") report "Test 1 FAILURE" severity error;

    d <= "XXXX";
    reset <= '0';
    preset <= 'X';
    direction <= '0';

    wait for 100 ns;


    assert (q = "0000") report "Test 2 FAILURE" severity error;

    -- CASE 2: PRESET AND D


    d <= "0000";
    reset <= '1';
    preset <= '0';
    direction <= 'X';

    wait for 100 ns;


    assert (q = "0000") report "Test 2.0 FAILURE" severity error;

    for i in 0 to ((2**WIDTH) - 1) loop


    d <= STD_LOGIC_VECTOR(unsigned(d) + 1);

    wait for 100 ns;


    assert (q = STD_LOGIC_VECTOR(unsigned(d) - 1)) report "Test 2." &
    integer'image(i) & " FAILURE" severity error;
    end loop;

    wait for 100 ns;

    -- CASE 3: DIRECTION (USING DEFINED D)


    report "Starting Test 3: Direction";
    d <= "1111";
    reset <= '1';
    preset <= '0';
    direction <= '1'; -- COUNTING DOWN
    wait for 100 ns;

    preset <= '1';


    for i in 0 to 15 loop -- CAN CHANGE 7
    wait for 100 ns;
    assert (q = STD_LOGIC_VECTOR(unsigned(d) - i)) report "Test 3.A." &
    integer'image(i) & " FAILURE" severity error;
    end loop;

    d <= "0000";
    reset <= '1';
    preset <= '0';
    direction <= '0'; -- COUNTING UP
    wait for 100 ns;

    preset <= '1';

    for i in 0 to 15 loop -- CAN CHANGE 7


    wait for 100 ns;
    assert (q = STD_LOGIC_VECTOR(unsigned(d) + i)) report "Test 3.B." &
    integer'image(i) & " FAILURE" severity error;
    end loop;

    report "Ending Test 3: Direction";

    done := true;
    wait;
    end process;

    end behave;

    You might also like