oie, 158 aM Understanding GPPR in Tempus and Innows Understanding CPPR in Tempus and Innovus Problem What is Clock Path Pessimism Removal (CPPR) or Clock Reconvergence Pessimism Removal (CRPR)? Solution CPPR or GRPR is the process of identifying and removing the pessimism introduced in the slack reports for clock paths, when the clock paths have a segment in common. ‘There can be a difference in the early and late path delay by using the set_analysis_mode ~analysisType onchipt on of set_timing_derate command. Ina CPPR calculation, the difference between the late and early delays (for the common clock segment between the launch and capture clock paths) is calculated first. This number is then adjusted in the slack calculations to remove the pessimism that exists because the common clock path is considered to be both late and early at the same time. CPPR in a BC/WC Analysis Mode A.BCIWC analysis mode and timing derates can be set using the following commands, which may result in a difference in the max delay and min delay: -cppr both ysis_mode -analysisType be! ming_derate late 1 -early 0.9 -c CPPR is the difference in the max and min delay values: BC/WC Max Delay: Delay x Scale (set_timing der: BC/WC Min Delay: Delay x Scale (set timing derate early) PPR = BC/WC Max Delay ~ BC/WC Min ay CPPR in the On Chip Variation Analysis (OCV) Mode The OCV analysis mode can be set using the following command, which may result in a difference in the max delay and min delay: cppr both sis_mode CPPR is the difference in the max and min delay values: Max Delay: Maximum Operating “in Delay: Minimum Operating CPPR = OCY Max D ay - OCV Min De CPPR with Reconvergent Logic If the design contains reconvergent logic on the clock path, the timing analysis might assume a certain pessimism while calculating the slack, The following figure shows a circuit in which the timing analysis is performed in single analysis mode. In this example, the two clock paths that feed into the mux cannot be active at the same time. However, the analysis can consider both the shorter and longer paths for one setup or hold check. This results in different launch and capture clock path delays and consequent pessimism. hitpsssupportcadence.com/apex/AricletachmentPorlal7id=a1 Od0000000nVa3EAE 18oie, 158 aM Understanding GPPR in Tempus and Innows D Tate Clock Path CLK Early Clock Path CPPR - Pessimism Calculation Consider the following circuit with a common clock path with a delay of de and an additional delay of d1 and d2 respectively, in the launch and capture clock paths in a non-OCV mode: Slow path x Mgoy a FFI 1 P| Dcommon (dc) root psy FF2 |__»__ d2 Fast path x Mag Delay calculation without OCV: gath to FFL = de + al ath to FF2 = de + a2 Delay calculation with OCV: In the case of OCY, launch clock takes the delay from the slow comer and capture clock takes the delay from the fast comer for setup analysis. Say, Mtast and Msiow are the early and late derates to FFL = (de + dl) x Mslow to £E2 = (de + d2) x Mfast ‘The common path cannot be derated by two different values at the same time. The slack calculation is too pessimistic. The pessimism is calculated as shown here: de x Ms. de x Mfast New slack = slack (w/o CPPR) + 2 CPPR - Special cases ‘There can be some special cases where the launch and capture clock paths are triggered with different clock edges as shown in the following circult hitpsssupportcadence.com/apex/AricletachmentPorlal7id=a1 Od0000000nVa3EAEoie, 158 aM Understanding GPPR in Tempus and Innows Slow: e.g. K Many a1 + FFA 7 FF2 | .—— Falling edge FF ara (LD — eh se x Mast, L x MEast CPPR: Transition Sense CPPR value is computed only ifthe same transition exists for launch and capture clocks at the common node and the following global is set to same_transit ion: bal timing eppr transition sense same t By default, CPPR value is computed even if opposite transition exists for launch and capture clocks at the common node: al timing_eppr_transition_sense norma (Default) Enabling CPPR CPPR can be enabled by setting the value of the sec _ana ysis_mode -cppr command to both, or setup, of hold With the noth option, it removes pessimism in both the setup and hold modes. While, with the se options, it removes pessimism only in the setup or hold mades, respectively CPPR can also be enabled using the following global variable: set_global timing remove clock reconvergence_pessinism true Setting timing_remove nvergence_pessinism{o true changes the se s_mode to both Reporting CPPR Using xeport_cppr command (o report the CPPR value at the common branching point of the early and late paths in the clock network of the specified data path: > report_cppr -from regi/elk -to req2/clk nt eegl/el sing edge falling edge of reg2/clk up : Rising mon Point : Falling 2.0000 arriv Late Early Pessimism hitpsssupportcadence.com/apex/AricletachmentPorlal7id=a1 Od0000000nVa3EAE 38oie, 158 aM Understanding GPPR in Tempus and Innows Rise 14311.0693 6364.7095 7946.3599, 6900.3145 6297.1992 603.1152 You can use the following attributes of the get_property command to report the arrival times at a common branch point in the setup mode: > get_property ~clock [get_clock clk1] [get_pins cb_bufl/y] actual_latency_late_rise_max 14311.0693 > get_property ~clock [get_clock clkl] [yet_pins ch_bufl/y) actual_latency late fall max 6900. 3145 > get_property -clock [get_clock clkl] [get_pins ch bufl/y) actual latency early rise max 6364.7095 > get_property ~clock [get_clock clk1] [get_pins cb_bufi/y] actual_latency_early_fall_max 297.1392 Using -debug cppr_point option of report_timing command > report timing -from regi/elk -to reg2/d ~path type full clock ~debug eppr_point Path 1: MET Setup Check with Pin reg2/clk Endpoint: reg2/D (v) checked with leading edge of ‘clkl' Beginpoint: regi/Q (v) triggered by leading edge of ‘clkl' Common point: cb_bufl/y Path Groups: (CTR) Other End Arrival Time 0.079 = setup 0.135 + Phase Shift 40.000 + CPPR Adjustment, 7946.3599 Using global timing report_enable_cppr_point When this global set to true, the report timing command output shows the Common point field. > set_glebal timing tenable cppr_point true > report_timing ~from regi/elk -to reg2/d -path_type full_clock Path 1: HET Setup Check with Pin reg2/clk Endpoint: req?/D (v) checked with leading edge of ‘clkt! Beginpoint: regl/Q (v) triggered by leading edge of ‘clki" Connon point: cb_bufi/y Path Groups: {CLR} Other End Arrival Time 0.079 = setup 0.135 + Phase Shift 40.000 + CEPR Adjustment 7946.3599 Tel commands to query CPPR properties The get_prove:ty command can be used to get CPPR related information, ‘+ To find the common branch point in a timing path, use the copz_branch_point property as shown here: > set path [report_timing -from regi/q -to reg2/d -collection } > get_property $path cppr_branch_point eb_bufl/y + Tofind the CPPR adjustment value in a timing path, use the cpr adjustment property as shown here: ion } > set path (report_timing from regi/q -to reg2/d ~collec > get_property Spath cppr_adjustment 7946.3599 hitpsssupportcadence.com/apex/AricletachmentPorlal7id=a1 Od0000000nVa3EAE 48oie, 158 aM Understanding GPPR in Tempus and Innows Global variables related to CPPR clock _ “self loop mode ming_cppr_skip_clock_reconvergence ming_eppr threshold ps timing enable_si_eppr You can also refer to the Understanding CPPR and Related Variables application note, by clicking here Return to the top of the page hitpsssupportcadence.com/apex/AricletachmentPorlal7id=a1 Od0000000nVa3EAE 58