Full range voltage-controlled ring oscillator frequency and the linear controllability of the tuning range.

The
in 0.18 mm CMOS for low-voltage operation Vcontrol controls the delay time by adjusting the loading of M9 and
M10. When Vcontrol . Vgs(4,3) þ Vds(1,2) , the complementary control
Y.-S. Tiao and M.-L. Sheu transistors become weak, on the contrary the latch becomes strong and
resists the voltage switching in the differential delay cell. As a result,
A new differential delay cell with a complementary current control to delay time is increased. The new differential delay cell is employed in
increase the control voltage range as well as the operation frequency is a four-stage VCRO [3] utilising the multiple-pass loops technique to
proposed for low-voltage operation. The new differential delay cell is obtain higher operation frequency, increase the tuning range and it
employed in a four-stage voltage-controlled ring oscillator (VCRO). also reduces the phase noise of the overall VCRO.
The VCRO is implemented using 0.18 mm 1P6M CMOS process
and 1.8 V supply voltage. Measured results show that a wide operation
VDD VDD
frequency range from 5.36 to 3.03 GHz is achieved for the full range
control voltage from 0 to 1.8 V. Measured phase noise is
M7 M9 M10 M8
2107 dBc/Hz at 1 MHz offset from the 5.22 GHz centre frequency.

IN2– M5 M6 IN2+
Introduction: The voltage-controlled oscillator (VCO) is the most Vcontrol
crucial element in a phase-locked loop (PLL) circuit. The VCO can
be built using a ring oscillator or LC resonator in CMOS process. M3 M4
Although the LC resonator possesses better noise performance and OUT- OUT+
higher operation frequency, it has deficiencies of a larger on-chip
spiral inductor and narrower tuning range. On the other hand, the ring
oscillator does not require any inductance and can achieve a wide M1 M2
tuning range, but it has worse noise performance and lower operation IN1+ IN1–
frequency.
The voltage-controlled ring oscillator (VCRO) has been continuously
studied and enhanced because of increasing demand for low-voltage
Fig. 2 Proposed new differential delay cell
operation and high integration. The architectures of source capacitively
coupled current amplifier (SC3A) [1] and multiple pass loops [2, 3] have
been proposed to improve the operation frequency and phase noise.
They adopt active components to control the operation frequency.
However, as Fig. 1a shows, the control-voltage of a conventional
VCRO cannot cover the full supply voltage range owing to the required
turn-on voltage of the active components. Therefore, a reduced supply
voltage will inevitably limit the linear voltage-frequency characteristic
and the operation frequency of the conventional VCRO. To subdue
the limitation of low-voltage operation, we propose a new complemen-
tary control technique on the delay cell of the VCRO for extending the
control-voltage to cover the full supply voltage range, as the dashed line
shown in Fig. 1b.

frequency frequency
f2
reference delay cell [2]
new delay cell

f1 improved f1
Fig. 3 Chip photograph of proposed VCRO

Vcontrol Vcontrol
0 turn-on voltage 0 turn-on voltage
1.8V 1.8V
a b

Fig. 1 Characteristic of V-F curves

Complementary control delay cell of ring oscillator: The oscillation fre-

quency of a VCRO is determined by the total propagation delay time of
the delay cell, as calculated by f0 ¼ 1/(2NTd), where N is the number of
stages and Td the propagation delay time. The direct method to enhance
the oscillation frequency is to decrease the number of stages [4] or the
propagation delay time [1 – 3]. However, the frequency control voltage
(Vcontrol ) has to ensure the turn-on of transistors, or the operation fre-
quency is out of control as the control voltage becomes lower than the
turn-on voltage. This also limits the achievable highest operation fre-
quency. In this Letter, a delay cell employing a complementary
control technique is proposed, as shown in Fig. 2. A pair of PMOS
complementary control transistors, M9 and M10, is added to the delay Fig. 4 Measured output spectrum of proposed VCRO
cell to provide an extra current to overcome the limitation of low
Vcontrol operation as well as to increase the oscillation frequency. The
delay cell has a differential structure to reduce the power supply injected Experiment results: The VCRO is implemented in 0.18 mm 1P6M
phase noise. A pair of PMOS load transistors, M5 and M6, is added to CMOS process. The chip photograph is shown in Fig. 3. The core
the delay cell to constitute a latch. The cross-coupled NMOS pass tran- area is 116  61.2 mm2 without including PADs. Fig. 4 shows the
sistors, M3 and M4, control the maximum gate voltages of the PMOS measured output spectrum, when the power supply voltage is 1.8 V
load transistors (M5, M6) and adjust strength of the added latch and and the DC current is about 55 mA. The VCRO output is at 5.22 GHz
the operation frequency. When Vcontrol , Vgs(4,3) þ Vds(1,2) , the strength with signal strength of 27.07 dBm at 50 V load. The measured
of latches becomes weak, so the complementary control transistors are tuning range is from 5.36 to 3.03 GHz (a tuning range of 43.39%) for
utilised here to provide extra current for increasing the operation Vcontrol ranging from 0 to 1.8 V, as shown in Fig. 5. Phase noise is

ELECTRONICS LETTERS 7th January 2010 Vol. 46 No. 1

2107 dBc/Hz at 1 MHz offset from 5.22 GHz centre frequency, as Table 1: Comparison of VCRO performance
shown in Fig. 6.
Tuning Phase
Process Supply Vcontrol f0 PDC FOM
Ref. range noise
(mm) (V) (V) (GHz) (mW) (dBc/Hz)
(GHz) (dBc/Hz)
10.6 – 8.4 285 at
[1] 0.12 1.5 0.5 – 1.5 10 52.5 2147.8
20% 1 MHz
5.93 – 5.16 299.5 at
[2] 0.18 1.8 0.8 – 1.8 5.79 80 2155.72
12.98% 1 MHz
2.5– 9 282 at
[4] 0.18 1.8 0 – 0.9 5 170 2133.67
72.2% 1 MHz
This 3.03 – 5.36 2107 at
0.18 1.8 0 – 1.8 5.22 100 2161.35
work 43.39% 1 MHz

FOM ¼ L f foffsetg 2 20 log( f0/foffset) þ 10 log(PDC/1mW )  Lf foffsetg: phase noise  foffset: 1MHz

Acknowledgment: The authors thank the Chip Implementation Center

(CIC) for assistance with chip implementation and measurement.

# The Institution of Engineering and Technology 2010

16 September 2009
doi: 10.1049/el.2010.2542
Fig. 5 Measured tuning range of proposed VCRO One or more of the Figures in this Letter are available in colour online.
Y.-S. Tiao and M.-L. Sheu (Department of Electrical Engineering,
National Chi Nan University, 1, University Road, Puli, Nantou,
54561, Taiwan)
E-mail: [email protected]

References
1 Tao, R., and Berroth, M.: ‘Low power 10 GHz ring VCO using source
capacitively coupled current amplifier in 0.12 mm CMOS technology’,
Electron. Lett., 2004, 40, (23), pp. 1484– 1486
2 Eken, A.Y., and Uyemura, J.P.: ‘A 5.9 GHz voltage-controlled ring
oscillator in 0.18-mm CMOS’, IEEE J. Solid-State Circuits, 2004, 39,
pp. 203– 233
3 Park, C.H., and Kim, B.: ‘A low-noise, 900-MHz VCO in 0.6-mm
CMOS’, IEEE J. Solid-State Circuits, 1999, 34, pp. 586– 591
4 Rezayee, A., and Martin, K.: ‘A coupled two-stage ring oscillator’. Proc.
IEEE Midwest Symp. Circuits and Systems, Dayton, OH, USA, 2001,
Vol. 2, pp. 878– 881
Fig. 6 Measured phase noise of proposed VCRO

Conclusion: Table 1 summarises the measured performance of our

VCRO and includes other reported results for comparison. Our proposed
VCRO has full range voltage controllability and achieves a wide tuning
range with a competitive FOM. The full range voltage controllability,
and hence it is very suitable for low-voltage operation, is accomplished
by employing the proposed complementary control technique in the
delay cell.

ELECTRONICS LETTERS 7th January 2010 Vol. 46 No. 1