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E6501 POWER ELECTRONIC CONVERTERS (39 h)
Semester 1, AY 2009/10
SECTION D: DC/AC INVERTERS (12 h)
By Associate Professor Luo Fang Lin (DR)
(S1-B1c-108, Tel: 5023, e-mail: [email protected])
I. Introduction
Since the students to take this course have studied the courses EE2001,
EE2005, E3015 and E4532, you have already known the conversion
technology that has four aspects:
• DC/DC converters
• DC/AC inverters
• AC/DC rectifiers
• AC/AC converters
DC/AC inversion technology is a big subject area in research
investigation and industrial applications. We study the DC/AC inverters
in advanced schemes: pulsewidth modulation (PWM) technique,
multilevel inversion technique and z-source inversion technique (not
introduced in this course). PWM technique was carefully discussed in
under-graduate courses. We just review some switching signal
arrangement; do NOT pay more attention in the whole technique in
detail.
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DC/AC inverters are quickly developed knowledge of the power
switching circuits applied in industrial applications in comparison with
other power switching circuits. In recent century, plenty of topologies of
DC/AC inverters have been created. Generally say, the DC/AC inverters
are mainly used in AC motor adjustable speed drive (ASD). Although
choppers were popular in DC/AC power supply long time ago, power
DC/AC inverters were widely used in industrial application since later
1980’s. Semiconductor manufacture development brought Power devices
such as GTO, Triac, BT, IGBT and MOSFET and so on in higher
switching frequency (say from thousands Hz up to few MHz) into the
DC/AC power supply since 1980’s. Because of the devices such as
thyristor (SCR) with low switching frequency, the above mentioned
devices have low power rate.
Square-waveform DC/AC inverters were used in early ages before 1980’s.
In those equipment thyristor, GTO and Triac could be used in low-
frequency switching operation. High frequency/high power devices such
as Power BT and IGBT were produced in 1980’s. The corresponding
equipment implementing the pulsewidth-modulation (PWM) technique
has large range of the output voltage and frequency, and low THD.
Nowadays, most DC/AC inverters are PWM DC/AC inverters in different
prototypes.
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DC/AC inverters are used for inverting DC power source into AC power
applications. They are generally used in following applications:
1. Variable voltage/Variable frequency AC supplies in adjustable
speed drive (ASD), such as induction motor drives, synchronous
machine drives and so on.
2. Constant regulated voltage AC power supplies such as
uninterruptible power supplies (UPS’s).
3. Static var (reactive power) compensations
4. Passive/Active series/parallel filters.
5. Flexible AC transmission systems (FACTS’s)
6. Voltage compensations.
(a) Switch-mode inverter in AC motor drive
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(b) Switch-mode converters for motoring/regenerative braking
Figure 1. A standard adjustable speed drive scheme
Adjustable speed induction motor drive systems are widely applied in
industrial applications. These system requested the DC/AC power supply
with variable frequency usually from 0 Hz to 400 Hz in fractional horse-
power (HP) to hundreds HP. A large number of DC/AC inverters are in
the world market. The typical block circuit of an ASD is shown in Figure
1. From this block diagram we can see that the power DC/AC inverter
produces variable frequency and voltage to implement ASD.
1.1. Pulse-Width Modulation (PWM)
The pulsewidth modulation (PWM) technique is a popular method to
implement DC/AC inversion technology. The corresponding circuit is
called the pulsewidth modulator. We believe you have already known the
knowledge in your undergraduate courses. We will review this technique,
and mainly introduce other advanced methodologies in this course.
4
Typical input and output waveforms of a pulsewidth modulator are shown
in Figure 2. The output pulse train has the pulses with same amplitude
and different widths, which corresponding to the input signal at the
sampling instants.
f (t )
(a) Input signal
f w (t )
t
T
(b) Output signal
Figure 2. Typical input and output waveforms of a pulsewidth modulator
The modulation ratio m is arranged in certain area, which is usually
yielded by a uniformed-amplitude triangle (carrier) signal with the
amplitude V tri-m . The maximum amplitude of the input signal is assumed
5
V in-m . We define the amplitude modulation ratio ma for a single-phase as
follow expression.
Vin −m
ma = (1)
Vtri −m
Figure 3. Voltage control by varying ma
We also define the frequency modulation ratio m f as follow expression.
f tri −m
mf = (2)
f in −m
Since the value of the input signal is always smaller than and/or equal to
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the maximum amplitude V in-m , the modulation ratio m is always smaller
than and/or equal to the modulation ratio m a . The voltage control by
varying ma for a single-phase PWM is spitted in three areas which are
shown in Figure 3.
1.1.1. Linear Range ( ma ≤ 1.0 )
The condition (Vˆ ) = m . V2

Ao 1 a
d
determines the linear region. It is a
sinusoidal PWM where the amplitude of the fundamental frequency
voltage varies linearly with the amplitude modulation ratio m a . The PWM
pushes the harmonics into a high frequency range around the switching
frequency and its multiples. However, the maximum available amplitude
of the fundamental frequency component may not be as high as desired.
1.1.2. Over modulation ( 1.27 > ma > 1.0 )
The condition
Vd
2
( )
< VˆAo 1 <
4 Vd
π 2
determines the over modulation region.
When the amplitude of the fundamental frequency component in the
output voltage is increase beyond 1.0, it reaches over modulation. In over
modulation range, the amplitude of the fundamental frequency voltage no
longer varies linearly with m a .
Over modulation causes the output voltage to contain many more
harmonics in the sidebands as compared with the linear range. The
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harmonics with dominant amplitudes in the linear range may not be
dominant during over modulation.
1.1.3. Square Wave (Sufficiently Large m a > 1.27)
The inverter voltage waveform degenerates from a pulse-width
modulated waveform into a square wave.
Figure 4. Typical waveforms of PWM for single-phase operation
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If the signal is a sinusoidal wave, we usually call this inversion is
sinusoidal pulse-width-modulation (SPWM). The typical waveforms of
SPWM are shown in Figure 4.
1.2. Total Harmonic Distortion (THD)
Refer to Figure 4 (c) some parameters are introduced in this sub-section.
1.2.1. Harmonic Factor (HF)
Harmonic Factor (HF) is a variable to describe the weighted percent of a
certain individual harmonic referring to the amplitude of the fundamental
harmonic V 1 . It is defined as
Vn
HFn = (3)
V1
where V n is the amplitude of the nth order harmonic. n = 1 corresponds
the fundamental harmonic.
1.2.2. Total Harmonic Distortion (THD)
Total Harmonic Distortion (THD) is an important variable to describe the
waveform distortion. It is defined as
9
∞
∑V
n =2
n
2
THD = (4)
V1
A pure sinusoidal waveform has THD = 0.
1.2.3. Weighted Total Harmonic Distortion (WTHD)
Weighted Total Harmonic Distortion (WTHD) is a variable to describe
the waveform distortion. It is defined as
∞
Vn2
∑ n
WTHD = n =2 (5)
V1
Note that THD gives an immediate measure of the inverter output voltage
waveform distortion. WTHD is often interpreted as the normalized
current ripple expected into an inductive load when fed from the inverter
output voltage.
1.3. Voltage Source Inverter and Current Source Inverter
DC/AC inverters have three typical supply methods:
• Voltage Source Inverter (VSI)
• Current Source Inverter (CSI)
• Impedance Source Inverter (z-source inverter)
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Generally say, the circuits of VSI and CSI can be same. The difference
between VSI and CSI is the type of the power supply sources, which are
voltage source and current source correspondingly.
1.3.1. Voltage Source Inverter (VSI)
A Voltage Source Inverter is supplied by a voltage source. Since the
source is a DC voltage it is necessary to avoid short-circuit of the DC
voltage source during operation. The control circuit and interface have to
be designed to leave small gaps between switching signals to the up-
switches and lower-switches. For example, the output voltage frequency
is in the range 0 – 400 Hz, and the PWM carrying frequency is in 2 – 20
kHz, the gaps are usually set in 20 - 100 ns.
This requirement is not very convenient for the control circuit and
interface design as well, but most DC/AC inverters are VSIs. VSI usually
converts the voltage from high to low such as a Buck technical feature.
1.3.2. Current Source Inverter (CSI)
A Current Source Inverter is supplied by a current source. Since the
source is a DC current source it is necessary to avoid open-circuit of the
DC voltage source during operation. The control circuit and interface
have to be designed to have a small overlaps between switching signals
to the up-switches and lower-switches. For example, the output voltage
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frequency is in the range 0 – 400 Hz, and the PWM carrying frequency is
in 2 – 20 kHz, the overlaps are usually set in 20 - 100 ns.
This requirement is easy for the control circuit and interface design, but
not many DC/AC inverters are CSIs. CSI usually converts the voltage
from low to high such as a Boost technical feature.
1.4. Circuits of DC/AC Inverters
The general used DC/AC inverters are introduced below.
1. Single-phase half-bridge voltage source inverter (VSI)
2. Single-phase full-bridge VSI
3. Three-phase full-bridge VSI
4. Three-phase full-bridge current source inverter (CSI)
5. Multistage PWM Inverters
6. Multilevel PWM Inverters
7. Soft-switching Inverters
8. z-source Inverters
1.4.1. Single-Phase Half-Bridge Voltage Source Inverter
12
A single-phase half-bridge voltage source inverter (VSI) is shown in
Figure 5. The carrier-based pulse-width modulation (PWM) technique is
applied in this single-phase half-bridge VSI. Two large capacitors are
required to provide a neutral point N, therefore, each capacitor keep the
half of the input DC voltage. Two switches S+ and S- are switched by the
PWM signal.
Figure 5. Single-phase half-bridge VSI
In general, linear modulation operation is considered, so that m a is
usually smaller than unity, e.g. m a = 0.8. Generally, in order to obtain
low THD, the m f is usually taken large number, e.g. mf = 9. In order to
well understand each inverter, we shown some typical circuit below:
13
(a) Carrier and modulating signals
(b) Switch S+ state
(c) Switch S- state
(d) AC output voltage
(e) AC output current
14
Figure 6. Single-phase half-bridge VSI (ma = 0.8, m f = 9)
How to determine the pulsewidth is the clue of the PWM. If the v C is a
sine-wave function as shown in Figure 6, we call the modulation is
sinusoidal pulsewidth modulation (SPWM). For example, the m a = 0.8
and m f = 9. Assume that the amplitude of the triangle wave is 1, the
amplitude of the sine-wave is 0.8. Refer to Figure 6 (a), the sine-wave
function is
f (t ) = ma sin ωt = 0.8sin100π t (6)
Where ω = 2πf, f = 50 Hz. The triangle functions are lines:
f Δ1 (t ) = −4 fm f t = −1800t f Δ2 (t ) = 4 fm f t − 2 = 1800t − 2
f Δ3 (t ) = 4 − 4 fm f t = 4 − 1800t f Δ4 (t ) = 4 fm f t − 6 = 1800t − 6
……
f Δ(2 n −1) (t ) = 4( n − 1) − 4 fm f t f Δ2 n (t ) = 4 fm f t − (4 n − 2) (7)
……
f Δ17 (t ) = 32 − 1800t f Δ18 (t ) = 1800t − 34
f Δ19 (t ) = 36 − 1800t
The leading edge of the first pulses are at t = 0. Refer to Figure 6 (a), the
first pulsewidth (time or degree) is determined by the equation:
0.8sin100π t = 1800t − 2 (8)

15
This is a transcendental equation with the unknown value of t. Using
iterative method to solve the equation, let x = 0.8sin100πt and y =
1800t-2, and initial t 0 = 1.38889 ms = 25 O ,
t (ms/degree) x y |x|:y remarks

1.38889/25 O 0.338 0.5 < decrease t
1.27778/23 O 0.3126 0.3 > increase t
1.2889/23.2 O 0.3152 0.32 < decrease t
1.2861/23.15 O 0.3145 0.315 ≈
The first pulsewidth to switch-on and off the switch S + is 1.2861 ms (or
23.15 O )
Other pulsewidths can be determined from other equations using iterative
method.
Figure 7. Sinusoidal PWM
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Figure 6 shows the ideal waveforms associated with the half-bridge VSI.
We can find out the phase delay between the output current and voltage.
For a large m f we can see the cross points demonstrated in Figure 7 with
smaller phase delay between the output current and voltage.
1.4.2. Single-Phase Full-Bridge Voltage Source Inverter
A single-phase full-bridge voltage source inverter (VSI) is shown in
Figure 8. The carrier-based pulsewidth modulation (PWM) technique is
applied in this single-phase full-bridge VSI. Two large capacitors may be
used to provide a neutral point N, therefore, each capacitor keep the half
of the input DC voltage. Four switches S 1 +/S 1 - and S 2 +/S 2 - are applied
and switched by the PWM signal.
Figure 8. Single-phase full-bridge VSI
Figure 9 shows the ideal waveforms associated with the full-bridge VSI.
There are two sine-waves used in Figure 9 (a)corresponding the two legs
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operation. We can find out the phase delay between the output current
and voltage.
(b) Switch S 1 + and S 1 - state
(c) Switch S 2 + and S 2 - state
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Figure 9. The full-bridge VSI (ma = 0.8, m f = 8)
The method to determine the pulsewidths is same as that introduced in
the previous section. Refer to Figure 9 (a), we can find that there are two
sine-wave functions:
f + (t ) = ma sin ω t = 0.8sin100π t (9)
and f − (t ) = − ma sin ω t = −0.8 sin100π t (10)
The triangle functions are:
f Δ1 (t ) = −4 fm f t = −1600t f Δ2 (t ) = 4 fm f t − 2 = 1600t − 2
……
f Δ(2 n −1) (t ) = 4( n − 1) − 4 fm f t f Δ2 n (t ) = 4 fm f t − (4 n − 2) (11)
……
f Δ15 (t ) = 28 − 1600t f Δ16 (t ) = 1600t − 30
f Δ17 (t ) = 32 − 1600t
19
The first pulsewidth to switch-on and switch-off the switches S 1 + and S 1 -
is determined by the equation below:
0.8sin100π t = 1600t − 2 (12)
The first pulsewidth to switch-on and switch-off the switches S 2 + and S 2 -
is determined by the equation below:
−0.8sin100π t = 1600t − 2 (13)
This is the exercise for student’s homework.
1.4.3. Three-Phase Full-Bridge Voltage Source Inverter
Figure 10. Three-phase full-bridge VSI
A three-phase full-bridge VSI is shown in Figure 10. The carrier-based
pulsewidth modulation (PWM) technique is applied in this three-phase
full-bridge VSI. Two large capacitors may be used to provide a neutral
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point N, therefore, each capacitor keep the half of the input DC voltage.
Six switches S 1 - S 6 are applied and switched by the PWM signal. Figure
11 shows the ideal waveforms associated with the full-bridge VSI. We
can find out the phase delay between the output current and voltage.
(b) Switch S 1 /S 4 state
(c) Switch S 3 /S 6 state
vab1
vab vi
ωt
0 90 180 270 360
21
Figure 11. Three-phase full-bridge VSI (m a = 0.8, m f = 9)
Figure 12. The function of m a for a three-phase inverter
The modulation indication of a three-phase VSI is shown in Figure 12.
1.4.4. Unipolar Single-Phase Half-Bridge Voltage Source Inverter
22
Bipolar inverters are not used in industrial applications. An unipolar
single-phase half-bridge voltage source inverter (VSI) with ma = 0.8 and
m f = 12 is shown in Figure 13. The circuit is same to the bipolar VSI, but
the regulation is different, which is like the two stage regulation.
ii
vi/2 S+ D+
C+ io
a +
vi vO
N _
vi/2
C- S- D-
(a) The circuit
(b) The regulation waveform
(c) The output waveform
Figure 13. An unipolar 1-Φ half-bridge VSI with ma =0.8 & m f =12
23
The sine waveforms’ equation is:
f (t ) = ma sin ωt = 0.8sin100π t (14)
Where ω = 2πf, f = 50 Hz. The positive triangle waveforms’ equations
triangle functions are lines:
……
f Δ(2 n −1) (t ) = (2 n − 1) − 2 fm f t f Δ2 n (t ) = 2 fm f t − (2 n − 1) (15)
……
f Δ11 (t ) = 11 − 1200t f Δ12 (t ) = 2 fm f t − 11
The leading edge of the first pulses is at point A, the tailing edge is at
point B Referring to Figure 13 (a), the first pulsewidth (time or degree) is
determined by the equation:
[A] 0.8sin100π t = 1 − 1200t (16)
And [B] 0.8sin100π t = 1200t − 1 (17)
These are transcendental equation with the unknown value of t. Using
iterative method to solve the equation for point [A], let x = 0.8sin100πt
and y = 1-1200t, and initial t 0 = 1.38889 or ωt 0 = 12 O ,
24
t (ms)/ωt(degree) x y |x|:y remarks
0.66667/12 O 0.16633 0.2 < increase t
0.72222/13 O 0.17996 0.13333 > decrease t
0.69444/12.5 O 0.17315 0.1667 > decrease t
0.68333/12.3 O 0.17042 0.18 < increase t
0.68889/12.4 O 0.17179 0.17333 ≈ end
The leading edge of the first pulse of the switch S + is 0.68889 ms (or
12.4 O )
Using iterative method to solve the equation for point [B], let x =
0.8sin100πt and y = 1200t -1, and initial t 0 = 1.38889 or ωt 0 = 18 O ,
t (ms)/ωt(degree) x y |x|:y remarks

1.0/18 O 0.24721 0.2 > increase t
1.05556/19 O 0.26045 0.26667 < decrease t
1.04444/18.8 O 0.25781 0.25333 ≈ end
The tailing edge of the first pulse of the switch S + is 1.04444 ms (or
18.8 O ). Therefore the first pulse width is 1.0444-0.68889 = 0.3555 ms (or
18.8-12.4 = 6.4 O ).
Students can try to obtain the first pulse width for the switch S -, which
should be same to the one of the first pulse width of the switch S +.
1.4.5. Three-Phase Full-Bridge Current Source Inverter
A three-phase full-bridge current source inverter (CSI) is shown in
Figure 14.
25
ii S1 S3 S5
D1 D3 D5 ioa
a +v
_ ab
vi b
c
S4 S6 S2 C C C
D4 D6 D2
Figure 14. Three-phase CSI
The carrier-based pulsewidth modulation (PWM) technique is applied in
this three-phase full-bridge CSI. The main objective of these static power
converters is to produce AC output current waveforms from a DC current
power supply. Six switches S 1 - S 6 are applied and switched by the PWM
signal. Figure 15 shows the ideal waveforms associated with the full-
bridge CSI.
(b) Switch S 1 + state
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(c) Switch S 3 state
(d) AC output current
(e) AC output voltage
Figure 15. Three-phase CSI (ma = 0.8, m f = 9)
We can find out the phase ahead between the output voltage and current.
1.4.6. Multistage PWM Inverter
Multistage PWM inverter consists of many cells. Each cell can be a
single-phase or three-phase input plus single-phase output VSI, which is
27
shown in Figure 16. If the three-phase AC supply is a secondary winding
of a main transformer, it is floating and isolated from other cells and
common ground point. Therefore, all cells can be link in series or parallel
manner.
ii
L
S1+
D1 D3 D5
vi/2 D1+ S2+ D2+
C+
isa
io
N a +
b vo
_
D4 D6 D2 vi/2 C- S1-
D1- S2- D2-
Figure 16. Three-phase input Single-phase output cell.
A three-stage PWM inverter is shown in Figure 17. Each phase consist of
three cells with difference phase-angle shift by 20 O each other.
The carrier-based pulsewidth modulation (PWM) technique is applied in
this three-phase multistage PWM Inverter. Figure 18 shows the ideal
waveforms associated with the full-bridge VSI. We can find out the
output the phase delayed between the output current and voltage.
28
Figure 17. Multistage converter based on a multicell arrangement.
vca vΔ1 vΔ2 vΔ3 -vca
ωt
0 90 180 270 360
vo211 v
vo21 i
ωt
0 90 180 270 360
(b) Cell c 11 AC output voltage
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(c) Cell c 21 AC output voltage
(d) Cell c 31 AC output voltage
(e) Phase a load voltage
Figure 18. Multicell PWM inverter (3 stages, m a = 0.8, m f = 6)
1.4.7. Multilevel PWM Inverter
A three-level PWM inverter is shown in Figure 19. The carrier-based
pulsewidth modulation (PWM) technique is applied in this multilevel
PWM inverter. Figure 20 shows the ideal waveforms associated with the
30
multilevel PWM inverter. We can find out the output the phase delayed
between the output current and voltage.
ii
S1a D1a S3a D3a S5a D5a
vi/2 C+
S1b S5b
Da+ Db+ S3b Dc+ D5b
D1b D3b
ioa
a +v
_ ab
N b
c
S4a S6a
Da- Db- Dc- S2a D2a
D4a D6a
vi/2 C-
S4b D4b S6b S2b D2b
D6b
Figure 19. Three-phase Three-level VSI.
(b) Switch S 1a status
31
(c) Switch S 4b status
(d) inverter phase a-N voltage
vab1
vab Vi
Vi/2
0 90 180 360
ωt
270
(e) AC output line voltage
van 0.66·Vi
0 90 ωt
270 360
180
van1
(f) AC output phase voltage
Figure 20. Three-level VSI (3 levels, ma = 0.8, m f = 15)
32
1.5. FFT - Fast Fourier Transform
FFT - Fast Fourier Transform is very versatile method to analyze the
waveforms. A periodical function with the radian frequency ω, can be
represented by a series of sinusoidal functions:
a0 ∞
f (t ) = + ∑ (an cos nωt + bn sin nωt ) (18)
2 n =1
where the Fourier coefficients are:
2π
1
an =
π ∫
0
f (t ) cos(nωt )d (ωt ) n = 0, 1, 2, … ∞ (19)
2π
1
bn =
π ∫
0
f (t )sin( nωt )d (ωt ) n = 1, 2, … ∞ (20)
In this case we call the item(s) with the radian frequency ω the
fundamental harmonic, and the items with the radian frequency nω (n > 1)
higher-order harmonics. Draw the amplitudes of all harmonics in the
frequency domain. We can get the spectrum in an individual peaks. The
item a 0 /2 is the DC component.
1.5.1. Central Symmetrical Periodical Function
33
If the periodical function is a central symmetrical periodical function the
all items with cosine function disappear. The FFT is remaining as
∞
f (t ) = ∑ bn sin nωt (21)
n =1
where:
2π
1
bn =
π ∫
0
f (t )sin( nωt )d (ωt ) n = 1, 2, … ∞ (22)
We usually call this function Odd-Order Function, or Odd-Function. In
this case, we call the item with the radian frequency ω the fundamental
harmonic, and the items with the radian frequency nω (n > 1) higher-
order harmonics. Draw the amplitudes of all harmonics in the frequency
domain. We can get the spectrum in an individual peaks. Since it is an
Odd-Function, the DC component is zero.
1.5.2. Axial (mirror) Symmetrical Periodical Function
If the periodical function is an axial symmetrical periodical function the
all items with sine function disappear. The FFT is remaining as
a0 ∞
f (t ) = + ∑ an cos nωt (23)
2 n =1
where a 0 /2 is the DC component and
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2π
1
an =
π ∫
0
f (t ) cos(nωt )d (ωt ) n = 0, 1, 2, … ∞ (24)
We usually call this function Even-Order Function, or Even-Function. In
this case, we call the item with the radian frequency ω the fundamental
harmonic, and the items with the radian frequency nω (n > 1) higher-
order harmonics. Draw the amplitudes of all harmonics in the frequency
domain. We can get the spectrum in an individual peaks. Since it is an
Even-Function, the DC component is usually not zero.
1.5.3. Non-Periodical Function
If a function is non-periodical function, it is possible represented by
Fourier Integration. The spectrum in the frequency domain is not a
discrete spectrum. It is a continuous function spectrum.
1.5.4. Useful Formulae and Data
Some trigonometric formulae are useful for FFT:
π
sin 2 x + cos2 x = 1 sin x = cos( − x)
2
sin x = − sin( − x ) sin x = sin(π − x )

cos x = cos( − x ) cos x = − cos(π − x )
35
d d
sin x = cos x cos x = − sin x
dx dx
∫ sin xdx = − cos x ∫ cos xdx = sin x
sin( x ± y ) = sin x cos y ± cos x sin y

cos( x ± y ) = cos x cos y ∓ sin x sin y
sin 2 x = 2sin x cos x

cos 2 x = cos2 x − sin 2 x
Some values corresponding the special angles are usually used:
π π
sin = sin15O = 0.2588 cos = cos15O = 0.9659
12 12
π π
sin = sin 22.5O = 0.3827 cos = cos 22.5O = 0.9239
8 8
π π 3
sin = sin 30O = 0.5 cos = cos30O = = 0.866
6 6 2
π 2 π 2
sin = sin 45O = = 0.7071 cos = cos 45O = = 0.7071
4 2 4 2
π π
tan = tan15O = 0.2679 tan = tan 22.5O = 0.4142
12 8
π 3 π
tan = tan 30O = = 0.5774 tan = tan 45O = 1
6 3 4
1 π
tan x = tan x = co− tan( − x)
co− tan x 2
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1.5.5. Example of FFT Applications
In order to help readers understand FFT and its applications, some
examples are listed below.
1.5.5.1. An odd-square waveform
The waveform is shown in Figure 21.
Figure 21. An Odd-square waveform
The function f(t) is
⎧1 2nπ ≤ ωt < (2n + 1)π

f (t ) = ⎨ (25)
⎩ −1 (2n + 1)π ≤ ωt < 2(n + 1)π
The Fourier coefficients are
37
2π nπ
1 2 1 − ( −1)n
bn =
π ∫
0
f (t )sin( nωt )d (ωt ) =
nπ ∫0 sin θ dθ = 2 nπ
4
or bn = n = 1, 3, 5, … ∞ (26)
nπ
Finally, we have obtain
4 ∞
sin(nωt )
F (t ) =
π
∑ n =1 n n = 1, 3, 5, … ∞ (27)
The fundamental harmonic has the amplitude 4/π. If we consider the
higher order harmonics until 7 th -order, i.e. n = 3, 5, 7. The HFs are
HF 3 = 1/3; HF 5 = 1/5; HF 7 = 1/7
The THD is
∑V
n =2
n
2
1 1 1
THD = = ( )2 + ( )2 + ( )2 = 0.41415 (28)
V1 3 5 7
The WTHD is
38
∞
Vn2
∑ n 1 1 1
WTHD = n =2 = ( )3 + ( )3 + ( )3 = 0.219 (29)
V1 3 5 7
1.5.5.2. An even-square waveform
Figure 22. An Even-square waveform
The function f(t) is
⎧1 (2n − 0.5)π ≤ ωt < (2n + 0.5)π

f (t ) = ⎨ (30)
⎩ −1 (2n + 0.5)π ≤ ωt < (2n + 1.5)π
a0 = 0
39
nπ nπ
1
2π
4 2 4sin
2
an =
π ∫
0
f (t ) cos(nωt )d (ωt ) =
nπ ∫ cosθ dθ =
0
nπ
4 nπ
or an = sin n = 1, 3, 5, … ∞ (31)
nπ 2
nπ
The item sin is used to define the sign. Finally, we have obtain
2
4 ∞
nπ
F (t ) =
π
∑ sin
n =1 2
cos( nωt ) n = 1, 3, 5, … ∞ (32)
The fundamental harmonic has the amplitude 4/π. If we consider the
higher order harmonics until 7 th -order, i.e. n = 3, 5, 7. The HFs are
HF 3 = 1/3; HF 5 = 1/5; HF 7 = 1/7
The THD is
∑V
n =2
n
2
1 1 1
THD = = ( ) 2 + ( ) 2 + ( ) 2 = 0.41415 (33)
V1 3 5 7
The WTHD is
40
∞
Vn2
∑
n =2 n 1 1 1
WTHD = = ( )3 + ( )3 + ( )3 = 0.219 (34)
V1 3 5 7
1.5.5.3. An odd-waveform pulse
Figure 23. An Odd-waveform pulse
The function f(t) is in the period –π - +π:
⎧ π −x π+x
⎪⎪ 1 ≤ ωt <
2 2
f (t ) = ⎨
⎪ −1 π+x π −x (35)
− ≤ ωt < −
⎪⎩ 2 2
41
π +x π −x π+x
1
2π
2
n
2 cos( n ) − cos( n )
2 2
bn =
π ∫
0
f (t ) sin( nωt )d (ωt ) =
nπ ∫
π −x
sin θ dθ = 2
nπ
n
2
π −x nπ nx
2 cos( n ) 4sin( )sin( )
=2 2 = 2 2
nπ nπ
4 nπ nx
or bn = sin sin n = 1, 3, 5, … ∞ (36)
nπ 2 2
4 sin(nωt )
∞
nπ nx
F (t ) = ∑ n
π n =1
sin
2
sin
2 n = 1, 3, 5, … ∞ (37)
4 x
The fundamental harmonic has the amplitude sin . If we consider
π 2
the higher order harmonics until 7 th -order, i.e. n = 3, 5, 7. The HFs are
3x 5x 7x
sin sin sin
HF3 = 2 HF5 = 2 HF7 = 2
x; x; x
3sin 5sin 7sin
2 2 2
The values of the HFs should be absolute values.
If x = π, The HFs are
42
3x 5x 7x
sin sin sin
HF3 = 2 =1 HF5 = 2 =1 HF7 = 2 =1
x 3; x 5; x 7
3sin 5sin 7 sin
2 2 2
the THD is
∞
∑V
n =2
n
2
1 1 1
THD = = ( )2 + ( )2 + ( ) 2 = 0.41415 (38)
V1 3 5 7
The WTHD is
∞
Vn2
∑ n 1 1 1
WTHD = n =2 = ( )3 + ( )3 + ( )3 = 0.219 (39)
V1 3 5 7
1.5.5.4. A 5-level odd-waveform
Figure 24. A 5-level Odd-waveform
43
The function f(t) is in the period –π - +π:
⎧ π 2π
⎪2 ≤ ωt <
3 3
⎪
⎪1 π π 2π 5π
≤ ωt < , ≤ ωt <
⎪ 6 3 3 6
⎪
f (t ) = ⎨ 0 other
⎪ 5π 2π π π (40)
⎪−1 − ≤ ωt < − , − ≤ ωt < −
⎪ 6 3 3 6
⎪ 2π π
⎪ −2 − ≤ ωt < −
⎩ 3 3
5 nπ 2 nπ
2π 6 3
1 2
bn =
π ∫0
f (t )sin( nωt )d (ωt ) =
nπ n∫π
[ sin θ dθ + ∫π sin θ dθ ] =
n
6 3
2 nπ 5nπ nπ 2nπ 4 nπ nπ
= [(cos − cos ) + (cos − cos )] = (cos + cos )
nπ 6 6 3 3 nπ 6 3
4 nπ nπ
or bn = (cos + cos ) n = 1, 3, 5, … ∞ (41)
nπ 6 3
4 ∞
sin(nωt ) nπ nπ
F (t ) = ∑ n
π n =1
(cos
6
+ cos
3
) n = 1, 3, 5, … ∞ (42)
44
2
The fundamental harmonic has the amplitude (1 + 3) . If we consider
π
the higher order harmonics until 7 th -order, i.e. n = 3, 5, 7. The HFs are
2 3 −1 3 −1
HF3 = = 0.244 ; HF5 = = 0.0536 ; HF7 = = 0.0383
3(1 + 3) 5(1 + 3) 7(1 + 3)
The values of the HFs should be absolute values. Therefore, THD is
∑V n
2
∞
THD = n =2
V1
= ∑ HF
n =2
n
2
= 0.2442 + 0.05362 + 0.03832 = 0.2527 (43)
The WTHD is
∞
Vn2
∑
n =2 n
∞
HFn2 0.2442 0.05362 0.03832
WTHD =
V1
= ∑
n =2 n
=
3
+
5
+
7
= 0.1436 (44)
II. Multilevel DC/AC Inverters
DC/AC inverters can be constructed as PWM inverters, z-source inverters
and multilevel inverters. PWM inverters accumulate the output voltage in
vertical pulses. A typical inverter is shown in Figure 25. Multilevel
inverters are newly developed. They accumulate the output voltage in
horizontal pulses.
45
Figure 25. Block diagram of a PWM DC/AC inverter
2.1. Introduction to Multilevel Inverters
Multilevel inverters contain several power switches and capacitors.
Output voltages of multilevel inverters are the additions of the voltages
due to the commutation of the switches. Figure 25 shows a schematic
diagram of one phase leg of inverters with different level-numbers. A
two-level inverter, as shown in Figure 26 (a), generates an output voltage
with two levels with respect to the negative terminal of the capacitor,
while the three-level inverter of Figure 26 (b) generates three voltages,
and so on. Thus, the output voltages of multilevel inverters have several
levels. Moreover, they can reach high voltage, while the power
semiconductors must withstand only reduced voltages.
46
Figure 26. One phase leg of an inverter: (a) Two levels, (b) Three levels, and
(c) n levels
Multilevel inverters have been receiving increasing attention in recent
years, since multilevel inverters have many attractive features. Firstly,
the output voltage distortion is very low due to multiple levels of the
output voltages. Secondly, the dv/dt of switches is low since the switches
endure reduced voltage. Thirdly, the switches can operate at a lower
switching frequency. Finally, in the applications of motor drives, the
draw input currents have low distortions and the common-mode voltages
are reduced. Additionally, the common-mode voltages can be eliminated
using sophisticated modulation methods.
Various kinds of multilevel inverters have been proposed, tested and
installed. They are diode-clamped (neutral-clamped) multilevel inverters;
capacitors-clamped (flying capacitors) multilevel inverters, cascaded
multilevel inverters with separate dc sources, hybrid multilevel inverters,
generalized multilevel inverters, mixed-level multilevel inverters,
multilevel inverters by the connection of three-phase two-level inverters,
47
and soft-switched multilevel inverters. The family tree of multilevel level
inverters is shown in Figure 27.
Figure 27. Family tree of multilevel inverters
The family of multilevel inverters has emerged as the solution for high
power application, since it is hard to be implemented via single power
semiconductor switch directly in medium-voltage network. Multilevel
inverters have been applied to different high power applications, such as
large motor drives, railway traction applications, high voltage dc
transmissions (HVDC), unified power flow controllers (UPFC), static var
compensators (SVC) and static synchronous compensators (STATCOM).
The output voltage of the multilevel inverter has many levels synthesized
from several dc voltage sources. The quality of the output voltage is
improved as the number of voltage levels increases, so the effort of
output filters can be decreased. The transformers can be eliminated due
48
to reduced voltage that the switch endures. Moreover, as cost effective
solutions, the applications of multilevel inverters are also extended to
medium and low power applications, such as electrical vehicle propulsion
systems, active power filters (APF), voltage sag compensations,
photovoltaic systems and distributed power systems.
Multilevel inverter circuits have been around for about 30 years. The
cascaded multilevel inverter was first proposed in 1975 by Baker.
Separate DC-sourced full-bridge cells in series to synthesize a staircase
ac output voltage. The diode-clamped inverter, also called the neutral-
point clamped (NPC) inverter, was presented in 1980 by Baker. Because
the NPC inverter effectively doubles the device voltage level without
requiring precise voltage matching, the circuit topology prevailed in
1980s. The capacitor-clamped multilevel inverter came in the 1990s.
Although the cascaded multilevel inverter was invented earlier, its
application did not prevail until the mid 1990s. The advantages of
cascaded multilevel inverters were indicated for motor drives and utility
applications. The cascaded inverter has drawn great interest due to the
great demand of medium-voltage high-power inverters.
The cascaded inverter is also used in regenerative-type motor drive
application. Recently, some new topologies of multilevel inverters
emerges, such as generalized multilevel inverters, mixed multilevel
49
inverters, hybrid multilevel inverters and soft-switched multilevel
inverters. Today, multilevel inverters are extensively used in high-power
applications with medium voltage levels, such as laminators, mills,
conveyors, pumps, fans, blowers, compressors, and so on. Moreover, as a
cost-effective solution, the applications of multilevel inverters are also
extended to low power application, such as photovoltaic systems, hybrid
electrical vehicles and voltage sag compensation, in which the effort of
output filter components can be decreased much due to low harmonics
distortions of output voltages of the multilevel inverters.
2.2. Multilevel Inverter Using Diode/Capacitor Clamped

Topologies
In this category, the switching devices are connected in series to make up
the desired voltage rating and output levels. The inner voltage points are
clamped by either two extra diodes or one high frequency capacitor. The
switching devices of an m-levels inverter are required to block a voltage
level of V dc /(m-1). The clamping diode or clamping capacitor needs to
have different voltage rating for different inner voltage levels.
2.2.1. Diode-Clamped Inverters
A three-level diode-clamped inverter is shown in Figure 28 (a). In this
circuit, the dc-bus voltage is split into three levels by two series-
connected bulk capacitors, C1 and C 2 . The middle point of the two
50
capacitors, n, can be defined as the neutral point. The output voltage v an
has three states: E, 0 and -E. For voltage level E, switches S 1 and S 2 need
to be turned on; for -E, switches S 1’ and S 2’ need to be turned on; and for
the 0 level, S 2 and S 1’ need to be turned on.
Figure 28. Diode-clamped multilevel inverter circuit topologies
(a) Three-level (b) Five-level
The key components that distinguish this circuit from a conventional
two-level inverter are D1 and D 1’ . These two diodes clamp the switch
voltage to half the level of the dc-bus voltage. When both S 1 and S 2 turn
on, the voltage across a and 0 is 2E, i.e., v a0 = 2E. In this case, D 1’
balances out the voltage sharing between S 1’ and S 2’ with S 1’ blocking the
voltage across C1 and S 2’ blocking the voltage across C 2 . Notice that
output voltage v an is ac, and v a0 is dc. The difference between v an and v a0
51
is voltage across C 2 , which is E. If the output is removed out between a
and 0, then the circuit becomes a dc/dc converter, which has three output
voltage levels: E, 0 and -E.
Figure 28 (b) shows a five-level diode-clamped converter in which the dc
bus consists of four capacitors, C 1 , C 2 , C 3 and C4 . For dc bus voltage 4E,
the voltage across each capacitor is E, and each device voltage stress will
be limited to one capacitor voltage level E through clamping diodes. The
corresponding example multilevel waveforms are shown in Figure 29
with the voltage unit is E.
(a) Three-level
(b) Five-level
Figure 29. Multilevel waveforms

52
To explain how the staircase voltage is synthesized, the neutral point n is
considered as the output phase voltage reference point. There are five
switch combination to synthesize five level voltage across a and n.
• For voltage level v an = 2E, turn on all upper switches S 1 ~ S 4 .
• For voltage level v an = E, turn on three upper switches S 2 ~ S 4 and one
lower switch S 1’ .
• For voltage level v an = 0, turn on two upper switches S 3 and S 4 and
two lower switches S1’ and S 2’ .
• For voltage level v an = -E, turn on one upper switch S 4 and three lower
switches S 1’ ~ S 3’ .
• For voltage level v an = -2E, turn on all lower switches S 1’ ~ S 4’ .
Four complementary switch pairs exist in each phase. The
complementary switch pair is defined such that turning on one of the
switches will exclude the other from being turn on. In this example, the
four complementary pairs are (S1 , S 1’ ), (S 2 , S 2’ ), (S 3 , S 3’ ), and (S 4 , S 4’ ).
Although each active switching device is only required to block a voltage
level of E, the clamping diodes must have different voltage ratings for
reverse voltage blocking. Using D 1’ of Figure 28 (b) as an example, when
lower devices S 2’ ~ S 4’ are turned on, D 1’ needs to block three capacitor
53
voltages, or 3E. Similarly, D2 and D 2’ need to block 2E, and D1 needs to
block 3E.
2.2.2. Capacitor-Clamped Inverter
Figure 30 illustrates the fundamental building block of a phase-leg
capacitor-clamped inverter. The circuit has been called the flying
capacitor inverter with dependent capacitors clamping the device voltage
to one capacitor voltage level. The inverter in Figure 30 (a) provides a
three-level output across a and n, i.e. v an = E, 0, or -E. For the voltage
level E, switches S 1 and S 2 need to be turned on; for -E, switches S 1’ and
S 2’ need to be turned on; and for the 0 level, either pair (S 1 , S 1’ ) or (S 2 ,
S 2’ ) needs to be turned on. Clamping capacitor C1 is charged when S 1 and
S 1’ are turned on, and is discharged when S 2 and S 2’ are turned on. The
charge of C 1 can be balanced by proper selection of the 0-level switch
combination.
The voltage synthesis in a five-level capacitor-clamped converter has
more flexibility than a diode-clamped converter. Using Figure 30 (b) as
the example, the voltage of the five-level phase-leg a output with respect
to the neutral point n, van , can be synthesized by the following switching
combinations.
54
Figure 30. Capacitor-clamped multilevel inverter circuit topologies
(a) Three-level (b) Five-level
• For voltage level v an = 2E, turn on all upper switches S 1 ~ S 4 .
• For voltage level v an = E, there are three combinations:
o S 1 , S 2 , S 3 , S 1’ : v an = 2E (upper C 4 ) - E (C1 );
o S 1 , S 3 , S 4 , S 3’ : v an = 2E (upper C 4 ) - 3E (C 3 ) + 2E (C 2 ).
o S 2 , S 3 , S 4 , S 4’ : v an = 3E (C 3 ) - 2E (lower C 4 ); and
o S 1 , S 2 , S 4 , S 2’ : v an = 2E (upper C 4 ) - 2E (C 2 ) + E (C1 ).
• For voltage level v an =0, there are six combinations:
o S 1 , S 2 , S 1’ , S 2’ : v an = 2E (upper C 4 ) - 2E (C 2 );
o S 3 , S 4 , S 3’ , S 4’ : v an = 2E (C 2 ) - 2E (lower C 4 );
o S 1 , S 3 , S 1’ , S 3’ : v an = 2E (upper C 4 ) - 3E (C 3 ) + 2E (C 2 ) - E (C1 );
o S 1 , S 4 , S 2’ , S 3’ : v an = 2E (upper C 4 ) - 3E (C 3 ) + E (C1 );
o S 2 , S 4 , S 2’ , S 4’ : v an = 3E (C3 ) - 2E (C2 ) + E (C 1 ) - 2E (lower C4 );
and
55
o S 2 , S 3 , S 1’ , S 4’ : v an = 3E (C 3 ) - E (C1 ) - 2E (lower C 4 ).
• For voltage level V an = -E, there are three combinations:
o S 1 , S 1’ , S 2’ , S 3’ : v an = 2E (upper C 4 ) - 3E (C 3 );
o S 2 , S 1’ , S 2’ , S 4’ : v an = -2E (lower C 4 ) + 3E (C 3 ) - 2E (C 2 );
o S 4 , S 2’ , S 3’ , S 4’ : v an = E (C1 ) - 2E (lower C 4 ); and
o S 3 , S 1’ , S 3’ , S 4’ : v an = 2E (C 2 ) - E (C1 ) - 2E (lower C 4 ).
• For voltage level v an = -2E, turn on all lower switches, S 1’ ~ S 4’ .
In the preceding description, the capacitors with positive signs are in
discharging mode, while those with negative sign are in charging mode.
By proper selection of capacitor combinations, it is possible to balance
the capacitor charge.
The output waveforms of the three-level and five-level capacitor-clamped
multilevel inverters can be also shown in Figure 29.
2.3. Multilevel Inverters using H-Bridges (HBs) Connected
The basic structure is based on the connection of H-bridges (HBs).
Figure 30 shows the power circuit for one phase leg of a multilevel
inverter with three HBs (HB 1 , HB 2 and HB 3 ) in each phase. Each HB is
supplied by a separate dc source. The resulting phase voltage is
synthesized by the addition of the voltages generated by the different
HBs. If the dc link voltages of HBs are identical, the multilevel inverter
is called the cascaded multilevel inverter. However, it is possible to have
56
different values among the dc link voltages of HBs, and the circuit can be
called as the hybrid multilevel inverter.
Figure 31. Multilevel inverter based on the connection of HBs
2.3.1. Cascaded multilevel inverter (CMI)
In cascaded multilevel inverter, the dc link voltages of HBs are identical,
etc. in Figure 31,
Vdc1 = Vdc 2 = Vdc 3 = E (45)
where E is unit voltage. Each HB generates three voltages at the output:
+E, 0, and -E. This is made possible by connecting the capacitors
sequentially to the ac side via the three power switches. The resulting
57
output ac voltage swings from -3E to 3E with seven levels as shown in
Figure 32.
Figure 32. Waveforms of cascaded multilevel inverter
2.3.2. Binary Hybrid Multilevel Inverter (BHMI)
In binary hybrid multilevel inverter (BHMI), the dc link voltages of HB i
(the ith HB), V dci , is 2 i-1 E. In a 3-HB one phase leg,
Vdc1 = E Vdc 2 = 2 E Vdc 3 = 4 E (46)
As shown in Figure 33, the output waveform, v an , has 15 levels. One of
the advantages is the HB with higher dc link voltage has lower number of
commutation and thereby reducing the associated switching losses. The
BHMI illustrates a seven-level (in half-cycle) inverter using this hybrid
topology. The HB with higher dc link voltage consists of lower switching
frequency component, e.g. IGBT. The higher switching frequency
components, e.g. IGBT, are used to construct the HB with lower dc link
voltage.
58
Figure 33. Waveforms of binary hybrid multilevel inverter
2.3.3. Quasi-Linear Multilevel Inverter (QLMI)
Figure 34. Waveforms of quasi-linear multilevel inverter
In quasi-linear multilevel inverter, the dc link voltages of HBi , V dci can
be expressed as
59
⎧ E i =1
Vdci = ⎨ i−2 (47)
⎩2 × 3 E i≥2
In a 3-HB one-phase leg,
Vdc1 = E Vdc 2 = 2 E Vdc 3 = 6 E (48)
As shown in Figure 34, the output waveform, v an , has 19 levels.
2.3.4. Trinary Hybrid Multilevel Inverter (THMI)
In trinary hybrid multilevel inverter, the dc link voltages of HB i , V dci , is
3 i-1 E. In a three-HB one phase leg,
Vdc1 = E , Vdc 2 = 3E , Vdc 3 = 9 E (49)
Figure 35. Waveforms of trinary hybrid multilevel inverter
60
As shown in Figure 35, the output waveform, v an , has 27 levels. To the
best of author’s knowledge, this circuit has the greatest level number for
a given number of HBs among existing multilevel inverters.
2.4. Other Kinds of Multilevel Inverters
The are several other kinds of multilevel inverters introduced in this sub-
section.
2.4.1. Generalized Multilevel Inverters (GMI)
A generalized multilevel inverter topology has previously been presented.
The existing multilevel inverters, such as diode-clamped and capacitor-
clamped multilevel inverters, can be derived from this generalized
multilevel inverter topology. Moreover, the generalized multilevel
inverter topology can balance each voltage level by itself regardless of
load characteristics. Therefore, the generalized multilevel inverter
topology provides a true multilevel structure that can balance each dc
voltage level automatically at any number of levels, regardless of active
or reactive power conversion, and without any assistance from other
circuits. Thus, in principle, it provides a complete multilevel topology
that embraces the existing multilevel inverters.
61
Figure 36. Generalized multilevel inverter structure
Figure 36 shows the generalized multilevel inverter structure per phase
leg. Each switching device, diode, or capacitor’s voltage is E, i.e., 1/(m-1)
of the dc-link voltage. Any inverter with any number of levels, including
the conventional two-level inverter can be obtained using this
generalized topology.
As an application example, a four-level bidirectional DC/DC converter,
shown in Figure 37, is suitable for the dual-voltage system to be adopted
in future automobiles. The four-level dc/dc converter has a unique
feature, which is that no magnetic components are needed. From this
62
generalized multilevel inverter topology, several new multilevel inverter
structures can be derived.
Figure 37. Application example: a four-level inverter for the dual-voltage
system in automobiles
2.4.2. Mixed-Level Multilevel Inverter Topologies
For high-voltage high-power applications, it is possible to adopt
multilevel diode-clamped or capacitor-clamped inverters to replace the
full-bridge cell in a cascaded multilevel inverter. The reason for doing so
is to reduce the amount of separate dc sources. The nine-level cascaded
inverter requires four separate DC sources for one phase leg and twelve
for a three-phase inverter. If a three-level inverter replaces the full-bridge
cell, the voltage level is effectively doubled for each cell. Thus, to
achieve the same nine voltage levels for each phase, only two separate
DC sources are needed for one phase leg and six for a three-phase
63
inverter. The configuration can be considered as having mixed-level
multilevel cells because it embeds multilevel cells as the building block
of the cascaded multilevel inverter.
2.4.3. Multilevel Inverters by Connection of Three-Phase Two-Level
Inverters
Figure 38. Cascaded inverter with three-phase cells
Standard three-phase two-level inverters are connected by transformers
as shown in Figure 38. In order for the inverter output voltages to be
added up, the inverter outputs of the three modules need to be
synchronized with a separation of 120 O between each phase. For example,
obtaining a three-level voltage between outputs a and b, the voltage is
synthesized by Vab = V a1-b1 + V a1-b1 + V a1-b1 . The phase between b 1 and a 2
is provided by a 3 and b 3 through an isolated transformer. With three
64
inverters synchronized, the voltages V a1-b1 , V a1-b1 , V a1-b1 are all in phase;
thus, the output level is simply tripled.
2.4.4. Soft-Switched Multilevel Inverters
There are numerous ways of implementing soft-switching methods, such
as zero voltage switching (ZVS) and zero current switching (ZCS), to
reduce the switching losses and to increase efficiency for different
multilevel inverters. For the cascaded multilevel inverter, because each
inverter cell is a two-level circuit, the implementation of soft switching is
not at all different from that of conventional two-level inverters. For
capacitor- or diode-clamped inverters, however, the choices of soft-
switching circuit can be found with different circuit combinations.
Although zero-current switching is possible, most literatures proposed
zero-voltage-switching types including auxiliary resonant commutated
pole (ARCP), coupled inductor with zero-voltage transition (ZVT), and
their combinations.
2.5. Multilevel Inverters in High Power Applications
In medium-voltage network, it is hard to connect a single power
semiconductor switch directly to medium-voltage grids (2.3, 3.3, 4.16, or
6.9 kV). Multilevel inverters are presented as the solutions for working
with higher voltage levels.
65
2.5.1. Large Motor Drives with Non-Regenerative Front Ends
Diode-clamped three-level multilevel inverters are now widely applied in
medium-voltage (2.3, 3.3, 4.16, and even 6 kV) application, using an
IGBT with forced-air cooling. There applications cover a wide range of
high-power loads including fans, pumps, blowers, compressors, and
conveyors. A three-level capacitor-clamped multilevel inverter is also
used as a motor drive. A seven -level cascaded multilevel inverter is used
in non-regenerative drives in 2.3 kV network. The input part of each HB
has a three-phase diode rectifier, which does not allow the regeneration
of power. It presents a transformerless multilevel inverter as an
application for high-power electric vehicle (HEV) motor drives.
Multilevel inverters have almost no electromagnetic interference or
common-mode voltage; and make an HEV more accessible/safer and
open wiring possible for most of an HEV’s power system. A hybrid
seven-level inverter is applied in 4.16 kV system, in which the top HB
uses IGBT and the low one uses GTO.
2.5.2. Large Motor Drives with Regenerative Front Ends
The use of a three-level active front end (AFE) at the input side of a
three-level diode-clamped inverter has become a very popular solution
for high-power regenerative loads. Especially, two three-level AFEs are
used in a so-called tandem configuration. It presents a multilevel
converter with regeneration capacity. Each cell in the converter contains

66
a single-phase inverter at the output side and a PWM rectifier at the input
side. The output side inverters of the cells are connected in series, while
the input side rectifiers are connected in parallel through the input
transformer. A single-phase AFE, instead of a three-phase one, has been
considered at the input side of each cell for the following reasons: less
power semiconductors and simpler control.
2.5.3. Applications in Power Systems
The first unified power flow controller (UPFC) in the world was based on
a diode-clamped three-level inverter. The UPFC is comprised of the
back-to-back connection of two identical GTO thyristor-based three-level
converters, each rated at 160 MVA. It was commissioned in mid 1998 at
the Inez Station of American Electric Power (AEP) in Kentucky for
voltage support and power-flow control. On the other hand, the cascaded
multilevel inverter is best suited for harmonic/reactive compensation and
other utility applications, since each HB inverter unit can balance its dc
voltage without requiring additional isolated power sources. GEC
Alsthom T&D has commercialized the cascaded multilevel inverter for
reactive power compensation/generation (STATCOM).
2.6. Multilevel Inverters in Medium and Low Power Application
67
The ac output terminal voltage that multilevel inverters synthesize have
low harmonic distortion, thus the filter requirement is reduced. Moreover,
with the topologies of multilevel inverters, the transformers can be
eliminated. In recent years, the volume and price of active components
(semiconductor switches) decreased much, while the passive components,
such as inductors, capacitors or transformers are kept the almost same.
Therefore, in the medium and low application, the systems with the
configuration of multilevel inverters can be compacter and cheaper.
2.6.1. Photovoltaic Systems
Various topologies of multilevel inverters are investigated for the
application of photovoltaic system. Amongst the topologies for
transformerless systems, the diode clamped multilevel inverters and the
cascaded multilevel inverters have been identified as the most promising
topologies. The design and control issues associated with the
development of a 1.8 kW prototype single-phase grid-connected
photovoltaic system incorporating a cascaded multilevel inverter are
discussed.
2.6.2. Voltage Sag Compensation
A cascaded multilevel inverter was studied as a cost-effective way of
series sag compensation, because it eliminates the bulky injection
68
transformers and other large filter components used in series active
filters. Batteries and high-current automotive MOSFETs proved to be
interesting options in terms of energy storage and switching components
for this design.
2.6.3. Distributed Energy Application
Distributed energy system, mostly those using alternative energies such
as fuel cells or photovoltaic panels, can be easily configured with a
separate source connected through the power conversion circuits used as
an energy module or building block to provide individual output. A
cascaded multilevel inverter can then be configured with multiple
modules. Such a system does not need a transformer to provide isolation,
and the system can be constructed in a cost effective manner.
2.7. Investigation of THMI
2.7.1. Topology and Operation
A single-phase THMI with h HBs connected in series is shown in Figure
39. The key feature of the THMI is that the ratio of dc link voltage is
1:3:…:3 h-1 , where h is the number of HBs. The maximum number of
synthesized voltage levels is 3 h .
69
Figure 39. Configuration of THMI
As shown in Figure 39, v Hi represents the output voltage of the i th HB.
V dci represents the dc link voltage of the ith HB. A switching function, F i ,
is used to relate V Hi and V dci as shown in
vHi = Fi ⋅ Vdci (50)
The value of F i can be either 1 or -1 or 0. For the value 1, switches S i1
and S i4 need to be turned on. For the value -1, switches S i2 and S i3 need
to be turned on. For the value 0, switches S i1 and S i3 need to be turned on
or S i2 and S i4 need to be turned on. Table 1 shows the relationship
between the switching function, the output voltage of a HB and states of
switches.
70
Table 1. Relationship between the switching function, output voltage of
a HB and states of switches

Fi v Hi Si1 Si2 Si3 Si4
1 V dci conduct block block conduct
-1 - V dci block conduct conduct block
0 0 conduct conduct block block
0 0 block block conduct conduct
The output voltage of the THMI, v an , is the summation of the output

h
voltages of HBs. van = ∑v

i =1
Hi (51)
From (50) and (51), we can get

h
van = ∑ Fi ⋅Vdci (52)
i =1
In a single-phase h-HB THMI, the ratio of dc link voltage is 1:3:…:3 h-1 .
Suppose E is unit voltage, the dc link voltage can be expressed as:
Vdci = 3i −1 E (53)
From (52) and (53), we can get

h
van = ∑ Fi ⋅ 3i −1 E (54)
i =1
Suppose l is ordinal of expected voltage level that the inverter outputs. If
l is not negative, the inverter output the positive lth voltage level. If l is
negative, the inverter outputs the negative (-l)th voltage level. In a single
phase THMI with h HBs, given the value of l, the value of F i can be
determined by
71
ABS(l ) 3h −1 − 1
Fh = Bb (ABS(l ) − )
l 2
ABS(l ) 3h − 2 − 1
Fh −1 = Bb (ABS(l ) − ABS(Fh ) ⋅ 3h −1 − )
l 2
ABS(l ) h
3i −1 − 1
Fi = Bb (ABS(l ) − ∑ (ABS(Fk ) ⋅ 3 ) −
k −1
) (55)
l k = i +1 2
h
ABS(l )
F2 = Bb (ABS(l ) − ∑ (ABS(Fk ) ⋅ 3k −1 ) − 1)
l k =3
h
ABS(l )
F1 = Bb (ABS(l ) − ∑ (ABS(Fk ) ⋅ 3k −1 ))
l k =2
where ABS is the function of absolute value and the bi-polar binary
function, Bb , is defined as
⎧1 τ >0
⎪
Bb (τ ) = ⎨ 0 τ =0 (56)
⎪ −1 τ <0
⎩
From (54), we can get the relationship between the output voltage of the
inverter, v an , and the values of switching functions in the THMI with
different number of HBs.
Table 2. Relationship between the output voltage of the inverter and the
values of switching functions in a single-phase two-HB THMI

v an -4E -3E -2E -E 0
F1 -1 0 1 -1 0
F2 -1 -1 -1 0 0
v an 4E 3E 2E E
F1 1 0 -1 1
F2 1 1 1 0
72
In the case of a two-HB THMI, Table 2 shows the relationship between
the output voltage of the inverter and the values of switching functions.
The waveforms of a single-phase two-HB THMI is shown in Figure 40.
4E
3E
Figure 40. Waveforms of a single-phase two-HB THMI
Table 3. Relationship between the output voltage of the inverter and the
values of switching functions in a single-phase three-HB THMI

v an 13E 12E 11E 10E 9E 8E 7E
F1 1 0 -1 1 0 -1 1
F2 1 1 1 0 0 0 -1
F3 1 1 1 1 1 1 1
v an 6E 5E 4E 3E 2E E 0
F1 0 -1 1 0 -1 1 0
F2 -1 -1 1 1 1 0 0
F3 1 1 0 0 0 0 0
The output voltage of a single-phase three-HB has 27 levels. v H1 , v H2 and
v H3 can be negative when v an is positive. Table 3 shows relationship
73
between the output voltage of the inverter and the values of switching
functions in a single-phase three-HB THMI. From (54), we can get
van = −v 'an ⇔ Fi = F'i i = 1...h (57)
The cases about the negative value of v an can be deduced from Table 3.
2.7.2. Prove for the Greatest Number of Output Voltage Levels of the
THMI
Among existing multilevel levels THMI has the greatest levels of output
voltage using the same number of components. In the section, firstly, the
theoretical prove for this conclusion is specified, then the comparison
between various kinds of multilevel inverters is given.
2.7.2.1. Theoretical prove
This section proves that the THMI has greatest levels of output voltage
using the same number of HBs among the multilevel inverters using HBs
connected. A phase voltage waveform is obtained by summing the output
voltages of h HBs as shown in (50). If the dc link sources of all HB cells
are equal, the multilevel inverter is called the cascaded multilevel
inverter and the maximum number of levels of phase voltage is given by
m = 1 + 2h (58)
74
On the other hand, if at least one of the dc link sources is different from
the other ones, the multilevel inverter is called the hybrid multilevel
inverter. In section 2.3, the BHMI, the quasi-linear multilevel inverter
and the THMI are introduced. Thus, considering that the lowest dc link
source E is chosen as base value for the p.u. notation, the normalized
values of all dc link voltages must be natural numbers to obtain a
uniform step multilevel inverter, i.e.:
Vdci* ∈ E , i = 1, 2,…, h (59)
Moreover, to obtain a uniform step multilevel inverter, the dc link
voltage of the HB cells must also respect the following relation:

i −1
Vdci* ≤ 1 + 2∑Vdck * , i = 2,3, …, h (60)
k =1
where it is also considered that the dc link voltages are arranged in an
increasing way, that is:
Vdc1* ≤ Vdc 2* ≤ Vdc 3* ≤ ≤ Vdch* (61)
Therefore, the maximum number of levels of output phase voltage
waveform can be given:
m = 1 + 2σ max (62)
where σ max is the maximum number of positive/negative voltage levels
and can be expressed:

h
σ max = ∑ Vdci* (63)
i =1
75
From (61), (62) and (63) it is possible to verify that hybrid multilevel
inverters can generate a large number of levels with the same number of
cells. Moreover, in the THMI, the dc link voltages respect

i −1
Vdci* = 1 + 2∑ Vdck * , i = 2,3, …, h (64)
k =1
Therefore, the THMI has greatest levels of output voltages using the
same number of HBs among multilevel inverters with HBs connected.
2.7.2.2. Comparison between various kinds of multilevel inverters
Two kinds of comparisons are presented in this section. In the first
comparison, the components are considered to have same voltage rating,
E. This comparison is for high power and high voltage applications, in
which the devices connected in series, are used to satisfy the requirement
of high voltage ratings. Table 4 shows the comparison between
multilevel inverters: diode-clamped multilevel inverter (DCMI),
capacitor-clamped multilevel inverter (CCMI), cascaded multilevel
inverter (CMI), generalized multilevel inverter (GMI), BHMI and THMI.
The m is the number of steps of phase voltage. From Table 4, we can find
that CMI, BHMI and THMI use fewer components. The CMI, BHMI and
THMI use the same number of components. However, in practical
systems, the redundancy requirement must be satisfied. THMI uses fewer
components than BHMI and CMI in practical systems since THMI use
less redundant components. Moreover, the THMI uses fewer dc sources
than the CMI and the BHMI.
76
Table 4. The first comparison between multilevel inverters
Converter
DCMI CCMI GMI CMI BHMI THMI
type
Main
switching 2 m -2 2 m -2 2 m -2 2 m -2 2 m -2 2 m -2
devices
Diodes m ( m -1) m -1 2 m -2 2 m -2 2 m -2 2 m -2
Capacitors m -1 0.5 m ( m -1) m -1 ( m -1)/2 ( m -1)/2 ( m -1)/2
Total ( m -1) ( m -1) 2 m +1 +
4.5( m -1) 4.5( m -1) 4.5( m -1)
components ( m +1) (0.5 m +3) m -5
Table 5. The second comparison between multilevel inverters

Converter
DCMI CCMI CMI GMI BHMI THMI
type
Main
switching 2 m -2 2 m -2 2 m -2 2 m -2 4×log 2 [( m +1)/2] 4×log 3 m
devices
Diodes 4 m -6 2 m -2 2 m -2 2 m -2 4×log 2 [( m +1)/2] 4×log 3 m
0.5 m
Capacitors m -1 2 m -3 m -1 log 2 [( m +1)/2] log 3 m
-0.5
Total 4.5 m 2 m +1 +
7 m -9 6m -7 9×log 2 [( m +1)/2] 9×log 3 m
components -4.5 m -5
The second comparison is for medium and low power application, in
which the voltage rating of main switching components, diodes and
capacitors can be researched easily. Therefore, the numbers of main
switching components, diodes and capacitors are minimal required values.
Table 5 shows the comparison results among DCMI, CCMI, CMI, GMI,
77
BHMI and THMI. From Table 5, we can find that the THMI uses the
fewest components among these multilevel inverters.
2.7.3. Modulation Strategies for THMI
Five modulation strategies for the THMI are investigated. They are the
step modulation strategy, the virtual stage modulation strategy, the
hybrid modulation strategy, the sub-harmonics pulse width modulation
(PWM) strategy and the simple modulation strategy. Since multilevel
inverters are used in three-phase systems typically generally, only
modulation strategies for the three-phase systems will be investigated
here. In the three-phase systems, triple-order harmonic components of
voltages need not be eliminated by the modulation strategies since they
can be eliminated by proper connection of three-phase voltage sources
and loads. In other words, only 5th, 7th, 11th, 13th, 17th, 19th …
harmonic components should be eliminated by the modulation strategies.
In addition, the amplitude of the fundamental component should be
controlled. The list can be expressed by
⎧ 3i -2 ∀i = odd
ηi = ⎨ i>0 (65)
⎩3i -1 ∀i = even
The step modulation strategy, the virtual stage modulation strategy and
the simple modulation strategy belong to low-frequency modulation
strategies. The high-frequency modulation strategies used in the hybrid
78
multilevel inverters include the hybrid modulation strategy and the sub-
harmonic PWM strategy.
2.7.3.1. Step modulation strategy
Figure 41. Step modulation strategy of THMI
Figure 41 shows a general quarter-wave symmetric stepped voltage
waveform synthesized by a THMI where E indicates unit voltage of dc
source. Consider that ς is the number of switching angles in quarter wave
of v an and σ is the number of positive/negative levels of v an . In step
modulation strategy,
ς =σ
By applying Fourier series analysis, the amplitude of any odd jth
harmonic of v an can be expressed as

ς
4
van j =
jπ
∑ [ E cos( jθ )]
i =1
i (66)
79
where j is an odd harmonic order and θ i is the ith switching angle. The
amplitudes of all even harmonics are zero. According to the values, θ 1 to
θ ς must satisfy
0 < θ1 < θ 2 < ... < θς < π / 2 (67)
The switching angles controlled by step modulation technique are derived
from (66). Up to (ς-1) harmonic contents can be removed from the
voltage waveform and the amplitude of fundamental component can be
controlled.
⎧ς
⎪∑ cos(η1θi ) = σ ⋅ MR
⎪ i =1
⎪ ς
⎪ ∑ cos(η2θi ) = 0
⎨ i =1 (68)
⎪
⎪
⎪ ς
⎪ ∑ cos(ης θi ) = 0
⎩ i =1
where MR is the relative modulation index and is expressed as
π van 1
MR = (69)
4σ E
where |v an | 1 is the amplitude of fundamental component of the output
voltage of the inverter.
The equation sets (68) from which the switching angles can be derived
are nonlinear and transcendental. For example, in a two-HB THMI, with
the step modulation technique, the equations set are expressed as (70)
when the relative modulation index is 0.83. The correct solution must
satisfy the inequational condition as shown in (67).
80
cos(θ1 ) + cos(θ 2 ) + cos(θ3 ) + cos(θ 4 ) = 0.83 × 4
cos(5θ1 ) + cos(5θ 2 ) + cos(5θ3 ) + cos(5θ 4 ) = 0
cos(7θ1 ) + cos(7θ 2 ) + cos(7θ3 ) + cos(7θ 4 ) = 0 (70)
cos(11θ1 ) + cos(11θ 2 ) + cos(11θ 3 ) + cos(11θ 4 ) = 0
The constrained optimization approach can be used to solve the nonlinear
and transcendental equations sets. Each equation is regarded as an
equational constraint. However, the computational problems of
constrained optimization do not converge easily. Since in the actual
electric system there are always mismatches and parameter tolerances,
lower order harmonics will be small but not exactly zero. This gives a
rise to an idea of transforming the constraint optimization model to a
non-constraint one. The non-constraint optimization is expected to have
better convergence property.
The target function of the new scheme of optimization without equational
constraints can be written as:

ς ς ς
FT = p1[∑ cos(η1θi ) − σ ⋅ M ]2 + p2 [∑ cos(η 2θi )]2 + + pς [∑ cos(ης θi )]2 (71)
i =1 i =1 i =1
The p 1 ~p ς are penalty factors. The penalty factors were selected as
4
pi = (72)
2i − 1
81
Thus, the penalty factors put more weight on elimination of lower order
harmonics.
Figure 42. Synthesized phase leg voltage waveform and frequency
spectrum of a two-HB THMI with step modulation technique
The two-HB THMI can synthesize nine-level output voltage. Figure 42
and Figure 43 show the typical synthesized waveform of the phase leg
voltage, line-to-line voltage waveform and their frequency spectrums, as
MR is equal to 0.83. The switching angles are 0.1478, 0.3232, 0.5738 and
0.9970. According to (38), the fifth, seventh and eleventh harmonics of
phase leg voltage can be eliminated in the two-HB THMI as shown in
Figure 42. The THD of phase leg voltage is 9.66%. The triple-order
82
harmonic components do not exist in the line-to-line voltage as shown in
Figure 43. The THD of line-to-line voltage is 5.91%.
Figure 43. Synthesized line-to-line voltage waveform and frequency
spectrum of a two-HB THMI with step modulation technique
According to (68), all switching angles must satisfy the constraint (67). If
switching angles do not satisfy the constraint, this scheme no longer
exists. The theoretical maximum amplitude of fundamental component is
4ςE/ π , which occurs as θ 1 ~ θ h equal to zero. Because of the internal
restriction of switching angles, the relative modulation index has upper
and lower limitation. The limitation of the relative modulation index can
be explained using Figures 44 and 45.

83
Figure 44. Limitation to the minimum MR in the step modulation
Figure 45. Limitation to the maximum MR in the step modulation
As shown in Figure 44, as the relative modulation index is less than a
certain value, denoted by MR (min), θ ς approaches to π /2 and the
limitation of minimum modulation index occurs. Similarly, when the
relative modulation index is greater than MR (max), θ 1 approaches to
zero and the limitation of maximum modulation index occurs as shown in
Figure 45.
84
For a THMI with h HBs, the maximum number of levels of the phase leg
voltage is m, which equals to 3 h . The maximum number of the
positive/negative phase leg voltage levels is σ max , which equals to (m-1)/2.
As mentioned above, the relative modulation index MR has limitations.
To extend to the smaller ranges of modulation index, the inverter will
output fewer voltage levels. Consequently, the number of
positive/negative voltage levels that the inverter outputs, σ, is smaller
than the maximum number of the positive/negative levels, σ max . In the
step modulation strategy, the number of switching angles in the quarter
wave of v an , ς, equals to σ. The definition of relative modulation index,
MR, is based on σ as shown in (69). This definition is easily included in
(68) to express the nonlinear transcendental equation sets that are used to
calculate the switching angles. In practice, the modulation index, M, is
used. M is based on the σ max and can be expressed as:

π van 1
M= (73)
4σ max E
The relationship between MR and M can be expressed as
M σ
= (74)
MR σ max
In the two-HB THMI, according to (69), the maximum MR is calculated
as 0.86 and the minimum MR is 0.55 as the levels of output voltage are
nine. The range of M is also from 0.55 to 0.86 with the nine-level output
voltage. To extend to lower modulation index, fewer output voltage
levels are synthesized. The range of MR is 0.46~0.83 when the output
85
voltage levels are seven. According to (74), the range of M is 0.34~0.62
when output voltage levels are seven. Thus, the modulation range is
extended to 0.34 by decreasing levels of output voltage.
Table 6. Range of modulation index under different output voltage
levels with the step modulation in a two-HB THMI

σ MR MR (max) M (min) M (max) Range of M
(min)
1 0 1 0 0.25 0-0.15
2 0.3 0.9 0.15 0.45 0.15-0.34
3 0.46 0.83 0.34 0.63 0.34-0.55
4 0.55 0.86 0.55 0.86 0.55-0.86
4* 0.3 0.94 0.3 0.94 0.86-0.94
Table 6 shows the relative modulation index and the modulation index
with different output voltage levels in the two-HB THMI. Firstly, the
minimum and maximum MR is calculated by the optimization method.
Secondly, the minimum and maximum M is calculated by (74). It is
preferable to use more output voltage levels. The last column of Table 6
shows the arrangement of M with different output voltage levels. In
addition, the maximum limitation of M can reach 0.94 without regard to
the elimination of the 11th harmonic as shown in last row of Table 6.
2.7.3.2. Virtual stage modulation strategy
In the step modulation strategy, the output voltage levels of the
multilevel inverter limit the amount of eliminated lower order harmonics.
86
Only three lower order harmonics can be eliminated by the step
modulation in a two-HB THMI. It is not very satisfied in the applications
that required a high-quality sinusoidal voltage output. The virtual stage
modulation strategy is a new modulation strategy that increases the
amount of eliminated lower order harmonics without increasing the
number of output voltage levels. The switching angles can be derived as:
β
⎧α
⎪ ∑ cos(η θ
1 pi ) − ∑ cos(η1θ ni ) = σ ⋅ MR
⎪ i =1 i =1
⎪ α β
⎪ ∑ cos(η2θ pi ) − ∑ cos(η2θ ni ) = 0
⎨ i =1 i =1 (75)
⎪
⎪
⎪ α β
⎪ ∑ cos(η θ
ς pi ) − ∑ cos(ης θ ni ) = 0
⎩ i =1 i =1
where σ is the number of positive/negative levels of v an and can be
expressed as
σ =α −β (76)
ς is the number of switching angles in quarter waveform of v an and can be

expressed as ς =α +β (77)
MR is shown in (69). The equation (75) is subject to
⎧ 0 < θ p1 < θ p 2 < ... < θ pα < π / 2

⎪
⎨ 0 < θ n1 < θ n 2 < ... < θ nβ < π / 2 (78)
⎪θ < θ j = 1, 2,..., β
⎩ nj p ( j +σ )
In the two-HB THMI, when the output voltage changes between E and 2E
or -E and -2E, the switching components of the higher voltage HB will
switch on/off as shown in Figure 46.
87
Figure 46. Scheme of switching angles with the step modulation as a function
of modulation index in a two-HB THMI
To keep high-voltage switching components switch at lower frequency in
the THMI, the limitation (79) is added into (75) to assure that higher
voltage switching components switch at the fundamental frequency.
θ p 2 < θ n1 (79)
Figure 47 illustrates the waveform using the virtual stage modulation for
the two-HB THMI whose output voltage levels are nine. The number of
virtual stages, β, is two.
88
Figure 47. Waveform using the virtual stage modulation Two-HB, nine-level,
α=6, β=2
Figures 47 and 48 show the typical synthesized waveform of phase leg
voltage, line-to-line voltage waveform and their frequency spectrum in
the virtual stage modulation strategy. The MR is 0.83 and the number of
virtual stages is two. θ p1 to θ p6 is 0.1321, 0.3320, 0.5307, 0.6226, 0.9133
and 1.0419. θ n1 is 0.5750 and θ n2 is 0.9652. Because of two additional
virtual stages, four more degrees of freedom of switching angles are
created such that 13th, 17th, 19th and 23rd harmonics can be eliminated
from the phase leg voltage as shown in Figure 48. The THD of phase leg
voltage is 10.67%. The triple-order harmonic components of line-to-line
voltage do not exist and the harmonics are pushed to 1250Hz as shown in
Figure 49. The THD of the line-to-line voltage is 7.3%.
89
Figure 48. Synthesized phase leg voltage waveform and frequency spectrum of
a two-HB THMI with the virtual stage modulation
Figure 49. Synthesized line-to-line voltage waveform and frequency spectrum
of a two-HB THMI with the virtual stage modulation
I n virtual stage modulation strategy, the relative modulation index also
has upper and lower limitation. Compared with the step modulation
90
strategy, the optimal computation of the virtual stage modulation strategy
endures more unequal restriction as shown in (78) and (79). When the
switching angles do not satisfy these restrictions, the themes of switching
angles no longer exist.
Table 7 Range of modulation index with the virtual stage modulation
in a two-HB THMI
σ β MR (min) MR (max) M M (max) Range of
(min) M
3 1 0.51 0.92 0.38 0.69 0.38-0.459
4 2 0.459 0.92 0.459 0.92 0.459-0.92
The concept of the relativ e mo dulatio n inde x c an b e use d in the ste p
m odulation strategy by the similar method. Table 7 shows two cases.
One is the nine-level output voltage with two virtual stages and the other
is the seven-level output voltage with one virtual stage. With the nine-
level output voltage and two virtual stages, the 5th, 7th, 11th, 13th, 17th,
19th and 23rd harmonics can be eliminated. With the seven-level output
voltage and one virtual stage, the 5th, 7th, 11th and 13th can be
eliminated. When output voltage levels are five or three, the virtual stage
modulation strategy is not applicable in the two-HB THMI since the
restriction (79) must be violated. Therefore, when M is less than 0.38 in
this case, the step modulation strategy will be used. With the virtual
stage modulation strategy, the scheme of switching angles is shown in
Figure 50.
91
Figure 50. Scheme of switching angles for the virtual stage modulation as a
function of modulation index in a two-HB THMI
p1 to p6 mean θp1 to θp6, n1 to n2 mean θn1 to θn2
2. 7.3.3. Hybrid modulation strategy
The hybrid modulation strategy for the hybrid multilevel inverters has
been presented, which incorporates stepped voltage waveform synthesis
in higher power HB cells in conjunction with hi gh frequency variable
PWM in the lowest power HB cell. Figure 51 presents a block diagram of
the command circuit utilized to determine the command signals of the
power devices of all HB. As shown in Figure 51, the reference signal of
the hybrid multilevel inverter, v ref is the command signal of the HB with
92
the highest dc voltage source (V dc,h ). This signal is compared with a
voltage level corresponding to the sum of all smaller dc voltage sources
of the hybrid multilevel inverter, σ max,h-1 . If the command signal is greater
than this level, the output of the inverter with the highest dc voltage
source must be equal to V dc,h . In addition, if the command signal is less
than the negative value of σ max,h-1 , the output of this cell must be equal to
-V dc,h , else the output of this cell must be zero.
Figure 51. Hybrid modulation for hybrid multilevel inverters
The command signal of ith HB cell is the difference b e tween the
command signal of the HB i+1 and the output voltage of the HBi+1 . In this
way, the command signal of the ith cell contains information ab out the
h armonic content of the output voltage of all higher voltage cells. This
command signal is compared with a voltage level corresponding to the
sum of all voltage sources until the HB i-1 (σ max,i-1 ). In the same way that
93
presented for the HB h , the output voltage of this cell is synthesized from
the comparison of these two signals.
Finally, the command signal of HB 1 ( lowest power inverter) is compared
with a high frequency triangle carrier signal, resulting in a high
frequency output voltage. Therefore, the output voltage harmonics will
be concentrated around the frequencies multiples of the switching
frequency of the inverter with the lowest dc voltage source. Consequently,
the spectral response of the output voltage depends on the switching
frequency of the lowest power inverter, while the power processing
depends on the inverter with the highest dc voltage source.
However, with the hybrid modulation strategy, a voltage waveform must
be synthesized to modulate at high frequency among all adjacent voltage
steps. Only the lower voltage HB can switch at high frequency, so the dc
voltages must satisfy the following equation:

i −1
Vdci* ≤ 2∑ Vdck * , j = 2,3,… , h (80)
k =1
where * mean the normalized value. Therefore , the hybrid modulation
strategy can be applied in binary hybrid multilevel inverters and quasi-
linear multilevel inverts. The relationship of DC voltages of the THMI is
shown in (64), so the THMI cannot use the hybrid modulation strategy.
94
2.7.3.4. Sub-harmonic PWM strategies
Sub-harmonic PWM strategies for multilevel inverters employ extensions
of carrier-based techniques used for conventional inverters. It has been
reported that the spectral performance of a five-l evel waveform can be
significantly improved by employing alternative dispositions and phase
shifts in the carrier signals. This concept can be extended to a nine-level
case with the available options for polarity and phase variation. A
representative sub-harmonic PWM waveform with the nine-level phase
leg voltage is shown in Figure 52.
Figure 52. Representative waveforms for sub-harmonic PWM waveform with
carrier polarity variation
If a two-HB THMI is used to synthe size the nine-level phase leg voltage
as shown in Figure 52 (b), the higher voltage HBs will switch at high
frequ encies, since the output voltage varies between E and 2E or -E and -
95
2E continually in certain interval. In THMI, it is not appropriate that the
higher voltage HBs switch at high frequency. Therefore, the sub-
harmonic PWM is not applicable in THMI.
Figure 53. Illustration of the simple modulation strategy
2.7.3.5. Simple modulation strategy
The simple modulation strategy is the simplest modulation strategy with
which the switching pattern is determined by comparing a reference
signal with stages and then choosing the stages most close to the
reference signal. Figure 53 shows the illustration of the simple
modulation strategy with the nine-level output voltage.
96
The advantage of this strategy is simple control algorithm, high
flexibility and dynamic response. The disadvantage is that the amplitudes
o f lower order harmonic components are relatively higher. The THMI can
generate the greatest voltage levels among all multilevel inverters using
the same number of components. If the number of voltage levels is high
enough, the lower-order harmonic components of output voltages will be
very small with the simple modulation strategy. For example, in the case
of a four-HB THMI that can generate 81-level voltage, with the simple
modulation strategy, the amplitude of each lower-order harmonic
components of the output voltage is less than 0.9% of the amplitude of
the fundamental component and THD of output voltage is less than 2%.
2.7.3.6. Summary of modulation strategies for THMI
Several modulation strategies have been investigated. With the hybrid
m odulation strategy and modulation strategies working with high
switching frequencies, such as sub-harmonic PWM s trategy, a voltage
waveform must be synthesized to modulate at high frequency among all
adjacent voltage steps. However, in THMI, it cannot be achieved when
only the lowest voltage HB switch at high frequency, which can be
derived from (64) and (80). In other words, if a voltage can be
synthesized to modulate at high frequency in THMI, the higher voltage
HBs must switch at high frequency. One of most important advantage of
THMI is that higher voltage HBs can switch at lower frequency.
Therefore, higher-frequency switching of higher voltage HBs not only is
97
unacceptable in high power application but also violate the main
advantage of THMI. Therefore, the hybrid modulation strategy and other
modulation strategies working with high switching frequencies are not
applicable in THMI. The low-frequency modulation strategies such as
step modulation strategy and virtual stage modulation strategy are
suitable in THMI. In the virtual stage modulation, additional constraint,
such as (79) for two-HB THMI, must be added to ensure the higher HB
switch at lower frequency. Additionally, the simple modulation strategy
can be used in the THMIs that can generate many voltage levels. At the
same time, for the THMIs that can generate many voltage levels, the
space vector modulation {Rodriguez, 2004 #54} can achieve a very good
linearity between the modulation index and the fundamental component
of load voltage and eliminate common-mode voltages.
2.7.4. Regenerative Power
The dc sources of the THMI can be batteries or bridge rectifies. Batteries
cannot endure large reverse current for a long ti me, which will damage
batteries. Diode bridge rectifies cannot permit reverse power. Controlled
bridge rectifies can transmit energy to supplies. However, compared to
simple diode bridge rectifies, the controlled bridge rectifies are much
more complex and costly because of complex control circuits and higher
price of controlled semiconductors.
98
2.7.4.1. Analysis of dc bus power injection
The switching function is involved in the analysis of dc bus power
in jection. The switching function, F, is shown in Table 1. The
relationship between output voltage of a HB , v H , and dc link voltage of
the HB, V dc , can be written as (82). The relationship between i dc (current
flowing through the dc bus) and i an (output current of the THMI) can be
also derived as (83).
vH = F⋅ Vdc (81)
idc = F⋅ ian (82)
Only fundamental component of output current of the THMI is
c onsidered since high frequ ency harmonic components do not gen erate
a verage power. So i an can be expressed as
ian = I an ⋅ sin(ωt + ϕ ) (83)
where I an is the amplitude of i an and ϕ is the angle of power factor.
General waveforms of v H and i an are shown in Figure 48. The average dc
p ower that supplies the HB over a p eriod can be calculated as (84)
1 T
T ∫0
Pdc = Vdc ⋅ idc dt (84)
where T is the period of i an . From (82) and (84), we can get
1 T 1 T
Pdc =
T ∫
0
Vdc ⋅ F⋅ ian dt =
T ∫0
vH ⋅ ian dt (85)
99
Figure 54. General waveform of dc bus voltage and THMI output current
Th e relationship between switching angles in Figure 54 can be express ed
a s (86).
⎧ π + θ i − 2ς i = (2ς + 1) 4ς
θi = ⎨ (86)
⎩π − θ 2ς +1−i i = (ς + 1) 2ς
Derived from (86), v H has following characteristic
vH (π − ωt ) = vH (ωt ) (87)
vH (ωt + π ) = −vH (ωt ) (88)
F rom (79), we can get
ian (ωt + π ) = −ian (ωt ) (89)
Derived from (88) and (89), the average dc power can be calculated over
h alf period as:
2 T2
Pdc = ∫ vH ⋅ ian dt (90)
T 0
Suppose P i mean the power is generated by the voltage pulse from θ i / ω to
θ i+1 / ω and corresponding voltage p ulse from θ 2 ς-i / ω to θ 2 ς+ 1 -i / ω. P i can be

expressed as:
100
(−1) n ω θi +1 / ω θ 2 ς +1−i / ω
Pi = (∫ Vdc ⋅ I an ⋅ sin(ωt + ϕ )dt + ∫ Vdc ⋅ I an ⋅ sin(ωt + ϕ )dt ) (91)
π θi / ω θ 2 ς −i / ω
where i = 2n – 1 a nd n is natural number. Derived from (86) and (91), P i
is expressed as
(−1) n
Pi = Vdc ⋅ I an ⋅ 2 ⋅ cos(ϕ ) ⋅ (cos(θi ) − cos(θi +1 )) (92)
π
Thus, the average dc power of the HB can be expressed as:
2
Pdc = Vdc ⋅ I an ⋅ cos(ϕ ) ⋅ ∑ (cos(θ 4 n −3 ) − cos(θ 4 n − 2 ) − cos(θ 4 n −1 ) + cos(θ 4 n )) (93)
π
In (89), if θ j is greater than π /2, θ j will be set as π /2.
In general, power factor angle ϕ is from - π /2 to π /2, so cos(φ) is greater
than zero. V dc and I an are positive. Thus, we can conc lude from (93) that
th e power of dc bus is negative if:
∑ (cos(θ 4 n +1 ) − cos(θ 4 n + 2 ) − cos(θ 4 n +3 ) + cos(θ 4 n + 4 )) < 0 (94)
Negative power of dc bus means regenerative power.
2.7.4.2. Regenerative power in THMI
Regenerative power may occur in lower-voltage HBs of THMI. Take the
e xample of a two-HB THMI. If the step modulation strategy is applied,
the restrictions that are added to (78) to ensure power of dc buses is
always positive are shown in Table 8. With these restrictions, ranges of
relative modulation index are calculated as shown in Table 9. The range
of relative modulation index decreases much when σ is two or three
compared with Table 6. The range of modulation index is not continuous

101
as shown in the last column of Table 9. The regenerative power will
occur in the lower voltage HB when M is from 0.51 to 0.55 or from 0.33
to 0.44.
Table 8. Additional restriction to avoid regenerative power of dc buses
in the step modulation

σ Restriction
1 cos(θ 1 ) > 0
2 cos(θ 1 ) - 2cos(θ 2 ) > 0
3 cos( θ 1 ) - 2cos( θ 2 ) + cos( θ 3 ) > 0
4 cos(θ 1 ) - 2cos(θ 2 ) + cos(θ 3 ) + cos(θ 4 ) > 0
Consider the v irt ual sta ge modulatio n strategy is used in a two-HB THMI.
In Table 7, tw o cases are analyzed. One is four-level positive/negative
output voltag e with two virtual stages and the other is fi ve-level
positive/negative output voltage with one virtual stage. Only dc bus of
the lower voltage HB is possible to have regenerative power. For the first
case, the restriction that ensures positive power can be written as:
cos(θ p1 ) − 2cos(θ p 2 ) + cos(θ p 3 ) + cos(θ p 4 ) + cos(θ p 5 ) + cos(θ p 6 ) − cos(θ n1 ) − cos(θ n 2 ) > 0 (95)
Table 9. Range of modulation index with the step modulation in a two-
HB THMI (avoid regenerative power of dc buses)

σ MR MR M M Range of
(min) (max) (min) (max) MA
1 0 1 0 0.25 0-0.15
2 0.3 0.66 0.15 0.33 0.15-0.33
3 0.59 0.68 0.44 0.51 0.44-0.51
4 0.55 0.86 0.55 0.86 0.55-0.8 6
4* 0.56 0.94 0.56 0.94 0.86-0.9 4
102
To the second case, the r est riction c an be exp ressed as :
cos(θ p1 ) − 2 cos(θ p 2 ) + cos(θ p 3 ) + cos(θ p 4 ) + cos(θ p 5 ) − cos(θ n1 ) > 0 (92)
With th ese res trictio ns, t he ran ge of relative modulation index de creases
a s shown in Table 10. The regenerative power will occur in the lower
voltage HB when M is from 0.53 to 0.62.
Table 10 . Range of modulation index range with the virtual stage
modulation strategy in a two-HB THMI (avoid regenerative power of dc bus)

σ β MR (min) MR (max) M (m in) M (max) Range of M
3 1 0.62 0.71 0.46 0.53 0.46-0.53
4 2 0.62 0.92 0.62 0.92 0.62-0.92
2.7.4.3. Method to avoid regenerative power
In last s ec tio n, the regenerative power that lower voltage HBs is possi ble
t o g ene rat e i s disc ussed . In t his se ction, the meth ods th at are use d to
s olve this problem will be introduced. A method is proposed that the dc
links of lower voltage HBs are supplied by the low power, isolated power
sources fed by a common power supply from the highest voltage HB.
These power sources is bidirectional and a bidirectional dc-dc power
supply is used for this purpose. It is also possible to use independent
output transformers with a common dc supply, as show in Figure 55. A
variation of this configuration was used by ABB in his 16 2/3 Hz
substation for railroads in Bremen (Germany). In the system described
here, the transforms are smaller for lower voltage HBs because the
103
voltages are scaled in power of three. Besides, the switching frequency of
transformers connected with lower voltage HBs are lower. Then the
transforms connected with lower voltage HBs become smaller for two
reasons: voltage and switching frequency.
Figure 55. THMI with output transformers
The above two methods to solve the problem of the regenerative power
use additional equipments, such as bi-directional dc-dc converter or
output transformers, which increase the cost of the inverter system and
power losses. A new method is presented to avoid regenerative power.
This method does not use additional devices. The regenerative power is
104
eliminated by avoiding outputting several null voltage levels, which will
be explained by an example of a four-HB THMI in the following.
The average power of the DC bus of a HB can be expressed as (93). In
general, power factor angle ϕ is from - π /2 to π /2, so cos(φ) is greater
th an zero. V dc and I an are positive. Therefore, from (93) and Figure 54, we
can conclude that the reason of the regenerative power is the negative
segments of v H when the fundamental components of v an is positive or the
positive segments of v H when the fundamental components of v an is
negative. The segments of v H resulting in the regenerative power of the
HB are called regenerative segments. The basic idea of eliminating
regenerative power is to avoid output several levels of v an which will
cause regenerative segments in HBs. Table 11 shows the voltage levels
of v an which cause regenerative segments of HBs in the case of a four-HB
THMI. The voltage levels of v an which are not selected to output are
called null voltage levels. Table 11 also shows the priory of null voltage
levels. For example, if the regenerative power occurs in the dc link of the
HB 1 , the voltage level (14) and (-14) are selected as null voltage levels
firstly. If the regenerative power still occurs, the voltage levels (17) and
(-17) are also selected as null voltage levels. With the priory shown in
the Table 11, the null voltage levels distribute as evenly as possible,
which results in better power quality.
105
Table 11. Voltage levels of van which cause regenerative segments of HBs
HB 1 ±14, ±17, ±32, ±23, ± 5, ± 20, ± 38, ± 29, ± 26, ± 11, ±2, ±8, ±35
HB 2 ±14, ±32, ±23, ±5, ±15, ± 34, ± 25, ± 7, ± 16, ± 6, ± 24, ±33
HB 3 ±14, ±17, ±15, ±20, ±19, ±16, ±21, ±18, ±22
Figure 56. Flow chart of the algorithm to stabilize dc link voltages
Figur e 56 shows the flow chart of the algorithm that stabilizes the dc link
v oltage of a HB. V dc is the dc link voltage of a HB. V dc,normal is the normal
dc link voltage. V dc,last is the dc link voltage in the previous sampling.
N null is the number of null voltage levels. In the switch table, the voltage
levels are set as null or not based on N null and Table 11.
106
Figure 57. Relationship between the modulation index and THD
With lower modulation index, the power quality that the THMI outputs is
a little bit poorer with the proposed control scheme because more null
v oltage levels do not devote themselves to the output voltage of the
THMI. In the case of the four-HB THMI, with up to 81-level output
voltage of the THMI, the simple modulation strategy as shown in section
3 is suitable for the THMI. If the simple modulation strategy is used and
the new method is applied to eliminate the effect of regenerative power,
the relationship between the modulation index and the THD is shown in
Figure 57.
2.7.4.4. Summary of regenerative power in THMI
The topolog y of THMI has distinct advantage of least components used
c ompared with other topologies of multilevel inverters, but the THMI

107
also has notable disadvantage that power of the lower voltage HBs is
possible to be regenerative with lower modulation index. If the THMI
feeds a RL or RC load and simple diode bridge rectifies are used as dc
sources, the regenerative power will cause the increase of the dc
capacitor voltages, which will damage devices.
Therefore, basically, the THMI is suitable for two applications. The first
one is the application of reactive power com pensation. The average
p ower of dc link of a HB is zero when power factor angle is zero as
shown in (89), so the problem of regenerative power is avoided. The
second one is the application in which the inverter always runs with
higher modulation index. From Table 9, we can find that the two-HB
THMI runs with step modulation without problem of regenerative power
when M is from 0.55 to 0.94. From Table 10, we can find that the two-
HB THMI runs with virtual stage modulation without problem of
regenerative power when M is from 0.62 to 0.92.
However, the inverter is required to work at any modulation index for
active load in most cases. Two methods have b een presented to solve
r egenerative power problem. The first one uses bidirectional dc/dc
converters and the second one use additional output transformers. A new
method to solve the regenerative power is presented as a cost-effective
solution because it does not use additional equipments. The dc capacitor
voltages of lower voltage HBs are kept stable by the new method. The
108
tradeoff is that power quality will decrease a little bit with lower
modulation index.
2.7.5. Experimental Results
2.7.5.1. Experiment to verify the step modulation and virtual stage
modulation
The performance of step modulation strategy and virtual stage
modulation strategy has been verified by the experimental of a single
two-HB THMI. In the control circuit, a TMS320F240 DSP is used as the
main processor, which provides the gate logic signals. In a HB, four
MOSFETs, IRF540, are used as the main switches, which are connected
in a full-bridge configuration. The load is a 23.2 Ω resistor. The total
ratio of voltage measure is 1:2. The frequency spectrums are analyzed by
the FFT (Fast Fourier Transform) function of oscilloscope. The scale of
Y-axis of frequency spectrum is 5dbV/div and reference level is 5dbV.
Figure 58. Output voltage of the THMI with the step modulation M = 0.83
(10V/div)
109
Figure 59. Frequency spectrum with the step modulation M = 0.83
The switching pattern of step modulation technique is programmed and is
loaded to the DSP. In step modulation strategy, when output voltage
levels are nine and M is 0.83, the switching angles are 0.14778, 0.32325,
0.57376 and 0.99696. The THMI output voltage is shown in Figure 58.
The frequency is 50Hz and the step voltage is about 5V. The frequency
spectrum is shown in Figure 59. The 5th, 7th and 11th harmonics are less
than 0.028V (–37db×2V), which means they are nearly eliminated. It
verifies the simulation result as shown in Figure 59.
When output voltage levels are seven and M is 0.49, the switching angles
are 0.44717, 0.9097 and 1.1215. The output voltage of the THMI is
shown in Figure 60 and the frequency spectrum is shown in Figure 61.
The 5th and 7th harmonics are less than 0.02V (–40db×2V), which means
they are nearly eliminated.
110
(10V/div)
111
(10V/div)
When output voltage levels are five and M is 0.32, the switching angles
are 0.51847 and 1.1468. The output voltage of the THMI is shown in
Figure 62 and the frequency spectrum is shown in Figure 63. The fifth
harmonics are less than 0.02V (–40db×2V), which means they are nearly
eliminated.
112
Figure 64. Output voltage of the THMI with the virtual stage modulation M =
0.83 (10V/div)
Figure 65. Frequency spectrum with the virtual stage modulation M = 0.83
The switching pattern of modified virtual stage modulation technique is
programmed and is loaded to the DSP. In virtual stage modulation, when
output voltage levels are nine and M is 0.83, the switch ing ang les are
0.13177, 0.33186, 0.52855, 0.6202, 0.91294, 1.0423, 0.57124 and
0.96573. The output voltage of the THMI is shown in Figure 64 and the
frequency spectrum is shown in Figure 65. T he 5th, 7th, 11th, 13th, 17th,
1 9th and 23rd harmonics are less than 0.035V (–35db×2V), which means
113
they are nearly eliminated. It verifies the simulation result as shown in
Figure 65.
Figure 66. Output voltage of the THMI with the virtual stage modulation M =
0.49 (10V/div)
Figure 67. Frequency spectrum with the virtual stage modulation M= 0.49
When output voltage levels are seven and M is 0.49, the switching angles
are 0.40549, 0.88038, 1.1497, 1.5318 and 1.5082. The output voltage of
the THMI is shown in Figure 66 and the frequency spectrum is shown in
114
Figure 67. The 5th, 7th, 11th and 13th harmonics are less than 0.02V (–
40db×2V), which means they are nearly eliminated
2.7.5.2. Experiment to verify the new method to eliminate the
regenerative power
Figure 68. General representation of experimental test system
The performance of the methods to eliminate the effect of regenerative
power by avoiding output the null voltage levels is verified by the
e xperiment of a 4-HB THMI, in which diode bridge rectifies are used as
the dc sources of HBs. The step voltage is 5.9V. The frequency of output
voltage is set at 50 Hz and the sampling frequency is set at 10 kHz. The
output voltage levels of the inverter has up to 81 levels, so the simple
modulation strategy as show in section 0. The control algorithm to
stabilize the dc link voltages is shown in Figure 68. A TMS320F240 DSP

115
controlled card is used to control the inverter. The configuration of
experimental system is shown in Figure 68.
Figure 69. Waveform of output voltage of the inverter with the simple
modulation strategy M = 0.79 (100V/div), Frequency = 50 Hz, THD = 1.94%
Figure 69 shows the waveform of output voltage of the 4-HB THMI with
simple modulation strategy when modulation index is 0.79. The power
quality is good due to a great deal of voltage levels.
Figure 70. Waveform of output voltage of the inverter M = 0.7 (100V/div)

116
Figure 70 shows the output voltage waveform with some null voltage
levels when modulation index is 0.7. From the enlarged figure, we can
observe that some voltage levels are not generated. Moreover, the step
voltages are kept nearly same, which means that the voltages of dc
cap acitors are kept stable. Figure 71 shows the worst case when the
m odulation index is 0.53. In this case, null voltage levels include ±5, ±14,
± 15, ±16, ±17, ±19, ±20, ±21, ±23, ±32 and ±34.
Figure 71. Waveform of output voltage of the inverter M = 0.42 (100V/div)
117

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E6501 POWER ELECTRONIC CONVERTERS (39 h)

SECTION D: DC/AC INVERTERS (12 h)

By Associate Professor Luo Fang Lin (DR)

(S1-B1c-108, Tel: 5023, e-mail: [email protected])

technology that has four aspects:

DC/AC inversion technology is a big subject area in research

investigation and industrial applications. We study the DC/AC inverters

in advanced schemes: pulsewidth modulation (PWM) technique,

multilevel inversion technique and z-source inversion technique (not

introduced in this course). PWM technique was carefully discussed in

under-graduate courses. We just review some switching signal

arrangement; do NOT pay more attention in the whole technique in

switching circuits applied in industrial applications in comparison with

other power switching circuits. In recent century, plenty of topologies of

are mainly used in AC motor adjustable speed drive (ASD). Although

DC/AC inverters were widely used in industrial application since later

1980’s. Semiconductor manufacture development brought Power devices

such as GTO, Triac, BT, IGBT and MOSFET and so on in higher

switching frequency (say from thousands Hz up to few MHz) into the

DC/AC power supply since 1980’s. Because of the devices such as

thyristor (SCR) with low switching frequency, the above mentioned

devices have low power rate.

Square-waveform DC/AC inverters were used in early ages before 1980’s.

In those equipment thyristor, GTO and Triac could be used in low-

frequency switching operation. High frequency/high power devices such

as Power BT and IGBT were produced in 1980’s. The corresponding

equipment implementing the pulsewidth-modulation (PWM) technique

Nowadays, most DC/AC inverters are PWM DC/AC inverters in different

applications. They are generally used in following applications:

1. Variable voltage/Variable frequency AC supplies in adjustable

speed drive (ASD), such as induction motor drives, synchronous

machine drives and so on.

2. Constant regulated voltage AC power supplies such as

uninterruptible power supplies (UPS’s).

3. Static var (reactive power) compensations

4. Passive/Active series/parallel filters.

5. Flexible AC transmission systems (FACTS’s)

(a) Switch-mode inverter in AC motor drive

Figure 1. A standard adjustable speed drive scheme

Adjustable speed induction motor drive systems are widely applied in

industrial applications. These system requested the DC/AC power supply

with variable frequency usually from 0 Hz to 400 Hz in fractional horse-

power (HP) to hundreds HP. A large number of DC/AC inverters are in

produces variable frequency and voltage to implement ASD.

1.1. Pulse-Width Modulation (PWM)

The pulsewidth modulation (PWM) technique is a popular method to

implement DC/AC inversion technology. The corresponding circuit is

knowledge in your undergraduate courses. We will review this technique,

and mainly introduce other advanced methodologies in this course.

and different widths, which corresponding to the input signal at the

(a) Input signal

(b) Output signal

Figure 2. Typical input and output waveforms of a pulsewidth modulator

The modulation ratio m is arranged in certain area, which is usually

yielded by a uniformed-amplitude triangle (carrier) signal with the

amplitude V tri-m . The maximum amplitude of the input signal is assumed

Figure 3. Voltage control by varying ma

We also define the frequency modulation ratio m f as follow expression.

than and/or equal to the modulation ratio m a . The voltage control by