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PVL333

The document appears to be an exam for a course on System on Chip design. It contains 5 questions related to topics like transaction level modeling, embedded memory testing approaches, power estimation techniques, verification flows, functional vs performance verification, and test data reduction techniques.

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Lets clear Jee maths
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29 views1 page

PVL333

The document appears to be an exam for a course on System on Chip design. It contains 5 questions related to topics like transaction level modeling, embedded memory testing approaches, power estimation techniques, verification flows, functional vs performance verification, and test data reduction techniques.

Uploaded by

Lets clear Jee maths
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Roll Number:

Thapar Institute of Engineering and Technology, Patiala


Department of Electronics and Communication Engineering
END SEMESTER EXAMINATION
M. Tech (2 nd Sem: (Jan- May,2022) Course Code: PVL 333
VLSI Course Name: System on Chip
May, 30th ,2022 Monday, 8.00 a.m-10.00 a.m.
Time: 2 Hours, M. Marks: 35 Name Of Faculty: GPK
Note: 1) Attempt any 5 questions
2) Assume missing data, if any, suitably
Q.1 What is Transaction Level modeling? Compare it with RTL and Cycle accurate (2+3+
modeling. Also list its advantages. 2)
Q.2 Discuss Different approaches for Testing of Embedded Memories in SoC (7)
Testing.

Q.3 (a) Consider below the architecture of a simple system to be designed. (5)
Assuming a high level power analysis is required which power estimation
approach would be preferred for power estimation and why? Discuss how
cache miss scenario would be used when power consumption is estimated.

Note: IU stands for Integer Unit

Q3(b) Explain difference between lint checker and compiler with help of an example. (2)
Q.4 Discuss the verification at different stages of Top down SoC design Flow. (7)
Compare it with platform based verification and cite the reasons for shift in
verification approach from top down to platform based.
Q5(a) With help of a suitable example explain the difference between functional (3)
verification and performance verification. Where do they fall in SoC design
flow?
Q5(b) What are different test data reduction techniques used in Chip testing? (4)
Show with help of a diagram the test schedule and use of TRP compression
techniques.

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