Scribd
Upload
54 views23 pages

C Sec Eiot Unit3

ARM processors use a RISC architecture and have gone through multiple revisions. They have a 5-stage pipeline and support both 32-bit ARM and 16-bit Thumb instruction sets. The ARM register set and program status register change based on the current operating mode, with some registers banked for different modes. Common versions include ARM7 and ARM9 families, with ARM7TDMI being a popular microcontroller.

Uploaded by

209X1A0467 KOTLA ANUSHA
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
54 views23 pages

C Sec Eiot Unit3

ARM processors use a RISC architecture and have gone through multiple revisions. They have a 5-stage pipeline and support both 32-bit ARM and 16-bit Thumb instruction sets. The ARM register set and program status register change based on the current operating mode, with some registers banked for different modes. Common versions include ARM7 and ARM9 families, with ARM7TDMI being a popular microcontroller.

Uploaded by

209X1A0467 KOTLA ANUSHA
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 23

ARM Processors

ARM Processor:

ARM Design Philosophy, RISC vs CISC, ARM 7 and 9 processor family

Block Diagram, Registers, Program Status Register

Five Stage Instruction Pipeline, and Architecture Revision.

Instruction Set, Addressing Mode.

Introduction to Thumb Instruction Set.


Necessity to select variety of Processors

Feature Enhancement

Architectural Modifications

Design Requirements

> Low Power

> High Speed

> Reliability

> Efficiency of the device for various environments


ARM stands for Advanced RISC Machine

Earlier called Acorn RISC Machine

Framed with RISC Architecture

Developed in 1990s.

Available in 16 bit , 32 bit and 64 bit size.


ARM Design Philosophy

RISC Architectures
VERSIONS of ARM family

ARM 1
ARM 2 -- 32 bit data and 26 bit address
ARM 3 to ARM 6

ARM 7 became popular Microcontroller and Real time


application based controller
Features of ARM 7

Deigned by ARM Holdings company

32 bit processor

Designed majorly for embedded applications

Around the years 1993- 2005

Various versions of this family


ARM700, ARM710,
ARM7DI, ARM710a,
ARM720T, ARM740T, ARM710T,

ARM7TDMI,
ARM7TDMI-S,
ARM7EJ-S
Most popular controller version of ARM 7 is

LPC 2148 with features of ARM 7 TDMI

LPC2148 Features

Vcc - 3 to 3.6 V

Clock - 30 MHz – 50 MHz

Data - 32 bit

RAM - 40 KB

Flash - 512 KB

Two 32 bit timers

One A to D converter

Inbuilt Interrupt controller


ARM BLOCK Diagram
REGISTER ORGANIZATION

Current Visible Registers


r0
Abort Mode
r1
r2
r3 Banked out Registers
r4
r5
r6 User FIQ IRQ SVC Undef
r7
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12
r13 r13 r13 r13 r13 r13
(sp)
r14 (sp)
r14 (sp)
r14 (sp)
r14 (sp)
r14 (sp)
r14
(lr)
r15 (lr) (lr) (lr) (lr) (lr)
(pc)
cpsr
spsr spsr spsr spsr spsr
Operating Modes

• Seven operating modes:


– User
– Privileged:
• System (version 4 and above)
• FIQ
• IRQ
• Abort
exception modes
• Undefined
• Supervisor
• The ARM has seven basic operating modes:

– User : unprivileged mode under which most tasks run

– FIQ : entered when a high priority (fast) interrupt is raised

– IRQ : entered when a low priority (normal) interrupt is raised

– Supervisor : entered on reset and when a Software Interrupt


instruction is executed
– Abort : used to handle memory access violations

– Undef : used to handle undefined instructions

– System : privileged mode using the same registers as user mode


The ARM Register Set
User mode IRQ FIQ Undef Abort SVC
r0
r1
ARM has 37 registers, all 32-bits long
r2
r3 A subset of these registers is accessible in
r4 each mode
r5 Note: System mode uses the User mode
r6 register set.
r7 SPSR registers are used to save CPSR
r8 r8 of previous mode
r9 r9
r10 r10
r11 r11
r12 r12
r13 r13 r13 r13 r13 r13
(sp)
r14 (sp)
r14 (sp)
r14 (sp)
r14 (sp)
r14 (sp)
r14
(lr)
r15 (lr) (lr) (lr) (lr) (lr)
(pc)

cpsr
spsr spsr spsr spsr spsr

Current mode Banked out registers


The ARM Register Set

Current Visible
Current Visible Registers
Registers
r0
Abort
SVC
Undef
FIQ
User Mode
Mode
Mode
IRQMode
Mode
Mode
r1
r2
r3 Banked
Banked
Bankedout
out
outRegisters
Registers
Registers
r4
r5
r6 User FIQ IRQ SVC Undef Abort
r7
r8 r8 r8
r9 r9 r9
r10 r10 r10
r11 r11 r11
r12 r12 r12
r13
r13 r13 r13 r13 r13 r13 r13
(sp)
(sp)
r14
r14 (sp)
r14 (sp)
r14 (sp)
r14 (sp)
r14 (sp)
r14 (sp)
r14
(lr)
(lr)
r15 (lr) (lr) (lr) (lr) (lr) (lr)
(pc)
cpsr
spsr
spsr spsr spsr spsr spsr spsr
CPSR Register

▪ Condition flags ▪ Interrupt masks


▪ N = Negative result from ALU ▪ I Disables IRQ interrupt
▪ Z = Zero result from ALU ▪ F Disables FRQ interrupt
▪ C = ALU operation Carried out ▪ T = 1 indicates Thumb execution
▪ V = ALU operation oVerflowed ▪ Mode bits determine the mode in
Which the processor operates
Program Status Registers
31 28 27 24 23 16 15 8 7 6 5 4 0

N Z C V Q J Un d e f i n e d I F T mode
f s x c

• Condition code flags • Interrupt Disable bits.


– N = Negative result from ALU – I = 1: Disables the IRQ.
– Z = Zero result from ALU – F = 1: Disables the FIQ.
– C = ALU operation Carried out
– V = ALU operation oVerflowed • T Bit
– Architecture xT only
• Sticky Overflow flag - Q flag – T = 0: Processor in ARM state
– Architecture 5TE/J only – T = 1: Processor in Thumb state
– Indicates if saturation has occurred
• Mode bits
• J bit – Specify the processor mode
– Architecture 5TEJ only
– J = 1: Processor in Jazelle state
Pipeline changes for ARM9TDMI

ARM7TDMI
ARM decode
Instruction Thumb→ARM Reg Reg
Shift ALU
Fetch decompress Read Write
Reg Select

FETCH DECODE EXECUTE

ARM9TDMI
ARM or Thumb
Instruction Inst Decode Memory Reg
Shift + ALU Write
Fetch Reg Reg Access
Decode Read
FETCH DECODE EXECUTE MEMORY WRITE
ARM Instruction Set
Data Sizes and Instruction Sets
• The ARM is a 32-bit architecture.

• When used in relation to the ARM:


– Byte means 8 bits
– Halfword means 16 bits (two bytes)
– Word means 32 bits (four bytes)

• Most ARM’s implement two instruction sets


– 32-bit ARM Instruction Set
– 16-bit Thumb Instruction Set

• Jazelle cores can also execute Java bytecode (8-bit


instructions)
Instruction Set
• Different types of instructions
– Data processing instructions
– Load-store instructions
– Branch instructions
– Software interrupt instruction
– Program status register instructions

• Some unique features of arm ISA


– Conditional execution
– Barrel shifter

You might also like