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International Journal of Electronics

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Step-by-step design procedure for

a grid-connected three-phase PWM
voltage source converter
a b a
Marco Liserre , Frede Blaabjerg & Antonio Dell’Aquila
a
Department of Electrotechnical and Electrical Engeneering,
Polytecnic of Bari, 70125, Bari, Italy
b
Institute of Energy Technology, Aalborg University, DK-9220,
Aalborg East, Denmark
c
Department of Electrotechnical and Electrical Engeneering,
Polytecnic of Bari, 70125, Bari, Italy E-mail:
Version of record first published: 20 Feb 2007.

To cite this article: Marco Liserre , Frede Blaabjerg & Antonio Dell’Aquila (2004): Step-by-step
design procedure for a grid-connected three-phase PWM voltage source converter, International
Journal of Electronics, 91:8, 445-460

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 INT. J. ELECTRONICS, VOL. 91, NO. 8, AUGUST 2004, 445–460

Step-by-step design procedure for a grid-connected

three-phase PWM voltage source converter

MARCO LISERREy*, FREDE BLAABJERGz and

ANTONIO DELL’AQUILAy

The voltage source active rectifier is one of the most interesting solutions to
interfacing dc power systems to the grid. Many elements are responsible for the
overall system behaviour, such as value of the passive elements, sensors position,
analog/digital filters and ac current/dc voltage controllers. In this paper a step-
by-step design procedure, taking into account all these elements, is proposed and
validated through the tests on an experimental prototype. The reported results are
particularly relevant to evaluate the influence on the grid current harmonic content
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of the grid sensor position and of the use of analog filters in the feedback signals.

Nomenclature
Rg, Lg resistance and inductance of the grid side reactor
R, L resistance and inductance of the converter side reactor
Cf capacitance of the input filter
Rd damping resistance of the input filter
C capacitance of the dc bus
Zb, Cb, !b base impedance, capacitance and pulsation
Xi reactance of the ith passive element
xi per unit (pu) reactance of the ith passive element
fn, !n grid frequency and pulsation
fres, !res resonance frequency and pulsation of the input filter
fsw switching frequency of the converter
e, E grid voltage and its rms value
i g, I g grid current and its rms value
i, I converter current and its rms value
v o, V o dc voltage and its average value
i L, I L dc load current and its average value
Po average value of the dc power

c, ,
v ac current and dc voltage constants
kp,c, TI,c current controller gain and time constant
kp,v, TI,v voltage controller gain and time constant

Received 3 March 2004. Accepted 25 August 2004.

*Author for correspondence. e-mail: [email protected]
yDepartment of Electrotechnical and Electrical Engeneering, Polytecnic of Bari, 70125,
Bari, Italy.
zInstitute of Energy Technology, Aalborg University, DK-9220, Aalborg East, Denmark.

International Journal of Electronics ISSN 0020–7217 print/ISSN 1362–3060 online # 2004 Taylor & Francis Ltd
http://www.tandf.co.uk/journals
DOI: 10.1080/00207210412331306186
 446 M. Liserre et al.

1. Introduction
The front-end stage of a dc power system is not a mass-produced product. In fact
it should be specifically designed for the application it is used for, such as chemical,
electrolysis, aluminum, graphitizing furnace, copper refining, traction substation, ac
and dc drive systems. If the attention is focused on applications that can take
advantage from dc voltage regulation, the diode bridge with on-load tap changers
or with saturable core reactors and the thyristor bridge are still the preferred design
solutions with respect to diode bridge plus chopper systems. For historical reasons
the diode bridge plus chopper has been considered as the ‘new’ solution in the
rectifier field. In fact the chopper has been successfully experimented in traction
system over the past 30 years. Hence it was quite natural to consider the chopper
as the next step for other rectifier applications. However, the use of a chopper stage
increases the number of switching devices that results in a higher failure rate and
mean time to repair (MTTR) (Siebert et al. 2002).
In this scenario, active rectifiers, employing voltage source converters (VSCs) first
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proposed by Wilson (1978) or current source converters (CSIs), are valid competitors
both for traditional solutions such as the thyristor and for newer ones such as a
chopper, due to the reduced number of power devices and the capability of grid
current and power factor control (Kolar and Ertl 1999).
Particularly, VSCs employing pulse width modulation (PWM) techniques, are
the widest used power converters for applications such as industrial motor drives,
robotics, air conditioning and ventilation, uninterruptible power supplies and elec-
tric vehicles. Thus they are also being considered as prime candidates for interfacing
high-power electronic equipment to power supply lines especially in the case when
the load is regenerative.
The active rectifier has been well studied in its theoretical aspects with detailed
models (Wu et al. 1991, Blasko and Kaura 1997). However its main limitations are in
the absence of guidelines for the design, of both the passive coupling, the filtering
elements and the control systems, specifically oriented to make it reliable and com-
petitive with respect to other solutions. The design key is in the trade-off between the
need for enough filtering, a satisfactory dynamic performance and the reduction
of costs.
In the following, guidelines for designing the passive elements of a VSC-based
active front-end stage and guidelines for designing the control of the VSC will be
explained and finally experimental results will confirm the proposed methods.

2. Passive elements
The voltage source converter needs both ac and dc passive elements, as shown in
figure 1. The passive elements, such as capacitors or inductors have both storage and
filtering functions.
The energy stored in the ac passive stage is less than 5% of all the energy stored,
thus the main storage element is the dc capacitor charged to a voltage which is able
to ensure the basic function of the VSC: the VSC can control the ac current ig,
through the switching and acting as current source. Then through the ac current
control, the VSC can change and control the dc value vo of the capacitor. Thus the
filtering action, which is necessary because of the fast switching PWM, is done both
on the dc side and on the ac side. The passive elements are charged/discharged
during the switching period, ensuring the smoothing of the ac currents and of the
 Design for a PWM Voltage Source Converter 447

PCC DC-BUS

ig Lg L
vo
Cf
e VSC

ea
vo
iga
ωt
t

Figure 1. Voltage source converter used as active rectifier with a sketch of the desired grid
current ig in phase with the grid voltage e and of the desired dc voltage vo.
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dc voltage. This filtering action is also the basis of the control performed. In fact the
dynamics of the ac-current/dc-voltage control depend on the time constants of the
two filtering stages. Generally, the overall design, that should include filtering and
control issues, is a trade-off between a high filtering and a fast dynamic performance.
Once clarified the main function of the passive elements, some design rules
regarding capacitors and inductors can be introduced. In order to have a reference
for all these parameters the following base values will be introduced
ðEn Þ2
Zb ¼ ð1Þ
Pn

1
Cb ¼ ð2Þ
!n Zb

!b ¼ !n ð3Þ
where En is the line to line rms voltage, !n is the grid frequency and Pn is the active
power absorbed by the converter in the rated conditions. Thus the reactance of
L (X ¼ !L), of Lg (Xg ¼ !Lg) and of Cf (XC ¼ 1/!C ) are expressed in pu of the
base Zb: x ¼ X/Zb, xg ¼ Xg/Zb and xC ¼
Zb/XC.

2.1. Capacitors
Capacitors permit electrical energy to be stored over a long charging time and
then released as required during very short periods, under controlled conditions.
The main capacitor systems used in active rectifiers for the dc side are based
on polypropylene for high frequency filtering and electrolytic (0.2 kJ/kg) or film
(0.4 kJ/kg) for energy storage. The polymer film has higher rms current ratings per
mF, higher reliability but also higher costs and less load ride-through protection
during utility voltage sag events compared to electrolytic.
Instead for the ac side polymer, ceramic and polypropylene are typically used.
The designer should choose which type of capacitor is better suited for the specific
application (ac or dc), function (storage and/or filtering) and the frequency range
(Sarjeant et al. 2001).
 448 M. Liserre et al.

2.1.1. DC capacitor design. The choice of the value of the dc side capacitor is made
mainly on the basis of four criteria (Malesani et al. 1995):
 the delays introduced by filtering of the dc-voltage and current control Tr;
 tolerable dc voltage variation
Vo;
 maximum known variation of the power
PLMAX on the dc bus;
 desired load ride-through protection during utility voltage sag events.
The following expression can be used for the rating of the dc capacitor
Tr
PLMAX
C : ð4Þ
2Vo
Vo
Thus to have a fast dc voltage loop is clearly in contrast to the maximization of
the allowable power excursion on the dc bus and to the limitation of the dc voltage
variation, in fact the first aim leads to a decrease of C while the other two lead
to an increase of C. Usually the latter two are more important and the higher the
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C the better the system; however C is limited by cost, encumbrance and safety
considerations.
In the presence of voltage unbalance that causes the propagation of low fre-
quency harmonics in the active rectifier, the use of filters with lower cut-off frequency
increases the time constant Tr.

2.1.2. AC capacitor design. On the grid side the use of capacitors is justified by the
necessity to filter the switching frequency harmonics that can interfere with other
equipment, thus an LCL-filter configuration is typically adopted. The capacitor has
a different influence on the control system depending on the position of the current
and voltage sensors.
The following four cases will be reviewed by calculating the grid side zTgrid and
the converter side zTconv pu impedance at fn (as shown in figure 2 with the equivalent
circuit for the first two cases) neglecting the damping resistor. The adopted approx-
imations are affected by a 1% error, if xc is less than 10%. In the Appendix we report
on the mathematical steps needed for the calculation of zTgrid in the first case in order
to evaluate how the approximation affects the final result. If the capacitor voltage is
sensed and the converter current is controlled to be in phase with the voltage then

)
zTgrid ¼ 1 þ j xg
xC
ð5Þ
zTconv ¼ 1 þ jx:
Thus the grid side behaviour will not be resistor-like and a part of the reactive
power will be absorbed with a consequent decrement of the power factor seen at the
point of common coupling. Hence, the following expression can be used for the
rating of the ac side capacitor, in order to minimize the absorbed reactive power
Lg
Cf ¼ : ð6Þ
Zb2
If the capacitor voltage is sensed and the grid current is controlled to be in
phase then
)
zTgrid ¼ 1 þ jxg
ð7Þ
zTconv ¼ 1 þ jðx
xC Þ:
 Design for a PWM Voltage Source Converter 449
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Figure 2. Equivalent circuit for a current controlled active rectifier: with voltage sensed on
the capacitor and current sensed on the converter side (a); with voltage sensed on the
capacitor and current sensed on the grid side (b); with voltage and current sensed on the
grid side (c); with voltage sensed on the grid side and current sensed on the converter
side (d ).

Hence in order not to over-rate the VSC the following formula can be used for
the rating of the ac side capacitor
L
Cf ¼ : ð8Þ
Zb2

If the grid voltage is sensed and the grid current is controlled to be in phase then
)
zTgrid ¼ 1
ð9Þ
zTconv ¼ 1 þ jðx
xg
xc Þ:

Hence in order not to over-rate the VSC the following formula can be used for
the rating of the ac side capacitor
L
Lg
Cf ¼ : ð10Þ
Zb2
 450 M. Liserre et al.

If the grid voltage is sensed and the converter current is controlled to be in phase
with the voltage then
)
zTgrid ¼ 1 þ jð
xC Þ
ð11Þ
zTconv ¼ 1 þ jð
xÞ:
Hence in order to have a unity power factor and not to oversize the VSC xc and x
should be chosen as small as possible. As it regards x the value will be chosen
in order to limit the converter side switching ripple, as will be explained in the
following. As regards xc, in order to choose a small value and to limit the number
of the variables in the design of the filter, it can be chosen equal to x or xg depending
on which one is the smallest (hence according to (6) or (8) respectively).
In conclusion Cf can be chosen according to
8 
> L =Z 2
if ðaÞ or ðdÞ 
>
<
g b Lg < L

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Cf ¼ L=Zb 2
if ðbÞ or ðdÞL<L ð12Þ
>
> g
:
ðL
Lg Þ=Zb2 if ðcÞ:

2.2. Inductors
The main design rules for inductors are on the choice of the core dimension,
material and gap, and of the winding. The most used magnetic cores are iron, ferrite,
laminated metalloy and powdered metal. The required energy must be stored in a
non-magnetic gap distributed in the case of a powdered metal core, or in a discrete
gap in series in the case of a ferrite core.
If the switching frequency and the percentage of the current ripple are both low
enough, core losses will be low, and the inductor core may be limited by saturation.
In this situation, powdered metal cores are feasible with respect to gapped ferrite
cores because of their higher saturation. But with higher frequencies and/or larger
percent ripple current, core losses will dominate, and ferrites are preferred to the
others (Lotfi and Wilkowski 2001, Dixon 2000).
2.2.1. Converter side inductance L. The converter side inductance is designed in
order to limit the current ripple generated by the VSC. In fact the current ripple
is mainly due to the switching of the VSC and at that frequency the v/i ratio is
determined only by the converter side inductance. Thus
 
vðkÞ
L ¼ max ð13Þ
k k!b iLIMIT ðkÞ
where v(k) is the k-harmonic voltage generated by the VSC and iLIMIT(k) is the
maximum current ripple tolerable at the k-frequency (Bojrup 1999).
2.2.2. Grid-side inductance Lg. The grid side inductance is determined by the
acceptable switching ripple in the grid. Once chosen the value of the converter
side inductor L on the basis of (13), the grid side inductance will be expressed as a
function of this value
Lg
r¼ : ð14Þ
L
 Design for a PWM Voltage Source Converter 451

Moreover, as discussed in x2.1.2, there are three possible choices of Cf leading

to three expressions of the current ratio at a frequency f
9
ig 1 2 >
  if C f ¼ L=Z b >
>
i ð1 þ rÞ
rð f =cÞ2 >
>
>
>
>
>
ig 1 =
2
 2 2
 if C f ¼ L g =Z b ð15Þ
i ð1 þ rÞ
r ð f =cÞ >
>
>
>
ig 1
 2>
>
>
 2 2
 if Cf ¼ L
Lg =Zb > >
;
i ð1 þ rÞ
ðr
r Þð f =cÞ

where c ¼ Zb =ð2LÞ is a constant because the converter side inductance value has
been already chosen.
If f ¼ fres it follows that
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi 9
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fres ¼ c 1 þ 1=r if Cf ¼ L=Zb2 >

>
>
=
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
pffiffi 2
fres ¼ c 1 þ 1=r  1= r if Cf ¼ Lg =Zb ð16Þ
>
>
pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
pffiffiffiffiffiffiffiffiffiffiffi >
;
fres ¼ c 1 þ 1=r  1= 1
r if Cf ¼ ðL
Lg Þ=Zb2 :

These relations have been illustrated in figure 3. In the first case the resonance
frequency is less sensitive to the inductance ratio. The resonance frequency decreases
as the grid side inductance increases in respect to the converter side.
Moreover, the ripple attenuation for a frequency around the switching frequency
fsw is obtained from (15) with f ¼ fsw
9
ig 1 2 >
  if C f ¼ L=Z b >
>
i ð1 þ rÞ
rð fsw =cÞ2 >
>
>
>
>
>
ig 1 =
2
 2 2
 if C f ¼ L g =Z b ð17Þ
i ð1 þ rÞ
r ð fsw =cÞ >
>
>
>
ig 1
 2 >
>
>
 2 2
 if Cf ¼ L
Lg =Zb : >>
;
i ð1 þ rÞ
ðr
r Þð fsw =cÞ

5 C =L / Z2
f g b
resonance frequency fres [kHz]

C =(L-L ) / Z2
f g b
4

1
C =L / Z2
f b

0
0.5 1 1.5 2
Lg/L

Figure 3. Design of converter side inductor in a VSC active rectifier: resonance frequency
as a function of the inductance ratio.
 452 M. Liserre et al.

In the first case the ripple attenuation is less sensitive to the inductance ratio once
chosen the switching frequency. Thus once known the desired ripple attenuation,
the value of Lg will be determined using (17).

2.3. Damping resistor

The introduction of a resistor in series with the filter capacitor or in parallel with
the grid side inductor may be used to ensure stability to the system. However, the
damping has to be designed taking into consideration the sampling frequency and
the resonance frequency in order not to have too high losses. A design method can
be found in Liserre et al. (2002). Moreover passive damping can be avoided if
the current control is modified adopting the so-called active damping that can be
tuned using genetic algorithms (Liserre et al. 2004).

3. VSC rating
The VSC rating is done in accordance to the dc load that should be supplied.
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Thus, it is worth considering the dc voltage limitation, due to the switching losses,
and the dc current limitation, due to grid side filter losses.
As it regards the dc voltage level, and in order to keep the switching losses down,
it is desired to operate with a dc-link voltage as low as possible. Typically, the
reference for the controlled dc-link voltage is chosen 10–15% above the natural
dc-link voltage (defined as the voltage obtainable if the transistors are not operating
and their free-wheeling diodes make the bridge acts as a standard three-phase diode
bridge). For example Vo ¼ 600/620 V if the phase to neutral grid voltage rms value is
E ¼ 220 V), Vo can be chosen equal to 600 V or 620 V approximately 10% and 15%
above the natural dc-link voltage. However, the control of the ac current depends on
the ac voltage that the VSC can generate. It is a function of the dc-link level and of
the adopted modulation strategy. If a sinusoidal modulation is used, the dead time is
neglected, and the dc link is charged to Vo ¼ 600/620 V, Vac,MAX ¼ 212/220 V; if a
space-vector modulation is adopted mMAX ¼ 1.154 and Vac,MAX ¼ 245/253 V. In
order to properly control the current, the Vac,MAX should at least be equal to the
phase to neutral grid voltage amplitude.
Thus if the dc-link is chosen 10% higher than the natural dc-link voltage the
space-vector modulation should be adopted. If the dc-link is chosen 15% higher than
the natural dc-link voltage the sinusoidal modulation is also acceptable.
Additional considerations for dc-link level choice are:
1. grid voltage may rise up to 15%,
2. the voltage needed in the regenerating mode is higher than in the motoring
mode,
which lead to an increase in the dc-link level of 10% with respect to previous
calculations.
In order to evaluate the maximum dc current that the active rectifier can supply
to the load, the grid current amplitude should be evaluated. Once the dc power Po
drained by the load is considered and the grid filter losses taken into account, the
resistance R þ Rg and the input–output power balance is
2 sffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi3
2
1 E E 4Po 5
I¼ 4

: ð18Þ
2 ðR þ Rg Þ R þ Rg 3ðR þ Rg Þ
 Design for a PWM Voltage Source Converter 453

Thus, from (18) it is possible to determine the maximum dc current that is

possible to feed to the load as

3E 2
IL, MAX ¼ : ð19Þ
4ðR þ Rg ÞVo

4. Control of the active rectifier

A well-known linear control technique such as the PI-based method could be
applied both to the ac current control and to the dc voltage control in order to obtain
a voltage oriented control (VOC) (Kazmierkowski et al. 2002).
The current controllers are designed in a bi-phase reference system rotating at !
speed and oriented such that the d-axis is aligned on the grid voltage vector; hence
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the fundamental harmonic has constant components in the dq-frame while the other
harmonic’s space-vectors have pulsating components. Since the main purpose of the
active rectifier is to generate or to absorb sinusoidal currents, the reference current’s
components in the dq-frame are dc quantities.
The reference current d-component id is controlled to perform the dc voltage
regulation while the reference current q-component iq is controlled to obtain a unity
power factor.
The control structure is defined as ‘cascade’ because the dc voltage controller
calculates the reference value for the d-axis current controller. The general control
structure is shown in figure 4.
In the figure the system is undamped (there are no passive resistors or damping
controllers), the grid voltages are sensed (in ideal conditions, no coupling trans-
former adopted) and the converter currents and dc voltage are also sensed. Three
PIs are adopted, one for dc voltage control and two for d- and q-current controls: all
of them adopt suitable limitations on the integrators as well as anti-wind-up devices
in order to limit dangerous current overshoots (Kazmierkowski et al. 2002).

Figure 4. Active rectifier control structure with dq-axis oriented cascade control.
 454 M. Liserre et al.

In order to give some guidelines for the design of the ac current and dc voltage
controllers it is worth introducing three parameters
9
L þ Lg >

c ¼ >
>
Ts >>
>
>
>
>
L þ Lg =
¼ ð20Þ
R þ Rg >
>
>
>
>
>
C >
>

v ¼ >
;
Ts
where Ts is the sampling period. In the following the controller parameters are
expressed as % of the (20).
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4.1. Current control

The design is carried out neglecting the LCL-filter capacitor Cf. In fact the PI
controller acts on the low frequency dynamics of the current control loop that are
not influenced by the presence of the LCL-filter capacitor as demonstrated by
(Liserre et al. 2001). To achieve a limitation of the current overshoot to 5%, if the
system has only one sample delay (due to microcontroller elaboration) plus one half
(due to the modulation, it can reduce sampling twice every switching period), the
proportional gain of the current controllers kp,c is chosen equal to 33% of
c leading
to a bandwidth of approximately 1/(20Ts). Then, the integral time constant TI,c can
be chosen in a range of 1–10 of  depending on the need to limit overshoot (TI,c ¼ )
or on the need to have a high rejection capability of the grid disturbance (TI,c ¼ 10)
(Blasko and Kaura 1997, Leonhard 1997).

4.2. Voltage control

The dc voltage control is achieved through the control of the power exchanged by
the converter. The increase or decrease of the dc voltage level is obtained taking
more or less power from the grid in respect to what is required by the dc load, thus
changing the value of the reference for the ac current control loops. The voltage loop
is the outer loop and the current loops are the inner loops. These internal loops are
designed to achieve short settling times and unity gain. On the other hand, the main
goals of the outer loop are optimum regulation and stability thus the voltage loop
could be designed to be somewhat slower (5–20 times). Therefore, the internal and
external loops can be considered decoupled. The actual grid current components can
be considered equal to their references when designing the outer dc controller.
If a cascade controller is used the dc voltage control is performed through the
selection of the input current value id ðtÞ. A PI-controller could be tuned following the
‘optimum symmetrical’ (Leonhard 1997). However, the dc voltage controller band-
width should be significantly smaller than the current loop in order to have a suitable
decoupling, which is usually compromised by the presence of the harmonics. Thus
the proportional gain of the voltage controllers kp,v is reduced from 20% of
v, to 2%
of
v, while the integral time constant TI,v is increased from 17Ts to 65Ts to limit the
oscillations. Generally both for current and voltage controllers anti-reset-wind-up
procedures are adopted.
 Design for a PWM Voltage Source Converter 455

No filter Filter 1=ð1 þ nTs sÞ

Current PI
kp,c 33%
c [100/(3þn)]%
c
 ! limit current overshoot
TI, c
10 ! high grid disturbance rejection
Voltage PI
20%
v
kp, v
2%
v ! better decoupling from the current loop
17 Ts [(3þn)/3]17Ts
TI, v
65 Ts ! better decoupling from [(3þn)/3]65Ts
the current loop

Table 1. Summary of the current and voltage PI controller design.

5. Filtering issues
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Once the values of the ac and dc passive elements have been chosen, the VSC has
been rated and the controllers correctly designed, filtering of the control signals is the
next important issue. The introduction of both analog and digital filters has a deep
impact on the overall system performance and it is often underestimated.
For example, if the current controllers have been designed for a sampling
frequency of 5 kHz and there is a filter on the feedback current to cut the switching
frequency ripple with a cut-off frequency of 2.5 kHz, the filter introduces two sam-
ples delay in the feedback loop. The effects are a decrease of stability margin and an
increase of the overshoot (from 5% to 70%). But changing the proportional gain
from 33% of
c to 15% of
c the poles can again be critically damped.
As regards the dc voltage loop the use of the same filter (cut-off frequency of
2.5 kHz) in the dc voltage without considering it in the controller design, makes the
system experience a higher overshoot and an oscillatory transient. The sample delays
can be considered in the design increasing further the integral time constant TI,v to
100Ts, thus reducing the overshoot again.
The controller design issues and the filter influence are summarized in table I.

6. Results
The experimental set-up (figure 5) used consists of a three-phase programmable
power supply, a commercial Danfoss inverter VLTÕ 3008 (nominal voltage 380 V
dc-link capacitor 500 mF) where the control card has been removed. The control has
been implemented on an Analog Devices ADSP-21062 SHARC floating-point digital
signal processor; the timing of the system and the PWM generation is performed by
a Siemens microcontroller SAB80C167. The maximum active power drained by the
active rectifier during the tests is 5 kW and it has been considered as the base power
to calculate the base impedance Zb ¼ 29
.

6.1. DC capacitor design

Under the assumption of a dc voltage level of 700 V (this choice will be justified
in the following) with a maximum acceptable dc voltage drop of 50 V (assumed
design constraint) and a maximum power excursion of 3.3 kW (2/3 rated power
assumed design constraint), and considering a delay Tr equal to 2 ms, 50 mF is
 456 M. Liserre et al.

Figure 5. LCL-filter active rectifier set-up.

Downloaded by [RMIT University] at 07:59 23 March 2013

enough according to (4). However 500 mF has been selected for the dc capacitor in
order to guarantee a high ride-through protection capability.

6.2. LCL-filter design

The LCL-filter has been designed considering that the grid voltage is sensed and
the converter current is controlled, i.e. the system is as shown in figure 2(d). This
choice is justified by the fact that usually in the power range kW–MW in which these
converters are used, the current sensors are integrated in the converter and the filter
is not integrated (so it is preferable that the current sensors are on the converter side
of the filter). Moreover, the over-current protection is also more effective if the
current sensors are on the converter side.
Thus the capacitor should be chosen equal to the lower in respect to Lg =Zb2 or
to L=Zb2 .
A value of L ¼ 3 mH is enough to limit the switching ripple on the converter side
and not to saturate the inductors. Then, it has been chosen to have L<Lg and
Cf ¼ L=Zb2 and to use the value of Lg to tune the LCL-filter. The choice has the
inherent advantage to have a resonance frequency of the system less dependent on
the grid side inductance (figure 3) that is variable depending on the grid stiffness.
Thus the capacitor value has been chosen equal to 2.2 mF with 10
damping. The
grid side inductance has been chosen to have 10% of the switching ripple of the
converter side, according to (17), thus Lg ¼ 5 mH.

6.3. VSC rating

The dc voltage level has been chosen equal to 700 V because the sinusoidal
modulation is used and according to the consideration of x3, a 25% increase with
respect to the dc natural voltage level is recommended in order to also control
properly the ac current in a regenerative operation. The maximum load current is
33 A in the hypothesis of 1.5
ac side resistance according to (19): the actual load
current is well below this limit.
The following results are obtained with kp,c ¼ 13.3, TI,c ¼ 0.003, kp,v¼ 0.15 and
TI,v¼ 0.015 if the switching and sampling frequencies are both equal to 5 kHz, and
 Design for a PWM Voltage Source Converter 457

with kp,c ¼ 21.3, TI,c ¼ 0.003, kp,v ¼ 0.25 and TI,v ¼ 0.015 if the switching and
sampling frequencies are both equal to 8 kHz.
The LCL-filter active rectifier behaviour is shown in figure 6 for 5 kHz and 8 kHz
switching frequencies: the difference is only as it regards the switching ripple on the
converter side (1.3% to 0.9% respectively); instead in both cases, the power factor is
close to unity and the current THD is 3%.
Figures 7–11 are obtained plotting the currents and voltages acquired through
the dsp-microntroller system. Hence, they are sampled at a frequency equal to the
switching frequency being, as a consequence, ripple-free. However, their low fre-
quency distortion is equal to the one measured with the oscilloscope (figure 6).
The position of the ac voltage and ac current sensors are determined not only for
the design of the passive elements of the LCL-filter, according to that discussed in x2,
but also for waveform and phase of the ac current. The position of the current
sensors can influence the phase of the ac current, i.e. the power factor and the
stability of the current loop (Liserre et al. 2002). Instead, the position of the grid
Downloaded by [RMIT University] at 07:59 23 March 2013

voltage sensors influence the ac current waveform, because the grid voltage is used
for the dq-frame orientation. If the grid voltage is measured across the capacitors

Figure 6. Grid voltage measured at the PCC, grid current, converter current and filter
capacitor current (4 kW). (a) 5 kHz two switching frequency. (b) 8 kHz two switching
frequency.

15
converter currents [A] iaibic

10
α
α-component of the converter current [A] i

10
0

-10 5

0 100 200 300 400 500

number of samples 0
(a)
710
-5
o
dc voltage [V] v

700 -10

-15
690 -15 -10 -5 0 5 10 15
0 100 200 300 400 500 β-component of the converter current [A] i
β
(b) number of samples (c)

Figure 7. Tests at 8 kHz sampling frequency, if the voltage sensors are across the ac
capacitor plus damping. (a) Measured converter currents. (b) Measured current
-locus. (c) Measured dc voltage.
 458 M. Liserre et al.

Figure 8. Tests at 8 kHz sampling frequency, if the voltage sensors are across the ac capa-
Downloaded by [RMIT University] at 07:59 23 March 2013

citor plus damping and a filter is used. (a) Measured converter currents. (b) Measured
current -locus. (c) Measured dc voltage.
15
converter currents [A] ia ib ic

10
α-component of the converter current [A] iα

10
0

-10 5

0 100 200 300 400 500

0
number of samples
(a)
710
-5
dc voltage [V] vo

700 -10

-15
690 -15 -10 -5 0 5 10 15
0 100 200 300 400 500 β-component of the converter current [A] iβ
(b) number of samples (c)
Figure 9. Tests at 8 kHz sampling frequency, if the voltage sensors are on the PCC.
(a) Measured converter currents. (b) Measured current -locus. (c) Measured
dc voltage.

of the LCL filter (figure 2(d)) the current can be highly distorted with a THD of
7.4% and a consequent grid voltage THD of 4.2% (figure 7); then the use of a filter
on this measurement improves the results with a consequent current THD of 4% and
a grid voltage THD of 2% (figure 8). Instead, if the grid voltage is sensed at the point
of common coupling (PCC) (figure 2(c)) the best results are obtained with a current
THD of 2.1% and a grid voltage THD of 0.4% (figure 9).
This is due to the fact that, in the tested situation, the grid side reactance of
the LCL-filter is dominant with respect to the VSC side. Thus, when the grid
voltage is sensed across the capacitors of the LCL-filter rather than at the PCC,
the voltage drop introduced by the grid reactance can significantly disturb the
dq-frame orientation.
Figures 10 and 11 prove the influence of analog filters (1.5 kHz and 10 kHz cut-
off frequency) on the system. The test is a step in the reference dc voltage from 650 V
 Design for a PWM Voltage Source Converter 459

700

dc voltage [V] vo
680

660

0 100 200 300 400 500

(b) number of samples

Figure 10. Tests at 5 kHz sampling frequency, for a voltage step in the dc voltage reference
if a filter is used with 1.5 kHz cut-off frequency. (a) Measured converter currents.
(b) Measured dc voltage.

20
converter currents [A]

700

dc voltage [V] vo
ia ib ic

0 680
Downloaded by [RMIT University] at 07:59 23 March 2013

660

-20
0 100 200 300 400 500 0 100 200 300 400 500
(a) number of samples (b) number of samples
Figure 11. Tests at 5 kHz sampling frequency, for a voltage step in the dc voltage reference
if a filter is used with 10 kHz cut-off frequency. (a) Measured converter currents.
(b) Measured dc voltage.

to 700 V at full load. The use of a 10 kHz analog filter is effective in reducing
disturbances on the signals and at the same time does not affect too much the
current control. In fact it introduces less than one sampling period delay if the
sampling frequency is in the range 5–8 kHz as is the case for the proposed tests.

7. Conclusions
In this paper a simple procedure to design an LCL-filter active rectifier based on
a VSC has been proposed. The guidelines for the design of the passive elements and
the guidelines for the design of the control have been reported and validated with
some experimental results. Particular attention has been paid to the different system
configurations for the control, such as grid and current sensor position and to the
influence of filters. It has been proven that if the position of sensors is not taken into
account and the filter cut-off frequency is too low the current absorbed by the active
rectifier could be highly distorted and the system design compromised.

Acknowledgement
This work was supported in part by the the Italian Ministero della Istruzione,
Università e Ricerca (CLUSTER 13).

References
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Appendix: calculations for (5)

Equation (5) can be derived with the following steps
jXc Zb
ZTgrid ¼ þ jXg ð21Þ
Zb þ jXc
ZTgrid jðXc =Zb Þ Xg
¼ þj ð22Þ
Zb 1 þ jðXc =Zb Þ Zb

jð1=xc Þ
zTgrid ¼ þ jxg ð23Þ
1
jð1=xc Þ
1
zTgrid ¼ þ jxg ð24Þ
1 þ jxc
1
jxc
zTgrid ¼ þ jxg ð25Þ
1 þ x2c
 
1 xc
zTgrid ¼ þ j x g
: ð26Þ
1 þ x2c 1 þ x2c
If xc<10%, x2c < 1%, hence x2c  0 and it follows that zTgrid ¼ 1 þ jðxg
xc Þ.