Introduction to Extraction and the Custom Design Flow

EE241B Lab 3
Written by Brian Zimmer (2013)
Updated by Sean Huang (2019), Daniel Grubb (2020), Harrison Liew (2021)

Overview
In Lab 2 (GCD: VLSI’s Hello World), you used the digital design flow to place-and-route a pre-
existing library of standard cells based on an RTL description, then pushed it through DRC and
LVS. In this lab, we take an even closer look at a design. First, we will place-and-route a 4-16
decoder using the Hammer flow as integrated in Chipyard. We will then extract the design and
simulate both the non-extracted and extracted netlist. With that, we can compare the timing and
energy results between pre- and post-extraction.

Then, we will take a closer look at the ASAP7 standard cells we have been using throughout the
course and start a custom cell design in Cadence Virtuoso. You will inspect a simple D flip-flop,
run DRC to verify the layout is manufacturable, and LVS to verify that your layout matches your
schematic. Lastly, you will run parasitic extraction on your design and run some basic simulations
to estimate some of its characteristics.

Getting Started: Decoder Extraction

We will once again start with updating our environment. Pull the latest changes to the lab Chipyard
repository.

Notice that there is now a folder called vlsi/lab3. Inside, there is a decoder.yml file, which
contains the Hammer inputs for the 4-16 decoder we will be working with (it is pretty similar to
gcd.yml from the last lab, minus simulation keys).

We will need to the the decoder through the tools using the Hammer flow, this time as integrated
in Chipyard for custom Verilog (if you wish, you can also run this with Hammer using the full
manual commands as in Lab 2 with --obj dir build/custom-decoder):

# These can be appended after the 'make <target>' instead of exporting them
export CUSTOM_VLOG=lab3/decoder.v
export VLSI_TOP=decoder
export INPUT_CONFS=lab3/decoder.yml
# Generates Hammer Makefile in build/custom-decoder/hammer.d
make build
# Uses that Makefile to run synthesis, P&R, and LVS
make lvs

Before continuing, examine the example-vlsi file more closely. This file contains a HammerDriver
that extends the base HammerDriver class. This is how the Hammer flow allows for flexibility
in the design. If you want to edit the default steps that Hammer runs, you can do it like this.
EE241B Lab 3, Introduction to the Custom Design Flow, Spring 2021 2

You may add Hammer hooks here to inject custom TCL that doesn’t fit into a Hammer API
(any real tapeout will certainly have some custom TCL). You may insert hooks before or after
any default Hammer step (or another hook), you may replace a default Hammer step, or you may
remove a Hammer step. In the get extra par hooks method, we have instructed Hammer to add
a visualize floorplan hook, which generates a pictorial floorplan in par-rundir/all.svg (this
will become more useful with more complicated floorplans). We also remove the place bumps and
clock tree as they are not useful for this lab.

Q1: Why do we need to remove the clock tree step for this decoder?

PEX: Parasitic Extraction

We will be using the Calibre tool PEX to run parasitic extraction. Parasitic extraction will produce
a netlist with more accurately modeled capacitances and resistances for the nets in the design. We
can then simulate this netlist with Spice to get more accurate results than just the original post
P&R netlist. PEX will first run LVS (again) before exporting the extracted netlist.

We will start by opening up the decoder in CalibreDRV:

cd build/custom-decoder/lvs-rundir
./generated-scripts/view_lvs

In CalibreDRV, click Verification > Run PEX... on the toolbar. A dialog will open asking for
a runset which you can exit out of. Click on Rules, then navigate to the vlsi/asap7 pex folder in
your repository and select rcxControl calibre asap7.rul. This is the PEX rule deck for ASAP7.
Then go to Inputs. For the Layout, PEX should extract it from the layout of the decoder it already
has. For the Netlist, select decoder.include.sp in your lvs-rundir (make sure ”Export from
schematic viewer” is unselected). Under Outputs, make sure the Netlist Format is set to HSPICE.
Finally, click Run PEX.

Q2: Submit the first 40 lines of the ”decoder.pex.netlist” file generated by PEX.

Q3: Simulate the decoder and measure the delay from A[3] rising (the rest are 0) to
Z[8] rising and the average power for both the extracted netlist and the original LVS
netlist to compare them (some tips below). State the output load capacitance you
used.

We have supplied some HSPICE files to start with in vlsi/asap7 pex that have the testbenches
mostly setup for you already. For the pre-extraction simulation, first run make hspice-netlist in
the asap7 pex directory. This will generate an HSPICE compatible netlist from the LVS netlist at
decoder.hspice.sp. For this simulation, make sure that the ports match up with the instantiation
of the decoder in decoder.sp (the port order is somewhat random in the PEX netlisting and SPICE
is sensitive to port ordering). Make sure that the ASAP7 CDLs are included in your testbench
(there are some provided helpers that already have this for you). You may then run the simulation
in the asap7 pex folder if you wish.
EE241B Lab 3, Introduction to the Custom Design Flow, Spring 2021 3

Getting Started: Custom Design

In this portion of the lab, we will be exploring custom cell design. Fig. 1 gives an overview of the
steps involved in the design flow of creating a custom cell and integrating it into a VLSI flow. We
will import an existing design of a flip-flop in the ASAP7 PDK and introduce the steps you would
take while building a custom standard cell. We will examine its schematic, export a netlist, run
DRC and LVS, and simulate it. In the next lab, we will discuss the remaining steps in the custom
design flow to integrate your design into the VLSI flow we have been using. You may also work
through a custom design of a C2MOS latch yourself for extra credit.

Schematic Entry
(Cadence Virtuoso)
SPICE Netlist

Layout Entry
(Cadence Virtuoso)
Physical Layout
DRC Abstract (LEF)
(Calibre) Generation
(Cadence Abstract)
Manufacturable Layout
LVS Timing Library (LIB)
(Calibre) Generation
Layout and (Cadence Liberate)
schematic match
Extraction
(Calibre PEX)
SPICE Netlist
Simulation including parasitics
(At any stage using
Synopsys HSpice)

VLSI Flow

Figure 1: Custom Cell Design Flow

Start by running this to setup and run Cadence Virtuoso (recommended in the lab3 directory to
minimize file clutter). You should then see 2 windows, a command intepreter window (CIW) and
a Library Manger window, as shown in Fig. 2.

source ~ee241/spring21-labs/asap7_virtuoso/sourceme.sh
tcsh # start C shell
source ~ee241/spring21-labs/asap7PDK_r1p5/cdslib/setup/setup_asap7.csh
exit # exit C shell
virtuoso &

In the Library Manager, you will notice that there are several libraries already setup (in addition
to the default Virtuoso libraries). asap7 TechLib is the ASAP7 library that contains the different
transistor flavors available in ASAP7. asap7ssc7p5t is another library provided by ASAP7 that
EE241B Lab 3, Introduction to the Custom Design Flow, Spring 2021 4

Figure 2: Virtuoso

contains a few example standard cell views, including a flip flop, inverter, and tapcell. If you
wanted to view the layouts for the other standard cells in ASAP7, you could make a new library by
going to File > New > Library. Call it (asap7 std cells). Then select ”Attach to an existing
technology library” and choose asap7 TechLib.

Then in the CIW, go to File > Import > Stream with Stream File as
ee241/spring20-labs/asap7libs 24/gds/asap7sc7p5t 24.gds and select the asap7 std cells
library. Attach it to asap7 TechLib and click Ok. This will stream in the layouts for all the existing
standard cells in ASAP7. If you go to the asap7 std cells library, you will notice there are only
SLVT layouts. This is a quirk of ASAP7 in which the PDK doesn’t provide different threshold
flavor cells which is why the ASAP7 Hammer plugin will automatically hack the PDK to make the
different threshold flavor cells available for use in a VLSI flow.

Creating the Custom Library

First, create a new library by going to File > New > Library in the Library Manager and name
it custom cell. Then select ”Attach to an existing technology library” and choose asap7 TechLib.
We will be exploring the flip-flop view that is already provided in ASAP7. In the library manager,
go to asap7ssc7p5t and right-click on DFFHQNx1 ASAP7 75t R and click Copy. In the new window,
change the To library to be custom cell and the Cell to be custom dff R, and click Ok. This will
give us a pre-made schematic, symbol, and layout for our ”custom” cell.
EE241B Lab 3, Introduction to the Custom Design Flow, Spring 2021 5

Schematic Entry

For a truly custom cell, you would create a new schematic view in your new library and build your
design using the components in the ASAP7 PDK. Once you built it, you can simulate it to verify
its operation, including Monte Carlo simulations to test its operation with process variations.

In this case, you can open up the existing schematic that we copied over (it should look like Fig.
3. Answer the following questions about the schematic:

Q4: What is the purpose of the tristate buffer that connect from the ”MS” node to
the ”MH” node (output of the input latch)? Does this affect the setup time? Why
do these tristate transistors have fewer fins than the input transistors?

Notice the top level pins of the schematic. These are the same pins that will be the inputs and
outputs of our standard cell layout.

Figure 3: Schematic of the DFF

If you want to instantiate this cell in a testbench or other schematic, you need to create a symbol
view. We already have one in this case, but to create one you can go to Create > Cellview >
From Cellview, and click Ok in the dialog box. You can leave the symbol as is, or use the drawing
tools to draw something custom. When you are done, save and close the window.

Schematic Netlist Export

We will be running LVS/PEX against this schematic later, so we will need to export this schematic
as a netlist. Most physical verification tools perform verification on generic filetypes, such as GDS
files for layout and SPICE netlists for schematics. To export the DFF schematic, go to File >
Export > CDL in the CIW, then populate the following fields:
EE241B Lab 3, Introduction to the Custom Design Flow, Spring 2021 6

• Library Name: Your new Custom Cell library

• Top Cell Name: custom dff R (or your top cell name)
• View Name: schematic
• Switch View List: auCdl schematic
• Stop View List: auCdl
• Output CDL Netlist File: custom dff R.cdl
• Make sure ”Map Bus Name from <> to [ ]” is checked.

Hit Apply and wait for the CDL to be exported, then sanity check it.

Layout Entry

As discussed above, we will be using the existing DFF layout, so no modifications are required for
this lab. The following instructions are a general tutorial for basic layout editing.

Figure 4: DFF Layout

Fig. 4 is a screenshot of what your copied DFF layout should look like. A great resource for
layout in ASAP7 can be found here. This describes most of the important layers and provides a
layout tutorial for a gate in ASAP7. If you are unfamiliar with transistor level layout, it would
be instructive for you to go through the DFF layout and correlate parts of it to the schematic. If
you’re unsure of where to start, you can use the top level input pins (M1 pins) and the number
of fins for different transistors as references. For simple things, you only need a few commands to
change the layout:

• By pressing ∼, 1, 2, 3 etc you can show only certain layers. Press Shift-1 to add M1 to
whatever is visible.
• To move something, hover over the object, then press ”m” on the keyboard.
• To make something bigger or smaller, hover over the edge of the object, then press ”s” on
the keyboard, then click again at the final location.
• Press ”Esc” if you selected something incorrectly.
• To add new wire, press Ctrl-Shift-W (then F3 will change the options such as the width).
• To just add a rectangle, select the desired layer in the layer pallete, and press ”r”. Then click
on the two corners to create.
• Selecting an object and hitting ”q” will bring up property info about it and allow you to edit
certain characteristics.
• ”k” allows you to place rulers to measure distances in the layout.
EE241B Lab 3, Introduction to the Custom Design Flow, Spring 2021 7

Cell Verification
When you are done with your schematic and layout, you can run Calibre DRC and LVS directly
from Virtuoso because there is a Calibre plugin accessible from the toolbar included in our setup.
This lets us use the same Calibre tools we ran in the previous lab to verify our custom cell.

DRC

To run DRC, go to Calibre > Run nmDRC in the layout editor. Select the rule file to be
~ee241/spring21-labs/asap7PDK r1p5/calibre/ruledirs/drc/drcRules calibre asap7.rul.
Make sure that under Inputs, ”Export from layout viewer” is selected and then Run DRC.

Like in the previous lab, you will see an RVE window with the DRC results. Your design should
be DRC clean except for a LUP error.

Q5: Read this DRC error and explain what the error is. What is the purpose and
operation of a tapcell? You can look at an ASAP7 tapcell layout in the the same
asap7ssc7p5t library we copied the DFF schmatic and layout from.

LVS

You don’t have to run LVS for this lab, but if you are building a custom cell from scratch, you can
do it similarly to DRC by going to Calibre > Run nmLVS. Change the runset file to
~ee241/spring20-labs/asap7PDK r1p5/calibre/ruledirs/lvs/lvsRules calibre asap7.rul.
Make sure to select the CDL we exported earlier as the netlist.

If you are running into LVS errors, Calibre will describe the discrepancies and allow you to highlight
the offending nets just like when we ran LVS for a larger design.

Extraction

To run parasitic extraction, go to Calibre > Run PEX. The settings for this extraction are essen-
tially the same as earlier in the lab, when you extracted the decoder. Make sure to select the CDL
we exported earlier as the netlist.

To avoid an LVS error due to substrate pins and power pins being physically separate at the
standard cell level (this is a hint for the tapcell question), you must select an additional option.
In the PEX window, select Setup > PEX Options. Click the new PEX Options button and go to
the Connect tab. Then, select Connect nets named and enter VDD VSS.

Most of the above PEX setup steps, minus filling in the exported netlist, are automated with
a runset file (in asap7 pex/pexRunset asap7). Next time, when you run PEX, you can select
this runset file instead of clicking all the options manually (but it is important to know what is
happening). Note that when you have finished extracting and close the PEX window, do not save
the changes to the runset file, otherwise the next time you run PEX, you’ll extract a previous
design instead!
EE241B Lab 3, Introduction to the Custom Design Flow, Spring 2021 8

Extracted Simulation
Finally, we will do a couple more simulations on the exported CDL and the extracted netlist. You
should be able to use a very similar testbench to the one used earlier for the decoder. We have
included a spice testbench in ee241/spring21-labs/asap7 virtuoso that may be useful to you.
Remember that the output of this flip flop is QN, not Q. Make sure to check the ordering of the
ports of your DFF between the different netlists.

Q6: Estimate the CLK-Q time of your DFF from for both the exported CDL and the
extracted netlist from PEX. Include a screenshot (or the text) of your spice/otherwise
testbench. State the load capacitance and rise/fall times you used.

Q7: Estimate the setup time of your DFF for both the exported CDL and the extracted
netlist from PEX. State the load capacitance and rise/fall times you used. Also,
include a screenshot of the waveforms of CLK, D, and QN for the simulation that you
determined the setup time from (if you’re using HSPICE, you can use WaveView or
wv on the command line to load the .tr0 waveforms).

Q8: Compare your setup time result to the timing parameters for DFFHQNx1 ASAP7 75t R
in ~ee241/spring21-labs/asap7libs 24/lib/asap7sc7p5t 24 SEQ RVT TT.lib. Copy the en-
tire section of the lib (starting at ”timing () {”) that corresponds to the setup time
and try to guess why it is presented as a look-up table instead of a single value with-
out consulting a LIB reference. Tip: you can find the table units and templates at the top
of the file, and then find the timing lookup tables for clk-q, setup, etc. by searching for the
DFFHQNx1 ASAP7 75t R entry.

Extra Credit Layout

For some extra credit, you can run through the flow described in this document but create a basic
dynamic (or static if you like) C2MOS latch in ASAP7 from scratch. Submit the schematic, layout,
and DRC/LVS results. You can also simulate after extraction like we did for the copied DFF. You
can do this from scratch, start from a gate an existing gate like a NAND2, or use the DFF layout
and delete portions and reconfigure it.

Conclusion
This lab was meant to bring you a bit closer to the actual hardware you are designing with in a VLSI
flow. The physical circuits you work with in a VLSI flow may sometimes seem quite abstracted
away by the tools, but having the ability to look at the transistor level and understand the design
is critical to solving problems that come up. The introduction to custom cell design is also meant
to have you take a closer look at the standard cells we have used throughout the semester and
understand the underlying circuits. One follow up activity to this would be to run a Monte Carlo
analysis with your schematic to analyze the effect of process variations.

In order to fully use your custom cell in a digital flow, you would also need to generate all of the
required collateral for the tools from your layout and schematic that we discussed in Lab 2. You
EE241B Lab 3, Introduction to the Custom Design Flow, Spring 2021 9

would need to describe the cell’s pre-computed timing characteristics (so it can be synthesized)
and physical attributes (so it can be place-and-routed), and we will explore tools like the Cadence
Virtuoso Abstract Generator (to create the LEF) and Cadence Liberate (to create the LIB) in the
next lab. Once you’ve done this, you can include it in your VLSI design flow for the synthesis and
P&R tools to use!

Acknowledgements
Thank you to ECE 6332 - Introduction to VLSI Design (for the 21st Century) at UVA for the
ASAP7 layout reference.