SPC572Lx: 32-Bit Power Architecture Based MCU For Automotive Powertrain Applications

SPC572Lx
32-bit Power Architecture® based MCU for automotive powertrain

applications
Datasheet - production data
– Intelligent complex timer module

– 72 channels (16 input and 56 output)
• Enhanced analog-to-digital converter system
with:
– Three 12-bit SAR analog converters
eTQFP80 eTQFP100
10 mm × 10 mm × 1.0 mm 14 mm × 14 mm × 1.0 mm – One 16-bit Sigma-Delta analog converters
0.4 mm pitch 0.5 mm pitch
• Decimation unit to support SD ADC data
conditioning
Features • Two deserial serial peripheral interface (DSPI)
modules
• AEC-Q100 qualified
• Two LIN and UART communication interfaces
• One main 32-bit Power Architecture® VLE (LINFlexD) modules
Compliant CPU core, single issue
• One μs-bus channel (composed by one DSPI
– Single-precision floating point operations
and one LINFlexD)
• 1568 KB on-chip RWW flash memory
• Four SENT channels
– Supporting EEPROM emulation (32 KB)
• Two modular controller area network (M_CAN)
• 64 KB general-purpose data SRAM modules
• System Memory Protection Unit (SMPU) • Fast Ethernet controller (FEC)
• Multi-channel direct memory access controllers • Fast Asynchronous Serial Transmission
(eDMA) with 16-channel for up to 60 DMA (LFAST)
sources
• Nexus development interface (NDI) per IEEE-
• Interrupt controller (INTC) ISTO 5001-2003 standard, with some support
• Four 32-bit and one 64-bit Periodic Interrupt for 2010 standard
Timer channels (PIT) • Device and board test support per Joint Test
• Single phase-locked loops with stable clock Action Group (JTAG) (IEEE 1149.1 and IEEE
domain for peripherals and core (PLL) 1149.7)
• System integration unit lite (SIUL2) • Single 5 V +/-10% Power supply supporting
• Boot assist flash (BAF) supports factory cold start conditions (down to 3.0 V)
programming through UART/LIN, CAN • Self Test capability
• Generic timer module (GTM101) • Designed for eTQFP80 and eTQFP100
Table 1. Device summary
Root Part Numbers
Memory Flash size
Package eTQFP80 Package eTQFP100
1056 KByte SPC572L60F2 SPC572L60E3

1568 KByte SPC572L64F2 SPC572L64E3
July 2017 DocID027866 Rev 5 1/112

This is information on a product in full production. www.st.com
Table of contents SPC572Lx
Table of contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.3 Device feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.5 Features overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 13

2.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.1 Power supply and reference voltage pins . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.2 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2.3 LVDS pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.4 Generic pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Electromagnetic Compatibility (EMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 Electrostatic discharge (ESD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.6 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7 DC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.8 I/O pad specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.8.1 I/O input DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.8.2 I/O output DC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.9 I/O pad current specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.10 Reset pad (PORST, ESR0) electrical characteristics . . . . . . . . . . . . . . . . 36
3.11 Oscillator and PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
3.12 ADC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.12.1 ADC input description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
3.12.2 SAR ADC electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
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SPC572Lx Table of contents
3.12.3 S/D ADC electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

3.13 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.14 LVDS Fast Asynchronous Serial Transmission (LFAST) pad electrical
characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
3.14.1 LFAST interface timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
3.14.2 LFAST and MSC/DSPI LVDS interface electrical characteristics . . . . . 59
3.15 Power management: PMC, POR/LVD, sequencing . . . . . . . . . . . . . . . . . 62
3.15.1 Power management integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
3.15.2 Main voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . 63
3.15.3 Device voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
3.15.4 Power up/down sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
3.16 Flash memory electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 67
3.17 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.17.1 Debug and calibration interface timing . . . . . . . . . . . . . . . . . . . . . . . . . 70
3.17.2 DSPI timing with CMOS and LVDS pads . . . . . . . . . . . . . . . . . . . . . . . . 75
3.17.3 FEC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.17.4 UART timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
3.17.5 GPIO delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4 Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
4.2 eTQFP80 case drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

4.3 eTQFP100 case drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
4.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
4.4.1 General notes for specifications at maximum junction temperature . . . 98
5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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List of tables SPC572Lx
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. SPC572Lx device feature summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Power supply and reference pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 5. LVDSM pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 6. Parameter classifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 7. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 8. ESD ratings, . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 9. Device operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 10. DC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. I/O pad specification descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. I/O input DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 13. I/O pull-up/pull-down DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 14. WEAK configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 15. MEDIUM configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 30
Table 16. STRONG configuration output buffer electrical characteristics. . . . . . . . . . . . . . . . . . . . . . 31
Table 17. VERY STRONG configuration output buffer electrical characteristics . . . . . . . . . . . . . . . . 32
Table 18. I/O consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 19. Reset electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 20. PLL0 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 21. External oscillator electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 22. Selectable load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 23. Internal RC oscillator electrical specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 24. ADC pin specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 25. SARn ADC electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 26. SDn ADC electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 27. Temperature sensor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 28. LVDS pad startup and receiver electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 29. LFAST transmitter electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 30. MSC/DSPI LVDS transmitter electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 31. Voltage regulator electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 32. Voltage monitor electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 33. Device supply relation during power-up/power-down sequence. . . . . . . . . . . . . . . . . . . . . 66
Table 34. Functional terminals state during power-up and reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 35. RWSC settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 36. Flash memory program and erase specifications (pending silicon characterization) . . . . . 68
Table 37. Flash memory module extended life specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 38. JTAG pin AC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 39. Nexus debug port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 40. DSPI channel frequency support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 41. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or 1
.............................................................................................................................................76
Table 42. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0 or
1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 43. DSPI LVDS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1,
CPOL = 0 or 1, continuous SCK clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 44. DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1,
CPOL = 0 or 1, continuous SCK clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
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Table 45. DSPI CMOS Slave timing - Modified Transfer Format (MTFE = 0/1) . . . . . . . . . . . . . . . . . 85
Table 46. RMII serial management channel timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 47. RMII receive signal timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 48. RMII transmit signal timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 49. UART frequency support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 50. GPIO delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 51. eTQFP80 – STMicroelectronics package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 52. eTQFP100 – STMicroelectronics package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 96
Table 53. Thermal characteristics for eTQFP80 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Table 54. Thermal characteristics for eTQFP100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 55. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
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List of figures SPC572Lx
List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 2. Periphery allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 3. 80-pin QFP configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 4. 100-pin QFP configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 5. I/O input DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6. Weak pull-up electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 7. I/O output DC electrical characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 8. Start-up reset requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 9. Noise filtering on reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 10. PLL integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 11. Test circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 12. Input equivalent circuit (Fast SARn channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 13. Input equivalent circuit (SARB channels) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 14. LFAST and MSC/DSPI LVDS timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 15. Power-down exit time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 16. Rise/fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 17. LVDS pad external load diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 18. Voltage regulator capacitance connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 19. Voltage monitor threshold definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 20. JTAG test clock input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 21. JTAG test access port timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 22. JTAG JCOMP timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 23. JTAG boundary scan timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 24. Nexus event trigger and test clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 25. Nexus TDI/TDIC, TMS/TMSC, TDO/TDOC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 26. DSPI CMOS master mode – classic timing, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 27. DSPI CMOS master mode – classic timing, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 28. DSPI PCS strobe (PCSS) timing (master mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 29. DSPI CMOS master mode – modified timing, CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 30. DSPI CMOS master mode – modified timing, CPHA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 31. DSPI PCS strobe (PCSS) timing (master mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 32. DSPI LVDS and CMOS master timing – output only – modified transfer format MTFE = 1,
CHPA = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 33. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) — CPHA = 0 . . . . . . . . 86
Figure 34. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) — CPHA = 1 . . . . . . . . 87
Figure 35. RMII serial management channel timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 36. RMII receive signal timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 37. RMII transmit signal timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 38. eTQFP80 – STMicroelectronics package mechanical drawing . . . . . . . . . . . . . . . . . . . . . 92
Figure 39. eTQFP100 – STMicroelectronics package mechanical drawing . . . . . . . . . . . . . . . . . . . . 95
Figure 40. Product code structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6/112 DocID027866 Rev 5

SPC572Lx Introduction
1 Introduction
1.1 Document overview

This document provides electrical specifications, pin assignments, and package diagrams for
the SPC572Lx series of microcontroller units (MCUs). For functional characteristics, see the
device reference manual.
1.2 Description
This family of MCUs is targeted at automotive powertrain controller applications for four-
cylinder gasoline and diesel engines, chassis control applications, transmission control
applications, steering and braking applications, as well as low-end hybrid applications.
The family is designed to achieve ISO26262 ASIL-A compliance.
1.3 Device feature summary

Table 2. SPC572Lx device feature summary
Feature Description
Process 55 nm
Main processor Core e200z2
Number of main cores 1
Single precision floating point Yes
VLE Yes
Main processor frequency 80 MHz
SMPU Yes
Software watchdog timer (task SWT/safety SWT) 2 (1/1)
Core Nexus class 3
Sequence processing unit (SPU) Yes
System SRAM 64 KB
Flash memory 1536 KB
Flash memory fetch accelerator 8 × 128 bit
Data flash memory (EEPROM) 2 × 16 KB
Flash memory overlay RAM 8 KB
DMA channels 16
LINFlexD (UART/MSC) 3 (2/1)
M_CAN/M_TTCAN 2/0
DSPI (SPI/MSC/sync SCI) 2 (1/1/0)
Microsecond bus downlink Yes
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Introduction SPC572Lx
Table 2. SPC572Lx device feature summary (continued)

Feature Description
SENT bus 4 channels

Ethernet Yes
Zipwire (SIPI / LFAST) Interprocessor bus High speed (4-phase only)
System timers 4 PIT channels
1 AUTOSAR® (STM)
64-bit PIT
GTM timer 16 input channels,
56 output channels
GTM RAM 18.53 KB
Interrupt controller 1024 sources
ADC (SAR) 3
ADC (SD) 1
Temperature sensor Yes
PLL Single PLL with no FM
Internal linear voltage regulator 1.2 V
External power supplies 5 V(1)
3.3 V(2)
Low-power modes Stop mode
Slow mode
Packages eTQFP80
eTQFP100
1. The device can be powered up at 5 V only.
2. Optional: can be used for special I/O segments
1.4 Block diagram

Figure 1 and Figure 2 show the top-level block diagrams.
8/112 DocID027866 Rev 5

Figure 1. Block diagram
DCI (without
SPU JTAGM JTAGC
LFAST support)
SWT_3
DMA CH MUX
SWT_2
Zipwire
(LFAST INTC_2 STM_2
Ethernet
& SIPI) 16ch eDMA e200z215An3–80 MHz
40 MHz Core Nexus 3
VLE Scalar SP-FPU
Concentrator BIU
40 MHz
Load/Store Instruction
32 ADD 32 ADD 32 ADD
32 DATA 32 DATA 32 DATA
M2 M0 M1
Cross Bar Switch (AMBA 2.0 v6 AHB)–80 MHz
System Memory Protection Unit (SMPU)
S2 S1 S0
32 ADD 32 ADD 32 ADD
32 DATA 32 DATA 32 DATA
Overlay Backdoor
Peripheral Bridge for system RAM
SRAM Control Flash Controller
40 MHz
Decorated Storage Decorated Access 8 x 128 Mini Cache
NAR
32 ADD 32 ADD
32 DATA 32 DATA 128-bit Page Line
1.5 MB flash
Peripheral Cluster 6 x 256 KB code flash
SRAM
(see Periphery
allocation diagram) 64 KB 2 x 16 KB data EEPROM
RAM 8 KB
Overlay/Trace NVM
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111
Figure 2. Periphery allocation
SSCM
PBRIDGE_A
PASS
XBAR_0
Flash control
SMPU_0
LFAST_0
PRAM_0
SIPI_0
PCM
SIUL2
PFLASH_0
MC_ME
INTC_0
MC_CGM
SWT_2
CMU_PLL
SWT_3
PLLDIG
STM_2
XOSC
DMA_0
IRCOSC
FEC_0
MC_RGM
EIM
PMCDIG
ERM
MC_PCU
GTM
WKPU
SAR ADC_0
DECIFILTER
SAR ADC_4
PIT_0
SAR ADC_B
PIT_1
Peripheral Bus A
SENT SRX_0
LINFlexD_14
LINFlexD_0
LINFlexD_1
CAN SRAM
SD ADC_3
M_CAN_1
M_CAN_2
DMAMUX
DSPI_0
DSPI_4
JTAGM
CCCU
DTS
JDC
Peripheral Cluster A
10/112 DocID027866 Rev 5

1.5 Features overview

On-chip modules within SPC572Lx include the following features:
• 1 main CPU, single issue, 32-bit CPU core complex (e200z2)
– Power Architecture embedded specification compliance
– Instruction set enhancement allowing variable length encoding (VLE), encoding a
mix of 16-bit and 32-bit instructions, for code size footprint reduction
– Single-precision floating point operations
– Saturation Instructions Extension adding scalar saturating arithmetic support to
the PowerISA Integer Saturation (ISAT)
• 1568 KB (1536 KB code flash + 32 KB data flash) on-chip flash memory
– Supporting multiple blocks allowing EEPROM emulation
– RWW between data EEPROM and code flash memory
• 64 KB general-purpose data SRAM
• System Memory Protection Unit (SMPU)
• 16-channel Direct Memory Access controllers (eDMA) with two channel multiplexers for
up to 60 DMA sources
• Interrupt Controller (INTC) supporting up to 1024 interrupt sources (all are not
assigned)
• System Timer Module (STM)
• 2 Software Watchdog Timers (SWT)
• 2 Periodic Interrupt Timers (PIT)
– 1 PIT with four standard 32-bit timer channels
– 1 PIT with two 32-bit timer channels which can be combined into one 64-bit
channel
• Single phase-locked loop with stable clock domain for peripherals and core (PLL)
• Single crossbar switch architecture for concurrent access to peripherals, flash memory,
or SRAM from multiple bus masters
• System Integration Unit Lite (SIUL2)
• Boot Assist Flash (BAF) supports factory programming using a serial bootload through
the UART Serial Boot Mode Protocol (physical interface (PHY) can be e.g., UART and
CAN)
• PASS module (supporting 256-bit JTAG password protection)
• Device life cycle monitoring
• Generic Timer Module (GTM101)
• Enhanced analog-to-digital converter system with:
– Three 12-bit SAR analog converters
– One 16-bit Sigma-Delta analog converter
• Decimation unit to support SD ADC data conditioning
• 1 Deserial Serial Peripheral Interface (DSPI) module
• 2 LIN and UART communication interfaces (LINFlexD) modules
• 1 microsecond-bus channel (composed of one DSPI and one LINFlexD)
• 4 SENT (Single Edge Nibble Transmission) channels
• 2 Modular Controller Area Network (M_CAN) modules
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• 1 Clock Calibration on CAN Unit (CCCU)

• Fast Ethernet Controller (FEC)
• Fast Asynchronous Serial Transmission (LFAST)
• Nexus Development Interface (NDI) per IEEE-ISTO 5001-2003 standard, with partial
support for 2010 standard
• Device and board test support per Joint Test Action Group (JTAG) (IEEE 1149.1 and
IEEE 1149.7)
• On-chip voltage regulator controller manages the supply voltage down to 1.2 V for core
logic
• Self-test capability
12/112 DocID027866 Rev 5

SPC572Lx Package pinouts and signal descriptions
2 Package pinouts and signal descriptions
2.1 Package pinouts

The QFP package pinouts are shown in Figure 3 and Figure 4.
Figure 3. 80-pin QFP configuration (top view)
VDD_HV_IO_MAIN
VDD_HV_IO_ETH
VDD_HV_IO_FLA
PC[12]
PC[13]
PC[14]
PE[12]
PC[10]
PC[15]
PA[10]
PA[13]
PA[12]
PC[11]
PA[11]
PD[0]
PD[1]
PD[2]
PD[3]
PA[1]
PA[2]
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PD[14] 1 eTQFP80 60 PE[9]
PD[15] 2 59 PD[5]
PC[9] 3 58 PD[4]
PC[8] 4 57 ESR0
PC[7] 5 56 PORST
PC[6] 6 55 VDD_HV_PMC
PC[5] 7 54 TESTMODE
PC[4] 8 53 PA[6]
PC[3] 9 52 PA[5]
PC[2] 10 51 PA[9]
PC[1] 11 50 PA[7]
PC[0] 12 49 PA[8]
PE[0] 13 48 PD[6]
PE[1] 14 47 PD[7]
VDD_LV 15 46 PF[13]
VDD_HV_IO_MAIN 16 45 VDD_HV_IO_JTAG/
VDD_HV_OSC
PB[15] 17 44 XTAL
PB[14] 18 43 EXTAL
PB[13] 19 42 VDD_LV
PB[12] 20 41 VDD_HV_IO_MAIN
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PG[7]
PG[8]
PE[14]
PB[4]
PE[13]
PD[11]
PB[3]
PB[2]
PB[1]
PB[0]
PB[11]
PB[10]
PB[9]
PB[8]
PA[3]
PD[8]
PA[15]
VSS_HV_ADR
VDD_HV_ADR
VDD_HV_ADV
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Package pinouts and signal descriptions SPC572Lx
Figure 4. 100-pin QFP configuration (top view)
VDD_HV_IO_MAIN
VDD_HV_IO_ETH
VDD_HV_IO_FLA
PC[10]
PC[12]
PC[13]
PC[14]
PC[15]
PE[12]
PE[10]
PC[11]
PE[11]
PA[10]
PA[13]
PA[12]
PA[11]
PD[0]
PD[1]
PD[2]
PD[3]
PF[2]
PF[3]
PA[0]
PA[1]
PA[2]
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
77
76
78
PD[14] 1 75 PE[9]
PD[15] 2 eTQFP100 74 PE[8]
PC[9] 3 73 PD[5]
PC[8] 4 72 PD[4]
PC[7] 5 71 PE[7]
PC[6] 6 70 PE[6]
PC[5] 7 69 PE[5]
PC[4] 8 68 VDD_LV
PC[3] 9 67 ESR0
PC[2] 10 66 PORST
PC[1] 11 65 ESR1
PC[0] 12 64 TESTMODE
PE[0] 13 63 PA[6]
PE[1] 14 62 PA[5]
PE[2] 15 61 PA[9]
PD[12] 16 60 PA[7]
PD[13] 17 59 PA[8]
PE[3] 18 58 PD[6]
VDD_LV 19 57 PD[7]
VDD_HV_IO_MAIN 20 56 PF[13]
PB[15] 21 55 VDD_HV_IO_JTAG/
VDD_HV_OSC
PB[14] 22 54 XTAL
PB[13] 23 53 EXTAL
PB[12] 24 52 VDD_LV
PG[6] 25 51 VDD_HV_IO_MAIN
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
PG[7]
PG[8]
PE[15]
PE[14]
PB[4]
PE[13]
PD[11]
PB[3]
PB[2]
PB[1]
PB[0]
PF[1]
PF[0]
PD[9]
PD[10]
PB[11]
PB[10]
PB[9]
PB[8]
PA[3]
PD[8]
PA[15]
VSS_HV_ADR
VDD_HV_ADR
VDD_HV_ADV
2.2 Pin descriptions

The following sections provide signal descriptions and related information about device
functionality and configuration.
2.2.1 Power supply and reference voltage pins

Table 3 contains information on power supply and reference pin functions for the devices.
See the Signal Table (Excel file) attached to this document. Locate the paperclip symbol on
the left side of the PDF window, and click it. Double-click on the excel file to open it and select
the Supply Pins Table tab.
14/112 DocID027866 Rev 5

Table 3. Power supply and reference pins

Supply QFP pin
Symbol Type Description 80 100
VSS_HV Ground High voltage ground Exposed Exposed

pad 81 pad 101
VSS_LV Ground Low voltage ground Exposed Exposed
pad 81 pad 101
VSS_HV_OSC Ground Ground supply for the oscillator Exposed Exposed
pad 81 pad 101
VDD_LV Power Low voltage power supply for 15, 42, 68 19, 52, 68
production device
(PLL is also powered by this pin.)
VDD_HV_PMC Power High voltage power supply for 55 —
internal power management unit
VDD_HV_IO_MAIN Power High voltage power supply for I/O 16, 41, 67 20, 51, 85
VDD_HV_IO_JTAG Power JTAG/Oscillator power supply 45 55
VDD_HV_OSC Power Oscillator voltage supply 45 55
VDD_HV_IO_ETH Power Ethernet 3.3 V I/O supply 77 95
VDD_HV_FLA Power Decoupling supply pin for flash 68 86
VDD_HV_ADV Power High voltage supply for ADC 33 39
VSS_HV_ADR Reference Ground reference of ADCs 23 28
VDD_HV_ADR Reference Voltage reference of ADCs 24 29
2.2.2 System pins

Table 4 contains information on system pin functions for the devices.
Table 4. System pins

QFP pin
Symbol Description Direction
80 100
PORST Power on reset with Schmitt trigger characteristics and Bidirectional 56 66

noise filter. PORST is active low
ESR0 External functional reset with Schmitt trigger Bidirectional 57 67
characteristics and noise filter. ESR0 is active low
TESTMODE Pin for testing purpose only. Input only 54 64
An internal pull-down is implemented on the
TESTMODE pin to prevent the device from entering
TESTMODE. It is recommended to connect the
TESTMODE pin to VSS_HV_IO on the board. The value
of the TESTMODE pin is latched at the negation of
reset and has no affect afterward. The device will not
exit reset with the TESTMODE pin asserted during
power-up.
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Package pinouts and signal descriptions SPC572Lx
Table 4. System pins (continued)

QFP pin
Symbol Description Direction
80 100
XTAL Analog output of the oscillator amplifier circuit Output 44 54

needs to be grounded if oscillator is used in bypass
mode.
EXTAL Analog input of the oscillator amplifier circuit when Input 43 53
oscillator is not in bypass mode
Analog input for the clock generator when oscillator is
in bypass mode
2.2.3 LVDS pins

Table 5 contains information on LVDS pin functions for the devices.
Table 5. LVDSM pin descriptions

Package pin number
Functional Port
Signal Signal description Direction
block pin eTQFP80 eTQFP100
SIPI PF[13] SIPI_RXN Interprocessor Bus LFAST, I 46 56

LFAST(1) LVDS Receive Negative
Terminal
PD[7] SIPI_RXP Interprocessor Bus LFAST, I 47 57
LVDS Receive Positive Terminal
PD[6] SIPI_TXN Interprocessor Bus LFAST, O 48 58
LVDS Transmit Negative
Terminal
PA[8] SIPI_TXP Interprocessor Bus LFAST, O 49 59
LVDS Transmit Positive
Terminal
DSPI 4 PD[3] SCK_N DSPI 4 Microsecond Bus Serial O 69 87
Microsecond Clock, LVDS Negative Terminal
Bus
PD[2] SCK_P DSPI 4 Microsecond Bus Serial O 70 88
Clock, LVDS Positive Terminal
PD[1] SOUT_N DSPI 4 Microsecond Bus Serial O 71 89
Data, LVDS Negative Terminal
PD[0] SOUT_P DSPI 4 Microsecond Bus Serial O 72 90
Data, LVDS Positive Terminal
1. DRCLK and TCK/DRCLK usage for SIPI LFAST is described in the SPC572Lx reference manual, refer to SIPI LFAST
chapter.
2.2.4 Generic pins

The I/O Signal Description Table contains information on generic pins. See the I/O Signal
Description and Input Multiplexing Tables (Excel file) attached to this document. Locate the
16/112 DocID027866 Rev 5

paperclip symbol on the left side of the PDF window, and click it. Double-click on the excel
file to open it and select the I/O Signal Description Table tab.
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111
Electrical characteristics SPC572Lx
3 Electrical characteristics
3.1 Introduction
This section contains detailed information on power considerations, DC/AC electrical
characteristics, and AC timing specifications.
In the tables where the device logic provides signals with their respective timing
characteristics, the symbol “CC” (Controller Characteristics) is included in the “Symbol”
column.
In the tables where the external system must provide signals with their respective timing
characteristics to the device, the symbol “SR” (System Requirement) is included in the
“Symbol” column.
Note: Within this document, VDD_HV_IO refers to supply pins VDD_HV_IO_MAIN, VDD_HV_IO_JTAG,
VDD_HV_IO_ETH, VDD_HV_PMC and VDD_HV_FLA.
3.2 Parameter classification

The electrical parameters shown in this supplement are guaranteed by various methods. To
give the customer a better understanding, the classifications listed in Table 6 are used and
the parameters are tagged accordingly in the tables where appropriate.
Table 6. Parameter classifications

Classification tag Tag description
P Parameters are guaranteed by production testing on each individual device.

C Parameters are guaranteed by the design characterization by measuring a statistically relevant
sample size across process variations.
T Parameters are guaranteed by design characterization on a small sample size from typical
devices under typical conditions unless otherwise noted. All values shown in the typical column
are within this category.
D Parameters are derived mainly from simulations.
Note: The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
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SPC572Lx Electrical characteristics
3.3 Absolute maximum ratings

Table 7 describes the maximum ratings of the device.
Table 7. Absolute maximum ratings(1)

Value
Symbol Parameter Conditions Unit
Min Max
Cycle SR Lifetime power cycles — — 1000 k

VSS_HV SR Ground voltage — — — —
(2),(3),(4)
VDD_LV SR 1.2 V core supply voltage — –0.3 1.5 V
VDD_HV_IO(5) SR I/O supply voltage (6)
— –0.3 6.0 V
(7)
VDD_HV_ADV SR SAR and S/D ADC supply voltage Reference to VSS_HV_ADV –0.3 6.0 V
VSS_HV_ADR SR SAR and S/D ADC low reference Reference to VSS_HV –0.3 0.3 V
VDD_HV_ADR SR SAR and S/D ADC high reference Reference to –0.3 6.0 V
corresponding VSS_HV_ADR
VIN SR I/O input voltage range(8) — –0.3 6.0 V
Relative to VSS_HV_IO –0.3 —
Relative to VDD_HV_IO — 0.3
IINJD SR Maximum DC injection current for Per pin, applies to all digital –5 5 mA
digital pad pins
IINJA SR Maximum DC injection current for Per pin, applies to all –5 5 mA
analog pad analog pins
IMAXD SR Maximum output DC current when Medium −7 8 mA
driven
Strong –10 10
Very strong –11 11
IMAXSEG SR Maximum current per power — –90 90 mA
segment(9)
TSTG SR Storage temperature range and — –55 175 °C
non-operating times
STORAGE SR Maximum storage time, assembled No supply; storage — 20 years
part programmed in ECU temperature in range –40
°C to 60 °C
TSDR SR Maximum solder temperature(10) — — 260 °C
Pb-free package
MSL SR Moisture sensitivity level(11) — — 3 —
tXRAY T X-ray screen time At 80÷130 KV; 20÷50 µA; — 200 ms
max 1 Gy dose
1. Functional operating conditions are given in the DC electrical specifications. Absolute maximum ratings are stress ratings
only, and functional operation at the maxima is not guaranteed. Stress beyond the listed maxima may affect device
reliability or cause permanent damage to the device.
2. Allowed 1.45 – 1.5 V for 60 seconds cumulative time at maximum TJ = 150 °C, remaining time as defined in note 5.
3. Allowed 1.375 – 1.45 V for 10 hours cumulative time at maximum TJ = 125 °C, remaining time as defined in note 5.
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111
4. 1.32 – 1.375 V range allowed periodically for supply with sinusoidal shape and average supply value below 1.288 V at
maximum TJ = 125 °C
5. VDD_HV_IO refers to supply pins VDD_HV_IO_MAIN, VDD_HV_IO_JTAG, VDD_HV_IO_ETH, VDD_HV_OSC, VDD_HV_FLA.
6. Allowed 5.5–6.0 V for 60 seconds cumulative time with no restrictions, for 10 hours cumulative time device in reset, TJ
= 150 °C remaining time at or below 5.5 V.
7. VDD_HV_ADV is also the supply for the device temperature sensor and bandgap reference.
8. The maximum input voltage on an I/O pin tracks with the associated I/O supply maximum. For the injection current
condition on a pin, the voltage equals the supply plus the voltage drop across the internal ESD diode from I/O pin to supply.
The diode voltage varies significantly across process and temperature, but a value of 0.3 V can be used for nominal
calculations.
9. Sum of all controller pins (including both digital and analog) must not exceed 150 mA. A VDD_HV_IO power segment is
defined as one or more GPIO pins located between two VDD_HV_IO supply pins.
10. Solder profile per IPC/JEDEC J-STD-020D.
11. Moisture sensitivity per JEDEC test method A112.
3.4 Electromagnetic Compatibility (EMC)

EMC measurements to IC-level IEC standards are available from STMicroelectronics on
request.
3.5 Electrostatic discharge (ESD)

The following table describes the ESD ratings of the device.
Table 8. ESD ratings(1),(2)

Parameter C Conditions Value Unit
ESD for Human Body Model (HBM)(3) T All pins 2000 V

ESD for field induced Charged Device Model (CDM)(4) T All pins 500 V
1. All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits.
2. Device failure is defined as: “If after exposure to ESD pulses, the device does not meet the device specification
requirements, which includes the complete DC parametric and functional testing at room temperature and hot temperature.
Maximum DC parametrics variation within 10% of maximum specification”.
3. This parameter tested in conformity with ANSI/ESD STM5.1-2007 Electrostatic Discharge Sensitivity Testing.
4. This parameter tested in conformity with ANSI/ESD STM5.3-1990 Charged Device Model - Component Level.
3.6 Operating conditions

The following table describes the operating conditions for the device for which all
specifications in the datasheet are valid, except where explicitly noted.
The device operating conditions must not be exceeded or the functionality of the device is not
guaranteed.
20/112 DocID027866 Rev 5

Table 9. Device operating conditions(1)

Value
Symbol C Parameter Conditions Unit
Min Typ Max
Frequency
fSYS CC C Device operating TJ −40 °C to 150 °C — — 80 MHz
frequency(2)
Temperature
TJ SR P Operating — –40.0 — 150.0 °C
temperature range -
junction
TA (TL to TH) SR P Ambient operating — –40.0 — 125.0 °C
temperature range
Voltage
VDD_LV CC P Core supply voltage Refer to Section 3.15: Power management: PMC, V
measured at external POR/LVD, sequencing
pin(3)(4)
VDD_HV_IO_MAIN(5) SR P I/O supply voltage LVD400 enabled(6) 4.5 — 5.5 V
C LVD400 disabled (6), 4.0 — 5.9
(7),(8),(9)
C 3.0 — 5.9
VDD_HV_IO_JTAG SR P JTAG I/O supply 5 V range 4.5 — 5.5 V
voltage(10)
C 3.3 V range 3.0 — 3.6
C 5 V range 4.0 — 5.9
VDD_HV_IO_ETH SR P Ethernet I/O supply 5 V range 4.5 — 5.5 V
voltage
C 3.3 V range 3.0 — 3.6
VDD_HV_FLA(11),(12) CC P Flash core voltage — 3.0 — 5.5 V
VDD_HV_ADV SR P SARADC and LVD295/ enabled 4.5 — 5.5 V
SDADC supply
C LVD400 4.0 — 5.9
voltage
disabled(10),(7),(8)
C LVD295/ 3.7 — 5.9
disabled(7),(8)
VDD_HV_ADR SR P SAR and S/D ADC — 4.5 — 5.5 V
reference
C 4.0 — 5.9
C 2.0 — 4.0
VDD_HV_ADR – SR D SAR and S/D ADC — — — 25 mV
VDD_HV_ADV reference voltage
VSS_HV_ADR SR P SD ADC ground — VSS_HV_ADV V

reference voltage
VRAMP_HV SR D Slew rate on HV — — — 100 V/ms
power supply pins
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111
Table 9. Device operating conditions(1) (continued)

Value
Min Typ Max
VIN SR C I/O input voltage — 0 — 5.5 V

range
Injection current
IIC SR T DC injection current Digital pins and –3.0 — 3.0 mA
(per pin)(13),(14),(15) analog pins
IMAXSEG SR D Maximum current per — –80 — 80 mA
power segment(16)
1. The ranges in this table are design targets and actual data may vary in the given range.
2. Maximum operating frequency is applicable to the core and platform for the device. See the Clocking chapter in the
SPC572Lx Microcontroller Reference Manual for more information on the clock limitations for the various IP blocks on the
device.
3. Core voltage as measured on device pin to guarantee published silicon performance.
4. During power ramp, voltage measured on silicon might be lower. Maximum performance is not guaranteed, but correct
silicon operation is guaranteed. Refer to the Power Management and Reset Generation Module chapters in the SPC572Lx
Microcontroller Reference Manual for further information.
5. The VDD_HV_PMC supply providing power to the internal regulator is shorted with the VDD_HV_IO supply within package.
6. LVD400 can be disabled by SW (always enabled after power-up).
7. Maximum voltage is not permitted for entire product life. See Absolute maximum rating.
8. When internal LVD/HVDs are disabled, external monitoring is required to guarantee correct device operation.
9. Reduced output/input capabilities below 4.2 V. See performance operating values in I/O pad electrical characteristics. Not
all functionality are guaranteed below 4.2 V. Please check specific supply constraints by module in Table 9 (Device
operating conditions).
10. VDD_HV_IO_JTAG supply is shorted with VDD_HV_OSC supply within package.
11. Flash read, program, and erase operations are supported for a minimum VDD_HV_FLA value of 3.0 V.
12. This voltage can be measured on the pin but is not supplied by an external regulator. The Power Management Controller
generates PORs based on this voltage.
13. Full device lifetime without performance degradation
14. I/O and analog input specifications are only valid if the injection current on adjacent pins is within these limits. See the
Absolute maximum ratings table for maximum input current for reliability requirements.
15. The I/O pins on the device are clamped to the I/O supply rails for ESD protection. When the voltage of the input pin is
above the supply rail, current is injected through the clamp diode to the supply rail. For external RC network calculation,
assume typical 0.3 V drop across the active diode. The diode voltage drop varies with temperature.
16. Sum of all controller pins (including both digital and analog) must not exceed 150 mA. A VDD_HV_IO power segment is
defined as one or more GPIO pins located between two VDD_HV_IO supply pins.
3.7 DC electrical specifications

The following table describes the DC electrical specifications.
22/112 DocID027866 Rev 5

Table 10. DC electrical specifications(1)

Value
Min Typ Max
IDD CC P Operating current all fMAX(2) — — 145 mA

supply rails
IDDPE CC C Operating current all fMAX(3) — — 165 mA
supplies including
program/erase
IDDAPP CC P Operating current all At TJ<150°C — — 125 mA
supplies with typical
application
IDDAR CC P VDD_HV_IO After Run At 40 °C — — 22 mA
operating current Total device consumption
on VDD_HV_IO, including
consumption for VDD_LV
generation.
No I/O activity
CC T After-run mode HV — — 24
current, TA = 55 °C,
VDD_HV_IO = 5.5 V
ISPIKE CC T Maximum short term < 20 µs observation — — 60 mA
current spike window
dI CC T Current difference ratio to < 20 µs observation — — 20 %
average current (dI/avg(I)) window
ISR CC D Current variation during — — — 50 mA
boot/shut-down
VREF_BG_T CC P Bandgap trimmed TJ = –40 °C to 150 °C 1.200 — 1.237 V
reference voltage VDD_HV_ADV = 5 V + 10%
VREF_BG_TC CC C Bandgap temperature TJ = –40 °C to 150 °C -50 — 50 ppm
coefficient(4) VDD_HV_ADV = 5 V + 10% /°C
VREF_BG_LR CC C Bandgap line regulation TJ = –40 °C — — 8000 ppm

VDD_HV_ADV = 5 V + 10% /V
C TJ = 150 °C — — 4000
VDD_HV_ADV = 5 V + 10%
1. The ranges in this table are design targets and actual data may vary in the given range.
2. fMAX as specified per IP, unloaded I/O with LVDS pins active and terminated. Measured on an application specific pattern.
3. fMAX as specified per IP, unloaded I/O with LVDS pins active and terminated. Measured on an application specific pattern
with active flash program and erase.
4. The temperature coefficient and line regulation specifications are used to calculate the reference voltage drift at an
operating point within the specified voltage and temperature operating conditions.
3.8 I/O pad specification

The following table describes the different pad type configurations.
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Table 11. I/O pad specification descriptions

Pad type Description
Weak configuration Provides a good compromise between transition time and low electromagnetic emission.
Pad impedance is centered around 800 Ω.
Medium configuration Provides transition fast enough for the serial communication channels with controlled
current to reduce electromagnetic emission.
Strong configuration Provides fast transition speed; used for fast interface.
Very strong configuration Provides maximum speed and controlled symmetric behavior for rise and fall transition.
Used for fast interface including Ethernet interfaces requiring fine control of rising/falling
edge jitter.
Differential configuration A few pads provide differential capability providing very fast interface together with good
EMC performances.
Input only pads These low input leakage pads are associated with the ADC channels.
Note: Each I/O pin on the device supports specific drive configurations. See the signal description
table in the device reference manual for the available drive configurations for each I/O pin.
3.8.1 I/O input DC characteristics

Table 12 provides input DC electrical characteristics as described in Figure 5.
Figure 5. I/O input DC electrical characteristics definition
VIN
VDD
VIH
VHYS
VIL
VINTERNAL
(SIUL register)
24/112 DocID027866 Rev 5

Table 12. I/O input DC electrical characteristics

Value
Min Typ Max
TTL
VIHTTL SR P Input high level TTL 4.5 V < VDD_HV_IO < 5.5 V(6) 2 — VDD_HV_IO + V
0.3
VILTTL SR P Input low level TTL 4.5 V < VDD_HV_IO < 5.5 V(6) –0.3 — 0.8
VHYSTTL — C Input hysteresis TTL 4.5 V < VDD_HV_IO < 5.5 V(6) 0.275 — —
VDRFTTTL — T Input VIL/VIH — — — 100 mV
temperature drift TTL
AUTOMOTIVE
VIHAUT(1) SR P Input high level 4.5 V < VDD_HV_IO < 5.5 V 3.8 — VDD_HV_IO + V
AUTOMOTIVE 0.3
VILAUT(2) SR P Input low level 4.5 V < VDD_HV_IO < 5.5 V –0.3 — 2.1(3) V
AUTOMOTIVE
VHYSAUT(4) — C Input hysteresis 4.5 V < VDD_HV_IO < 5.5 V 0.4(3) — — V
AUTOMOTIVE
VDRFTAUT — T Input VIL/VIH 4.5 V < VDD_HV_IO < 5.5 V — — 100(5) mV
temperature drift
CMOS
VIHCMOS_H SR P Input high level CMOS 3.0 V < VDD_HV_IO < 3.6 V 0.65 * — VDD_HV_IO V
(6) (with hysteresis) VDD_H
4.5 V < VDD_HV_IO < 5.5 V + 0.3
V_IO
VIHCMOS(7) SR P Input high level CMOS 3.0 V < VDD_HV_IO < 3.6 V 0.6 * — VDD_HV_IO+ 0 V
(without hysteresis) VDD_H .3
4.5 V < VDD_HV_IO < 5.5 V
V_IO
VILCMOS_H(6 SR P Input low level CMOS 3.0 V < VDD_HV_IO < 3.6 V –0.3 — 0.35 * V
) (with hysteresis)
4.5 V < VDD_HV_IO < 5.5 V VDD_HV_IO
(7)
VILCMOS SR P Input low level CMOS 3.0 V < VDD_HV_IO < 3.6 V –0.3 — 0.4 * V
(without hysteresis) VDD_HV_IO
4.5 V < VDD_HV_IO < 5.5 V
VHYSCMOS — C Input hysteresis CMOS 3.0 V < VDD_HV_IO < 3.6 V 0.1 * — — V
4.5 V < VDD_HV_IO < 5.5 V(8) VDD_H
V_IO
VDRFTCMOS — T Input VIL/VIH 3.0 V < VDD_HV_IO < 3.6 V — — 100(5) mV

temperature drift CMOS
4.5 V < VDD_HV_IO < 5.5 V
INPUT CHARACTERISTICS(7)
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Table 12. I/O input DC electrical characteristics (continued)

Value
Min Typ Max
ILKG CC Digital input leakage 4.5 V < VDD_HV < 5.5 V — — 1 µA

P 0.1*VDD_HV < VIN < 0.9*VDD_HV
TJ < 150 °C
C 4.5 V < VDD_HV < 5.5 V — — 2
VSS_HV < VIN < VDD_HV
ILKG_MED CC C Digital input leakage for 4.5 V < VDD_HV < 5.5 V — — 500 nA
MEDIUM pad 0.1*VDD_HV < VIN < 0.9*VDD_HV
CIN CC D Digital input capacitance GPIO input pins — — 10 pF

Ethernet input pins — — 8
1. A good approximation for the variation of the minimum value with supply is given by formula VIHAUT = 0.69 × VDD_HV_IO.
2. A good approximation for the variation of the maximum value with supply is given by formula VILAUT = 0.49 × VDD_HV_IO.
3. Sum of VILAUT and VHYSAUT is guaranteed to remain above 2.6 V in the 4.5 V < VDD_HV_IO < 5.5 V. Production test done
with 2.06 V limit at cold, TJ < 25 oC.
4. A good approximation of the variation of the minimum value with supply is given by formula VHYSAUT = 0.11 × VDD_HV_IO.
5. In a 1 ms period, assuming stable voltage and a temperature variation of ±30 °C, VIL/VIH shift is within ±50 mV. For SENT
requirement refer to NOTE on page 34.
6. Only for VDD_HV_IO_JTAG and VDD_HV_IO_ETH power segment. The TTL threshold are controlled by the VSIO bit.
VSIO[VSIO_xx] = 0 in the range 3.0 V < VDD_HV_IO < 4.0 V, VSIO[VSIO_xx] = 1 in the range 4.5 V < VDD_HV_IO < 5.5 V.
7. For LFAST, microsecond bus and LVDS input characteristics, refer to dedicated communication module chapters.
8. Only for VDD_HV_IO_JTAG and VDD_HV_IO_ETH power segment.
Table 13 provides weak pull figures. Both pull-up and pull-down current specifications are
provided.
Table 13. I/O pull-up/pull-down DC electrical characteristics

Value
Min Typ Max
|IWPU| CC T Weak pull-up VIN = 0 V 10.6 * VDD_HV – — — µA

current absolute VDD_POR(2) < VDD_HV_IO 10.6
value(1) < 3.0 V(3)(4)
CC T VIN > VIL = 1.1 V (TTL) — — 130
4.5 V < VDD_HV_IO < 5.5 V
CC P VIN = 0.69* VDD_HV_IO 23 — 65
4.5 V < VDD_HV_IO < 5.5 V
CC T VIN = 0.49* VDD_HV_IO — — 82
4.5 V < VDD_HV_IO < 5.5 V
RWPU CC D Weak pull-up 0.49* VDD_HVIO < VIN < 0.69* 34 — 62 kΩ
resistance VDD_HV_IO
4.5 V < VDD_HV_IO < 5.5 V
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Table 13. I/O pull-up/pull-down DC electrical characteristics (continued)

Value
Min Typ Max
|IWPD| CC T Weak pull-down VIN < VIL = 0.9 V (TTL) 16 — — µA

current absolute 4.5 V < VDD_HV_IO < 5.5 V
value
P VIN = 0.69* VDD_HV_IO 50 — 130
4.5 V < VDD_HV_IO < 5.5 V
T VIN = 0.49* VDD_HV_IO 40 — —
4.5 V < VDD_HV_IO < 5.5 V
RWPD CC D Weak pull-down 0.49* VDD_HV_IO < VIN < 0.69* 30 — 55 kΩ
resistance VDD_HV_IO
4.5 V < VDD_HV_IO < 5.5 V
1. Weak pull-up/down is enabled within tWK_PU = 1 µs after internal/external reset has been asserted. Output voltage will
depend on the amount of capacitance connected to the pin.
2. VDD_POR is the minimum VDD_HV_IO supply voltage for the activation of the device pull-up/down, and is given in the Reset
electrical characteristics table of Section Reset pad (PORST, ESR0) electrical characteristics in this Datasheet.
3. VDD_POR is defined in the Table 19: Reset electrical characteristics of Section 3.10: Reset pad (PORST, ESR0) electrical
characteristics in this Datasheet.
4. Weak pull-up behavior during power-up. Operational with VDD_HV_IO > VDD_POR.
Figure 6. Weak pull-up electrical characteristics definition
tWK_PU tWK_PU
VDD_HV_IO
VDD_POR
RESET(INTERNAL)
pull-up
enabled
YES
NO
PAD (1)
(1)
(1)
POWER-UP Application defined RESET Application defined POWER-DOWN
1. Actual PAD slopes will depend on external capacitances and VDD_HV_IO supply.
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3.8.2 I/O output DC characteristics

The figure below provides description of output DC electrical characteristics.
Figure 7. I/O output DC electrical characteristics definition
VINTERNAL
(SIUL register)
50% 50%
VHYS
tPD10-90 (rising edge) tPD10-90 (falling edge)
Vout tSKEW20-80
90%
80%
20%
10%
tR20-80
tF20-80
tR10-90
tF10-90
tTR(max) = MAX(tR10-90;tF10-90) tTR20-80(max) = MAX(tR20-80;tF20-80)

tTR(min) = MIN(tR10-90;tF10-90) tTR20-80(min) = MIN(tR20-80;tF20-80)
tSKEW = |tR20-80-tF20-80|
The following tables provide DC characteristics for bidirectional pads:

• Table 14 provides output driver characteristics for I/O pads when in WEAK
configuration.
• Table 15 provides output driver characteristics for I/O pads when in MEDIUM
configuration.
• Table 16 provides output driver characteristics for I/O pads when in STRONG
configuration.
• Table 17 provides output driver characteristics for I/O pads when in VERY STRONG
configuration.
Note: Driver configuration is controlled by SIUL2_MSCRn registers. It is available within two
PBRIDGEA_CLK clock cycles after the associated SIUL2_MSCRn bits have been written.
Table 14 shows the WEAK configuration output buffer electrical characteristics.
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Table 14. WEAK configuration output buffer electrical characteristics

Value(2)
Symbol C Parameter Conditions(1) Unit
Min Typ Max
ROH_W CC P PMOS output impedance 4.5 V < VDD_HV_IO < 5.5 V 520 800 1040 Ω
weak configuration Push pull, IOH < 0.5 mA
ROL_W CC P NMOS output impedance 4.5 V < VDD_HV_IO < 5.5 V 520 800 1040 Ω
weak configuration Push pull, IOL < 0.5 mA
fMAX_W CC T Output frequency CL = 25 pF(3) — — 2 MHz
weak configuration CL = 50 pF (3)
— — 1
D CL = 200 pF (3)
— — 0.25
tTR_W CC T Transition time output pin CL = 25 pF, 40 — 120 ns
weak configuration(4) 4.5 V < VDD_HV_IO < 5.5 V
CL = 50 pF, 80 — 240
4.5 V < VDD_HV_IO < 5.5 V
D CL = 200 pF, 320 — 820
4.5 V < VDD_HV_IO < 5.5 V
CL = 25 pF, 50 — 150
3.0 V < VDD_HV_IO < 3.6 V(5)
CL = 50 pF, 100 — 300
3.0 V < VDD_HV_IO < 3.6 V(5)
CL = 200 pF, 350 — 1050
3.0 V < VDD_HV_IO < 3.6 V(5)
|tSKEW_W| CC T Difference between rise — — — 25 %
and fall time
IDCMAX_W CC D Maximum DC current — — — 4 mA
TPHL/PLH CC D Propagation delay CL = 25 pF, — — 120 ns
4.5 V < VDD_HV_IO < 5.9 V
CL = 25 pF, — — 150
3.0 V < VDD_HV_IO < 3.6 V
CL = 50 pF, — — 240
4.5 V < VDD_HV_IO < 5.9 V
CL = 50 pF, — — 300
3.0 V < VDD_HV_IO < 3.6 V(5)
1. All VDD_HV_IO conditions for 4.5V to 5.5V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid
for VSIO[VSIO_xx] = 0
2. All values need to be confirmed during device validation.
3. CL is the sum of external capacitance. Device and package capacitances (CIN, defined in Table 12) are to be added to
calculate total signal capacitance (CTOT = CL + CIN).
4. Transition time maximum value is approximated by the following formula:
0 pF < CL < 50 pFtTR_W(ns) = 22 ns + CL(pF) × 4.4 ns/pF
50 pF < CL < 200 pFtTR_W(ns) = 50 ns + CL(pF) × 3.85 ns/pF
5. Only for VDD_HV_IO_JTAG segment when VSIO[VSIO_IJ] = 0 or VDD_HV_IO_ETH segment when VSIO[VSIO_IF] = 0.
Table 15 shows the MEDIUM configuration output buffer electrical characteristics.
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Table 15. MEDIUM configuration output buffer electrical characteristics

Value(2)
(1)
Min Typ Max
ROH_M CC P PMOS output impedance 4.5 V < VDD_HV_IO < 5.5 V 120 200 260 Ω
MEDIUM configuration Push pull, IOH < 2 mA
ROL_M CC P NMOS output impedance 4.5 V < VDD_HV_IO < 5.5 V 120 200 260 Ω
MEDIUM configuration Push pull, IOL < 2 mA
fMAX_M CC T Output frequency CL = 25 pF(3) — — 12 MHz
MEDIUM configuration CL = 50 pF (3)
— — 6
D CL = 200 pF(3) — — 1.5
tTR_M CC T Transition time output pin CL = 25 pF 10 — 30 ns
MEDIUM configuration(4) 4.5 V < VDD_HV_IO < 5.5 V
CL = 50 pF 20 — 60
4.5 V < VDD_HV_IO < 5.5 V
D CL = 200 pF 60 — 200
4.5 V < VDD_HV_IO < 5.5 V
CL = 25 pF, 12 — 42
3.0 V < VDD_HV_IO <
3.6 V(5)
CL = 50 pF, 24 — 86
3.0 V < VDD_HV_IO <
3.6 V(5)
CL = 200 pF, 70 — 300
3.0 V < VDD_HV_IO <
3.6 V(5)
|tSKEW_M| CC T Difference between rise and — — — 25 %
fall time
IDCMAX_M CC D Maximum DC current — — — 4 mA
4.5 V < VDD_HV_IO < 5.9 V
CL = 25 pF, — — 42
3.0 V < VDD_HV_IO < 3.6 V
CL = 50 pF, — — 70
4.5 V < VDD_HV_IO < 5.9 V
CL = 50 pF, — — 85
3.0 V < VDD_HV_IO <
3.6 V(5)
1. All VDD_HV_IO conditions for 4.5 V to 5.5 V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0V to 3.6V are valid
30/112 DocID027866 Rev 5

4. Transition time maximum value is approximated by the following formula:

0 pF < CL < 50 pFtTR_M(ns) = 5.6 ns + CL(pF) × 1.11 ns/pF
50 pF < CL < 200 pFtTR_M(ns) = 13 ns + CL(pF) × 0.96 ns/pF
5. Only for VDD_HV_IO_JTAG segment when VSIO[VSIO_IJ] = 0 or VDD_HV_IO_ETH segment when VSIO[VSIO_IF] = 0
Table 16 shows the STRONG configuration output buffer electrical characteristics.
Table 16. STRONG configuration output buffer electrical characteristics

Value(2)
(1)
Min Typ Max
ROH_S CC P PMOS output impedance 4.5 V < VDD_HV_IO < 5.5 V 30 50 65 Ω

STRONG configuration Push pull, IOH < 8 mA
ROL_S CC P NMOS output impedance 4.5 V < VDD_HV_IO < 5.5 V 30 50 65 Ω
STRONG configuration Push pull, IOL < 8 mA
fMAX_S CC T Output frequency CL = 25 pF(3) — — 40 MHz
STRONG configuration
CL = 50 pF(3) — — 20
CL = 200 pF(3) — — 5
tTR_S CC T Transition time output pin CL = 25 pF 2.5 — 10 ns
STRONG configuration(4) 4.5 V < VDD_HV_IO < 5.5 V
CL = 50 pF 3.5 — 16
4.5 V < VDD_HV_IO < 5.5 V
CL = 200 pF 13 — 50
4.5 V < VDD_HV_IO < 5.5 V
CL = 25 pF, 4 — 15
3.0 V < VDD_HV_IO <
3.6 V(5)
CL = 50 pF, 6 — 27
3.0 V < VDD_HV_IO <
3.6 V(5)
CL = 200 pF, 20 — 83
3.0 V < VDD_HV_IO <
3.6 V(5)
IDCMAX_S CC D Maximum DC current — — — 10 mA
|tSKEW_S| CC T Difference between rise and — — — 25 %
fall time
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Table 16. STRONG configuration output buffer electrical characteristics (continued)

Value(2)
Min Typ Max

4.5 V < VDD_HV_IO < 5.9 V
CL = 25 pF, — — 18
3.0 V < VDD_HV_IO < 3.6 V
CL = 50 pF, — — 20
4.5 V < VDD_HV_IO < 5.9 V
CL = 50 pF, — — 36
3.0 V < VDD_HV_IO <
3.6 V(5)
1. All VDD_HV_IO conditions for 4.5 V to 5.5 V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0 V to 3.6 V are valid
4. Transition time maximum value is approximated by the following formula: tTR_S(ns) = 4.5 ns + CL(pF) x 0.23 ns/pF.
5. Only for VDD_HV_IO_JTAG segment when VSIO[VSIO_IJ] = 0 or VDD_HV_IO_ETH segment when VSIO[VSIO_IF] = 0
Table 17 shows the VERY STRONG configuration output buffer electrical characteristics.
Table 17. VERY STRONG configuration output buffer electrical characteristics

Value(2)
Min Typ Max
ROH_V CC P PMOS output impedance VDD_HV_IO = 5.0 V ± 10%, 20 40 60 Ω

VERY STRONG VSIO[VSIO_xx] = 1,
configuration IOH = 8 mA
C VDD_HV_IO = 3.3 V ± 10%, 30 50 75
VSIO[VSIO_xx] = 0,
IOH = 7 mA(3)
ROL_V CC P NMOS output impedance VDD_HV_IO = 5.0 V ± 10%, 20 40 60 Ω
VERY STRONG VSIO[VSIO_xx] = 1,
configuration IOL = 8 mA
C VDD_HV_IO = 3.3 V ± 10%, 30 50 75
VSIO[VSIO_xx] = 0,
IOL = 7 mA(3)
fMAX_V CC T Output frequency VDD_HV_IO = 5.0 V ± 10%, — — 50 MHz
VERY STRONG CL = 25 pF(4)
configuration
VSIO[VSIO_xx] = 1, — — 50
CL = 15 pF(3),(4)
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Table 17. VERY STRONG configuration output buffer electrical characteristics (continued)
Value(2)
Min Typ Max
tTR_V CC T 10–90% threshold VDD_HV_IO = 5.0 V ± 10%, 1 — 5.3 ns

transition time output pin CL = 25 pF(4)
VERY STRONG
VDD_HV_IO = 5.0 V ± 10%, 2.5 — 12
configuration
CL = 50 pF(4)
VDD_HV_IO = 5.0 V ± 10%, 11 — 45
CL = 200 pF(4)
tTR20-80 CC — 20–80% threshold VDD_HV_IO = 5.0 V ± 10%, 0.8 — 4 ns
transition time output pin CL = 25 pF(4)
VERY STRONG
VDD_HV_IO = 3.3 V ± 10%, 1 — 5
configuration
CL = 15 pF(4)
tTRTTL CC — TTL threshold transition VDD_HV_IO = 3.3 V ± 10%, 1 — 5 ns
time(5) for output pin in CL = 25 pF(4)
VERY STRONG
configuration
ΣtTR20-80 CC — Sum of transition time 20– VDD_HV_IO = 5.0 V ± 10%, — — 9 ns
80% output pin VERY CL = 25 pF
STRONG configuration
VDD_HV_IO = 3.3 V ± 10%, — — 9
CL = 15 pF(4)
|tSKEW_V| CC T Difference between rise VDD_HV_IO = 5.0 V ± 10%, 0 — 1 ns
and fall time at 20–80% CL = 25 pF(4)
4.5 V < VDD_HV_IO < 5.9 V
CL = 25 pF, — — 10.5
3.0 V < VDD_HV_IO < 3.6 V
CL = 50 pF, — — 15
4.5 V < VDD_HV_IO < 5.9 V
CL = 50 pF, — — 12
3.0 V < VDD_HV_IO < 3.6 V
IDCMAX_VS CC D Maximum DC current — — — 10 mA
1. All VDD_HV_IO conditions for 4.5 V to 5.5 V are valid for VSIO[VSIO_xx] = 1, and all specifications for 3.0 V to 3.6 V are valid
for VSIO[VSIO_xx] = 0.
3. Only available on the VDD_HV_IO_JTAG and VDD_HV_IO_ETH segments.
4. CL is the sum of external capacitance. Add device and package capacitances (CIN, defined in the Table 12: I/O input DC
electrical characteristics in this Datasheet) to calculate total signal capacitance (CTOT = CL + CIN).
5. TTL transition time as for Ethernet standard.
3.9 I/O pad current specification

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is
associated to a VDD/VSS supply pair.
Table 18 provides I/O consumption figures.
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In order to ensure device reliability, the average current of the I/O on a single segment should
remain below the IAVGSEG maximum value.
In order to ensure device functionality, the sum of the dynamic and static currents of the I/O
on a single segment should remain below the IDYNSEG maximum value.
Pad mapping on each segment can be optimized using the pad usage information provided
in the I/O Signal Description table. The sum of all pad usage ratios within a segment should
remain below 100%.
Note: In order to maintain the required input thresholds for the SENT interface, the sum of all I/O
pad output percent IR drop as defined in the I/O Signal Description table, must be below
50 %. See the I/O Signal Description attachment.
Note: The SPC572Lx I/O Signal Description and Input Multiplexing Tables are contained in a
Microsoft Excel® workbook file attached to this document. Locate the paperclip symbol on
the left side of the PDF window, and click it. Double-click on the Excel file to open it and
select the I/O Signal Description Table tab.
Table 18. I/O consumption(1)

Value
Min Typ Max
IRMS_SEG SR D Sum of all the DC I/O current VDD = 5.0 V ± 10% — — 80 mA

within a supply segment
VDD = 3.3 V ± 10% — — 80
IRMS_W CC D RMS I/O current for WEAK CL = 25 pF, 2 MHz — — 1.1 mA
configuration VDD = 5.0 V ± 10%
CL = 50 pF, 1 MHz — — 1.1
VDD = 5.0 V ± 10%
CL = 25 pF, 2 MHz — — 0.6
VDD = 3.3 V ± 10%
CL = 50 pF, 1 MHz — — 0.6
VDD = 3.3 V ± 10%
IRMS_M CC D RMS I/O current for MEDIUM CL = 25 pF, 12 MHz — — 4.7 mA
CL = 50 pF, 6 MHz — — 4.8
VDD = 5.0 V ± 10%
CL = 25 pF, 12 MHz — — 2.6
VDD = 3.3 V ± 10%
CL = 50 pF, 6 MHz — — 2.7
VDD = 3.3 V ± 10%
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Table 18. I/O consumption(1) (continued)

Value
Min Typ Max
IRMS_S CC D RMS I/O current for STRONG CL = 25 pF, 50 MHz — — 19 mA

CL = 50 pF, 25 MHz — — 19
VDD = 5.0 V ± 10%
CL = 25 pF, 50 MHz — — 10
VDD = 3.3 V ± 10%
CL = 50 pF, 25 MHz — — 10
VDD = 3.3 V ± 10%
IRMS_V CC D RMS I/O current for VERY CL = 25 pF, 50 MHz, — — 22 mA
STRONG configuration VDD = 5.0V +/- 10%
CL = 50 pF, 25 MHz, — — 22
VDD = 5.0V ± 10%
CL = 25 pF, 50 MHz, — — 11
VDD = 3.3V ± 10%
CL = 25 pF, 25 MHz, — — 11
VDD = 3.3V ± 10%
IDYN_SEG SR D Sum of all the dynamic and DC I/O VDD = 5.0 V ± 10% — — 195 mA
current within a supply segment
VDD = 3.3 V ± 10% — — 150
IDYN_W(2) CC D Dynamic I/O current for WEAK CL = 25 pF, — — 5.0 mA
CL = 50 pF, — — 5.1
VDD = 5.0 V ± 10%
CL = 25 pF, — — 2.2
VDD = 3.3 V ± 10%
CL = 50 pF, — — 2.3
VDD = 3.3 V ± 10%
IDYN_M CC D Dynamic I/O current for MEDIUM CL = 25 pF, — — 15 mA
CL = 50 pF, — — 15.5
VDD = 5.0 V ± 10%
CL = 25 pF, — — 7.0
VDD = 3.3 V ± 10%
CL = 50 pF, — — 7.1
VDD = 3.3 V ± 10%
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Table 18. I/O consumption(1) (continued)

Value
Min Typ Max
IDYN_S CC D Dynamic I/O current for STRONG CL = 25 pF, — — 50 mA

CL = 50 pF, — — 55
VDD = 5.0 V ± 10%
CL = 25 pF, — — 22
VDD = 3.3 V ± 10%
CL = 50 pF, — — 25
VDD = 3.3 V ± 10%
IDYN_V CC D Dynamic I/O current for VERY CL = 25 pF, — — 60 mA
STRONG configuration VDD = 5.0 V ± 10%
CL = 50 pF, — — 64
VDD = 5.0 V ± 10%
CL = 25 pF, — — 26
VDD = 3.3 V ± 10%
CL = 50 pF, — — 29
VDD = 3.3 V ± 10%
1. I/O current consumption specifications for the 4.5 V <= VDD_HV_IO <= 5.5 V range are valid for VSIO_[VSIO_xx] = 1, and
VSIO[VSIO_xx] = 0 for 3.0 V <= VDD_HV_IO <= 3.6 V.
2. Stated maximum values represent peak consumption that lasts only a few ns during I/O transition. When possible (timed
output) it is recommended to delay transition between pads by few cycles to reduce noise and consumption.
3.10 Reset pad (PORST, ESR0) electrical characteristics

The device implements a dedicated bidirectional reset pin (PORST).
Note: PORST pin does not require active control. It is possible to implement an external pull-up to
ensure correct reset exit sequence. Recommended value is 4.7 kΩ.
36/112 DocID027866 Rev 5

Figure 8. Start-up reset requirements
VDD
VDDMIN
VDD_POR
PORST
VIH
VIL
PORST undriven. device start-up phase

Device reset by
internal power-on PORST driven low by Device reset forced by
reset. internal power-on reset. external circuitry.
Figure 9 describes device behavior depending on supply signal on PORST:

1. PORST low pulse amplitude is too low—it is filtered by input buffer hysteresis. Device
remains in current state.
2. PORST low pulse duration is too short—it is filtered by a low pass filter. Device remains
in current state.
3. PORST low pulse generates a reset:
a) PORST low but initially filtered during at least WFRST. Device remains initially in
current state.
b) PORST potentially filtered until WNFRST. Device state is unknown: it may either be
reset or remains in current state depending on other factors (temperature, voltage,
device).
c) PORST asserted for longer than WNFRST. Device is under reset.
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Figure 9. Noise filtering on reset signal
VPORST, VESR0
VDD
VIH
VHYS
VIL
internal
reset
filtered by
filtered by filtered by unknown reset
hysteresis lowpass filter lowpass filter state device under hardware reset
WFRST WFRST
WNFRST
1 2 3a 3b 3c
Table 19. Reset electrical characteristics

Value
Min Typ Max
VIH SR P Input high level TTL 2.0 — VDD_HV_IO V

—
(Schmitt trigger) +0.4
VIL SR P Input low level TTL — –0.4 — 0.8 V
(Schmitt trigger)
VHYS CC C Input hysteresis TTL — 275 — — mV
(Schmitt trigger)
VDD_POR CC C Minimum supply for strong — — — 1.2 V
pull-down activation
38/112 DocID027866 Rev 5

Table 19. Reset electrical characteristics (continued)

Value
Min Typ Max
IOL_R CC C Strong pull-down current(1) Device under power-on 0.2 — — mA

reset
VDD_HV_IO = VDD_POR,
VOL = 0.35 * VDD_HV_IO
— — — — —
Device under power-on 12 — — mA
reset
3.0 V < VDD_HV_IO < 5.5 V,
VOL > 1.0 V
|IWPU| CC P Weak pull-up current absolute ESR0 pin 23 — — µA
value VIN = 0.69 * VDD_HV_IO
ESR0 pin — — 82
VIN = 0.49 * VDD_HV_IO
|IWPD| CC P Weak pull-down current PORST pin — — 130 µA
absolute value VIN = 0.69 * VDD_HV_IO
PORST pin 40 — —
VIN = 0.49 * VDD_HV_IO
WFRST SR P PORST and ESR0 input — — — 500 ns
filtered pulse
WNFRST SR P PORST and ESR0 input not — 2000 — — ns
filtered pulse
WFNMI SR P ESR1 input filtered pulse — — — 15 ns
WNFNMI SR P ESR1 input not filtered pulse — 400 — — ns
1. IOL_R applies to both PORST and ESR0: Strong pull-down is active on PHASE0 for PORST. Strong pull-down is active on
PHASE0, PHASE1, PHASE2, and the beginning of PHASE3 for ESR0.
PORST must be connected to an external power-on supply circuitry. Minimum requested

circuitry is external pull-up to ensure device can exit reset.
Note: No restrictions exist on reset signal slew rate apart from absolute maximum rating
compliance.
3.11 Oscillator and PLL

Single phase-locked loop (PLL) module with the reference PLL (PLL0) generating the system
and auxiliary clocks from the main oscillator driver.
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Figure 10. PLL integration
IRCOSC PLL0_PHI0
PLL0 PLL0_PHI1
XOSC
Table 20. PLL0 electrical characteristics

Value
Min Typ Max
fPLL0IN SR — PLL0 input clock(1),(2) — 8 — 44 MHz

ΔPLL0IN SR — PLL0 input clock duty — 40 — 60 %
cycle(1)
fPLL0VCO CC P PLL0 VCO frequency — 600 — 1250 MHz
fPLL0PHI0 CC P PLL0 output frequency — 4.762 — 80 MHz
fPLL0PHI1 CC P PLL0 output frequency — 4.762 — 100 MHz
tPLL0LOCK CC P PLL0 lock time — — — 110 µs
|ΔPLL0PHI0SPJ| CC T PLL0_PHI0 single period fPLL0PHI0 = 400 MHz, — — 200 ps
jitter 6-sigma pk-pk
fPLL0IN = 20 MHz
(resonator)
|ΔPLL0PHI1SPJ| CC T PLL0_PHI1 single period fPLL0PHI1 = 40 MHz, 6- — — 300(3) ps
jitter sigma pk-pk
fPLL0IN = 20 MHz
(resonator)
ΔPLL0LTJ CC T PLL0 output long term 10 periods — — ± 250 ps
jitter(3) accumulated jitter
fPLL0IN = 20 MHz (80 MHz equivalent
(resonator), VCO frequency), 6-sigma
frequency = 800 MHz pk-pk
16 periods — — ± 300 ps
accumulated jitter
(50 MHz equivalent
frequency), 6-sigma
pk-pk
long term jitter — — ± 500 ps
(< 1 MHz equivalent
frequency), 6-sigma
pk-pk
IPLL0 CC C PLL0 consumption FINE LOCK state — — 5 mA
fPLL0FREE CC D VCO free running — 35 — 400 MHz
frequency
40/112 DocID027866 Rev 5

1. PLL0IN clock retrieved directly from either Internal RC Oscillator (IRCOSC) or External Oscillator (XOSC) clock. Input
characteristics are granted when using XOSC.
2. fPLL0IN frequency must be scaled down using PLLDIG_PLL0DV[PREDIV] to ensure PFD input signal is in the range of
8 MHz-20 MHz.
3. VDD_LV noise due to application in the range VDD_LV = 1.25 V ± 5% with frequency below PLL bandwidth (40 kHz) is
filtered.
Table 21. External oscillator electrical specifications

Value
Min Max
fXTAL CC D Crystal frequency range(1) — 4 8 MHz

— >8 20
—
> 20 40
(2)(3)
tcst CC T Crystal start-up time — — 5 ms
trec CC T Crystal recovery time(4) — — 0.5 ms
VIHEXT CC D EXTAL input high voltage VREF = 0.28 * VDD_HV_IO_JTAG VREF + 0.6 — V
(External Reference)
VILEXT CC D EXTAL input low voltage(5) VREF = 0.28 * VDD_HV_IO_JTAG — VREF - 0.6 V
CS_EXTAL CC T Total on-chip stray — — 2.5 + value pF
capacitance on EXTAL pin from
Table 22
CS_XTAL CC T Total on-chip stray — — 2.5 + value pF
capacitance on XTAL pin from
Table 22
gm CC D Oscillator Transconductance TJ = -40 °C to fXTAL ≤ 8 MHz 2.6 11.0 mA/V
150 °C
D fXTAL ≤ 20 MHz 7.9 26.0
4.5 V <
D VDD_HV_IO < fXTAL ≤ 40 MHz 10.4 34.0
5.5 V
IXTAL CC D XTAL current(6) TJ = 150 °C — 14 mA
VHYS CC D Comparator Hysteresis TJ = 150 °C 0.1 1.0 V
1. The range is selectable by DCF record.
2. This value is determined by the crystal manufacturer and board design.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal recovery time is the time for the oscillator to settle to the correct frequency after adjustment of the integrated load
capacitor value.
5. Applies to an external clock input and not to crystal mode.
6. IXTAL is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded. Test circuit is shown in
Figure 11.
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Table 22. Selectable load capacitance

Capacitance offered on EXTAL/XTAL
load_cap_sel[4:0] from DCF record
(Cx and Cy)(1),(2) (pF)
00000 1.0
00001 2.0
00010 2.9
00011 3.8
00100 4.8
00101 5.7
00110 6.6
00111 7.5
01000 8.5
01001 9.4
01010 10.3
01011 11.2
01100 12.2
01101 13.1
01110 14.0
01111 15.0
10000–11111(3) Reserved
1. Values are determined from simulation across process corners and voltage and temperature variation. Capacitance values
vary ±12% across process, 0.25% across voltage, and no variation across temperature.
2. Values in this table do not include the die and package capacitances given by CS_XTAL/CS_EXTAL in Table 21 (External
oscillator electrical specifications).
3. Configurations 10000–11111 should not be used. Configurations 10000–11100 result in same capacitances of
configurations 00011–01111. Configurations 11101, 11110, and 11111 select maximum capacitances.
42/112 DocID027866 Rev 5

Figure 11. Test circuit

VDDOSC
AL Bias
IXTAL XTAL
-
EXTAL
+ Comparator
A OF
VSSOSC
V
VSS
Conditions
Z = R + jωL
VEXTAL = 0 V
VXTAL = 0 V
Tester ALC INACTIVE
PCB GND
Table 23. Internal RC oscillator electrical specifications

Value
Min Typ Max
fTarget CC D IRC target frequency — — 16 — MHz

δfvar_noT CC P IRC frequency variation without temperature — –8 — +8 %
compensation
δfvar_T CC T IRC frequency variation with temperature TJ < 150 °C –1.5 — +1.5 %
compensation
δfvar_SW — T IRC frequency accuracy after software Trimming temperature –1 — +1 %
trimming accuracy(1)
tstart_noT CC T Startup time to reach within fvar_noT Factory trimming — — 5 µs
already applied
tstart_T CC D Startup time to reach within fvar_T Factory trimming — — 120 µs
already applied
1. The typical user trim step size of δfTRIM = 0.35 %
3.12 ADC specifications
3.12.1 ADC input description

Figure 12 shows the input equivalent circuit for fast SARn channels.
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Figure 12. Input equivalent circuit (Fast SARn channels)
INTERNAL CIRCUIT SCHEME
VDD
Channel
Sampling
Selection
RSW1 RAD
CP1 CP2 CS
Common mode
switch
RSW1 Channel Selection Switch Impedance Common mode

resistive ladder
RADSampling Switch Impedance
CP Pin Capacitance (two contributions, CP1 and CP2)
CS Sampling Capacitance
RCMSWCommon mode switch
RCMLCommon mode resistive ladder
This figure can be used as approximation circuitry for
external filtering definition.It is also applicable for channel
AN16, AN17 and AN24 (Fast channels).
Figure 13 shows the input equivalent circuit for SARB channels.
44/112 DocID027866 Rev 5

Figure 13. Input equivalent circuit (SARB channels)
INTERNAL CIRCUIT SCHEME

VDD
Channel Extended
Sampling
Selection Switch
RSW1 RSW2 RAD
CP1 CP3 CP2 CS
Common mode
switch
Common mode
RSW: Channel Selection Switch Impedance (two contributions resistive ladder
RSW1 and RSW2)
RAD: Sampling Switch Impedance
CP: Pin Capacitance (three contributions, CP1, CP2 and CP3)
CS: Sampling Capacitance
RCMSW: Common mode switch
RCML: Common mode resistive ladder
The above figure can be used as approximation circuitry for

external filtering definition.
It is applicable for all SARB channels except AN 16, AN17 and
AN24 (Fast channels).
Table 24. ADC pin specification(1)

Value
Min Max
ILK_INUD CC C Input leakage current, two ADC TJ < 40 °C, no current — 70 nA

channels input with weak pull-up and injection on adjacent
weak pull-down pin
C TJ < 150 °C, no current — 220
injection on adjacent
pin
ILK_INUSD CC C Input leakage current, two ADC TJ < 40 °C, no current — 80 nA
strong pull-down pin
pin
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Table 24. ADC pin specification(1) (continued)

Value
Min Max
ILK_INREF CC C Input leakage current, two ADC TJ< 40 °C, no current — 160 nA
weak pull-down and alternate reference pin
pin
ILK_INOUT CC C Input leakage current, two ADC TJ < 40 °C, no current — 140 nA
channels input, GPIO output buffer with injection on adjacent
weak pull-up and weak pull-down pin
pin
IINJ CC T Injection current on analog input Applies to any analog –3 3 mA
preserving functionality pins
CHV_ADC SR D VDD_HV_ADV external capacitance(2) 1 2.2 µF
CP1 CC D Pad capacitance — 0 10 pF
CP2 CC D Internal routing capacitance SARn channels 0 0.5 pF
(3)
D SARB channels 0 1
CP3 CC D Internal routing capacitance Only for SARB 0 1 pF
channels
CS CC D SAR ADC sampling capacitance — 6 8.5 pF
RSWn CC D Analog switches resistance SARn channels 0 1.1 kΩ
(4)
D SARB channels 0 1.7
RAD CC D ADC input analog switches resistance — 0 0.6 kΩ
RCMSW CC D Common mode switch resistance — 0 2.6 kΩ
RCMRL CC D Common mode resistive ladder — 0 3.5 kΩ
(4)
RSAFEPD CC D Discharge resistance for AN7 channels — 0 300 W
(strong pull-down for safety)
ΣIADR CC C+ Sum of ADC and S/D reference ADC enabled — 40 µA
P consumption
1. All specifications in this table valid for the full input voltage range for the analog inputs.
2. For noise filtering, add a high frequency bypass capacitance of 0.1 µF between VDD_HV_ADV and VSS_HV_ADV.
3. Characteristics corresponding to fast SARn channels also apply to SARB fast channels (AN16, AN17 and AN24).
4. Safety pull-down is available for port pin PE[14]. It enables discharge of up to 100 nF from 5 V every 300 ms.
3.12.2 SAR ADC electrical specification

The SARn ADCs are 12-bit Successive Approximation Register analog-to-digital converters
with full capacitive DAC. The SARn architecture allows input channel multiplexing.
46/112 DocID027866 Rev 5

Table 25. SARn ADC electrical specification(1)

Value
Min Max
VALTREF SR P ADC alternate VALTREF < VDD_HV_IO_MAIN 4.5 5.5 V

reference voltage VALTREF < VDD_HV_ADV
C 2.0 4.0
C 4.0 5.9
VIN SR D ADC input signal 0 < VIN < VDD_HV_IO_MAIN VSS_HV_ADR VDD_HV_ADR V
fADCK SR P Clock frequency TJ < 150 °C 7.5 14.6 MHz
tADCPRECH SR T ADC precharge time Fast SAR—fast precharge 135 — ns
Fast SAR—full precharge 270 —
Slow SAR (SARADC_B)(2)— 270 —
fast precharge
Slow SAR (SARADC_B)(2)— 540 —
full precharge
ΔVPRECH SR D ADC precharge voltage Full precharge –0.25 0.25 V
VPRECH = VDD_HV_ADR/2
TJ < 150 °C
D Fast precharge –0.5 0.5 V
VPRECH = VDD_HV_ADR/2
TJ < 150 °C
ΔVINTREF CC P Internal reference Applies to all internal −0.20 0.20 V
voltage precision reference points
(VSS_HV_ADR,
1/3 * VDD_HV_ADR,
2/3 * VDD_HV_ADR,
VDD_HV_ADR)
tADCSAMPLE SR P ADC sample time(3) Fast SAR – 12-bit 0.750 — µs
configuration
D Fast SAR – 10-bit 0.555 —
configuration
P Slow SAR (SARADC_B)(2) – 1.500 —
12-bit configuration
D Slow SAR (SARADC_B)(2) – 0.833 —
10-bit configuration
tADCEVAL SR P ADC evaluation time 12-bit configuration (25 clock 1.712 — µs
cycles)
D 10-bit configuration (21 clock 1.458 —
cycles)
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Table 25. SARn ADC electrical specification(1) (continued)

Value
Min Max
IADCREFH(4), CC T ADC high reference Dynamic consumption — 3.5(7) µA

(5)
current(6) tconv ≥ 5 µs
(average across all codes)
— 7(8)
Dynamic consumption
tconv > 2.5 µs
(average across all codes)
Static consumption (Power — +8
Down mode)
T Bias Current(9) — +2
(5)
IADCREFL CC D ADC low reference Run mode tconv ≥ 5 µs — 15 µA
current VDD_HV_ADR <= 5.5 V
Run mode tconv = 2.5 µs — 30
VDD_HV_ADR <= 5.5 V
Power Down mode — 1
VDD_HV_ADR <= 5.5 V
IADV_S CC P VDD_HV_ADV power Run mode(5) tconv ≥ 5 µs — 4.0 mA
supply current
TUE12 CC T(10) Total unadjusted error in TJ < 150 °C, –4 4 LSB
12-bit configuration(11) VDD_HV_ADV > 4 V, (12b)
VDD_HV_ADR, VALTREF> 4 V
P TJ < 150 °C, –6 6
VDD_HV_ADV > 4 V,
VDD_HV_ADR, VALTREF> 4 V
T TJ < 150 °C, –6 6
VDD_HV_ADV > 4 V,
4 V > VALTREF> 2 V
T TJ < 150 °C, –12 12
4 V > VDD_HV_ADV > 3.5 V
TUE10 CC T Total unadjusted error in TJ < 150 °C, –1.5 1.5 LSB
10-bit configuration VDD_HV_ADV > 4 V (10b)
VDD_HV_ADR, VALTREF > 4 V
T TJ < 150 °C, –2.0 2.0
VDD_HV_ADV > 4 V,
4 V > VDD_HV_ADR,
VALTREF> 2 V
48/112 DocID027866 Rev 5

Table 25. SARn ADC electrical specification(1) (continued)

Value
Min Max
ΔTUE12 CC D TUE degradation due to VIN < VDD_HV_ADV 0 0 LSB

VDD_HV_ADR offset with VDD_HV_ADR − VDD_HV_ADV (12b)
respect to VDD_HV_ADV ∈ [0:25 mV]
D VIN < VDD_HV_ADV –2 2

VDD_HV_ADR − VDD_HV_ADV
∈ [25:50 mV]
∈ [50:75 mV]
∈ [75:100 mV]
D VDD_HV_ADV < VIN < –2.5 2.5
VDD_HV_ADR
∈ [0:25 mV]
D VDD_HV_ADV< VIN < –4 4
VDD_HV_ADR
∈ [25:50 mV]
D VDD_HV_ADV < VIN < –7 7
VDD_HV_ADR
∈ [50:75 mV]
D VDD_HV_ADV < VIN < –12 12
VDD_HV_ADR
∈ [75:100 mV]
DNL CC P Differential non-linearity VDD_HV_ADV > 4 V –1 2 LSB
VDD_HV_ADR > 4 V (12b)
2. Characteristics corresponding to SARB channels apply only for slow SAR channels i.e., all SARB channels except AN16,
AN17, and AN24.
3. Minimum ADC sample times are dependent on adequate charge transfer from the external driving circuit to the internal
sample capacitor. The time constant of the entire circuit must allow the sampling capacitor to charge within 1/2 LSB within
the sampling window. Please refer to Figure 12 and Figure 13 for models of the internal ADC circuit, and the values to use
in external RC sizing and calculating the sampling window duration.
4. IADCREFH and IADCREFL are independent from ADC clock frequency. It depends on conversion rate: consumption is driven
by the transfer of charge between internal capacitances during the conversion.
5. Current parameter values are for a single ADC.
6. Total consumption is given by the sum for all ADCs (associated to the reference pin) of their dynamic consumption and their
static consumption.
7. Typical consumption is 2 µA.
8. Typical consumption is 4 µA.
DocID027866 Rev 5 49/112

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9. Extra bias current is present only when BIAS is selected. Apply only once for all ADCs.
10. Extended bench validation performed on 3 samples for each process corner.
11. This parameter is guaranteed by bench validation with a small sample of typical devices, and tested in production to ± 6
LSB.
3.12.3 S/D ADC electrical specification

The SDn ADCs are Sigma Delta 16-bit analog-to-digital converters with 333 Ksps maximum
output rate.
Table 26. SDn ADC electrical specification(1)

Value
Min Typ Max
VIN SR P ADC input signal — 0 — VDD_HV_ADR_ V

D
VIN_PK2PK(2) SR D Input range peak to Single ended VDD_HV_ADR/GAIN V

peak VINM = VSS_HV_ADR
D VIN_PK2PK = VINP(3) Single ended ±0.5*VDD_HV_ADR
– VINM (4)
VINM = 0.5*VDD_HV_ADR
GAIN = 1
D Single ended ±VDD_HV_ADR/GAIN
VINM = 0.5*VDD_HV_ADR
GAIN = 2,4,8,16
D Differential, ±VDD_HV_ADR/GAIN
0 < VIN < VDD_HV_IO_MAIN
fADCD_M SR P S/D modulator Input — 4 14.4 16 MHz
Clock
fIN SR D Input signal SNR = 80 dB 0.01 — 50(5) kHz
frequency fADCD_S = 150 kHz
D SNR = 74 dB 0.01 — 111(5)
fADCD_S = 333 kHz
fADCD_S SR D Output conversion — — — 333 ksps
rate
— CC D Oversampling ratio Internal modulator 24 — 256 —

External modulator — — 256 —
RESOLUTION CC D S/D register 2’s complement notation 16 bit
resolution(6)
GAIN SR D ADC gain Defined via ADC_SD[PGA] 1 — 16 —
register. Only integer
powers of 2 are valid gain
values.
50/112 DocID027866 Rev 5

Table 26. SDn ADC electrical specification(1) (continued)

Value
Min Typ Max
|δGAIN| CC C Absolute value of Before calibration (applies to — — 1.5 %

the ADC gain gain setting = 1)
error(7),(8)
D After calibration, — — 5 mV
ΔVDD_HV_ADR < 5%
ΔVDD_HV_ADV < 10%
ΔTJ < 50 °C
After calibration, — — 7.5
ΔVDD_HV_ADR < 5%
ΔVDD_HV_ADV < 10%
ΔTJ < 100 °C
After calibration, — — 10
ΔVDD_HV_ADR < 5%
ΔVDD_HV_ADV < 10%
ΔTJ < 150 °C
VOFFSET CC P Input Referred Before calibration (applies to — 10* 20 mV
Offset Error(7),(8),(9) all gain settings – 1, 2, 4, 8, (1+1/gain)
16)
D After calibration, — — 5
ΔVDD_HV_ADR < 10%
ΔTJ < 50 °C
After calibration, 7.5
ΔVDD_HV_ADV < 10%
ΔTJ < 100 °C
After calibration, 0.5 10
ΔVDD_HV_ADV < 10%
ΔTJ < 150 °C
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Value
Min Typ Max
SNRDIFF150 CC P Signal to noise ratio 4.5 < VDD_HV_ADV < 5.5 80 — — dBFS
in differential mode VDD_HV_ADR = VDD_HV_ADV
150 ksps output rate GAIN = 1
TJ < 150 °C
C 4.5 < VDD_HV_ADV < 5.5 77 — —
VDD_HV_ADR = VDD_HV_ADV
GAIN = 2
TJ < 150 °C
C 4.5 < VDD_HV_ADV < 5.5 74 — —
GAIN = 4
TJ < 150 °C
C 4.5 < VDD_HV_ADV < 5.5 71 — —
GAIN = 8
TJ < 150 °C
D 4.5 < VDD_HV_ADV < 5.5 68 — —
GAIN = 16
TJ < 150 °C
SNRDIFF333 CC P Signal to noise ratio 4.5 < VDD_HV_ADV < 5.5 74 — — dBFS
in differential mode VDD_HV_ADR = VDD_HV_ADV
333 ksps output rate GAIN = 1
TJ < 150 °C
C 4.5 < VDD_HV_ADV < 5.5 71 — —
GAIN = 2
TJ < 150 °C
C 4.5 < VDD_HV_ADV < 5.5 68 — —
GAIN = 4
TJ < 150 °C
C 4.5 < VDD_HV_ADV < 5.5 65 — —
GAIN = 8
TJ < 150 °C
D 4.5 < VDD_HV_ADV < 5.5 62 — —
GAIN = 16
TJ < 150 °C
52/112 DocID027866 Rev 5


Value
Min Typ Max
SNRSE150 CC C Signal to noise ratio 4.5 < VDD_HV_ADV < 5.5 74 — — dBFS
in single ended VDD_HV_ADR = VDD_HV_ADV
mode 150 ksps GAIN = 1
output rate(10) TJ < 150 °C
P 4.5 < VDD_HV_ADV < 5.5 68 — —
GAIN = 1
TJ < 150 °C
T 4.5 < VDD_HV_ADV < 5.5 71 — —
GAIN = 2
TJ < 150 °C
4.5 < VDD_HV_ADV < 5.5 68 — —
GAIN = 4
TJ < 150 °C
4.5 < VDD_HV_ADV < 5.5 65 — —
GAIN = 8
TJ < 150 °C
D 4.5 < VDD_HV_ADV < 5.5 62 — —
VDD_HV_ADR=VDD_HV_ADV
GAIN = 16
TJ < 150 °C
SFDR CC P Spurious free GAIN = 1 60 — — dBc

dynamic range
C GAIN = 2 60 — —
C GAIN = 4 60 — —
C GAIN = 8 60 — —
D GAIN = 16 60 — —
ZDIFF(11) CC D Differential input GAIN = 1 1000 1250 1500 kΩ
impedance
GAIN = 2 600 800 1000
GAIN = 4 300 400 500
GAIN = 8 200 250 300
GAIN = 16 200 250 300
ZCM(11) CC D Common mode GAIN = 1 1400 1800 2200 kΩ
input impedance
GAIN = 2 1000 1300 1600
GAIN = 4 700 950 1150
GAIN = 8 500 650 800
GAIN = 16 500 650 800
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Value
Min Typ Max
ΔVINTCM CC D Common mode — -12% — +12%

input reference
voltage
RBIAS CC D Bare bias resistance — 110 144 180 kΩ
VBIAS CC D Bias voltage — — VDD_HV_ — V
ADR/2
δVBIAS CC D Bias voltage — –2.5 — +2.5 %

accuracy
CMRR SR D Common mode — 54 — — dB
rejection ratio
RCaaf SR D Anti-aliasing filter External series resistance — — 20 kΩ
CC D Filter capacitances 180 — — pF
(12)
fPASSBAND CC D Pass band — 0.01 — 0.333 * kHz
fADCD_S
δRIPPLE CC D Pass band ripple(13) 0.333 * fADCD_S –1 — 1 %
Frolloff CC D Stop band [0.5 * fADCD_S, 40 — — dB
attenuation 1.0 * fADCD_S]
[1.0 * fADCD_S, 45 — —
1.5 * fADCD_S]
[1.5 * fADCD_S, 50 — —
2.0 * fADCD_S]
[2.0 * fADCD_S, 55 — —
2.5 * fADCD_S]
[2.5 * fADCD_S, fADCD_M/2] 60 — —
54/112 DocID027866 Rev 5


Value
Min Typ Max
δGROUP CC D Group delay Within pass band – Tclk is — — — —

fADCD_M / 2
OSR = 24 — — 238.5 Tclk
OSR = 28 — — 278
OSR = 32 — — 317.5
OSR = 36 — — 357
OSR = 40 — — 396.5
OSR = 44 — — 436
OSR = 48 — — 475.5
OSR = 56 — — 554.5
OSR = 64 — — 633.5
OSR = 72 — — 712.5
OSR = 75 — — 699
OSR = 80 — — 791.5
OSR = 88 — — 870.5
OSR = 96 — — 949.5
OSR = 112 — — 1107.5
OSR = 128 — — 1265.5
OSR = 144 — — 1423.5
OSR = 160 — — 1581.5
OSR = 176 — — 1739.5
OSR = 192 — — 1897.5
OSR = 224 — — 2213.5
OSR = 256 — — 2529.5
Distortion within pass band –0.5/ — +0.5/ —
fADCD fADCD_S
_S
fHIGH CC D High pass filter 3dB Enabled — 10e-5* — —

frequency fADCD_S
tSTARTUP CC D Start-up time from — — — 100 µs
power down state
tLATENCY CC D Latency between HPF = ON — — δGROUP + —
input data and fADCD_S
converted data
HPF = OFF — — δGROUP —
when input mux
does not change
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Value
Min Typ Max
tSETTLING CC D Settling time after Analog inputs are muxed — — 2*δGROUP + —

mux change HPF = ON 3*fADCD_S
HPF = OFF — — 2*δGROUP + —
2*fADCD_S
tODRECOVERY CC D Overdrive recovery After input comes within — — 2*δGROUP + —
time range from saturation fADCD_S
HPF = ON
HPF = OFF — — 2*δGROUP —
CS_D CC D S/D ADC sampling GAIN = 1, 2, 4, 8 — — 75*GAIN fF
capacitance after
D GAIN = 16 — — 600 fF
sampling switch(14)
IBIAS CC D Bias consumption At least 1 ADCD enabled — — 3.5 mA
IADV_D CC P VDD_HV_ADV power S/D ADC Dynamic — — 3.5 mA
supply current consumption
(single S/D ADC)
IADCS/D_REFH CC T S/D ADC Reference Dynamic consumption — — 3.5 µA
High Current (Conversion)
T Static consumption (Power — — +8
down)
2. For input voltage above the maximum and below the clamp voltage of the input pad, there is no latch-up concern, and the
signal will only be ‘clipped’.
3. VINP is the input voltage applied to the positive terminal of the SDADC.
4. VINM is the input voltage applied to the negative terminal of the SDADC.
5. Maximum input of 166.67 kHz supported with reduced accuracy. See SNR specifications.
6. When using a GAIN setting of 16, the conversion result will always have a value of zero in the least significant bit. This
gives an effective resolution of 15 bits.
7. Offset and gain error due to temperature drift can occur in either direction (+/-) for each of the SDADCs on the device.
8. Calibration of gain is possible when gain = 1.
Offset Calibration should be done with respect to 0.5*VDD_HV_ADR for differential mode and single ended mode with
negative input=0.5*VDD_HV_ADR.
Offset Calibration should be done with respect to 0 for "single ended mode with negative input=0".
Both offset and Gain Calibration is guaranteed for ±5% variation of VDD_HV_ADR, ±10% variation of VDD_HV_ADV, and ± 50
°C temperature variation.
9. Conversion offset error must be divided by the applied gain factor (1, 2, 4, 8, or 16) to obtain the actual input referred offset
error.
10. This parameter is guaranteed by bench validation with a small sample of typical devices, and tested in production to a
value of 6 dB less.
11. Impedance given at fADCD_M = 16 MHz. Impedance is inversely proportional to frequency:
ZDIFF(fADCD_M) = 16 MHz/fADCD_M * ZDIFF
ZCM(fADCD_M) = 16 MHz/fADCD_M * ZCM
12. SNR values guaranteed only if external noise on the ADC input pin is attenuated by the required SNR value in the
frequency range of fADCD_M – fADCD_S to fADCD_M + fADCD_S, where fADCD_M is the input sampling frequency, and fADCD_S
is the output sample frequency. A proper external input filter should be used to remove any interfering signals in this
frequency range.
13. The ±1% passband ripple specification is equivalent to 20 * log10 (0.99) = 0.087 dB.
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14. This capacitance does not include pin capacitance, that can be considered together with external capacitance, before
sampling switch.
3.13 Temperature sensor

The following table describes the temperature sensor electrical characteristics.
Table 27. Temperature sensor electrical characteristics

Value
Min Typ Max
— CC — Temperature monitoring range — –40 — 150 °C

TSENS CC P Sensitivity — — 5.18 — mV/°C
TACC CC P Accuracy TJ < 150 °C –3 — 3 °C
ITEMP_SENS CC C VDD_HV_ADV power supply — — — 700 µA
current
3.14 LVDS Fast Asynchronous Serial Transmission (LFAST) pad

electrical characteristics
The LFAST pad electrical characteristics apply to both the SIPI and high-speed debug serial
interfaces on the device. The same LVDS pad is used for the Microsecond Channel (MSC)
and DSPI LVDS interfaces, with different characteristics given in the following tables.
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3.14.1 LFAST interface timing diagrams
Figure 14. LFAST and MSC/DSPI LVDS timing definition
Signal excursions above this level NOT allowed

1743 mV
Max. common mode input at RX

1600 mV
|ΔVOD|
Max Differential Voltage =
285 mV p-p (LFAST)
400 mV p-p (MSC/DSPI)
Minimum Data Bit Time

Opening =
0.55 * T (LFAST)
0.50 * T (MSC/DSPI)
“No-Go” Area VOS = 1.2 V +/- 10%
TX common mode
|ΔVOD|
Min Differential Voltage =
100 mV p-p (LFAST)
150 mV p-p (MSC/DSPI)
VICOM
|ΔPEREYE |ΔPEREYE
Data Bit Period
T = 1 /FDATA
Min. common mode input at RX

150 mV
0V
Signal excursions below this level NOT allowed
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Figure 15. Power-down exit time
lfast_pwr_down
tPD2NM_TX
Differential TX
Data Lines pad_p/pad_n Data Valid
Figure 16. Rise/fall time
VIH
Differential TX 90%
Data Lines
10%
pad_p/pad_n VIL
tTR
tTR
3.14.2 LFAST and MSC/DSPI LVDS interface electrical characteristics

The following table contains the electrical characteristics for the LFAST interface.
Table 28. LVDS pad startup and receiver electrical characteristics(1)(2)

Value
Min Typ Max
STARTUP(3),(4)
tSTRT_BIAS CC T Bias current reference startup — — 0.5 4 µs
time(5)
tPD2NM_TX CC T Transmitter startup time (power — — 0.4 2.75 µs
down to normal mode)(6)
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Table 28. LVDS pad startup and receiver electrical characteristics(1)(2) (continued)
Value
Min Typ Max
tSM2NM_TX CC T Transmitter startup time (sleep Not applicable to the — 0.2 0.5 µs
mode to normal mode)(7) MSC/DSPI LVDS
pad
tPD2NM_RX CC T Receiver startup time (power down — — 20 40 ns
to normal mode)(8)
tPD2SM_RX CC T Receiver startup time (power down Not applicable to the — 20 50 ns
to sleep mode)(9) MSC/DSPI LVDS
pad
ILVDS_BIAS CC T LVDS bias current consumption Tx or Rx enabled — — 0.95 mA
TRANSMISSION LINE CHARACTERISTICS (PCB Track)
Z0 SR D Transmission line characteristic — 47.5 50 52.5 Ω
impedance
ZDIFF SR D Transmission line differential — 95 100 105 Ω
impedance
RECEIVER
VICOM SR T Common mode voltage — 0.15(10) — 1.6(11) V
|ΔVI| SR P Differential input voltage(12) — 100 — — mV
VHYS CC C Input hysteresis — 25 — — mV
RIN CC D Terminating resistance VDD_HV_IO = 80 125 150 Ω
5.0 V ± 10%
D VDD_HV_IO = 80 115 150 Ω
3.3 V ± 10%
CIN CC D Differential input capacitance(13) — — 3.5 6.0 pF
ILVDS_RX CC T Receiver DC current consumption Enabled — — 0.5 mA
1. The LVDS pad startup and receiver electrical characteristics in this table apply to the LFAST LVDS pad, and the MSC/DSPI
LVDS pad except where noted in the conditions.
2. All LVDS pad electrical characteristics are valid from –40 °C to 150 °C.
3. All startup times are defined after a 2 peripheral bridge clock delay from writing to the corresponding enable bit in the LVDS
control registers (LCR) of the LFAST and module. The value of the LCR bits for the LFAST/HSD modules don’t take effect
until the corresponding SIUL2 MSCR ODC bits are set to LFAST LVDS mode. Startup times for MSC/DSPI LVDS are
defined after 2 peripheral bridge clock delay after selecting MSC/DSPI LVDS in the corresponding SIUL2 MSCR ODC field.
4. Startup times are valid for the maximum external loads CL defined in both the LFAST/HSD and MSC/DSPI transmitter
electrical characteristic tables.
5. Bias startup time is defined as the time taken by the current reference block to reach the settling bias current after being
enabled.
6. Total transmitter startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_TX + 2 peripheral bridge clock
periods.
7. Total transmitter startup time from sleep mode to normal mode is tSM2NM_TX + 2 peripheral bridge clock periods. Bias block
remains enabled in sleep mode.
8. Total receiver startup time from power down to normal mode is tSTRT_BIAS + tPD2NM_RX + 2 peripheral bridge clock periods.
9. Total receiver startup time from power down to sleep mode is tPD2SM_RX + 2 peripheral bridge clock periods. Bias block
remains enabled in sleep mode.
10. Absolute min = 0.15 V – (285 mV/2) = 0 V
11. Absolute max = 1.6 V + (285 mV/2) = 1.743 V
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12. The LXRXOP[0] bit in the LFAST LVDS Control Register (LCR) must be set to one to ensure proper LFAST receive timing.
13. Total internal capacitance including receiver and termination, co-bonded GPIO pads, and package contributions.
Table 29. LFAST transmitter electrical characteristics(1)(2)

Value
Min Typ Max
fDATA SR D Data rate — — — 320 Mbps

VOS CC P Common mode voltage — 1.08 — 1.32 V
|VOD| CC P Differential output voltage swing — 110 171 285 mV
(terminated)(3)(4)
tTR CC T Rise/Fall time (absolute value of the — 0.26 — 1.5 ns
differential output voltage
swing)(3),(4)
CL SR D External lumped differential load VDD_HV_IO = 4.5 V — — 9.0 pF
capacitance(3)
VDD_HV_IO = 3.0 V — — 8.5
ILVDS_TX CC T Transmitter DC current consumption Enabled — — 3.2 mA
1. The LFAST pad electrical characteristics are based on worst case internal capacitance values shown in Figure 17.
2. All LFAST LVDS pad electrical characteristics are valid from –40 °C to 150 °C.
3. Valid for maximum data rate fDATA. Value given is the capacitance on each terminal of the differential pair, as shown in
Figure 17.
4. Valid for maximum external load CL.
Table 30. MSC/DSPI LVDS transmitter electrical characteristics (1)(2)

Value
Min Typ Max
Data Rate
fDATA SR D Data rate — — — 80 Mbps
VOS CC P Common mode voltage — 1.08 — 1.32 V
|VOD| CC P Differential output voltage swing — 150 214 400 mV
(terminated)(3)(4)
tTR CC T Rise/Fall time (absolute value of the — 0.8 — 4.0 ns
differential output voltage swing)(3),(4)
CL SR D External lumped differential load VDD_HV_IO = 4.5 V — — 41 pF
capacitance(3)
VDD_HV_IO = 3.0 V — — 39
ILVDS_TX CC T Transmitter DC current consumption Enabled — — 4.0 mA
1. The MSC and DSPI LVDS pad electrical characteristics are based on the application circuit and typical worst case internal
capacitance values given in Figure 17.
2. All MSC and DSPI LVDS pad electrical characteristics are valid from –40 °C to 150 °C.
3. Valid for maximum data rate fDATA. Value given is the capacitance on each terminal of the differential pair, as shown in
Figure 17.
4. Valid for maximum external load CL.
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Figure 17. LVDS pad external load diagram
bond pad
GPIO Driver
CL
1pF
2.5pF
100Ω
terminator
LVDS Driver
bond pad
GPIO Driver
CL
1pF
2.5pF
Die Package PCB
3.15 Power management: PMC, POR/LVD, sequencing

The power management module monitors the different power supplies. It also generates the
internal supplies that are required for correct device functionality. The power management is
supplied by the VDD_HV_PMC supply, with voltage monitors ensuring safe state operation.
62/112 DocID027866 Rev 5

3.15.1 Power management integration

Refer to the integration scheme provided below to ensure correct functionality of the device.
Figure 18. Voltage regulator capacitance connection

CDECHV CDECBV
(regulator supply decoupling) (regulator supply decoupling)
VDD_HV_PMC
VDD_HV_IO_MAIN VDD_HV_IO VSS VDD_HV_PMC VSS
CDECREG4 (LV_COR)
VREF VDD_LV
VDD_LVn
CDECREG1 (LV_COR/LV_FLA)
Voltage
Regulator VDD_LV VSS
I DEVICE
CDECREG3 (LV_COR\LV_PLL)
VSS
VSS
DEVICE
VSS
VDD_LV
VSS VDD_LV
CDECREG2
(LV_COR)
CREG
(LV_COR)
The internal voltage regulator requires external capacitance (CREGn) to be connected to the
device in order to provide a stable low voltage digital supply to the device. Capacitances
should be placed on the board as near as possible to the associated pins. Care should also
be taken to limit the serial inductance of the board to less than 5 nH.
A decoupling capacitor must be placed between each VDD_LV supply pin and VSS ground
plane to ensure stable voltage. The capacitor should be placed as near as possible to the
VDD_LV supply pin.
3.15.2 Main voltage regulator electrical characteristics

The device implements an internal voltage regulator to generate the low voltage core supply
VDD_LV from the high voltage ballast supply VDD_BV_PMC. The regulator itself is supplied by
VDD_HV_PMC.
Note: Both HV supplies, VDD_HV_PMC and VDD_BV_PMC, are shorted with VDD_HV_IO supply at
package level.
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The following supplies are involved:

• HV—High voltage external power supply for voltage regulator module. It is shorted with
VDD_HV_IO.
• BV—High voltage external power supply for internal ballast module. It is shorted with
VDD_HV_IO.
• LV—Low voltage internal power supply for core, PLL and flash digital logic. This is
generated by the internal voltage regulator but provided outside to connect stability
capacitor. It is split into three further domains to ensure noise isolation between critical
LV modules within the device:
– LV_COR—Low voltage supply for the core. It is also used to provide supply for
PLL through double bonding.
– LV_FLA—Low voltage supply for code flash module. It is supplied with dedicated
ballast and shorted to LV_COR through double bonding.
– LV_PLL—Low voltage supply for PLL. It is shorted to LV_COR through double
bonding.
Table 31. Voltage regulator electrical characteristics

Value(2)
Symbol Parameter Conditions(1) Unit
Min Typ Max
CREG SR Internal voltage regulator stability — 1.1 2.2(3) 2.97 µF

external capacitance
RREG SR Stability capacitor equivalent serial Total resistance including 1 — 50 mΩ
resistance board track
CDECREGn SR Internal voltage regulator decoupling — 50 100 135 nF
external capacitance
RDECREGn SR Stability capacitor equivalent serial — 1 — 50 mΩ
resistance
CDECBV SR Decoupling capacitance(4) ballast VDD_HV_IO_MAIN/VSS pair — 4(3) — µF
CDECHV SR Decoupling capacitance regulator VDD_HV_IO_MAIN/VSS pair 10 100 — nF
supply
CDECFLA SR Decoupling capacitance for flash VDD_HV_FLA/VSS pair 65 100 — nF
supply
D
VMREG CC Main regulator output voltage Before trimming 1.19 1.26 1.33(5) V
CC After trimming 1.16 1.28 1.32(6)
IDDMREG SR Main regulator current provided to — — — 125 mA
VDD_LV domain
ΔIDDMREG SR Main regulator current variation 20 µs observation window –60 — 60 mA
IMREGINT(7) D Main regulator current consumption — — 1.5 3.0 mA
1. VDD = 5.0 V ± 10%, TA = –40 / 125 °C, unless otherwise specified.
3. Recommended X7R or X5R ceramic –50% / +35% variation across process, temperature, voltage and after aging.
4. This capacitance value is driven by the constraints of the external voltage regulator supplying the VDD_BV voltage. A typical
value is in the range of 470 nF.
5. At power-up condition before trimming at 27 °C, no load.
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6. Across the whole process, voltage and temperature range with full load.
7. By simulation.
3.15.3 Device voltage monitoring

Voltage monitoring thresholds are shown in the following figure.
Figure 19. Voltage monitor threshold definition
VDD_xxx
VLVD_290
tVDRELEASE tVDASSERT
LVD TRIGGER
(INTERNAL)
The LVDs for the device and their levels are given in the following table.
Table 32. Voltage monitor electrical characteristics(1)

Value(2)
Min Typ Max
VLVD270_C CC P HV supply low voltage Pre-trimming 2610 2760 2910 mV

monitoring
Trimmed(3) 2710 2760 2800 mV
VLVD290_C/IJ/F/IF CC P HV supply low voltage Pre-trimming 2660 2820 2980 mV
monitoring
Trimmed(3) 2890 2940 2990 mV
VLVD400_A/IM CC P HV supply low voltage Untrimmed(3) 3990 4230 4470 mV
monitoring
Trimmed(3) 4150 4230 4310 mV
VLVD108 CC P Core LV internal — 1080 — 1170 mV
supply low voltage
monitoring
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Table 32. Voltage monitor electrical characteristics(1) (continued)

Value(2)
Min Typ Max
tVDASSERT CC D Voltage detector — 0.1 — 2 µs

threshold crossing
assertion
tVDRELEASE CC D Voltage detector — 5 — 20 µs
threshold crossing
de-assertion
1. For VDD_LV levels, a maximum of 30 mV IR drop is incurred from the pin to all sinks on the die. For other LVD, the IR drop
is estimated by the multiplying the supply current by 0.5 Ω.
2. The threshold for all PORs and LVDs are defined when the output transits to 1, i.e., when the sense goes above the
reference.
3. Across process, temperature and voltage range.
3.15.4 Power up/down sequencing

The following table shows the constraints and relationships for the different power supplies.
Table 33. Device supply relation during power-up/power-down sequence

Supply 2(1)
VDD_LV VDD_HV_IO VDD_HV_ADV VDD_HV_ADR ALTREF(2)
VDD_LV
VDD_HV_IO
Supply 1(1)
VDD_HV_ADV
VDD_HV_ADR 5 mA
ALTREF 10 mA(3) 10 mA(3)
1. Grey cells: Supply 1 (row) can exceed Supply 2 (column), granted that external circuitry ensures current flowing from
supply1 is less than absolute maximum rating current value provided.
2. ALTREF are the alternate references for the ADC that can be used in place of the default reference (VDD_HV_ADR_*). It is
the SARB.ALTREF.
3. ADC performance is not guaranteed with ALTREFn above VDD_HV_IO/VDD_HV_ADV.
During power-up, all functional terminals are maintained into a known state as described in
the following table.
Table 34. Functional terminals state during power-up and reset

POWER-UP(2) RESET Default
TERMINAL(1) Comments
pad state pad state pad state(3)
PORST Strong pull- Weak pull-down Weak pull-down Power-on reset pad
down(4)
ESR0(5) Strong pull-down Strong pull-down Weak pull-up Functional reset pad
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Table 34. Functional terminals state during power-up and reset (continued)
POWER-UP(2) RESET Default
TERMINAL(1) Comments
pad state pad state pad state(3)
ESR1 High impedance Weak pull-down Weak pull-down —

(6) (6)
TEST_MODE Weak pull-down Weak pull-down Weak pull-down —
GPIO Weak pull-up(4) Weak pull-up Weak pull-up —

ANALOG High impedance High impedance High impedance —
ERROR High impedance High impedance High impedance —
TRST High impedance Weak pull-down Weak pull-down —
TCK High impedance Weak pull-down Weak pull-down —
TMS High impedance Weak pull-up Weak pull-up —
TDI High impedance Weak pull-up Weak pull-up —
TDO High impedance High impedance High impedance —
1. Refer to pinout information for terminal type.
2. POWER-UP state is guaranteed from VDD_HV_IO > 1.1 V and maintained until supply crosses the power-on reset threshold:
VPORUP_LV for LV supply, VPORUP_HV for high voltage supply.
3. Before software configuration.
4. Pull-down and pull-up strength are provided as part of Section 3.8.2, I/O output DC characteristics.
5. As opposed to ESR0, ESR1 is provided via normal GPIO and implements weak pull-up during power-up.
6. TESTMODE pull-down is implemented to prevent device to enter TESTMODE. It is recommended to connect TESTMODE
pin to VSS_HV_IO on the board.
3.16 Flash memory electrical characteristics

The flash array access time for reads is affected by the number of wait-states added to the
minimum time, which is one cycle.
Wait states are set in the RWSC field of the Platform Flash Configuration Register 1 (PFCR1)
to a value corresponding to the operating frequency of the flash memory controller and the
actual read access time of the flash memory controller. Higher operating frequencies require
non-zero settings for this field for proper flash operation.
Shown below are the maximum operating frequencies (fsys) for legal RWSC settings based
on specified access times at 150 °C:
Table 35. RWSC settings

Flash operating frequency range (MHz) RWSC
00 MHz < fsys < 20 MHz 0

Table 36 shows the estimated Program/Erase characteristics.
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Table 36. Flash memory program and erase specifications (pending silicon characterization) (1)
Value
Lifetime
Initial max
Symbol Characteristics(2) Typical max(5) Unit
Typ(3) C end of C
All
life(4) < 1 K < 100 K
25 °C(6) temp C
(7) cycles cycles
tdwprogram Double Word (64 bits) program 38 C 150 — — 94 500 C µs

time [Packaged part]
tpprogram Page (256 bits) program time 78 C 300 — — 214 1000 C µs
tpprogrameep Page (256 bits) program time 90 C 330 — — 250 1000 C µs
EEPROM (partition 2)
[Packaged part]
tqprogram Quad Page (1024 bits) program 274 C 1000 1500 — 802 2000 C µs
time
tqprogrameep Quad Page (1024 bits) program 315 C 1100 1650 P 925 2000 C µs
time EEPROM (partition 2)
[Packaged part]
t256kpperase 256 KB block pre-program and 1800 C 2400 3400 P 1980 15000 — C ms
erase time
t256kprogram 256 KB block program time 584 C 760 1140 P 650 17000 — C ms
t16kprogrameep Program 16 KB EEPROM 37 C 48 72 P 69 1000 C ms
(partition 1)
t16keraseeep Erase 16 KB EEPROM (partition 350 C 1200 1200 P 600 5000 C ms
1)
ttr Program rate(8) 2.34 C 3.04 4.56 C 2.60 — C s/MB
tpr Erase rate(8) 7.2 C 14.4 28.8 C 7.92 — C s/MB
tffprogram Full flash programming time(9) 4 C 16 24 P 5 26 — C s
tfferase Full flash erasing time(9) 12 C 24 30 P 15 40 — C s
tESRT Erase suspend request rate(10) 5.5 T — — — — — T ms
tPSRT Program suspend request 20 T — — — — — T µs
rate(10)
tPSUS Program suspend latency(11) — — — — — — 15 T µs
tESUS (11)
Erase suspend latency — — — — — — 30 T µs
tAIC0S Array Integrity Check Partition 0 20 T — — — — — — — ms
(1.5 MB, sequential)(12)
tAIC0P Array Integrity Check Partition 0 3.35 T — — — — — — — s
(1.5 MB, proprietary)(12)
tMR0S Margin Read Partition 0 (1.5 100 T — — — — — — — ms
MB, sequential)
tMR0P Margin Read Partition 0 (1.5 16.7 T — — — — — — — s
MB, proprietary)
1. Characteristics are valid both for DATA Flash and CODE Flash, unless specified in the characteristics column.
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2. Actual hardware programming times; this does not include software overhead.
3. Typical program and erase times assume nominal supply values and operation at 25 °C. All times are subject to change
pending device characterization.
4. Typical End of Life program and erase times represent the median performance and assume nominal supply values.
Typical End of Life program and erase values may be used for throughput calculations. These values are characteristic, but
not tested.
5. Lifetime maximum program & erase times apply across the voltages and temperatures and occur after the specified
number of program/erase cycles. These maximum values are characterized but not tested or guaranteed.
6. Initial factory condition: < 100 program/erase cycles, 20 °C < TJ < 30 °C junction temperature, and nominal (± 2%) supply
voltages. These values are verified at production testing.
7. Initial maximum “All temp” program and erase times provide guidance for time-out limits used in the factory and apply for
less than or equal to 100 program or erase cycles, –40 °C < TJ < 150 °C junction temperature, and nominal (± 2%) supply
voltages. These values are verified at production testing.
8. Rate computed based on 256K sectors.
9. Only code sectors, not including EEPROM.
10. Time between erase suspend resume and next erase suspend.
11. Timings guaranteed by design.
12. AIC is done using system clock, thus all timing is dependant on system frequency and number of wait states. Timing in the
table is calculated at 160 MHz.
Table 37. Flash memory module extended life specification(1)

Value
Min Typ Max
P/E16 CC C Number of — 100,000 — — P/E

program/erase cycles cycles
per block for 16 KB
EEPROM emulation (2)
P/E256 CC C Number of — 1000 100,000 — P/E
program/erase cycles cycles
per block for 256 KB
blocks(2)
Data retention CC C Minimum data retention Blocks with 0 – 10000 20 — — years
P/E cycles
Blocks with 10001– 10 — —
250000 P/E cycles.
Data Retention limited
to 2, in total, 16 KB
sectors within module 1
1. All stated module life data are preliminary targets, and subject to change pending silicon characterization.
2. Program and Erase supported for standard operating temperature range.
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3.17 AC specifications
3.17.1 Debug and calibration interface timing
3.17.1.1 JTAG interface timing
Table 38. JTAG pin AC electrical characteristics (1)(2)

Value
# Symbol C Characteristic Unit
Min Max
1 tJCYC CC D TCK cycle time 100 — ns

2 tJDC CC T TCK clock pulse width 40 60 %
3 tTCKRISE CC D TCK rise and fall times (40%–70%) — 3 ns
4 tTMSS, tTDIS CC D TMS, TDI data setup time 5 — ns
5 tTMSH, tTDIH CC D TMS, TDI data hold time 5 — ns
6 tTDOV CC D TCK low to TDO data valid — 16(3) ns
7 tTDOI CC D TCK low to TDO data invalid 0 — ns
8 tTDOHZ CC D TCK low to TDO high impedance — 15 ns
9 tJCMPPW CC D JCOMP assertion time 100 — ns
10 tJCMPS CC D JCOMP setup time to TCK low 40 — ns
11 tBSDV CC D TCK falling edge to output valid — 600(4) ns
12 tBSDVZ CC D TCK falling edge to output valid out of high — 600 ns
impedance
13 tBSDHZ CC D TCK falling edge to output high impedance — 600 ns
14 tBSDST CC D Boundary scan input valid to TCK rising edge 15 — ns
15 tBSDHT CC D TCK rising edge to boundary scan input invalid 15 — ns
1. These specifications apply to JTAG boundary scan only. See Table 39 for functional specifications.
2. JTAG timing specified at VDD_HV_IO_JTAG = 4.0 V to 5.5 V, and maximum loading per pad type as specified in the I/O
section of the datasheet.
3. Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.
4. Applies to all pins, limited by pad slew rate. Refer to IO delay and transition specification and add 20 ns for JTAG delay.
70/112 DocID027866 Rev 5

Figure 20. JTAG test clock input timing
TCK
2
3 2
1 3
Figure 21. JTAG test access port timing
TCK
TMS, TDI
7 8
TDO
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Figure 22. JTAG JCOMP timing
TCK
10
JCOMP
72/112 DocID027866 Rev 5

Figure 23. JTAG boundary scan timing
TCK
11 13
Output
Signals
12
Output
Signals
14
15
Input
Signals
3.17.1.2 Nexus interface timing
Table 39. Nexus debug port timing(1)

Value
Min Max
7 tEVTIPW CC D EVTI pulse width 4 — tCYC(2)

8 tEVTOPW CC D EVTO pulse width 40 — ns
9 tTCYC CC D TCK cycle time 2(3),(4) — tCYC(2)
9 tTCYC CC D Absolute minimum TCK cycle time(5) (TDO/TDOC sampled 40(6) — ns
on posedge of TCK)
Absolute minimum TCK cycle time(7) (TDO/TDOC sampled 20(6) —
on negedge of TCK)
11(8) tNTDIS CC D TDI/TDIC data setup time 5 — ns
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Table 39. Nexus debug port timing(1) (continued)

Value
Min Max
12 tNTDIH CC D TDI/TDIC data hold time 5 — ns

13(9) tNTMSS CC D TMS/TMSC data setup time 5 — ns
14 tNTMSH CC D TMS/TMSC data hold time 5 — ns
(10) (11)
15 — CC D TDO/TDOC propagation delay from falling edge of TCK — 16 ns
16 — CC D TDO/TDOC hold time with respect to TCK falling edge 2.25 — ns
(minimum TDO/TDOC propagation delay)
1. Nexus timing specified at VDD_HV_IO_JTAG = 4.0 V to 5.5 V, and maximum loading per pad type as specified in the I/O
section of the datasheet.
2. tCYC is system clock period.
3. Achieving the absolute minimum TCK cycle time may require a maximum clock speed (system frequency / 8) that is less
than the maximum functional capability of the design (system frequency / 4) depending on the actual peripheral frequency
being used. To ensure proper operation TCK frequency should be set to the peripheral frequency divided by a number
greater than or equal to that specified here.
4. This is a functionally allowable feature. However, it may be limited by the maximum frequency specified by the Absolute
minimum TCK period specification.
5. This value is TDO/TDOC propagation time 36 ns + 4 ns setup time to sampling edge.
6. This may require a maximum clock speed (system frequency / 8) that is less than the maximum functional capability of the
design (system frequency / 4) depending on the actual system frequency being used.
7. This value is TDO/TDOC propagation time 16 ns + 4 ns setup time to sampling edge.
8. TDIC represents the TDI bit frame of the scan packet in compact JTAG 2-wire mode.
9. TMSC represents the TMS bit frame of the scan packet in compact JTAG 2-wire mode.
10. TDOC represents the TDO bit frame of the scan packet in compact JTAG 2-wire mode.
11. Timing includes TCK pad delay, clock tree delay, logic delay and TDO/TDOC output pad delay.
Figure 24. Nexus event trigger and test clock timings
TCK
EVTI
EVTO 9
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Figure 25. Nexus TDI/TDIC, TMS/TMSC, TDO/TDOC timing
TCK
11
13
12
14
TMS/TMSC,
TDI/TDIC
15
16
TDO/TDOC
3.17.2 DSPI timing with CMOS and LVDS(a) pads

DSPI channel frequency support is shown in Table 40. Timing specifications are shown in
Table 41, Table 42 and Table 43.
Table 40. DSPI channel frequency support

Max usable
DSPI use mode
frequency (MHz)(1),(2)
CMOS (Master mode) Full duplex – Classic timing (Table 41) 17

Full duplex – Modified timing (Table 42) 30
Output only mode (SCK/SOUT/PCS) (Table 41 and Table 42) 30
Output only mode TSB mode (SCK/SOUT/PCS) (Table 44) 30
LVDS (Master mode) Output only mode TSB mode (SCK/SOUT/PCS) (Table 43) 40
1. Maximum usable frequency can be achieved if used with fastest configuration of the highest drive pads.
a. DSPI in TSB mode with LVDS pads can be used to implement Micro Second Channel bus protocol.
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2. Maximum usable frequency does not take into account external device propagation delay.
3.17.2.1 DSPI master mode full duplex timing with CMOS and LVDS pads
3.17.2.1.1 DSPI CMOS Master Mode – Classic Timing
Table 41. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or
1(1)
Condition Value(2)
Pad drive(3) Load (CL) Min Max
1 tSCK CC D SCK cycle time SCK drive strength

Very strong 25 pF 33.0 — ns
Strong 50 pF 80.0 —
Medium 50 pF 200.0 —
2 tCSC CC D PCS to SCK delay SCK and PCS drive strength
Very strong 25 pF (N(4) × tSYS(5)) – — ns
16
Strong 50 pF (N(4) × tSYS(5)) – —
16
Medium 50 pF (N(4) × tSYS(5)) – —
26
PCS medium PCS = 50 pF (N(4) × tSYS(5)) – —
and SCK strong SCK = 50 pF 38
3 tASC CC D After SCK delay SCK and PCS drive strength
Very strong PCS = 0 pF (M(6) × tSYS(5)) – — ns
SCK = 50 pF 35
Strong PCS = 0 pF (M(6) × tSYS(5)) – —
SCK = 50 pF 35
Medium PCS = 0 pF (M(6) × tSYS(5)) – —
SCK = 50 pF 35
PCS medium PCS = 0 pF (M(6) × tSYS(5)) – —
and SCK strong SCK = 50 pF 35
4 tSDC CC D SCK duty cycle(7) SCK drive strength
Very strong 0 pF 1/ t –2 1/
2 SCK 2tSCK +2 ns
Strong 0 pF 1/ t –2 1/
2 SCK 2tSCK +2
1/ t 1/
Medium 0 pF 2 SCK –5 2tSCK +5
PCS strobe timing
5 tPCSC CC D PCSx to PCSS PCS and PCSS drive strength
time(8)
Strong 25 pF 12.0 — ns
6 tPASC CC D PCSS to PCSx PCS and PCSS drive strength
time(8)
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Table 41. DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0, CPHA = 0 or
1(1) (continued)
Condition Value(2)
SIN setup time

7 tSUI CC D SIN setup time to SCK drive strength
SCK(9)
SIN hold time
8 tHI CC D SIN hold time from SCK drive strength
SCK(9)
Very strong 0 pF –1.0 — ns
Strong 0 pF –1.0 —
Medium 0 pF –1.0 —
SOUT data valid time (after SCK edge)
9 tSUO CC D SOUT data valid SOUT and SCK drive strength
time from SCK(10)
Very strong 25 pF — 7.0 ns
Strong 50 pF — 9.0
Medium 50 pF — 25.0
SOUT data hold time (after SCK edge)
10 tHO CC D SOUT data hold SOUT and SCK drive strength
time after SCK(10)
1. All output timing is worst case and includes the mismatching of rise and fall times of the output pads.
2. All timing values for output signals in this table are measured to 50% of the output voltage.
3. Timing is guaranteed to same drive capabilities for all signals, mixing of pad drives may reduce operating speeds and may
cause incorrect operation.
4. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable
using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous
SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same
edge of DSPI_CLKn).
5. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 80 MHz (min
tSYS = 10 ns).
6. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable
using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK
clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge
of DSPI_CLKn).
7. tSDC is only valid for even divide ratios. For odd divide ratios the fundamental duty cycle is not 50:50. For these odd divide
ratios cases, the absolute spec number is applied as jitter/uncertainty to the nominal high time and low time.
8. PCSx and PCSS using same pad configuration.
9. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds.
10. SOUT Data Valid and Data hold are independent of load capacitance if SCK and SOUT load capacitances are the same
value.
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Figure 26. DSPI CMOS master mode – classic timing, CPHA = 0
tCSC tASC
PCSx
tSDC tSCK
SCK Output
(CPOL = 0)
tSDC
SCK Output
(CPOL = 1)
tSUI
tHI
SIN First Data Data Last Data
tSUO tHO
SOUT First Data Data Last Data
Figure 27. DSPI CMOS master mode – classic timing, CPHA = 1
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
tSUI tHI
tSUO tHO
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Figure 28. DSPI PCS strobe (PCSS) timing (master mode)
tPCSC tPASC
PCSS
PCSx
3.17.2.1.2 DSPI CMOS Master Mode – Modified Timing
Table 42. DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1, CPHA = 0
or 1(1)
Condition Value(2)

2 tCSC CC D PCS to SCK delay SCK and PCS drive strength
Very strong 25 pF (N(4) × tSYS(5)) – 16 — ns
Strong 50 pF (N(4) × tSYS(5)) – 16 —
Medium 50 pF (N(4) × tSYS(5)) – 26 —
PCS medium PCS = 50 pF (N(4) × tSYS(5)) – 38 —
and SCK SCK = 50 pF
strong
3 tASC CC D After SCK delay SCK and PCS drive strength
Very strong PCS = 0 pF (M(6) × tSYS(5)) – — ns
SCK = 50 pF 35
Strong PCS = 0 pF (M(6) × tSYS(5)) – —
SCK = 50 pF 35
Medium PCS = 0 pF (M(6) × tSYS(5)) – —
SCK = 50 pF 35
PCS medium PCS = 0 pF (M(6) × tSYS(5)) – —
and SCK SCK = 50 pF 35
strong
1/ t 1/ t
Very strong 0 pF 2 SCK –2 2 SCK +2 ns
Strong 0 pF 1/ t –2 1/ t +2
2 SCK 2 SCK
1/ t 1/ t
Medium 0 pF 2 SCK –5 2 SCK +5
PCS strobe timing
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or 1(1) (continued)
Condition Value(2)
5 tPCSC CC D PCSx to PCSS PCS and PCSS drive strength

time(8)
6 tPASC CC D PCSS to PCSx PCS and PCSS drive strength
time(8)
SIN setup time
7 tSUI CC D SIN setup time to SCK drive strength
SCK
Very strong 25 pF 25 – — ns
CPHA = 0(9)
(P(10) × tSYS(5))
Strong 50 pF 31 – —
(P(10) × tSYS(5))
Medium 50 pF 52 – —
(P(10) × tSYS(5))
SIN setup time to SCK drive strength
SCK
CPHA = 1(9)
SIN hold time
8 tHI CC D SIN hold time from SCK drive strength
SCK
Very strong 0 pF – — ns
CPHA = 09
1 + (P(9) × tSYS(4))
Strong 0 pF – —
1 + (P(9) × tSYS(4))
Medium 0 pF – —
1 + (P(9) × tSYS(4))
SIN hold time from SCK drive strength
SCK
CPHA = 19
80/112 DocID027866 Rev 5

or 1(1) (continued)
Condition Value(2)
9 tSUO CC D SOUT data valid SOUT and SCK drive strength

time from SCK
Very strong 25 pF — 7.0 + tSYS(5) ns
CPHA = 0(10)
Strong 50 pF — 9.0 + tSYS(5)
Medium 50 pF — 25.0 + tSYS(
5)
SOUT data valid SOUT and SCK drive strength

time from SCK
CPHA = 1(10)
Strong 50 pF — 9.0
Medium 50 pF — 25.0
10 tHO CC D SOUT data hold SOUT and SCK drive strength
time after SCK
Very strong 25 pF –7.7 + tSYS(5) — ns
CPHA = 0(11)
Strong 50 pF –11.0 + tSYS(5) —
Medium 50 pF –15.0 + tSYS (5) —
SOUT data hold SOUT and SCK drive strength
time after SCK
CPHA = 1(11)
4. N is the number of clock cycles added to time between PCS assertion and SCK assertion and is software programmable
using DSPI_CTARx[PSSCK] and DSPI_CTARx[CSSCK]. The minimum value is 2 cycles unless TSB mode or Continuous
SCK clock mode is selected, in which case, N is automatically set to 0 clock cycles (PCS and SCK are driven by the same
edge of DSPI_CLKn).
5. tSYS is the period of DSPI_CLKn clock, the input clock to the DSPI module. Maximum frequency is 80 MHz (min
tSYS = 10 ns).
6. M is the number of clock cycles added to time between SCK negation and PCS negation and is software programmable
using DSPI_CTARx[PASC] and DSPI_CTARx[ASC]. The minimum value is 2 cycles unless TSB mode or Continuous SCK
clock mode is selected, in which case, M is automatically set to 0 clock cycles (PCS and SCK are driven by the same edge
of DSPI_CLKn).
8. PCSx and PCSS using same pad configuration.
9. Input timing assumes an input slew rate of 1 ns (10% – 90%) and uses TTL / Automotive voltage thresholds.
10. P is the number of clock cycles added to delay the DSPI input sample point and is software programmable using
DSPI_MCR[SMPL_PT]. The value must be 0, 1 or 2. If the baud rate divide ratio is /2 or /3, this value is automatically set to
1.
value.
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Figure 29. DSPI CMOS master mode – modified timing, CPHA = 0
tCSC tASC
PCSx
tSDC tSCK
SCK Output
(CPOL = 0)
tSDC
SCK Output
(CPOL = 1)
tSUI
tHI
tSUO tHO
Figure 30. DSPI CMOS master mode – modified timing, CPHA = 1
PCSx
SCK Output
(CPOL = 0)
SCK Output
(CPOL = 1)
tSUI tHI tHI
tSUO tHO
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Figure 31. DSPI PCS strobe (PCSS) timing (master mode)
tPCSC tPASC
PCSS
PCSx
3.17.2.1.3 DSPI Master Mode – Output Only
Table 43. DSPI LVDS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1,
CPOL = 0 or 1, continuous SCK clock(1)(2)
Condition Value
Pad drive Load Min Max
1 tSCK CC D SCK cycle time LVDS 15 pF 25.0 — ns

to 50 pF
differential
2 tCSV CC D PCS valid after Very strong 25 pF — 6.0 ns
SCK(3)
Strong 50 pF — 10.5 ns
(SCK with 50 pF
differential load cap.)
3 tCSH CC D PCS hold after Very strong 0 pF –4.0 — ns
SCK(3)
Strong 0 pF –4.0 — ns
(SCK with 50 pF
differential load cap.)
1/ – 2 1/2tSCK + 2
4 tSDC CC D SCK duty cycle LVDS 15 pF 2tSCK ns
(SCK with 50 pF to 50 pF
differential load cap.) differential
5 tSUO CC D SOUT data valid time SOUT and SCK drive strength
from SCK(4)
LVDS 15 pF — 8.0 ns
to 50 pF
differential
6 tHO CC D SOUT data hold time SOUT and SCK drive strength
after SCK(4)
LVDS 15 pF 0.0 — ns
to 50 pF
differential
1. All DSPI timing specifications apply to pins when using LVDS pads for SCK and SOUT and CMOS pad for PCS with pad
driver strength as defined. Timing may degrade for weaker output drivers.
2. TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.
3. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This
timing value is due to pad delays and signal propagation delays.
value.
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Table 44. DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or ITSB = 1,
CPOL = 0 or 1, continuous SCK clock(1)(2)
Condition Value(3)

Medium 50 pF 200.0 — ns
2 tCSV (5)
CC D PCS valid after SCK SCK and PCS drive strength
Very strong 25 pF 16 — ns
Strong 50 pF 16 — ns
Medium 50 pF 26 — ns
PCS medium PCS = 50 pF 38 — ns
and SCK SCK = 50 pF
strong
3 tCSH CC D PCS hold after SCK(5) SCK and PCS drive strength
Very strong PCS = 0 pF –14 — ns
SCK = 50 pF
Strong PCS = 0 pF –14 — ns
SCK = 50 pF
Medium PCS = 0 pF –33 — ns
SCK = 50 pF
PCS medium PCS = 0 pF –35 — ns
and SCK SCK = 50 pF
strong
1/ 1/
Very strong 0 pF 2tSCK –2 2tSCK + 2 ns
1 1
Strong 0 pF /2tSCK – 2 /2tSCK + 2 ns
1 1
Medium 0 pF /2tSCK – 5 /2tSCK + 5 ns
9 tSUO CC D SOUT data valid time SOUT and SCK drive strength
from SCK
CPHA = 1(7)
Strong 50 pF — 9.0 ns
Medium 50 pF — 25.0 ns
10 tHO CC D SOUT data hold time SOUT and SCK drive strength
after SCK
CPHA = 1(7)
Strong 50 pF –11.0 — ns
Medium 50 pF –15.0 — ns
1. TSB = 1 or ITSB = 1 automatically selects MTFE = 1 and CPHA = 1.
84/112 DocID027866 Rev 5

5. With TSB mode or Continuous SCK clock mode selected, PCS and SCK are driven by the same edge of DSPI_CLKn. This
timing value is due to pad delays and signal propagation delays.
value.
Figure 32. DSPI LVDS and CMOS master timing – output only – modified transfer
format MTFE = 1, CHPA = 1
PCSx
tCSV
tSDC tSCK tCSH
SCK Output
(CPOL = 0)
tSUO tHO
3.17.2.2 Slave Mode timing
Table 45. DSPI CMOS Slave timing - Modified Transfer Format (MTFE = 0/1)(1)
Condition
# Symbol C Characteristic Min Max Unit
Pad Drive Load
1 tSCK CC D SCK Cycle Time(2) — — 62 — ns

2 tCSC (2)
SR D SS to SCK Delay — — 16 — ns
3 tASC SR D SCK to SS Delay(2) — — 16 — ns
4 tSDC CC D SCK Duty Cycle(2) — — 30 — ns
5 tA (2),(3),(4)
CC D Slave Access Time Very Strong 25 pF — 50 ns
(SS active to SOUT driven) Strong 50 pF — 50 ns
Medium 50 pF — 60 ns
6 tDIS CC D Slave SOUT Disable Very Strong 25 pF 5 22 ns
Time(2),(3),(4)
Strong 50 pF 5 28 ns
(SS inactive to SOUT High-Z
or invalid) Medium 50 pF 5 54 ns
9 tSUI CC D Data Setup Time for Inputs(2) — — 10 — ns

10 tHI (2)
CC D Data Hold Time for Inputs — — 10 — ns
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Table 45. DSPI CMOS Slave timing - Modified Transfer Format (MTFE = 0/1)(1) (continued)
Condition
# Symbol C Characteristic Min Max Unit
Pad Drive Load
11 tSUO CC D SOUT Valid Time(2),(3),(4) Very Strong 25 pF — 30 ns

(after SCK edge) Strong 50 pF — 30 ns
Medium 50 pF — 55 ns
(2),(3),(4)
12 tHO CC D SOUT Hold Time Very Strong 25 pF 2.5 — ns
(after SCK edge) Strong 50 pF 2.5 — ns
Medium 50 pF 2.5 — ns
1. DSPI slave operation is only supported for a single master and single slave on the device. Timing is valid for that case only.
2. Input timing assumes an input slew rate of 1 ns (10% - 90%) and uses TTL / Automotive voltage thresholds.
3. All timing values for output signals in this table, are measured to 50% of the output voltage.
Figure 33. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) —
CPHA = 0
tASC
tCSC
SS
tSCK
SCK Input tSDC

(CPOL=0)
tSDC
SCK Input
(CPOL=1)
tSUO tHO
tA tDIS
tSUI tHI
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Figure 34. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) —
CPHA = 1
SS
SCK Input
(CPOL=0)
SCK Input
(CPOL=1)
tSUO
tA tDIS
tHO

tHI
tSUI
3.17.3 FEC timing
3.17.3.1 RMII serial management channel timing (MDIO and MDC)

The FEC functions correctly with a maximum MDC frequency of 2.5 MHz.
Table 46. RMII serial management channel timing(1)

Value
Symbol C Characteristic Unit
Min Max
M10 CC D MDC falling edge to MDIO output invalid 0 — ns

(minimum propagation delay)
M11 CC D MDC falling edge to MDIO output valid — 25 ns
(maximum propagation delay)
M12 CC D MDIO (input) to MDC rising edge setup 10 — ns
M13 CC D MDIO (input) to MDC rising edge hold 0 — ns
M14 CC D MDC pulse width high 40% 60% MDC period
M15 CC D MDC pulse width low 40% 60% MDC period
1. All timing specifications are referenced from MDC = 1.4 V (TTL levels) to the valid input and output levels, 0.8 V and 2.0 V
(TTL levels). For 5 V operation, timing is referenced from MDC = 50% to 2.2 V/3.5 V input and output levels.
DocID027866 Rev 5 87/112

111
Figure 35. RMII serial management channel timing diagram
M14 M15
MDC (output)
M10
MDIO (output)
M11
MDIO (input)
M12
M13
3.17.3.2 RMII receive signal timing (RXD[1:0], CRS_DV)

The receiver functions correctly up to a REF_CLK maximum frequency of 50 MHz +1%.
There is no minimum frequency requirement. The system clock frequency must be at least
equal to or greater than the RX_CLK frequency, which is half that of the REF_CLK frequency.
Table 47. RMII receive signal timing(1)

Value
Min Max
R1 CC D RXD[1:0], CRS_DV to REF_CLK setup 4 — ns

R2 CC D REF_CLK to RXD[1:0], CRS_DV hold 2 — ns
R3 CC D REF_CLK pulse width high 35% 65% REF_CLK period
R4 CC D REF_CLK pulse width low 35% 65% REF_CLK period
1. All timing specifications are referenced from REF_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V.
88/112 DocID027866 Rev 5

Figure 36. RMII receive signal timing diagram

R3
REF_CLK (input)
R4
RXD[1:0] (inputs)
CRS_DV
R1 R2
3.17.3.3 RMII transmit signal timing (TXD[1:0], TX_EN)

The transmitter functions correctly up to a REF_CLK maximum frequency of 50 MHz + 1%.
There is no minimum frequency requirement. The system clock frequency must be at least
equal to or greater than the TX_CLK frequency, which is half that of the REF_CLK frequency.
The transmit outputs (TXD[1:0], TX_EN) can be programmed to transition from either the
rising or falling edge of REF_CLK, and the timing is the same in either case. This options
allows the use of non-compliant RMII PHYs.
Table 48. RMII transmit signal timing(1)

Value
Min Max
R5 CC D REF_CLK to TXD[1:0], TX_EN invalid 2 — ns

R6 CC D REF_CLK to TXD[1:0], TX_EN valid — 16 ns
R7 CC D REF_CLK pulse width high 35% 65% REF_CLK period
R8 CC D REF_CLK pulse width low 35% 65% REF_CLK period
1. RMII timing is valid only up to a maximum of 150 °C junction temperature.
Figure 37. RMII transmit signal timing diagram
R7
REF_CLK (input)
R5
R8
TXD[1:0] (outputs)
TX_EN
R6
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3.17.4 UART timing

UART channel frequency support is shown in the following table.
Table 49. UART frequency support

LINFlexD clock
Max usable frequency
frequency LIN_CLK Oversampling rate Voting scheme
(Mbaud)
(MHz)
80 16 3:1 majority voting 5

8 10
6 Limited voting on one 13.33
sample with configurable
5 16
sampling point
4 20
100 16 3:1 majority voting 6.25
8 12.5
6 Limited voting on one 16.67
sample with configurable
5 20
sampling point
4 25
3.17.5 GPIO delay timing

The GPIO delay timing specification is provided in the following table.
Table 50. GPIO delay timing

Value
Symbol C Parameter Unit
Min Max
IO_delay CC D Delay from MSCR bit update to pad function enable 5 25 ns
90/112 DocID027866 Rev 5

SPC572Lx Package characteristics
4 Package characteristics
4.1 ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
DocID027866 Rev 5 91/112

111
Package characteristics SPC572Lx
4.2 eTQFP80 case drawing

Figure 38. eTQFP80 – STMicroelectronics package mechanical drawing
MECHANICAL PACKAGE DRAWINGS
eTQFP80 BODY 10x10x1.0 mm

FOOT PRINT 1.0 mm EXPOSED PAD DOWN
PACKAGE CODE :A0R6
JEDEC/EIAJ REFERENCE NUMBER : JEDEC MS-026-ACE-HD
REFERENCE : 8384969
92/112 DocID027866 Rev 5

Table 51. eTQFP80 – STMicroelectronics package mechanical data

Dimensions
Symbol Millimeters Inches(1)
Min Typ Max Min Typ Max
q 0° 3.5° 7° 0° 3.5° 7°
q1 0° — — 0° — —
q2 10° 12° 14° 10° 12° 14°
q3 10° 12° 14° 10° 12° 14°
(2)
A — — 1.20 — — 0.047
A1(3) 0.05 — 0.15 0.002 — 0.006
A2(2) 0.95 1.00 1.05 0.037 0.039 0.041
(4) (5)
b 0.13 0.18 0.23 0.005 0.007 0.009
b1(4) 0.13 0.16 0.19 0.005 0.006 0.007
c(4) 0.09 — 0.20 0.004 — 0.008
(4)
c1 0.09 — 0.16 0.004 — 0.006
D(6) 12.00 BSC 0.472 BSC
(7) (8)
D1 10.00 BSC 0.394 BSC
D2(9) — — 5.83 — — 0.229
D3(10) 4.00 — — 0.157 — —
e 0.40 BSC 0.016 BSC
(6)
E 12.00 BSC 0.472 BSC
E1(7) (8) 10.00 BSC 0.394 BSC
(9)
E2 — — 5.83 — — 0.229
(10)
E3 4.00 — — 0.157 — —
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 REF 0.039 REF
(11)
N 80 3.149
R1 0.08 — — 0.003 — —
R2 0.08 — — 0.003 — —
S 0.20 — — 0.008 — —
aaa(12) 0.20 0.008
(12)
bbb 0.20 0.008
(12)
ccc 0.08 0.003
ddd(12) 0.07 0.003
1. Values in inches are converted from millimeters (mm) and rounded to three decimal digits.
2. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude
beyond that surface.
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111
3. A1 is defined as the distance from the seating plane to the lowest point on the package body.
4. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed
the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum
space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
5. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
6. To be determined at seating datum plane C.
7. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm.
8. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side.
D1 and E1 are maximum plastic body size dimensions including mold mismatch.
9. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located
(if present). It includes all metal protrusions from exposed pad itself. Type of exposed pad is variable depending on
leadframe pad design (T1, T2, T3). End user should verify D2 and E2 dimensions according to specific device application.
10. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of exposed pad which is guaranteed to
be free from resin flashes/bleeds, bordered by internal edge of inner groove.
11. “N” is the number of terminal positions for the specified body size.
12. Tolerance
94/112 DocID027866 Rev 5

4.3 eTQFP100 case drawing

Figure 39. eTQFP100 – STMicroelectronics package mechanical drawing
MECHANICAL PACKAGE DRAWINGS
eTQFP100 BODY 14x14x1.0 mm

FOOT PRINT 1.0 mm EXPOSED PAD DOWN
PACKAGE CODE :YE
JEDEC/EIAJ REFERENCE NUMBER : JEDEC MS-026-AED-HD
REFERENCE : 7357321
DocID027866 Rev 5 95/112

111
Table 52. eTQFP100 – STMicroelectronics package mechanical data

Dimensions
Symbol Millimeters Inches(1)
Min Typ Max Min Typ Max
q 0° 3.5° 7° 0° 3.5° 7°
q1 0° — — 0° — —
q2 10° 12° 14° 10° 12° 14°
q3 10° 12° 14° 10° 12° 14°
(2)
A — — 1.20 — — 0.047
A1 0.05 — 0.15 0.002 — 0.006
A2(2) 0.95 1.00 1.05 0.037 0.039 0.041
(3) (4)
b 0.17 0.22 0.27 0.007 0.009 0.011
b1(4) 0.175 0.20 0.23 0.007 0.008 0.009
c(4) 0.09 — 0.20 0.004 — 0.008
(4)
c1 0.09 — 0.16 0.004 — 0.006
D(5) 16.00 BSC 0.629 BSC
(6) (7)
D1 14.00 BSC 0.551 BSC
D2(8) — — 5.67 — — 0.223
D3(9) 4.00 — — 0.157 — —
e 0.50 BSC 0.019 BSC
(5)
E 16.00 BSC 0.629 BSC
E1(6) (7) 14.00 BSC 0.551 BSC
(8)
E2 — — 5.67 — — 0.223
(9)
E3 4.00 — — 0.157 — —
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 REF 0.039 REF
(10)
N 100 3.937
R1 0.08 — — 0.003 — —
R2 0.08 — — 0.003 — —
S 0.20 — — 0.008 — —
aaa(11) 0.15 0.006
(11)
bbb 0.20 0.008
(11)
ccc 0.05 0.002
ddd(11) 0.07 0.003
1. Values in inches are converted from millimeters (mm) and rounded to three decimal digits.
2. The optional exposed pad is generally coincident with the top or bottom side of the package and not allowed to protrude
beyond that surface.
96/112 DocID027866 Rev 5

3. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed
the maximum “b” dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum
space between protrusion and an adjacent lead is 0.07 mm for 0.4 mm and 0.5 mm pitch packages.
4. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.
5. To be determined at seating datum plane C.
6. The Top package body size may be smaller than the bottom package size by as much as 0.15 mm.
7. Dimensions D1 and E1 do not include mold flash or protrusions. Allowable mold flash or protrusions is “0.25 mm” per side.
D1 and E1 are maximum plastic body size dimensions including mold mismatch.
8. Dimensions D2 and E2 show the maximum exposed metal area on the package surface where the exposed pad is located
(if present). It includes all metal protrusions from exposed pad itself. Type of exposed pad is variable depending on
leadframe pad design (T1, T2, T3). End user should verify D2 and E2 dimensions according to specific device application.
9. Dimensions D3 and E3 show the minimum solderable area, defined as the portion of exposed pad which is guaranteed to
be free from resin flashes/bleeds, bordered by internal edge of inner groove.
10. “N” is the number of terminal positions for the specified body size.
11. Tolerance
4.4 Thermal characteristics

Table 53 and Table 54 describe the thermal characteristics of the device.
Table 53. Thermal characteristics for eTQFP80(1)

Symbol C Parameter Conditions Value Unit
RθJA CC D Junction-to-ambient, natural Four layer board—2s2p 29.6 °C/W

convection(2)
RθJMA CC D Junction-to-moving-air, ambient(2) At 200 ft./min., four layer 23.5 °C/W
board—2s2p
RθJB CC D Junction-to-board(3) Ring cold plate 9.6 °C/W
RθJCtop CC D Junction-to-case top(4) Cold plate 13.2 °C/W
RθJCbotttom CC D Junction-to-case bottom(5) Cold plate 1.0 °C/W
ΨJT CC D Junction-to-package top(6) Natural convection 0.4 °C/W
1. The values are based on simulation; actual data may vary in the given range. The specified characteristics are subject to
change per final device design and characterization. Junction temperature is a function of die size, on-chip power
dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power
dissipation of other components on the board, and board thermal resistance.
2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
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111
Table 54. Thermal characteristics for eTQFP100(1)

Symbol C Parameter Conditions Value Unit
RθJA CC D Junction-to-ambient, natural Four layer board—2s2p 27.9 °C/W

convection(2)
RθJMA CC D Junction-to-moving-air, ambient(2) At 200 ft./min., four layer 22.8 °C/W
board—2s2p
RθJB CC D Junction-to-board(3) Ring cold plate 11.3 °C/W
RθJCtop CC D Junction-to-case top(4) Cold plate 13.0 °C/W
(5)
RθJCbotttom CC D Junction-to-case bottom Cold plate 1.0 °C/W
ΨJT (6)
CC D Junction-to-package top Natural convection 0.4 °C/W
1. The values are based on simulation; actual data may vary in the given range. The specified characteristics are subject to
change per final device design and characterization. Junction temperature is a function of die size, on-chip power
dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power
dissipation of other components on the board, and board thermal resistance.
2. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.
3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
5. Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
4.4.1 General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, TJ, can be obtained from the equation:
Equation 1 TJ = TA + (RθJA * PD)

where:
TA = ambient temperature for the package (°C)
RθJA = junction-to-ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
The thermal resistance values used are based on the JEDEC JESD51 series of standards to
provide consistent values for estimations and comparisons. The difference between the
values determined for the single-layer (1s) board compared to a four-layer board that has two
signal layers, a power and a ground plane (2s2p), demonstrate that the effective thermal
resistance is not a constant. The thermal resistance depends on the:
• Construction of the application board (number of planes)
• Effective size of the board which cools the component
• Quality of the thermal and electrical connections to the planes
• Power dissipated by adjacent components
Connect all the ground and power balls to the respective planes with one via per ball. Using
fewer vias to connect the package to the planes reduces the thermal performance. Thinner
planes also reduce the thermal performance. When the clearance between the vias leave the
planes virtually disconnected, the thermal performance is also greatly reduced.
98/112 DocID027866 Rev 5

As a general rule, the value obtained on a single-layer board is within the normal range for
the tightly packed printed circuit board. The value obtained on a board with the internal planes
is usually within the normal range if the application board has:
• One oz. (35 micron nominal thickness) internal planes
• Components are well separated
• Overall power dissipation on the board is less than 0.02 W/cm2
The thermal performance of any component depends on the power dissipation of the
surrounding components. In addition, the ambient temperature varies widely within the
application. For many natural convection and especially closed box applications, the board
temperature at the perimeter (edge) of the package is approximately the same as the local
air temperature near the device. Specifying the local ambient conditions explicitly as the
board temperature provides a more precise description of the local ambient conditions that
determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following
equation:
Equation 2 TJ = TB + (RθJB * PD)

where:
TB = board temperature for the package perimeter (°C)
RθJB = junction-to-board thermal resistance (°C/W) per JESD51-8
When the heat loss from the package case to the air does not factor into the calculation, the
junction temperature is predictable if the application board is similar to the thermal test
condition, with the component soldered to a board with internal planes.
The thermal resistance is expressed as the sum of a junction-to-case thermal resistance plus
a case-to-ambient thermal resistance:
Equation 3 RθJA = RθJC + RθCA

where:
RθJA = junction-to-ambient thermal resistance (°C/W)
RθJC = junction-to-case thermal resistance (°C/W)
RθCA = case to ambient thermal resistance (°C/W)
RθJC is device related and is not affected by other factors. The thermal environment can be
controlled to change the case-to-ambient thermal resistance, RθCA. For example, change the
air flow around the device, add a heat sink, change the mounting arrangement on the printed
circuit board, or change the thermal dissipation on the printed circuit board surrounding the
device. This description is most useful for packages with heat sinks where 90% of the heat
flow is through the case to heat sink to ambient. For most packages, a better model is
required.
A more accurate two-resistor thermal model can be constructed from the junction-to-board
thermal resistance and the junction-to-case thermal resistance. The junction-to-case thermal
resistance describes when using a heat sink or where a substantial amount of heat is
dissipated from the top of the package. The junction-to-board thermal resistance describes
the thermal performance when most of the heat is conducted to the printed circuit board. This
model can be used to generate simple estimations and for computational fluid dynamics
(CFD) thermal models. More accurate compact Flotherm models can be generated upon
request.
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111
To determine the junction temperature of the device in the application on a prototype board,
use the thermal characterization parameter (ΨJT) to determine the junction temperature by
measuring the temperature at the top center of the package case using the following
equation:
Equation 4 TJ = TT + (ΨJT x PD)

where:
TT = thermocouple temperature on top of the package (°C)
ΨJT = thermal characterization parameter (°C/W)
The thermal characterization parameter is measured in compliance with the JESD51-2
specification using a 40-gauge type T thermocouple epoxied to the top center of the package
case. Position the thermocouple so that the thermocouple junction rests on the package.
Place a small amount of epoxy on the thermocouple junction and approximately 1 mm of wire
extending from the junction. Place the thermocouple wire flat against the package case to
avoid measurement errors caused by the cooling effects of the thermocouple wire.
When board temperature is perfectly defined below the device, it is possible to use the
thermal characterization parameter (ΨJPB) to determine the junction temperature by
measuring the temperature at the bottom center of the package case (exposed pad) using
the following equation:
Equation 5 TJ = TB + (ΨJPB x PD)

where:
TT = thermocouple temperature on bottom of the package (°C)
ΨJT = thermal characterization parameter (°C/W)
100/112 DocID027866 Rev 5

SPC572Lx Ordering information
5 Ordering information
Figure 40. Product code structure
Example code:
SPC57 2 L 64 E3 B C 6 A R
Product identifier Core Family Memory Package Reserved Temperature Frequency Reserved Packing
Y = Tray
R = Tape and Reel
6 = 80 MHz
4 = 64 MHz
C = 125 oC Ta
F2 = eTQFP80, 0.4 mm pitch

E3 = eTQFP100, 0.5 mm pitch
64 = 1.5 MB
60 = 1 MB
L = SPC57L family
2 = Single Computing e200z2 core
SPC57 = Power Architecture in

55 nm
1. Order on 1 MB part numbers can be entered upon ST’s acceptance conditioned by volumes. Please
contact your ST sales office to ask for the availability of a particular commercial product.
2. Features (e.g. flash, RAM or peripherals) not included in the commercial product cannot be used. ST
cannot be called to take any liability for features used outside the commercial product.
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111
Revision history SPC572Lx
6 Revision history
Table 55 summarizes revisions to this document.

Table 55. Document revision history
Date Revision Changes
18-Jul- 2012 1 Initial release.

Formatting and editorial changes throughout document.
Table 2: SPC572Lx device feature summary:
Changed title (was SPC5726SPC572L64 device feature summary)
Figure 2 (Periphery allocation):
Removed BAR module from diagram.
Section 1.5, Features overview:
Added detail to PIT descriptions (2 bullets).
Added Saturation Instructions Extension... feature item.
Figure 4 (100-pin QFP configuration (top view)):
Changed pin 65 to “ESR1”
Table 3 (Power supply and reference pins):
For row VDD_LV: added pin 68 for 100 pin and 80 pin packages.
Section 2.2.1, Power supply and reference voltage pins:
Added 2 sentences starting from “The Supply Pins Table contains...”
Table 5 (Port pins description):
From PC[10] to PC[15] - changed VDD_HV_IO_FLEX to VDD_HV_IO_ETH
Table 7 (Absolute maximum ratings):
Added footnote VDD_HV_IO refers to...
Section 2.2.1, Power supply and reference voltage pins:
Added 2 sentences starting from The Supply Pins Table contains...
Table 8 (ESD ratings,):
Added classification column
03-Apr-2013 2 Table 9 (Device operating conditions):
Removed rows VDD_HV_ADR_D and VDD_HV_ADR_S
For row VDD_HV_ADR: divided Value Min column data into “C” (3.0) and “P” (4.0) values
and added the word reference to the Parameter description column
Changed row VSS_HV_ADR symbol (was VSS_HV_ADR_D)
Changed VDD_HV_ADV Value Min column data for P characteristic to 4.0 (was 4.2)
Table 9 (Device operating conditions):
For row VDD_HV_ADR: inverted the C and P Parameter Classification values.
Table 10 (DC electrical specifications):
Removed the following rows: VDD_HV_IO, VDD_HV_IO_JTAG, VDD_HV_IO_ETH, VDD_HV_ADV,
VDD_HV_ADR, VDD_HV_ADR – VDD_HV_ADV
Table 12 (I/O input DC electrical characteristics):
In row VIHTTL condition changed to 4.5 V < VDD_HV_IO < 5.5 V.
In row VILTTL condition changed to 4.5 V < VDD_HV_IO < 5.5 V.
In row VHYSTTL condition changed to 4.5 V < VDD_HV_IO < 5.5 V.
In row VIHCMOS_H condition changed to 2.7 V < VDD_HV_IO < 3.0 V and
4.0 V < VDD_HV_IO < 4.5 V.
In row VIHCMOS condition changed to 2.7 V < VDD_HV_IO < 3.0 V and
4.0 V < VDD_HV_IO < 4.5 V.
In row VILCMOS_H condition changed to 2.7 V < VDD_HV_IO < 3.0 V and
4.0 V < VDD_HV_IO < 4.5 V.
In row VHYSCMOS condition changed to 2.7 V < VDD_HV_IO < 3.0 V and
4.0 V < VDD_HV_IO < 4.5 V.
102/112 DocID027866 Rev 5

SPC572Lx Revision history
Table 55. Document revision history (continued)

Table 13 (I/O pull-up/pull-down DC electrical characteristics):

In row |IWPU| changed to Weak pull-up current absolute value
In row |IWPU| (P) condition changed to VIN < VIH = 0.69*VDD_HV_IO,
4.5 V < VDD_HV_IO < 5.5 V.
In row |IWPU| (P) minimum changed to 23 µA; maximum value deleted.
In row |IWPD| (P) minimum deleted; maximum value changed to 130 µA.
In row |IWPD| (P) condition changed to VIN > VIH = 0.69*VDDE, 4.5 V < VDD < 5.5 V.
Deleted: |IWPU| (T) at VIN = 0 V, 3.0 V < VDD_HV_IO < 4.0 V.
Added |IWPU| (T) at VIN > VIL = 0.49*VDDE, 4.5 V < VDD < 5.5 V.
Added |IWPU| (T) at VIN > VIL = 1.1 V (TTL), 4.5 V < VDD < 5.5 V.
Added RWPU (Weak pull-up resistance).
Deleted: |IWPD| (T) at VIN = VDD_HV_IO, 3.0 V < VDD_HV_IO < 4.0 V.
Added |IWPD| (T) at VIN < VIL = 0.49*VDDE, 4.5 V < VDD < 5.5 V.
Added |IWPD| (T) at VIN < VIL = 0.9 V (TTL), 4.5 V < VDD < 5.5 V.
Added RWPD (Weak pull-down resistance).
Table 14 (WEAK configuration output buffer electrical characteristics):
Added footnote 4.
Specification changes:
In row ROH_W condition changed to 4.5 V < VDD_HV_IO < 5.9 V, Push pull, IOH < 0.5 mA.
In row ROL_W condition changed to 4.5 V < VDD_HV_IO < 5.9 V, Push pull, IOH < 0.5 mA.
In row tTR_W condition CL = 25 pF, 4.0 V < VDD_HV_IO < 5.9 V changed to CL = 25 pF,
4.5 V < VDD_HV_IO < 5.9 V
4.5 V < VDD_HV_IO < 5.9 V
2 4.5 V < VDD_HV_IO < 5.9 V
03-Apr-2013
(cont.) Table 15 (MEDIUM configuration output buffer electrical characteristics):
Added footnote 4.
In ROH_M condition changed to 4.5 V < VDD_HV_IO < 5.9 V, Push pull, IOH < 2 mA.
In ROL_M condition changed to 4.5 V < VDD_HV_IO < 5.9 V, Push pull, IOH < 2 mA.
In tTR_M condition changed to CL = 25 pF, 4.5 V < VDD_HV_IO < 5.9 V.
Table 16 (STRONG configuration output buffer electrical characteristics):
Added footnote 4.
In ROH_S condition changed to 4.5 V < VDD_HV_IO < 5.9 V, Push pull, IOH < 8 mA.
IN ROL_S condition changed to 4.5 V < VDD_HV_IO < 5.9 V, Push pull, IOH < 8 mA.
In tTR_S condition changed to CL = 50 pF, 4.5 V < VDD_HV_IO < 5.9 V.
In tTR_S condition changed to CL = 200 pF, 4.5 V < VDD_HV_IO < 5.9 V.
In tTR_S condition CL = 50 pF, 4.5 V < VDD_HV_IO < 5.9 V.
Table 17 (VERY STRONG configuration output buffer electrical characteristics):
Removed footnote: For specification per Electrical Physical Layer Specification 3.0.1...
Section 3.9, I/O pad current specification:
Changed Note In order to ensure ... remain below 10%. changed to ...below 50%.
Table 19 (Reset electrical characteristics)
Added footnote to row IOL_R: IOL_R applies to both PORST and ESR0...
In row IOL_R condition changed to Device under power-on reset,
3.0 V < VDD_HV_IO < 5.5 V, VOL > 1.0 V.
In row IOL_R minimum for conditions Device under power-on reset,
3.0 V < VDD_HV_IO < 5.5 V, VOL > 1.0 V changed to12 mA.
Table 23 (Internal RC oscillator electrical specifications):
In row tstart_T Parameter Classification changed to D (was T).
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111

Table 25 (SARn ADC electrical specification):

Row VDD_HV_ADR_S removed.
In row VIN Max Value cell changed to VDD_HV_ADR (was VDD_HV_ADR_S)
In row TUE12 updated conditions
In row TUE10 changed Characteristic for both conditions to T and updated conditions
In row VALTREF changed the Parameter Classification to C (was P).
Added phrase For parameters classified as T and D. to footnote TUE and DNL...
Table 26 (SDn ADC electrical specification)
In row fIN - changed Parameter Classification for both conditions to D (was P)
Removed rows – VDD_HV_ADV, VSS_HV_ADR_D, VDD_HV_ADR_D
For VIN_PK2PK (Input range peak to peak VIN_PK2PK = VINP – VINM) corrected GAIN
condition for Single ended – VINM = 0.5*VDD_HV_ADR_D GAIN = 2,4,8,16.
In δGROUP condition OSR = 75, changed Max Value to 596.
Added footnote VINM is the input voltage applied to the negative terminal of the SDADC.
For rows SNRDIFF150, SNRDIFF333 and SNRSE150 added footnote SNR degradated by
3dB, in the range 3.6 V< VDD_HV_ADV < 5.5 V.
Table 27 (Temperature sensor electrical characteristics):
In row ITEMP_SENS changed description to VDD_HV_ADV power supply current.
Section 3.15.2, Main voltage regulator electrical characteristics:
Changed HV and BV supply voltage descriptions.
Table 31 (Voltage regulator electrical characteristics):
Updated all values.
Figure 19 (Voltage monitor threshold definition):
Reworked diagram
Table 32 (Voltage monitor electrical characteristics):
2 Refomatted table and updated all content.
03-Apr-2013 Table 34 (Functional terminals state during power-up and reset):
(cont.)
in TERMINAL ERROR row removed Comments.
Section 3.16, Flash memory electrical characteristics:
Added content relating to Flash read wait states and added Table 35 (RWSC settings).
Table 36 (Flash memory program and erase specifications (pending silicon
characterization)):
Updated footnotes, parameter classifications, Initial Max 25 °C values, Initial max
parameter classifications and Typical end of life values.
Added rows tpprogrameep and tqprogrameep
In Rows t16kprogrameep and t16keraseeep changed partition information to partition 1.
Table 41 (DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0,
CPHA = 0 or 1)
Changed footnote Maximum frequency is 100 MHz to Maximum frequency is 80 MHz.
Table 42 (DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1,
CPHA = 0 or 1)
Table 49 (DSPI LVDS slave timing – full duplex – modified transfer format
(MTFE = 0/1)):
Table 49 (UART frequency support):
Added row clock frequency 100.
Section 4.2: eTQFP80 case drawing
Added mechanical drawings.
Section 4.3: eTQFP100 case drawing
Added mechanical drawings.
Table 53 (Thermal characteristics for eTQFP80):
104/112 DocID027866 Rev 5


Updated table, added RθJA Min and Max values

2
03-Apr-2013 Table 54 (Thermal characteristics for eTQFP100):
(cont.)
Updated table, added RθJA Min and Max values
Following are the changes in this version of the Datasheet:
Formatting and editorial changes throughout document.
Table 2 (SPC572Lx device feature summary):

Replaced SIPI/LAST Interprocessor bus with Zipwire (SIPI/LAST) Interprocessor bus.
Updated the description of SENT bus.
Figure 1 (Block diagram):

Replaced LFAST & SIPI with Zipwire (LFAST & SIPI).
Section 1.5, Features overview

Reworded the PIT bullet points.
Replaced “two channel multiplexer” with “two channel multiplexers”
Removed “Port pins description” table since the table is included in the
JPC5726M_IO_Signal_Table.xlsx sheet.
Section 3.1, Introduction

Added VDD_HV_PMC to the note section.
18-May-2015 3
Table 7 (Absolute maximum ratings):
In row VDD_LV added footnotes:
Allowed 1.375 – 1.45 V for 10 hours...
1.32 – 1.375 V range allowed periodically for supply...
In footnote: 1.32 – 1.375 V range allowed periodically... changed 1.275 V to 1.288 V
Removed VDD_HV_FLA and VDD_HV_IO_JTAG rows.
Removed TJ row.
For IMAXD, replaced minimum and maximum values of “-10” and “10” with “-11” and “11”.
Updated tXRAY.
Added a note to VDD_HV_ADV.
Table 9 (Radiated emissions testing specification):

Added “36 dBµV” in all the rows of column “BISS radiated emissions limit”.
Table 10 (Conducted emissions testing specifications):

Added “BISS limit” column.
Table 8 (ESD ratings,):

Classification parameter for ESD for Human Body Model is now T.
DocID027866 Rev 5 105/112

111


Changed VRAMP to VRAMP_LV, changed parameter to “slew rate on core power supply
pins”.
Added VRAMP_HV specification, parameter “Slew rate on HV power supply pins”, max
value 100 V/ms.
Updated the classification of fSYS to “C”.
Updated the VDD_HV_IO_MAIN classification, minimum, and maximum values.
Updated the VDD_HV_IO_JTAG classification, minimum, and maximum values.
Added VIN symbol.
Updated all the columns of the VDD_HV_ADV symbol.
Replaced note below the table “Reduced output/input capabilities below 4.2 V. See
performance ...” with “Reduced output/input capabilities below 4.2 V. See performance
operating values in I/O pad electrical characteristics. Not all functionality are
guaranteed below 4.2V. Please check ...”
Table 10 (DC electrical specifications):

Updated the maximum values of IDD from “100” to “145”.
Changed the classification of IDDPE from “P” to “C”.
Updated the condition of IDDAPP and the maximum value is updated to 125 mA.
Updated the parameter, conditions, and maximum values of IDDAR. Added another row to
it.
Changed the classification of ISPIKE from “C” to “T”.
Changed the classification of dl from “C” to “T”.
Replaced “20 us” with “< 20 us” in the conditions column of dl.
Changed the classification of ISR from “C” to “D”.
3 Updated the parameter column of ISR.
18-May-2015 Deleted IINACT_D, IIC, and TA (TL to TH).
(cont.)
Replaced the maximum value of “90” with “60” for ISPIKE
Replaced the maximum value of “120” with “165” for IDDPE.
Added VREF_BG_T, VREF_BG_TC, and VREF_BG_LR symbols.
Table 11 (I/O pad specification descriptions):

In row Very Strong Configuration, removed reference to FlexRay.
Table 12 (I/O input DC electrical characteristics):

For VHYSTTL replaced “0.3” with “0.275” for minimum value.
For VILAUT replaced “2.2” with “2.1” for maximum value.
For VHYSAUT replaced “0.5” with “0.4” for minimum value.
Updated the ILKG.
Updated the conditions of ILKG_MED.
Added “GPIO input pins” to the conditions column of CIN.
Updated Note 6 below the table.
For VDRFTTT, VDRFTAUT, and VDRFTCMOS replaced “C” with “T” in characteristics column.
Updated note in maximum value of VIHAUT.
Table 13 (I/O pull-up/pull-down DC electrical characteristics):

VDDE replaced by VDD_HV_IO.
Updated IWPU rows.
Updated IWPD rows.
Added RWPU parameter.
Added conditions to RWPD parameter.
106/112 DocID027866 Rev 5


Table 14 (WEAK configuration output buffer electrical characteristics):

“4.5 V < VDD_HV_IO < 5.9 V” replaced by “4.5 V < VDD_HV_IO < 5.5 V” in ROH_W and
ROL_W rows.
Minimum values of ROH_W and ROL_W changed from “560” to “520”
Replaced “VDD_HV_IO_FLEX” with “VDD_HV_IO_ETH” in note below the table.
Table 15 (MEDIUM configuration output buffer electrical characteristics):

Added note to the conditions column.
“4.5 V < VDD_HV_IO < 5.9 V” replaced by “4.5 V < VDD_HV_IO < 5.5 V” in ROH_M and
ROL_Mrows.

Minimum values of ROH_M and ROL_M changed from “140” to “120”
Table 16 (STRONG configuration output buffer electrical characteristics):

“4.5 V < VDD_HV_IO < 5.9 V” replaced by “4.5 V < VDD_HV_IO < 5.5 V” in ROH_S and ROL_S
rows.
Minimum values of ROH_S and ROL_S changed from “35” to “30”
Updated the minimum values of tTR_S
Table 17 (VERY STRONG configuration output buffer electrical characteristics):

Updated ROH_V and ROL_V rows.
Removed footnotes:
3 • Refer to FlexRay section for...
18-May-2015
(cont.) • 20–80% transition time...
Updated the minimum values of tTR_V
Removed “EBI output driver electrical characteristics” table.
Table 18 (I/O consumption):

Added a footnote to the table.
Removed footnote: Data based on simulation results...
Updated all the condition rows of the table.
Table 19 (Reset electrical characteristics):

Replaced minimum value of “300” with “275” in the VHYS row.
Replaced “0.9 V” with “1.0 V” in the in the condition column of IOL_R row.
Replaced minimum value of “11” with “12” in the IOL_R row.
Updated IWPU and IWPD rows.
Table 20 (PLL0 electrical characteristics):

Added fPLL0PHI1 and fPLL0FREE symbols.
Replaced maximum value of “100” with “80” in the fPLL0PHI0 row.
In footnote: PLL0IN clock retrieved... the second sentence now reads Input
characteristics are granted when using XOSC.
In fPLL0IN added a second note to parameter column.
Updated maximum value of fPLL0LOCK.
DocID027866 Rev 5 107/112

111

18-May-2015 3 Table 21 (External oscillator electrical specifications):

(cont.) Updated the minimum and maximum values of fXTAL.
Updated VIHEXT, VILEXT, gm, and IXTAL.
Added VHYS.
Table 22 (Selectable load capacitance):

Updated the table.
Table 23 (Internal RC oscillator electrical specifications):

Removed IAVDD5, and IDVDD12 rows.
Updated parameter column of δfvar_SW.
Table 24 (ADC pin specification):

Removed ILK_IN symbol.
Added VREF_BG_T, VREF_BG_TC, and VREF_BG_LR symbols.
Updated conditions column of IBG symbol.
Removed the table footnote “Leakage current is a....”
Added ΣIADR
Updated ILK_INUD, ILK_INUSD, ILK_INREF, and ILK_INOUT.
Replaced maximum value of “6.5” with “8.5” for CS.
Table 25 (SARn ADC electrical specification):

Updated conditions, minimum, and maximum columns of VALTREF.
Updated parameter, conditions, and maximum columns of IADCREFH.
Replaced the maximum value of “1” with “+8” in IADCREFH symbol (power down mode).
Replaced “IADCVDD” with “IADV_S” and updated its conditions and maximum columns.
Updated minimum and maximum columns of DNL.
Table 26 (SDn ADC electrical specification):

In the fADCD_M symbol replaced “S/D clock 3” with “S/D modulator Input clock”.
Added minimum value of “4”.
Updated the maximum values of |δGAIN|
Replaced the unit values of “dB” with “dBFS” in the SNRDIFF150, SNRDIFF333, and
SNRSE150 symbols.
Replaced the unit values of “dB” with “dBc” in SFDR symbol.
Added CMRR symbol and replaced the minimum value of “20” with “54”.
Added RCaaf and Frolloff symbols.
Updated the maximum values of IADV_D and ΣIADR_D.
Removed ΣIADR_D.
Replaced maximum value of “2*δGROUP” with “δGROUP” for tLATENCY.
Replaced maximum value of “15” with “16” for GAIN.
Added IADCS/D_REFH.
Updated the minimum, typical and maximum values of ZIN.
Table 27 (Temperature sensor electrical characteristics):

Added rows:
• temperature monitoring range
• temperature sensitivity (TSENS)
• temperature accuracy (TACC)
108/112 DocID027866 Rev 5


Table 28 (LVDS pad startup and receiver electrical characteristics):

Replaced “C” with “T” in the characteristics column of ILVDS_BIAS and ILVDS_RX.
Table 29 (LFAST transmitter electrical characteristics), and Table 30 (MSC/DSPI LVDS

transmitter electrical characteristics):
Replaced “C” with “T” in the characteristics column of ILVDS_TX.
Table 39 (Nexus debug port timing):

Replaced “P” with “D” in the characteristics column of tEVTIPW and tEVTOPW.
Figure 18 (Voltage regulator capacitance connection):

Updated the figure.

Replaced RDECREGn with RREG.
Updated the conditions column of CDECBV and CDECHV.
Changed the classification of IMREGINT from “P” to “D”.
Added “- at 27 oC , no load” to note 6.
Added “with full load” to note 7.
Table 36 (Flash memory program and erase specifications (pending silicon

characterization)):
For tESUS, replaced lifetime max value of “20” WITH “30”.
For tpsus, replaced lifetime max value of “10” WITH “15”.
3
18-May-2015
(cont.) Table 40 (DSPI channel frequency support):
Removed “Full duplex” from LVDS (Master mode).
Table 41 (DSPI CMOS master classic timing (full duplex and output only) – MTFE = 0,
CPHA = 0 or 1):
Updated the minimum values of tCSC, tPCSC, and tPASC and maximum values of tSUO.
Table 42 (DSPI CMOS master modified timing (full duplex and output only) – MTFE = 1,
CPHA = 0 or 1):
Updated the minimum values of tCSC, tPCSC, and tPASC and maximum values of tSUO.
Removed section “DSPI LVDS Master Mode — Modified Timing.”
Table 44 (DSPI CMOS master timing – output only – timed serial bus mode TSB = 1 or
ITSB = 1, CPOL = 0 or 1, continuous SCK clock):
Updated the minimum values of tCSV and maximum values of tSUO.
Table 45 (DSPI CMOS Slave timing - Modified Transfer Format (MTFE = 0/1)):
Updated the minimum and maximum values of tDIS.
Replaced the maximum value of “50” with “55” in tSUO (medium).
Table 48 (RMII transmit signal timing):

Replaced the maximum value of “14” with “16” for R6.
DocID027866 Rev 5 109/112

111

Section 3.17.5, GPIO delay timing:

Added this section.
Replaced “four” with “three” in the table footnotes in Table 51 (eTQFP80 –

STMicroelectronics package mechanical data) and Table 52 (eTQFP100 –
STMicroelectronics package mechanical data).
Table 51 (eTQFP80 – STMicroelectronics package mechanical data):

3 Second note removed from E2 parameter and added to E3 parameter.
18-May-2015
(cont.)
Updated the table and its values.

Updated the table and its values.
Table 60 (Order codes (ST))

Updated the table.
Following are the changes in this version of the Datasheet:
Replaced eLQFP100 with eTQFP100 throughout the document.
Removed all requirement tagging from the document.
Replaced RPNs: SPC572L64F2B, SPC572L64E3B with SPC572Lx.
Replaced SPC572LxB with SPC572Lx.
Replaced bullet point “On-chip voltage...” with “Single 5V +/-10%....” on the cover page.
Table 1 (Device summary):
– Updated the table.
Table 2 (SPC572Lx device feature summary):
– Updated the notes of “External power supplies”
Section 3.4: Electromagnetic Compatibility (EMC):
– Updated the section.
– Updated the values of parameter VDD_LV.
– Updated notes in the table.
15-Jun-2017 4
Removed section: “Temperature profile.”
Table 26 (SDn ADC electrical specification):
– Updated the values for RBIAS parameter.
– Added parameters ZDIFF, ZCM, and ΔVINTCM.
– Added parameter CDECFLA
Table 32 (Voltage monitor electrical characteristics):
– Added parameter VLVD108
Section 4.3: eTQFP100 case drawing:
– Updated the Figure 39: eTQFP100 – STMicroelectronics package mechanical
drawing.
– Updated the Table 52 (eTQFP100 – STMicroelectronics package mechanical data).
Section 5: Ordering information:
– Removed table: Order codes (ST).
Added Figure 40: Product code structure.
110/112 DocID027866 Rev 5


06-Jul-2017 5 Removed “ST Restricted” watermark
DocID027866 Rev 5 111/112

111
SPC572Lx
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on
ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or
the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2017 STMicroelectronics – All rights reserved
112/112 DocID027866 Rev 5

SPC572Lx: 32-Bit Power Architecture Based MCU For Automotive Powertrain Applications

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SPC572Lx

32-bit Power Architecture® based MCU for automotive powertrain

– Intelligent complex timer module

1056 KByte SPC572L60F2 SPC572L60E3

July 2017 DocID027866 Rev 5 1/112

2 Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . 13

2/112 DocID027866 Rev 5

3.12.3 S/D ADC electrical specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

4.2 eTQFP80 case drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

DocID027866 Rev 5 3/112

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

4/112 DocID027866 Rev 5

DocID027866 Rev 5 5/112

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6/112 DocID027866 Rev 5

1.1 Document overview

1.3 Device feature summary

DocID027866 Rev 5 7/112

Table 2. SPC572Lx device feature summary (continued)

SENT bus 4 channels

1.4 Block diagram

8/112 DocID027866 Rev 5

Figure 1. Block diagram

VLE Scalar SP-FPU

DocID027866 Rev 5 9/112

Figure 2. Periphery allocation

10/112 DocID027866 Rev 5

1.5 Features overview

DocID027866 Rev 5 11/112

• 1 Clock Calibration on CAN Unit (CCCU)

12/112 DocID027866 Rev 5

2 Package pinouts and signal descriptions

2.1 Package pinouts

Figure 3. 80-pin QFP configuration (top view)

DocID027866 Rev 5 13/112

Figure 4. 100-pin QFP configuration (top view)

2.2 Pin descriptions

2.2.1 Power supply and reference voltage pins

14/112 DocID027866 Rev 5

Table 3. Power supply and reference pins

Symbol Type Description 80 100

VSS_HV Ground High voltage ground Exposed Exposed

2.2.2 System pins

Table 4. System pins

PORST Power on reset with Schmitt trigger characteristics and Bidirectional 56 66

DocID027866 Rev 5 15/112

Table 4. System pins (continued)

XTAL Analog output of the oscillator amplifier circuit Output 44 54

2.2.3 LVDS pins

Table 5. LVDSM pin descriptions

SIPI PF[13] SIPI_RXN Interprocessor Bus LFAST, I 46 56

2.2.4 Generic pins

16/112 DocID027866 Rev 5

DocID027866 Rev 5 17/112

3.2 Parameter classification

Table 6. Parameter classifications

P Parameters are guaranteed by production testing on each individual device.