Digital Logic Design

07 – Synchronous Sequential Logic

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Analysis of Clocked Sequential Circuits
• Analysis describes what a given circuit will do under certain
operating conditions
• The behavior of a clocked sequential circuits is determined from:
• The inputs
• The outputs
• The state of its flip-flops
• The outputs and the next state are both a function of
• The inputs
• The present state

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Analysis of Clocked Sequential Circuits
• The analysis of sequential circuit consists of:
• Obtaining a table or a diagram for the time sequence of
• Inputs
• Outputs
• Internal states
• It is possible to write Boolean expression that describe the behavior of the
sequential circuit

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State Equations
• The behavior of a clocked sequential circuit can be described
algebraically by means of state equations (transition equations)
• A state equation specifies the next state as a function of
• The present state
• inputs

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 State Equations
• Example: The circuit consists of x
• Two D flip-flops 𝐴 and 𝐵 D Q A
• An input 𝑥
• An output 𝑦 Q

• It is possible to write a set of

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 State Equations
• 𝐴 𝑡+1 =𝐴 𝑡 ⋅𝑥 𝑡 +𝐵 𝑡 ⋅𝑥 𝑡
x
• 𝐵 𝑡 + 1 = 𝐴′ 𝑡 ⋅ 𝑥 𝑡 D Q A

• 𝑡 + 1 -> next state of the flip-flop Q

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 State Equations
• Similarly, x
′
• 𝑦 𝑡 = 𝐴 𝑡 +𝐵 𝑡 𝑥 𝑡 D Q A
• 𝑦 = 𝐴 + 𝐵 𝑥′
Q

• The full state equations are

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State Table
• The time sequence of inputs, outputs and flip-flop can be
enumerated in state table (transition table)
• In general, a sequential circuit with 𝑚 flip-flops and 𝑛 inputs needs
2𝑚+𝑛 rows in the state table

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 State Table
• 𝐴 𝑡 + 1 = 𝐴𝑥 + 𝐵𝑥
• 𝐵 𝑡 + 1 = 𝐴′ 𝑥
• 𝑦 = 𝐴 + 𝐵 𝑥′

x
D Q A

D Q B

CLK Q

y
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 State Table
• 𝐴 𝑡 + 1 = 𝐴𝑥 + 𝐵𝑥
• 𝐵 𝑡 + 1 = 𝐴′ 𝑥
• 𝑦 = 𝐴 + 𝐵 𝑥′

x
D Q A

D Q B

CLK Q

y
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State Diagram
• The information available in a state table can be represented graphically in the
form of a state diagram
• States are represented by circles
• Transition between states are indicated by directed lines connecting the circles

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Analysis with D Flip-Flops

𝐴 𝑡 + 1 = 𝐷𝐴 = 𝐴 ⊕ 𝑥 ⊕ 𝑦

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Analysis with JK Flip-Flops
• 𝐽𝐴 = 𝐵 𝐾𝐴 = 𝐵𝑥 ′
• 𝐽𝐵 = 𝑥 ′ 𝐾𝐵 = 𝐴 ⊕ 𝑥

𝐴 𝑡 + 1 = 𝐽𝐴 𝑄𝐴′ + 𝐾𝐴′ 𝑄𝐴
= 𝐴′ 𝐵 + 𝐴𝐵′ + 𝐴𝑥

𝐵 𝑡 + 1 = 𝐽𝐵 𝑄𝐵′ + 𝐾𝐵′ 𝑄𝐵
= 𝐵′ 𝑥 ′ + 𝐴𝐵𝑥 + 𝐴′ 𝐵𝑥 ′

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Analysis with JK Flip-Flops
• 𝐽𝐴 = 𝐵 𝐾𝐴 = 𝐵𝑥 ′
• 𝐽𝐵 = 𝑥 ′ 𝐾𝐵 = 𝐴 ⊕ 𝑥

𝐴 𝑡 + 1 = 𝐽𝐴 𝑄𝐴′ + 𝐾𝐴′ 𝑄𝐴
= 𝐴′ 𝐵 + 𝐴𝐵′ + 𝐴𝑥

𝐵 𝑡 + 1 = 𝐽𝐵 𝑄𝐵′ + 𝐾𝐵′ 𝑄𝐵
= 𝐵′ 𝑥 ′ + 𝐴𝐵𝑥 + 𝐴′ 𝐵𝑥 ′

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Analysis with JK Flip-Flops

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Analysis with T Flip-Flops
• 𝑇𝐴 = 𝐵𝑥 𝑇𝐵 = 𝑥
• 𝑦 = 𝐴𝐵
𝐴 𝑡 + 1 = 𝑇𝐴 ⊕ 𝐴 = 𝑇𝐴′ 𝐴 + 𝑇𝐴 𝐴′
= 𝐵𝑥 ′ 𝐴 + 𝐵𝑥𝐴′
= 𝐵′ + 𝑥 ′ 𝐴 + 𝐴′𝐵𝑥
= 𝐴𝐵′ + 𝐴𝑥 ′ + 𝐴′ 𝐵𝑥

𝐵 𝑡 + 1 = 𝑇𝐵 ⊕ 𝐵 = 𝑇𝐵′ 𝐵 + 𝑇𝐵 𝐵′
= 𝑥 ′ 𝐵 + 𝑥𝐵′
=𝑥⊕𝐵

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Analysis with T Flip-Flops
• 𝑇𝐴 = 𝐵𝑥 𝑇𝐵 = 𝑥
• 𝑦 = 𝐴𝐵

𝐴 𝑡 + 1 = 𝑇𝐴 ⊕ 𝐴 = 𝑇𝐴′ 𝐴 + 𝑇𝐴 𝐴′
= 𝐵𝑥 ′ 𝐴 + 𝐵𝑥𝐴′
= 𝐵′ + 𝑥 ′ 𝐴 + 𝐴′𝐵𝑥
= 𝐴𝐵′ + 𝐴𝑥 ′ + 𝐴′ 𝐵𝑥

𝐵 𝑡 + 1 = 𝑇𝐵 ⊕ 𝐵 = 𝑇𝐵′ 𝐵 + 𝑇𝐵 𝐵′
= 𝑥 ′ 𝐵 + 𝑥𝐵′
=𝑥⊕𝐵
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Analysis with T Flip-Flops

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Mealy and Moore Models
• Sequential circuits are divided into two models (they differ in the
way output is generated):
• Mealy Model
• Moore Model

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Mealy Model
• The output is a function of both the present
state and input
• The output may change if the input changes
during the clock pulse period x
• The output may have momentary false values D Q A

unless the input is synchronized with the clock Q

D Q B

CLK Q

y
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Moore Model
• The output is function of the present
state only
• The output is synchronous with the clock

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Design Procedure

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Design Procedure
• The design of a clocked sequential circuit
• Starts from a set of specifications
• Results in
• A logic diagram
• Or a list of Boolean function from which the logic diagram can be obtained

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Design Procedure
1. Derive a state diagram for the circuit from the word description
2. Reduce the number of states if necessary
3. Assign binary values to the states
4. Obtain the binary-coded state table
5. Choose the type of flip-flops
6. Derive the simplified flip-flop equations and output equations
7. Draw the logic diagram

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Design Procedure: Example 1
• Design a circuit that detects 3 or more consecutive 1’s in a string of
bits coming through the input line (i.e., the input is a serial bit
stream)

• This is a Moore model sequential circuit

State Meaning
𝑆0 Initial state
𝑆1 1 is detected
𝑆2 11 is detected
𝑆3 111 or more 1’s is detected
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 Design Procedure: Example 1

State A B
S0 0 0
S1 0 1
S2 1 0
S3 1 1

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Design Procedure: Example 1
• Synthesis using D flip-flops
• Two D flip-flops (𝐴 and 𝐵) are required to represent the four states
• There is one input 𝑥
• There is one output 𝑦
• The characteristic equation of the D flip-flops is
• 𝑄 𝑡+1 =𝐷

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 Design Procedure: Example 1
• Synthesis using D flip-flops
• The flip-flop input equations can be
obtained directly from the next state
columns of 𝐴 and 𝐵
• 𝐴 𝑡 + 1 = 𝐷𝐴 𝐴, 𝐵, 𝑥 = σ 𝑚 3,5,7
• 𝐵 𝑡 + 1 = 𝐷𝐵 𝐴, 𝐵, 𝑥 = σ 𝑚(1,5,7)
• 𝑦 𝐴, 𝐵, 𝑥 = σ 𝑚 6,7

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Design Procedure: Example 1
• 𝐴 𝑡 + 1 = 𝐷𝐴 𝐴, 𝐵, 𝑥 = σ 𝑚 3,5,7 = 𝐴𝑥 + 𝐵𝑥
• 𝐵 𝑡 + 1 = 𝐷𝐵 𝐴, 𝐵, 𝑥 = σ 𝑚(1,5,7) = 𝐴𝑥 + 𝐵′ 𝑥
• 𝑦 𝐴, 𝐵, 𝑥 = σ 𝑚 6,7 = 𝐴𝐵

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Design Procedure: Example 1

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Design Procedure: Example 1
• When D flip-flops are employed, the input equations are obtained
directly from the next state
• This is not the case for the JK and T types of flip-flops
• It is necessary to derive a functional relationship between the state table and
the input equations
• A table that lists the required inputs for a given change of state is need
• Such a table is called excitation table

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 Excitation Tables
• JK flip-flop excitation table

Characteristic Table
Excitation Table

𝑸 𝒕 + 𝟏 = 𝑱𝑸′ + 𝑲′ 𝑸
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Excitation Tables
• T flip-flop excitation table

Characteristic Table Excitation Table

𝑸 𝒕 + 𝟏 = 𝑻 ⊕ 𝑸 = 𝑻𝑸′ + 𝑻′ 𝑸

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 Design Procedure: Example 1
• Synthesis using JK flip-flops

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Design Procedure: Example 1

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 Design Procedure: Example 2
• Synthesis using T flip-flops: 3-bit binary counter
• An 𝑛-bit binary counter consists of 𝑛 flip-flops that can count in binary
from 0 to 2𝑛 − 1.

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Design Procedure: Example 2

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Design Procedure: Example 2

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Design Procedure: Example 3
• Design a sequence detector that will examine a string of 0’s and 1’s
applied to the input 𝑋 and generate an output 𝑍 = 1 when a
sequence ending in 101 is received.
• The circuit does not reset when a 1 output occurs.

• A typical input sequence and the corresponding output sequence

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 Design Procedure: Example 3
• Design using Mealy machine

State Meaning
𝑆0 Initial state
𝑆1 1 is detected
𝑆2 10 is detected

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Design Procedure: Example 3

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 Design Procedure: Example 3
• Design using Moore machine

State Meaning
𝑆0 Initial state
𝑆1 1 is detected
𝑆2 10 is detected
𝑆3 101 is detected

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Design Procedure: Example 4
• Design a sequence detector that generates an output 𝑍 = 1 when
the input sequence ends in either 010 or 1001 and 𝑍 should be 0
otherwise.
• The circuit does not reset when a 1 output occurs.

• Typical sequence:

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Design Procedure: Example 4
• Using Mealy machine

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Design Procedure: Example 5
• Design a Moore sequential circuit with one input 𝑋 and one output
𝑍. The output 𝑍 = 1 if the total number of 1’s received is odd and at
least two consecutive 0’s have been received.

• Typical sequence:

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Design Procedure: Example 5

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