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Home > Ethernet-Mac-feb22-notes
SESSION#1
notes:
1. OSI model
o ISO
2. What is covered as part of training.

Cour
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o Ethernet protocol (10G/100G) gistr
ation
o Protocol
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VLSI Guru Ethernet-Mac-feb22-notes - VLSI Guru https://www.vlsiguru.com/ethernet-mac-feb22-notes/
o Ethernet MAC design understanding(specification)
o Ethernet MAC design verification
o Using SV
o Register model without using SV class
o few sessions on how to do using SV & UVM
o Register model using RAL base classes
3. Schedule
o Monday to Saturday, 10:30AM to 1PM
o recorded video access for all the sessions
4. Ethernet protocol
o Analogies
5. 1984: one organization was formed called as ‘ISO’
o Laptop ecosystem
o Laptop ==> Lenovo
o Wifi router ==> Netgear
o LAN cables ==> Dlink
o LAN cable needs to be connected to router

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o switch (8 port switch) gistr
ation
o We require a common set of guidelines which needs to be followed by everyone who develops the
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compoentns meant for networking purpose.
o ISO
o OSI model(OSI reference model)
o Anything we want to implement in networking devices, should be implemented in to 7 layers.
o Networking
o IEEE802 : 802.1, 802.2, 802.3, 802.4, 802.4, 5, .6
6. food delivery : two entities involved
o customer
o restaurant 1000’s of people placing 1000’s of orders from 1000’s of restaurants
o all those are tracking using various sessions
7. Connection between two compoentns can be
o Ethernet Protocol => LAN
o WIFI
o Bluetooth
8. Hardware layer and software layer
o software layer
o Implemented as a set of driver, which is loaded in to memory, microcontroller/processor fetches this

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application and run the instruction present in this application. gistr
ation
o hardware
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o thse instructions require a hardware to execute o College campus
o 100 of systems are connected using LAN
o 120.100.10.1 series of IP numbers
o a system of IP=120.100.10.15 wants to copy a movie file from IP=120.100.10.95
o we open the application where we see what all IP are connected in systme
o we invoke a application request to copy a file from the destination system(node)
o this request is essentially is series of Ethernet Frame transfer request
o at bigger level(application and presentation layer level): Requesting for some packet transfers.
o This session layers, sets up a transfer session(file data is being transferred to your system)
o the DLL(~MAC) of the destination laptop, create ethernet frames using above session request.
o Session(transferring of whole movie file to my laptop)
o this is still at software level.
o destination laptop processor(intel I5)
o based on above session created(it knows where the movie file is present inside my(dest) laptop)
o LAN specification application, presentation and session layer
o it programs Ethernet MAC registers (handover is happening from software to hardware layer)
o These registers are called as ‘transmit descriptors’ and ‘receive descriptors’
o these descriptors indicate to the Ethernet MAC where the data is present in harddisk.
o MAC performs read to this harddisk location, get the data. Cour
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gistr
ation
o MAC DLL develops an ethernet frame
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o PREAMBLE | SFD | DA | SA | LEN | PAYLOAD | FCS
o once these registers are configured, the overall work is now with hardware.
o Ethernet mAC hardware layers
o frame teh ethernet frame using the movie data. o Laptop itself can be divided in to two parts
o OSI software specific layer =>
o set of drivers(~binary code), which is loaded in to some memory
o this software layer gets requests from other node software layer
o how software layer to hardware layer handover happens?
o by programming descriptor registers.
o These frames reaches the source laptop(one requesting)
o it goes through exact reverse process.
9. MAC can be divided in two aspects
o Logical layer
o All the core functionality is implemented
o framing of packet, receiivng the packet, understnaidng descriptors
o Physical layer
10. flow control Cour

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gistr
ation
▪ controling of the flow
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o does the receiving device has enough space to accomodate whatever frames I am sending.
o it is done so that, we don’t lose the packets.
o it is about buffer space(place where packet is stored) management
o giving proper numbering to the packets.
o it can also exhcanging of informaiton on how much buffer space is available.
▪ analogy:
o we placed a order
o one delivery boy in on the way
o can we make him deliver another parcel which he is in other work?
o I am sending the frame, whether receiving side has space to accommodate what I am sending
11. Error control
o whatever I sent, is it received properly?
o if not received properly, what to do?
o should I resend?
o should I drop the packet?
o if received properly, what to do => marked as a success
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SESSION#2 gistr
ation
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revision
2. OSI model
o how it is divided in to 7 layers
o basic overview of each layer
o 7 layers: 2 categories
o software layers
o hardware layers
3. networking components are implemented using IEEE 802 standards
802.1 to 802.15
4. Ethernet and computer netowkring components are very important
o 2 kind of startups
o ecommerce
o networking based (billion dollars)
o Arista
Agenda:
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gistr
1. Ethernet protocol ation
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2. MAC design
Notes:
1. terminologies
o MAC address
o 48 bits
o IP address
o 32 bit : IPv4
o 128 bit : IPv6
o IPv4
o IPv6
o switches & routers
o they route the packet in the right direction based on the destination IP address.
o repeaters
o when the signal stregnth is lost, it makes sure to bring it to required level.
o LAN
o Frame & Packet
o server
o where data is hosted, we can make request to get the data. Cour
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gistr
ation
o topology
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o how the things are connected.
o WLAN : not exactly related to Ethernet
o Wireless =>
o gateways
o firewall
o intrusion detection system
2. www.vlsiguru.com is hosted on a server present at New Delhi
o we browsed www.vlsiguru.com and page opened in 6 seconds
o what all happened in this time?
o Where is Ethernet coming in to picture?
o My laptop figures out what I am trying to access?
o is it a MAC address?
o It is part of LAN
o There is server present in same building connected through LAN cables.
o 3 servers, all are connected to various rooms through Lab cabling.
o When we make a request, it will be through ‘Ethernet Frames’
o is it a IP address?
o when I browsed a website or IP address

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o request went to firewall sitting in my office room gistr
ation
o it makes decision, whether the target is in to LAN or outside the network
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o my whole building is one network
o when I access, 10.0.0.1 => it is part of LAN, response comes from inside LAN only.
o www.vlsiguru.com => has an IP address
o the request gets routed to my internet service provider.
o My laptop generates a frame => which it turn gets wrapper as IPv6 packet(or IPv4 packet)
o this IPv6 packet goes to ACT switch
o IPv6 uses 128 bit source address and 128 bit destination address
o my laptop node has an IP address(not same as 48 bit source address)
o using my source address: my browser generates on IPv6 packet
o it went to ACT switch
o ACT switch would have mapping of what www.vlsiguru.com destination IP address value.
o there might a connection between my laptop and ACT switch => which gives destination IP address.
o it happens in network interface where it checks the routing table
o IPv6
o India as a whole has lot of switches.
o ACT switch further forwards this IPv6 to the further direction.
o IPv6 packet gets routed through some algorithm, where it establishes that path for connecting to the final
server where vlsiguru.com is hosted.

Cour
o it may be using some lookup tables, which tells in which direction packet should be forwarded.
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gistr
ation
o packet finally reaches the destination IP.
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o place where vlsiguru.com is hosted
o It gets the payload as part of IPv6 packet.
o That payload tells the destination(server), what part of website we want to access.
o server it turn frames the data, creates another IPv6 packet
o which gets routed exactly in the same reverse path, how we sent request packet
o IPv6 packet finally gets devivered to our system.
o It decodes the payload, HTML browser understands the data, displays as wbesite content.
3. what is packet and what is frame?
frame: preamble | sof | da | sa | len | payload | fcs
o communication inside the LAN should happen through frame
packet: any communication that happens between network to network
o IPv4
o 32 bit source address and 32 bit destination address
o ACT group of networks
o IP inside ACT network
o anotehr IP inside ACT network
o ACT group of networks will be limited in count
o smaller source and destination address is sufficinent

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o IPv6 gistr
ation
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o some networks outside
o we require bigger addresses.
4. what is LAN?
▪ Network
▪ Local area => IP address is not being used
5. When sending IPv4 and IPv6 packets, they should do encryption.
▪ for security purpose.
▪ some AES-128 or 256 alogorthm to encrypt the packet.
o receiving side using the same algorithm, they does decryption.
6. Optical cables
o speed of transmission: speed of light
o 100Mbps/10Gbps/100Gbps/400Gbps/1.8Tbps => Physical layer
o it requires advanced hardware which can transmit or receive the data at this speed.
o Using optical cable Cour

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gistr
o light needs to be converted to bit level transitions ation
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o this needs to be captured by a circuit o Small form factor converts electrical signal to optical signal
o 10G/100G
o C form factor (CFP)
o 400G
7. Assume all nodes are connected using bus topology
o we need a mechansim where each node is able to sense whether bus is idle or bus has some packet/frame
being transmitted. => Carrier sense o Node needs to a mechansim to check if transmtited packet has got in
to collision with packet from some other node. => Collision detection o multiple access
o ability to transmit multiple times that same packet
o or multiple nodes wanting the access CSMA/CD
8Q. from project protocol level may not be involved in DV work
9. Ethernet
o unicast
o sending to only one node
o multicast
o sending to multiple nodes
o broadcast
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o sending to all connected nodes gistr
ation
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10. CRC?
o 32 bit polynomial
x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
0x82608EDB
32’b1000_0010_0110_0000_1000_1110_1101_1011 101)1101010110(
101 (instead of subtraction, do XOR operation)
011 (how many upper most bits are 0, bring those many bits down from the dividend)
111
101 (XOR)
0100 (how many bits to bring down: 1)
101
—-
00110 (bring down 2 bits)
101
—-
0111
101 Cour
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gistr
ation
—
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0101
101
0000 => remainder 000 => CRC = 000
if I use 32 bit divisor, then the remainder is called as 32 bit CRC
11. pause frames
o A node is requesting data.
o It is getting the data at much faster rate than it can process.
o how does it tell to transmitting device, hold on for sometime.
o the receiveing node will send a pause frame(indicating how much time to pause)
o for that duration, transmitting node, will not send any frame.
12. Inter packet gap
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gistr
ation
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13. Ethernet MAC architecture
o Host interface
o This is the interface through which Ethernet MAC is getting connected wtih the rest of the system.
o MAC control module
o Transmit(Tx) Ethernet MAC
o Receive(Rx) Ethernet MAC
o MII Management module
14. Why this project will be useful for you?
o DMA controller (internal DMA engine)
o common concept in all most 80% of the complex designs you work on.
o How high speed serial communication protocol is working
o packet transmission, receive
o CRC calcuation
o how to implement scoreboarding logic for design based on serial communication protocol
o we are going to work on complete flow from specification to regression setup and coverage analysis
15. USB controller
o USB controller internally has concept of DMA
PCIe controller Cour

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gistr
ation
o PCIe controller internall has concept of DMA
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16. Transfer of 100MB of data from my node to destination node, involves two steps
o Processor to MAC
o Harddisk to Processor
o Processor to MAC
o MAC to destination node
17. What is the problem with Processor directly giving 100MB data to MAC?
o Processor gets occupied, it can’t do anything during that transfer time. => it is not a good idea to keep the
processor busy for such a long time.
o Solution?
o Ethernet MAC internally implements a component called as ‘DMA engine/block’
o Processor tells to the DMA engine that
o read from this specific location of the harddisk
o get the data
o MAC will create a ethernet frame using this data and send it to destination node.
18. How Processor will tell DMA engine, from where to read, how much data to read?
o Transmit descriptor (transmit description => descriptor)
o 64 bits transmit descriptor
o 32 bits | 16 bits | 16 bits Cour

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gistr
ation
o 32 bits : what is the harddisk address from where DMA engine should perform the data read.
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o 16 bits : how much(how many bytes) of data to read from the hard disk?
o 16 bits : control bits
o once I am done with this transfer, what to do?
o it is last transfer or one more such transfer is pending?
o should I generate an interrupt indicating transfer is done?
o Receive descriptor (Receive description => descriptor)
o 64 bits receive descriptor
o 32 bits | 16 bits | 16 bits
o 32 bits : when I(Ethernet MAC) receives ethernet frame(it is getting payload), where that payload should be
stored to, which part of the harddisk this data should be stored to.
o 16 bits : how much(how many bytes) of data to write to the hard disk?
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gistr
ation
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19. where is transmit descriptor presnet?
processor or MAC or destination node or harddisk?
– transmit descriptor is set of registers which are present inside Ethernet MAC(not exactly inside DMA engine)
– processor programs these registers(transmit descriptors)
o essentially indicating from where to read and where to write.
20. what a transmit descriptor can do?
o 32 bit address: 32’h1000_0000 : from this part of harddisk start reading
o 16 bits length: 2*16 = 64KBytes o once DMA engine processor this descriptor, it starts reading from
32’h1000_0000 location o how many times does it read? o depends on size of data bus. lets say 32 bits, 4
bytes o 64KBytes => how many beats should happen totally = 16K = 161024 beats = 16396 beats
o Lets assume AXI protocol master interface(instead of Wishbone)
o AXI can do maximum of 16 beat transaction(arlen = 15)
o 16396/16 = 1024 transactions
o by processing one transmit descriptor, DMA engine figures out that, it needs to get 64KB of data starting
from 32’h1000_0000 location
– end address = 32’h1000_0000 + 64KBytes
– to get this much data, DMA engine does 1024 transactions of 16 burst lenght
o this 64KBytes is divided in to 1500+1500+… bytes each

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o each 1500 bytes used to create one Ethernet frame gistr
ation
o that frame will be transmitted
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o totally how many frame will be required?
– 64KB/1500B = 64KB/1.5KB = 43 packets
o total size of movie file = 100MB
o 100MB/1.5KB = 100*1024/1.5 = 66000 packets
20Q. why u took 1500 byets and not 46 byte?
o to send whole data in minimal number of packets => hence take biggest possible size
SES#2
revision
2. OSI model
o how it is divided in to 7 layers
o basic overview of each layer
o 7 layers: 2 categories
o software layers
o hardware layers
3. networking components are implemented using IEEE 802 standards Cour

se Re
802.1 to 802.15 gistr
ation
20 of 80 10-12-2022, 02:32
4. Ethernet and computer netowkring components are very important
o 2 kind of startups
o ecommerce
o networking based (billion dollars)
o Arista
Agenda:
2. MAC design
Notes:
1. terminologies
o MAC address
o 48 bits
o IP address
o 32 bit : IPv4
o 128 bit : IPv6
o IPv4
Cour
se Re
o IPv6 gistr
ation
o switches & routers
21 of 80 10-12-2022, 02:32
o they route the packet in the right direction based on the destination IP address.
o repeaters
o when the signal stregnth is lost, it makes sure to bring it to required level.
o LAN
o Frame & Packet
o server
o where data is hosted, we can make request to get the data.
o topology
o how the things are connected.
o WLAN : not exactly related to Ethernet
o Wireless =>
o gateways
o firewall
o intrusion detection system
2. www.vlsiguru.com is hosted on a server present at New Delhi
o we browsed www.vlsiguru.com and page opened in 6 seconds
o what all happened in this time?
o Where is Ethernet coming in to picture?

Cour
se Re
o My laptop figures out what I am trying to access? gistr
ation
o is it a MAC address?
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o It is part of LAN
o There is server present in same building connected through LAN cables.
o 3 servers, all are connected to various rooms through Lab cabling.
o When we make a request, it will be through ‘Ethernet Frames’
o is it a IP address?
o when I browsed a website or IP address
o request went to firewall sitting in my office room
o it makes decision, whether the target is in to LAN or outside the network
o my whole building is one network
o when I access, 10.0.0.1 => it is part of LAN, response comes from inside LAN only.
o www.vlsiguru.com => has an IP address
o the request gets routed to my internet service provider.
o My laptop generates a frame => which it turn gets wrapper as IPv6 packet(or IPv4 packet)
o this IPv6 packet goes to ACT switch
o IPv6 uses 128 bit source address and 128 bit destination address
o my laptop node has an IP address(not same as 48 bit source address)
o using my source address: my browser generates on IPv6 packet
o it went to ACT switch

Cour
o ACT switch would have mapping of what www.vlsiguru.com destination IP address value. se Regi
stra
o there might a connection between my laptop and ACT switch => which gives destination IP address. tion
23 of 80 10-12-2022, 02:32
o it happens in network interface where it checks the routing table
o IPv6
o India as a whole has lot of switches.
o ACT switch further forwards this IPv6 to the further direction.
o IPv6 packet gets routed through some algorithm, where it establishes that path for connecting to the final
server where vlsiguru.com is hosted.
o it may be using some lookup tables, which tells in which direction packet should be forwarded.
o packet finally reaches the destination IP.
o place where vlsiguru.com is hosted
o It gets the payload as part of IPv6 packet.
o That payload tells the destination(server), what part of website we want to access.
o server it turn frames the data, creates another IPv6 packet
o which gets routed exactly in the same reverse path, how we sent request packet
o IPv6 packet finally gets devivered to our system.
o It decodes the payload, HTML browser understands the data, displays as wbesite content.
3. what is packet and what is frame?
frame: preamble | sof | da | sa | len | payload | fcs
o communication inside the LAN should happen through frame

Cour
se Re
packet: any communication that happens between network to network gistr
ation
o IPv4
24 of 80 10-12-2022, 02:32
o ACT group of networks
o IP inside ACT network
o anotehr IP inside ACT network
o ACT group of networks will be limited in count
o smaller source and destination address is sufficinent
o IPv6
o some networks outside
o we require bigger addresses.
4. what is LAN?
▪ Network
▪ Local area => IP address is not being used
5. When sending IPv4 and IPv6 packets, they should do encryption.
▪ for security purpose.

Cour
se Re
gistr
ation
25 of 80 10-12-2022, 02:32
▪ some AES-128 or 256 alogorthm to encrypt the packet.
o receiving side using the same algorithm, they does decryption.
6. Optical cables
o speed of transmission: speed of light
o 100Mbps/10Gbps/100Gbps/400Gbps/1.8Tbps => Physical layer
o it requires advanced hardware which can transmit or receive the data at this speed.
o Using optical cable
o light needs to be converted to bit level transitions
o this needs to be captured by a circuit o Small form factor converts electrical signal to optical signal
o 10G/100G
o C form factor (CFP)
o 400G
7. Assume all nodes are connected using bus topology
o we need a mechansim where each node is able to sense whether bus is idle or bus has some packet/frame
being transmitted. => Carrier sense o Node needs to a mechansim to check if transmtited packet has got in
to collision with packet from some other node. => Collision detection o multiple access
o ability to transmit multiple times that same packet Cour

se Re
gistr
o or multiple nodes wanting the access CSMA/CD ation
26 of 80 10-12-2022, 02:32
8Q. from project protocol level may not be involved in DV work
9. Ethernet
o unicast
o sending to only one node
o multicast
o sending to multiple nodes
o broadcast
o sending to all connected nodes
10. CRC?
o 32 bit polynomial
x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
0x82608EDB
32’b1000_0010_0110_0000_1000_1110_1101_1011 101)1101010110(
101 (instead of subtraction, do XOR operation)
011 (how many upper most bits are 0, bring those many bits down from the dividend)
111
101 (XOR) Cour

se Re
gistr
— ation
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0100 (how many bits to bring down: 1)
101
—-
00110 (bring down 2 bits)
101
—-
0111
101
0101
101
0000 => remainder 000 => CRC = 000
if I use 32 bit divisor, then the remainder is called as 32 bit CRC
Cour
se Re
gistr
ation
28 of 80 10-12-2022, 02:32
11. pause frames
o A node is requesting data.
o It is getting the data at much faster rate than it can process.
o how does it tell to transmitting device, hold on for sometime.
o the receiveing node will send a pause frame(indicating how much time to pause)
o for that duration, transmitting node, will not send any frame.
12. Inter packet gap
13. Ethernet MAC architecture
o Host interface
o This is the interface through which Ethernet MAC is getting connected wtih the rest of the system.
o Transmit(Tx) Ethernet MAC
o Receive(Rx) Ethernet MAC
o MII Management module
14. Why this project will be useful for you?
o DMA controller (internal DMA engine)
o common concept in all most 80% of the complex designs you work on.
Cour
se Re
o How high speed serial communication protocol is working gistr
ation
o packet transmission, receive
29 of 80 10-12-2022, 02:32
o CRC calcuation
o how to implement scoreboarding logic for design based on serial communication protocol
o we are going to work on complete flow from specification to regression setup and coverage analysis
15. USB controller
o USB controller internally has concept of DMA
PCIe controller
o PCIe controller internall has concept of DMA
16. Transfer of 100MB of data from my node to destination node, involves two steps
o Processor to MAC
o Harddisk to Processor
o Processor to MAC
o MAC to destination node
17. What is the problem with Processor directly giving 100MB data to MAC?
o Processor gets occupied, it can’t do anything during that transfer time. => it is not a good idea to keep the
processor busy for such a long time.
o Solution?
o Ethernet MAC internally implements a component called as ‘DMA engine/block’

Cour
se Re
o Processor tells to the DMA engine that gistr
ation
o read from this specific location of the harddisk
30 of 80 10-12-2022, 02:32
o get the data
o MAC will create a ethernet frame using this data and send it to destination node.
18. How Processor will tell DMA engine, from where to read, how much data to read?
o Transmit descriptor (transmit description => descriptor)
o 64 bits transmit descriptor
o 32 bits : what is the harddisk address from where DMA engine should perform the data read.
o 16 bits : how much(how many bytes) of data to read from the hard disk?
o Receive descriptor (Receive description => descriptor)
o 64 bits receive descriptor
o 32 bits : when I(Ethernet MAC) receives ethernet frame(it is getting payload), where that payload should be
stored to, which part of the harddisk this data should be stored to.
o 16 bits : how much(how many bytes) of data to write to the hard disk?
Cour
se Re
o 16 bits : control bits gistr
ation
31 of 80 10-12-2022, 02:32
19. where is transmit descriptor presnet?
processor or MAC or destination node or harddisk?
– transmit descriptor is set of registers which are present inside Ethernet MAC(not exactly inside DMA engine)
– processor programs these registers(transmit descriptors)
o essentially indicating from where to read and where to write.
20. what a transmit descriptor can do?
o 32 bit address: 32’h1000_0000 : from this part of harddisk start reading
o 16 bits length: 2*16 = 64KBytes o once DMA engine processor this descriptor, it starts reading from
32’h1000_0000 location o how many times does it read? o depends on size of data bus. lets say 32 bits, 4
bytes o 64KBytes => how many beats should happen totally = 16K = 161024 beats = 16396 beats
o Lets assume AXI protocol master interface(instead of Wishbone)
o AXI can do maximum of 16 beat transaction(arlen = 15)
o 16396/16 = 1024 transactions
o by processing one transmit descriptor, DMA engine figures out that, it needs to get 64KB of data starting
from 32’h1000_0000 location
– end address = 32’h1000_0000 + 64KBytes Cour

se Re
gistr
ation
– to get this much data, DMA engine does 1024 transactions of 16 burst lenght
32 of 80 10-12-2022, 02:32
o this 64KBytes is divided in to 1500+1500+… bytes each
o each 1500 bytes used to create one Ethernet frame
o that frame will be transmitted
o totally how many frame will be required?
– 64KB/1500B = 64KB/1.5KB = 43 packets
o total size of movie file = 100MB
o 100MB/1.5KB = 100*1024/1.5 = 66000 packets
20Q. why u took 1500 byets and not 46 byte?
o to send whole data in minimal number of packets => hence take biggest possible size
SES#3
revision:
1. Ethernet MAC design architecture
o transmit descriptor
o receive descriptor
2. Role of MAC in this data transmit and receive flow
o ethernet frame = 1500 bytes = 1.5KB

Cour
o 100MB => number of frames = 100MB/1.5KB = 66000 frames se Re
gistr
ation
o the data is present in harddisk
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o MAC internally has a DMA which goes and read the harddisk memory.
o then create ethernet frames, sends them to the PHY block
o PHY further drives it to the LAN cable.
o this frames goes to destination laptop
o understands the frame, extracts the payload
3. Functional verification flow of Ethernet MAC
o reading the design specification
o understand the design architecture
o number of interfaces
o number of registers, detailed functionality of each registers
o features
o interrupts, source of interrupt
o develop verification plan
o top level plan of how we approach the verification
o develop testplan
o features, scenarios, test cases, description, status, if failing what is the reason
o develop testbench architecture
o implement testbench components

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o develop sanity testcases gistr
ation
o develop functional testcases
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o implement regression flow
o get coverage numbers (functional and code coverage)
o close teh verification using regression results, and coverage numbers
Notes:
1. understand the design architecture
o design interfaces:
o wishbone slave interface
o processor will configure(program or write-read) to the MAC registers
o processor: master, MAC: Slave
o wishbone master interface
o MAC performs write-reads to the external memory
o to get the data
o to store the data
o MAC : master, external memory: slave
o Transmit interface
o to transmit the data(frames)
o ex: 100MB movie file -> ethernet frames => preamble, sfd, da, sa, etc are tranmsitted on this infc
o MAC : master, PHY : Slave Cour

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o BFM will mimick the PHY behavior
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o Receive interface
o to receive the frames
o MAC : slave, PHY : master
o Management data interface
o MAC will use this interface to configure the MDI block behavior
o MAC : master, PHY MDI : Slave
o Block
o Host interface
o Register
o Understand the wishbone transactions
o DMA implementation
o Tx MAC
o transmitting the frames
o Rx MAC
o receiveing the frames
o does the flow control
o decides when to transmit
o whether to accept Cour

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o MII management module
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o To control MDI module behavior
o get the some status information of PHY
2Q. what are following terms: deferral and back off algorithm, dribble nibbles
– deferal:
o MAC receives Pause frame, it defers transmission to later time
– back off
o I am sending some frame, collision is detected
o I don’t send for some time(backing off)
o next when to attempt => back off algorithm
– dribble nibble
o frame length in bits is not an integral multiple of 8 bits
3. We want to send 50 byte payload, ethernet frame
total lenght of frame = 22 + 4 + 50 = 76
7+1+6+6+2+4+50 = 76 bytes => 152 nibbles
4Q. once repeat the whole clock circuitary, and how its proceeding?
▪ We are trying to minimize the number of external clocks provided to the MAC design
Cour
▪ we are only getting one clock (wb_clk) at host interface as an input se Re
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▪ same clock is given MII management module
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o clock division circuit is present MII MM
o wb_clk/Divisor = MII clock(MDCLK) => clock is given as input to PHY
o PHY should synchronize everything w.r.t to this clock
o PHY internally has PLL
o through that it generate a clock, gives as input TX block of MAC
o TX block of MAC will transmit data at rising edge of this clock.
o summary:
o all transmit and receive is synchronized w.r.t to the PHY Clock.
o we are only using one clock.
1. features, registers, operation of MAC
2. registers
o processor wants to tell some information to the Ethernet MAC
o medium used for telling this is ‘registers’
o processor programs registers to control the MAC behavior
o registers are two types
o control registers
o these are read-write registers, processor can write to these registers.

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o by writing to tehse registers, processor can control the MAC behavior. se Re
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o status registers
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o these are Read only registers, processor can’t write to these registers
o processor can only get the design status by reading these registers.
o analogy: washing machine
o turning on knob => programming control registers of the washing machine
o time to time, we get status from washing machine => those are like status registers
o registers are very important
o how to measure complexity of a design? => number of control registers is directly proporational to the
design complexity
o why would I want increase number of control registers => I want to implement more features
o as we implement more features => design gets more complicated
o design < 10 registers => simple design ==> 4 weeks
o 11 < design < 30 registers => medium complex => 8 weeks
o 31 < design < 100 registers => complex => 16 weeks
o 100 < design => very complex => 24 weeks o in general, registers are 32 bit
o each register is 4 byte
o each byte has one unique address
o each register uses how many addresses? 4
o MODER : 0x0 (addr)
o INT_SOURCE : 0x4 Cour

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o INT_MASK : 0x8
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SES#4
notes:
1. MODER
o MODE Register
o Indicates of Mode of operation of Ethernet MAC
o 32 bits
o further divided in to multiple fields
2. MODER
o RECSMALL
o PAD
o FULLD
o Processor configures the MAC for type of Duplex behavior
o EXDFREN
o Node wants to transmit
o Since link is busy, it is defering.
o LOOPBACK
o not used in normal operations

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o used only link debugging purpose se Re
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3. MINFL, MAXFL
4. How the testcase flow will look like
o step#1
o load external memory with data(ex: movie file to sent to other laptop)
o step#2
o configure all the MAC control registers for required design(MAC) behavior
o confiugre the DMA tx and rx buffer descriptors
o step#3
o Configure MODER TXEN = 1
o MAC understands that user(processor) wants me to start transmitting the frames.
o MAC transmit block creates the frames.
o Configure MODER RXEN = 1
o MAC understands that user(processor) wants me to start processing the incoming frames.
o MAC stores the data from incoming frames to the memory o MAC supports in total 128 descriptors
o ideally, it should be divided as 64 for transmit and 64 for receive descriptors
o but user can configure specific to the requirements
o ex: TD_BD_NUM=0x80 (128 descriptors), Transmit itself is utilizing all the buffer descriptors.
o ex: TD_BD_NUM=0x0 (0 descriptors), Transmit will not have any buffer descriptors. Recive will have all 128
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buffer descriptors. gistr
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5Q. is there any specific reason to have reset value like this 0000a000h?
6. How the interrupt concept works?
o MAC generates an interrupt to the processor
o MAC is asking processor attention
o Processor reads INT_SOURCE registers
o it gets data(32 bit data, lower 7 bits are only valid)
o 7 bits will tell, wy the interrupt got generated
7. when MAC receive control frame(pause frame), it wants to tell processor that, “I have receive a pause frame”
o it generates an interrupt
o processor reads INT_SOURCE register
o processor will get data=32’h0000_0040
o processors knows that pause frame has come
o MAC will not transmit any data for pause amount of time.
o Processor also will not write any data to memory
o once processor has done required things, it will clear by writing ‘1’ to the INT_SOURCE
8Q. are these registers active low?
in VLSI, there is nothing like active low registers

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9. W1C : Write 1 to clear the register field ation
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W0C : Write 0 to clear the register field
10Q. these error are notified by crc or any other process is also there?
o here CRC doesn’t come in to picture.
o please do not confuse interrupt with error.
11. INT_SOURCE and INT_MASK will always have 1-1 mapping.
12. IPG
96 bit times
24 nibble times
24-3 = 21 (0x15) 100Mbps=> 100MHz = 10ns
0.96us = 960ns => 96 bits
13. what if we want 0.48us IPG
48 bit times
12 nibble times
o 12-3 = 9
SES#5
revision: Cour
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1. register description
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▪ fields
o size of the fields
o possible values, significance
▪ reset value
▪ type of access
o RO, RW, W1C, W0C
agenda:
1. remaining registers
2. MAC features
questions:
1. VLSI industry global standard, each byte has a unique address.
o memories are exception, where 32 bits of memory has a unique address.
Notes:
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1. MII can do 3 things to the PHY se Re
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o write the control data to configure the PHY Media dependant interface(MDI)
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o read the status from PHY MDI
o Scan status
2. Processor wants to configure the PHY behavior
o how the PHY should behave?
o PHY has some registers
o Processor configures the MII registers
o MIIAddress
o MIITX_DATA
o MIIRX_DATA (processor will use this for reading the status data)
o MIICommand[2] = 1
o MII should perform a write a MIIAddress, wtih MIITX_DATA
o MII interface signal
3. Size of MAC address = 48 bits
o it requires 2 registers
32 + 16 bits(2nd registers)
4. Pause frame is generated by the Ehternet MAC
o It is the processor who decides how much time of pause is required

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Flow: gistr
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o Node2 is sending data to me.
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o this data is stored in to system memory
o processor is reading from system memory
o processor is not able to read fast
o processor wants to tell Node2 to pause for some time.
o processor don’t directly talk to Node2
o processor configures TXCTRL registers with Pause time value, when to generate pause frame
o as soon as TXCTRL reigster[16] bit=1 is configured, Node1 generates Pause frame with pause time(15:0)
o this Pause frame goes to Node2
o Node2 understands that I need to Pause.
5. How many registers totally?
o 3 MODE registers
MODER
CTRLMODER
MIIMODER
o 2 interrupt registers
INTR_SOURCE
INTR_MASK
o IPGT
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o IPGT, IPGR1, IPGR2 gistr
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o COLLCOFG
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o TX_BD_NUM
o MII
o MAC_ADDR0, MAC_ADDR1
o TX_CTRL
o HASH0, HASH1
▪ these register configuration is what finally translates in to different testcases.
testcase#1:
– RECSMALL=0
testcase#2:
– RECSMALL=1
if we start doing all thise, we will require how many testcases? 1000+ testcases
our primary goal:
– to complete whole MAC veification exhaustively by using only 50 testcases.
o SEED=48483 => RECSMALL=0
o same test, SEED=89489 => RECSMALL=1
6. If I develop 50 testcases, what is actually differing between thse 50 testcases is?
o register programming values Cour

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7. Only design in VLSI chips, which don’t have registers are ?
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o bridge components
o AXI2AHB bridge, it generally won’t have any registers
8. Features supported by MAC
o full duplex
o half duplex
o CSMA/CD
9. Reset
o MAC
o RST_I
o MIIM
o MIIMODER.MIIMRST=1
o PHY
o configure a register in the PHY
o MIIM will configure this register through MII interface
10. why this is starting from 0x400?
o registers are ending 0x50
o they are keeping 0x51 to 0x3ff as reserved space for future revision of Ethernet MAC
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o in future revision, we may add anotehr 200 registers => 200 * 4 = 800 address range gistr
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11. why is this space ending with 0x7FF?
o Each buffer descriptor requires: 64 bits
o bytes : 8
o each buffer descriptor requires: address range of 8
o how many buffer descriptors = 128
o total space for 128 BD’s = 128*8 = 1024 bytes => 0x400 space is required
o Base : 0x400
end : 0x400 + 0x3FF = 0x7FF
hence range: 0x400 – 0x7FF
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12. within 0x400 – 0x7FF, we can allot required number of TX BD, remaining will be RX BD.
I want to configure Ethernet MAC for 16 TX BD, remaining 112 RX BD
o I am expecitng lot of data to come in to my laptop, I will be sending less data.
for this configuration, what will be TX_BD range, what will RX_BD range?
o TX_BD rnage =
o 16 BD = 168 = 128 bytes o 2*7 = 0x80 => 0x7F
o 0x400 to 0x47F
o RX_BD rnage =
o 0x480 to 0x7FF
o 112 BD * 8 addresses/BD =
o if TX_BD0 is at 0x10, next TX_BD1 address=0x18, next = 0x20
13. LEN
o WHen Ethernet MAC is processing this TX descriptor, LEN indeidates, how many bytes MAC-DMA should read
from external memory.
LEN = 16’h200 = 512; (200 is configured by processor)
DMA should perform WB read txs to read 512 bytes from the external memory.
At what address these reads should happen?
o TXPNT will be the starting address

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o TXPNT=32’h1000_0000 gistr
ation
at what range WB Reads will happen?
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o start address= 32’h1000_0000
o end address= 32’h1000_0000 + 16’200 – 1 = 32’h1000_01FF o lets say, there are totally 40 TX_B_DESCR
o each of them has continous range, each with LEN=512
o what will be total range read as per these TX_BD processing?
o 32’h1000_0000 : 1st BD starting
1st BD ending = 32’h1000_01FF
o 2nd buffer descriptor
starting = 32’h1000_0200
ending = 32’h1000_03FF
o 3rd buffer descriptor
starting = 32’h1000_0400
ending = 32’h1000_05FF o 40 BD starting = 32'h1000_0000 + 39*512 ending = 32'h1000_0000 + 40*512 - 1
14. Buffer descriptors are further classified in to BD tables.
o how do we know what is the first BD number in the table?
SES#5
revision:
1. register description Cour

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▪ fields
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o size of the fields
o possible values, significance
▪ reset value
▪ type of access
o RO, RW, W1C, W0C
agenda:
1. remaining registers
2. MAC features
questions:
1. VLSI industry global standard, each byte has a unique address.
o memories are exception, where 32 bits of memory has a unique address.
Notes:
1. MII can do 3 things to the PHY

Cour
o write the control data to configure the PHY Media dependant interface(MDI) se Re
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ation
o read the status from PHY MDI
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o Scan status
2. Processor wants to configure the PHY behavior
o how the PHY should behave?
o PHY has some registers
o Processor configures the MII registers
o MIIAddress
o MIITX_DATA
o MIIRX_DATA (processor will use this for reading the status data)
o MIICommand[2] = 1
o MII should perform a write a MIIAddress, wtih MIITX_DATA
o MII interface signal
3. Size of MAC address = 48 bits
o it requires 2 registers
32 + 16 bits(2nd registers)
4. Pause frame is generated by the Ehternet MAC
o It is the processor who decides how much time of pause is required
Flow:
Cour
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o Node2 is sending data to me. gistr
ation
o this data is stored in to system memory
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o processor is reading from system memory
o processor is not able to read fast
o processor wants to tell Node2 to pause for some time.
o processor don’t directly talk to Node2
o processor configures TXCTRL registers with Pause time value, when to generate pause frame
o as soon as TXCTRL reigster[16] bit=1 is configured, Node1 generates Pause frame with pause time(15:0)
o this Pause frame goes to Node2
o Node2 understands that I need to Pause.
5. How many registers totally?
o 3 MODE registers
MODER
CTRLMODER
MIIMODER
o 2 interrupt registers
INTR_SOURCE
INTR_MASK
o IPGT
o IPGT, IPGR1, IPGR2

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o COLLCOFG gistr
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o TX_BD_NUM
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o MII
o MAC_ADDR0, MAC_ADDR1
o TX_CTRL
o HASH0, HASH1
▪ these register configuration is what finally translates in to different testcases.
testcase#1:
– RECSMALL=0
testcase#2:
– RECSMALL=1
if we start doing all thise, we will require how many testcases? 1000+ testcases
our primary goal:
– to complete whole MAC veification exhaustively by using only 50 testcases.
o SEED=48483 => RECSMALL=0
o same test, SEED=89489 => RECSMALL=1
6. If I develop 50 testcases, what is actually differing between thse 50 testcases is?
o register programming values
Cour
7. Only design in VLSI chips, which don’t have registers are ? se Re
gistr
ation
o bridge components
55 of 80 10-12-2022, 02:32
o AXI2AHB bridge, it generally won’t have any registers
8. Features supported by MAC
o full duplex
o half duplex
o CSMA/CD
9. Reset
o MAC
o RST_I
o MIIM
o MIIMODER.MIIMRST=1
o PHY
o configure a register in the PHY
o MIIM will configure this register through MII interface
10. why this is starting from 0x400?
o registers are ending 0x50
o they are keeping 0x51 to 0x3ff as reserved space for future revision of Ethernet MAC
o in future revision, we may add anotehr 200 registers => 200 * 4 = 800 address range
Cour
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gistr
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11. why is this space ending with 0x7FF?
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o Each buffer descriptor requires: 64 bits
o bytes : 8
o each buffer descriptor requires: address range of 8
o how many buffer descriptors = 128
o total space for 128 BD’s = 128*8 = 1024 bytes => 0x400 space is required
o Base : 0x400
end : 0x400 + 0x3FF = 0x7FF
hence range: 0x400 – 0x7FF
12. within 0x400 – 0x7FF, we can allot required number of TX BD, remaining will be RX BD.
I want to configure Ethernet MAC for 16 TX BD, remaining 112 RX BD
o I am expecitng lot of data to come in to my laptop, I will be sending less data.
for this configuration, what will be TX_BD range, what will RX_BD range?
o TX_BD rnage =
o 16 BD = 168 = 128 bytes o 2*7 = 0x80 => 0x7F
o 0x400 to 0x47F
o RX_BD rnage =
o 0x480 to 0x7FF
o 112 BD * 8 addresses/BD =
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o if TX_BD0 is at 0x10, next TX_BD1 address=0x18, next = 0x20 gistr
ation
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13. LEN
o WHen Ethernet MAC is processing this TX descriptor, LEN indeidates, how many bytes MAC-DMA should read
from external memory.
LEN = 16’h200 = 512; (200 is configured by processor)
DMA should perform WB read txs to read 512 bytes from the external memory.
At what address these reads should happen?
o TXPNT will be the starting address
o TXPNT=32’h1000_0000
at what range WB Reads will happen?
o start address= 32’h1000_0000
o end address= 32’h1000_0000 + 16’200 – 1 = 32’h1000_01FF o lets say, there are totally 40 TX_B_DESCR
o each of them has continous range, each with LEN=512
o what will be total range read as per these TX_BD processing?
o 32’h1000_0000 : 1st BD starting
1st BD ending = 32’h1000_01FF
o 2nd buffer descriptor
starting = 32’h1000_0200
ending = 32’h1000_03FF
o 3rd buffer descriptor Cour

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starting = 32’h1000_0400
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ending = 32’h1000_05FF o 40 BD starting = 32'h1000_0000 + 39*512 ending = 32'h1000_0000 + 40*512 - 1
14. Buffer descriptors are further classified in to BD tables.
o how do we know what is the first BD number in the table?
SES#6
1. BD
o transmit
o receive
2. MAC can receive two types of packets
o data packets
o control packets => Pause frame
3. verification flow
o testplan
o feature listing down
o scenario
o testcase listing down
o testbench architecture
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o testbench development gistr
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o testcase coding
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o verification closure
4. feature listing down, splitting features in to scenarios.
▪ top level division of design functionality.
o mostly involves glancing through the spec.
o register testing
o 10Mbps and 100MBps
o reset
o modes
o full duplex
o control frame
o flow control
o RX Flow control
o TX Flow control
o PASS All
o half duplex
o collision detection and retransmission
o back off algorithm

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o inter packet gap se Re
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o different types of frame transmission
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o unicast
o multicast
o HASH0, HASH1
o broadcast
o interrupt
o for all 7 possible reasons
o various types of packets
o small packets
o padding enabled
o normal packets
o larger packets
o crc enabled
o packet length
o loopback
o promiscuous mode
o MII
o CLock division
o MIINOPRE
o different commands Cour

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o write
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o read
o scan
o Error conditions
o Dribble nibble
o invalid symbol received
o overrun
o underrun
o too long
o short
o Buffer descriptors
o Tx
o Length (different possible)
o Tx BD ready
o IRQ
o Wrap
o Underrun
o RTRY
o Retrasmission Limit
o Late collision Cour

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o Defer indication
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o CS lost
o Rx
o LEN
o Empty
o IRQ
o Wrap
o Control frame
o Miss
o Overrun
o Invalid Symbol
o Dribble Nibble
o Too long
o Short frame
o Rx CRC error
o Late collision
▪ 65 features and scenarios.
▪ optimal number of testcases, we can use to check all above featurs and scenarios.
o 1000 testcases => it becomes too many, takes a lot of time to run. It delays overall project.
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o 5 testcases => it becomes very few testcases, many features getting tested in same testcase, when gisthat
trati
on
testcase fails, it takes time to figure out, what actually caused the failure.
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o what is right way to develop testcases?
o try to target one scenario in each testcases.
o overall it may take 50 to 70 testcases
▪ Ethernet MAC
SES#7
1. each scenario => one testcase
2. you are assigned with a block,
1st thing to ask is: is testplan available?
No, is it availble from previous version of the project
No project started
if (is testplan available) begin
check what all testcases are implemented, what is their status
develop remaining testcases
end
else begin
if (testplan available from previous version of project) begin Cour

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use that testplan, do required updates for new features added in the current version ation
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end
else begin
Develop complete testplan from scratch.
end
end
//now start developing TB => testplan must be available.
3. How testplan is further divided?
o testcases in testplan is divided in to 3 or 4 phases, duration: 4 months(18 weeks)
o P1
o basic tests: register wr-rd, register reset, basic MAC transmit and receive tests
o 2-3 weeks
o P2
o feature specific testcases, interrupt generation testcases
o 8-10 weeks
o P3
o 6 weeks
o advanced testcases
o error
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o concurrent transfer tests gistr
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4. functional coverage point listing down
o what is guarantee that our testplan is checking everything in the design? what is some feature or some
scenario is missed out?
o solution: functional coverage
o We will have another verification engineer(not the person who developed testplan) to list down the
functional coverage points.
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5. functional coverage point listing down ==> these will be implemented in to .sv file
o ethernet mac in 10Mbps mode and 100Mbps mode?
o is all 7 types of interrupt generated?
o is different IPG values configured?
o Did we configure different packet length?
o did we do different collconf?
o all register field configuration values?
o TX_BD_NUM and RX_BD_NUM?
o MAC DA coverage
o MAC SA coverage
o MII write command
o MII read command
o MII Scan status
o whether receiving small packet, large packet?
6. Verification engineer primary motive is not to develop testbench.
o primary motive: Make sure that design is bug(error) free for all design features.
7. TB architecture
o design has how many interfaces? Cour

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o wishbone master interface
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o master interface connecting to external memory
o wishbone slave interface (I am talking from Ethernet MAC)
o slave interface connecting to RISC processor
o MAC tx interface
o master interface connecting to the PHY
o MAC rx interface
o slave interface connecting to the PHY
o MII interface
o master interface connecting to the PHY
8. Testbench component development and bringup
o VPN connection, login to server, copy RTL code to your home directory => S0
o Make sure that RTL is getting compiled => S1
o develop the skeletal structure of the TB => S2
o refer to the TB architecture diagram
o Do DUT connection, interface connections : S3
o DUT has 5 interfaces
o wb_mst, wb_slv => wb_intf
o phy_tx, phy_rx => phy_intf

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o mii => mii_intf gistr
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o generate clock and reset
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o make sure that waveform shows all signals in green(no x or z)
o Implement Wishbone interface for register programming => S4
o implement register access tests o Implement the PHY Interface VIP => S5
o Implement some basic testcases => S6
o Implement the MII interface VIP => S7
o Implement the scoreboard and checker => S8
o Implement all the functional tests => S9
o Setup regression, Generate the coverage report => S10
o Verification closure => S11
9. Make sure that RTL is getting compiled => S1
10. Implement Wishbone interface for register programming => S3
o register access testcases
o register write-read testcases
o register reset value read testcases
o any design verification we do, whether register access is working fine or not.
o you may verify any design
o 1st 2 rtestcases are always
– register write-read Cour

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– register reset read
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SES#8
1. connecting to the server
o Install VPN
o CrSLL (Cyberoam VPN)
o admin will provide steps and video on how to do
o VPN username and password is different from server login username and password
o how to confirm if we are connected to VPN?
ping 10.0.0.19 or 20 or 10.0.0.25 or 26 or 10.0.0.30 or 31
o https://www.youtube.com/watch?v=R7tv7Mw8M5s
2. login to server
o putty
o vnc viewer
o login username: sreeniv
password: vlsiguru
o ‘passwd’ to change the password
o vncserver command to create a VNC session
o at anytime, you should only have one VNC session
o VN session number is :9 Cour

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o complete VNC path: 10.0.0.19:9 ation
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o invoke vnc viewer application
o enter 10.0.0.19:
o enter 10.0.0.19:9
o login and password
3. setting up project database
o open a terminal
o tcsh
o move to t-shell
o source /home/tools/mentor/cshrc_mentor
o if institute admin restarts the server, then your VNC won’t be valid.
o how to check if my VNC is exsting or not?
4. developing the project
o change directory to place where we want to develop the project
o mkdir ETH_MAC
o cd ETH_MAC
o cp -rf /home/vlsiguru/FUNCTIONAL_VERIFICATION/ETHERNET_MAC/rtl .
5. troubleshooting at every stage

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SES#9
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1. institute building
searching for laptop
$PATH: where all we should look for the laptop?
/institute/grnd_flr/room_no1:/institute/grnd_flr/room_no2:/institute/1st_floor/room_no1
2.
1. Apply reset
o top most module
2. Read all registers
o wb master generator
3. Check the read value with the spec. value.
o reference model
SES#10
S1: connecting to server
S2: copying RTL files to your home directory
S3: RTL compile clean in top module ==> 11:56
S4: Setting up template env Cour

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S5: clock generation and reset apply
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S6: register tests
SES#11
1. Implement Wishbone interface for register programming => S4
o register starting address: 0
o register end address: 50 (hexa)
how many registers in total = 50 => 80(dec)
▪ 80/4 + 1 = 21
2. register reset testcase
o we should perform read to above 21 registers in the Ethernet MAC
checks:
o 1st check
is 21 txs happening? Yes
o 2nd check?
is correct address is being read?
o 3rd check?
is read data matching the data from the spec? => we will check manually from waveform(later we will
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o register reset testcase is passing.
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3. A good verification engineer always create a very organized wave.do file.
cadence: wave.rc
4. 32 bit register => 32 Flip flops
5. 21 register, each register is 32 bits in size(32 FF’s)
o how many FF’s = 32 * 21 = 672 FF’s (32*21 = 640 + 32 = 672)
6. How to trace RTL signals
temp_wb_dat_o:
– 524
7. current simulation is getting over in 30 sec.
o in real project: run time can be 1 to 5 hours also.
o for every small detail, we can’t rerun the simulation?
o lot of time goes in to running simulation only
o in a day, how many runs can be done? 2 (9 hours working)
o we should make best analysis out of what is availble.
8. test register write read

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wdata = 6ee4_b68a (16th bit value = 0)
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rdata = 0000_b68a
what do we notice above?
o upper 16 bits are read as 0, they are mismatching
o open spec., check those 16 bits
how to fix this issue?
o we should write 0’s to all reserved and Read only fields o bitwise and operator
SES#11 WEEKEND
1. weekend lab agenda
o VPN connection, login to server, copy RTL code to your home directory => S0
o Make sure that RTL is getting compiled => S1
o develop the skeletal structure of the TB => S2
o refer to the TB architecture diagram
o Do DUT connection, interface connections : S3
o DUT has 5 interfaces
o wb_mst, wb_slv => wb_intf
o phy_tx, phy_rx => phy_intf
o mii => mii_intf
o generate clock and reset Cour

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o make sure that waveform shows all signals in green(no x or z)
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2. Revision
o Ethernet protocol
o Ethenet MAC architecture
o Etherent MAC specification
o interfaces, registers, operation, interrupt
o testplan development
o TB environment development
3. SV
o 1 or 2 weeks => SV TB => UVM TB
o SV Register model => UVM RAL model
SES#12
revision:
1. register reset read testcases
o checked from the waveform
o we have also learnt the waveform tracing
2. waveform or dataflow tracing

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o tracking how a data is flowing.
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o collconf_reg => 32’h00ee_11ff;
o WB_BFM is seeing this data.
o this data is coming from “somewhere” in the Design.
o dataflow tracing helps us reach that point from where this data is originating.
o Debugging
o ability to figure out the cause(point from where things are going wrong) of failure
o Debugging is done as a mix of dataflow tracing + RTL file search
3. What is that newly, I learn form this project?
o concept of dataflow tracing.
o 50% of your time only goes in debugging the failures => 8 hours => 4 hours will spent on some kind of
debugging
notes:
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1. register wr-rd test
o design can only update the RO register(status register)
o backdoor update to RO register => must not be done =>
o TB won’t be able to RO register
o configuration registers can be updated external TB component
o functional test
o some functionality inside design will result in above register value getting updated.
2. R0 : read only register
o implemented as Read write register.
▪ writing all registers
o read back these register.
o we expect it to give default value(value before write happened)
o we get different value =>
3. register testcases
o register write-read
o 4 combinations : FD Wr – FD RD
o error testcases Cour

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o RO register targeted
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o Write to RO register, read back those registers, data should not match(data should match with default
data)
4. register access is working fine.
o we can implement functional testcases
o eth_frame_transmit_testcase : full duplex
SES#13
1. test_fd_tx
o MAC Full duplex transmit mode
o MII is not involved
o There is no need to configure anything for MII registers
SES#14
▪ develop memory
o instaintate the memory
o handshaking should be asynchronous
▪ testcase development
o register programming Cour

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o preload the memory ation
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o configure transmit descriptors
o trigger the transfer
▪ 3-4 days to do this, please do it.
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VLSI Guru Ethernet-Mac-feb22-notes - VLSI Guru

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2. What is covered as part of training.

o Ethernet MAC design understanding(specification)

o Ethernet MAC design verification

o Register model without using SV class

o few sessions on how to do using SV & UVM

o Register model using RAL base classes

o Monday to Saturday, 10:30AM to 1PM

o recorded video access for all the sessions

5. 1984: one organization was formed called as ‘ISO’

o Laptop ==> Lenovo

o Wifi router ==> Netgear

o LAN cables ==> Dlink

o LAN cable needs to be connected to router

compoentns meant for networking purpose.

o OSI model(OSI reference model)

o Anything we want to implement in networking devices, should be implemented in to 7 layers.

o IEEE802 : 802.1, 802.2, 802.3, 802.4, 802.4, 5, .6

6. food delivery : two entities involved

o restaurant 1000’s of people placing 1000’s of orders from 1000’s of restaurants

o all those are tracking using various sessions

7. Connection between two compoentns can be

o Ethernet Protocol => LAN

8. Hardware layer and software layer

o Implemented as a set of driver, which is loaded in to memory, microcontroller/processor fetches this

o thse instructions require a hardware to execute o College campus

o 100 of systems are connected using LAN

o 120.100.10.1 series of IP numbers

o a system of IP=120.100.10.15 wants to copy a movie file from IP=120.100.10.95

o we invoke a application request to copy a file from the destination system(node)

o this request is essentially is series of Ethernet Frame transfer request

o Session(transferring of whole movie file to my laptop)

o this is still at software level.

o destination laptop processor(intel I5)

o LAN specification application, presentation and session layer

o These registers are called as ‘transmit descriptors’ and ‘receive descriptors’

o PREAMBLE | SFD | DA | SA | LEN | PAYLOAD | FCS

o Ethernet mAC hardware layers

o OSI software specific layer =>

o set of drivers(~binary code), which is loaded in to some memory

o how software layer to hardware layer handover happens?

o by programming descriptor registers.

o These frames reaches the source laptop(one requesting)

o it goes through exact reverse process.

9. MAC can be divided in two aspects

o All the core functionality is implemented

o framing of packet, receiivng the packet, understnaidng descriptors

10. flow control Cour

o it is done so that, we don’t lose the packets.

o it is about buffer space(place where packet is stored) management

o giving proper numbering to the packets.

o it can also exhcanging of informaiton on how much buffer space is available.

o one delivery boy in on the way

o can we make him deliver another parcel which he is in other work?

11. Error control

o whatever I sent, is it received properly?

o if not received properly, what to do?

o should I drop the packet?