MOTOROLA

MEMORIES
Prepared by
Technical Information Center

Motorola has developed a very broad range of MOS and bipolar memories for
virtually any digital data processing system application. Complete specifications
for the individual circuits are provided in the form of data sheets. In addition,
selector guides are included to simplify the task of choosing the best combina-
tion of circuits for optimum system architecture.
New Motorola memories are being introduced continually. For late releases,
additional technical information or pricing, contact your nearest authorized
Motorola distributor or Motorola sales office.
Motorola reserves the right to make changes to any products herein to
improve reliability, function or design. Motorola does not assume any liability
arising out of the application or use of any product or circuit described herein;
neither does it convey any license under its patent rights nor the rights of others.

Series A
©MOTOROLA INC., 1979
Printed in U.S.A. "All Rights Reserved"

_._--- --;---~-~-----
MECL, EXORciser are trademarks of Motorola Inc.
 Table of Contents
Page
Alphanumeric Index .................................. ,;' ..................................... v
CHAPTER 1
Selector Guide ............................................................................ 1-2
Cross- Reference .......................................................................... 1-8

CHAPTER 2 - NMOS Memories

RAMs
MCM2114,21L14 1K x 4 Static ................................................. 2-3
MCM2115A,2125A 1 K x 1 Static ................................ , ................ 2-8
MCM2147 4K x 1 Static ................................ , ................ 2-9
MCM4027A 4K x 1 Dynamic ................. , ... , ....... , ........... , .. 2-14
MCM4096 4K x 1 Dynamic ................. , ..... ,.................... 2-24
MCM4116A 16K x 1 Dynamic ........ ,., ..... , ........... , ........... ,;, 2-32
MCM4516 16K x 1 Dynamic ................... , .. , ..... , ..... , ..... ,., 2-39
MCM6604A 4K x 1 Dynamic ......... , .. , ...... , ... , ..... , ....... ;, .... , 2-43
MCM6605A 4K x 1 Dynamic ....................... , ..... ,., ........ ,... 2-52
MCM6641,66L41 4K x 1 Static ., .............................. ,., ....... ,.... 2-66
MCM6664 64K x 1 Dynamic ............................ ,.............. 2-69
MCM681 0, 68A 10,68810 1281(;' x 8 Static ...................... ,...................... 2-74

EPROMs
MCM2532,25A32 4K x8 2-78
MCM2708,27A08 1K x8 2-84
MCM2716, 27A 16 2K x8 2-90
MCM68708, 68A 708 . 1K x 8 ...................... , ... , .. , .. , .. , .. ,..............
2-95
MCM68764,68A764 8K x 8 ......... , ................... "., .. , .. , ............. 2-101
TMS2716, 27 A 16 2K x 8 .......................... , .. , .. ,', .... , ............. 2-106

ROMs
MCM6670, 6674 128 x (7 x 5) Character Generators ........... ,............. 2-112
MCM66700, 71 0,714,720,
730,734,740,750,751,
760,770,780,790 128 x (9 x 7) Character Generators .. " ..................... , 2-118
MCM68A30A,68830A 1K x 8 Binary ................................ , ... , ......... 2"132
MCM68A308,688308 1K x 8 Binary .................... , ........ , ................ 2-137
MCM68A316A 2K x 8 Binary ........................ , . , ..... , . , ....... , ... (12-142
MCM68A316E 2K x 8 Binary ............................. , .. , ........ ".,. 2-146
MCM68A332 4K x 8 Binary ............ , ............. , ..... , ........ " ... 2-150
MCM68A364,688364 8K x 8 Binary ....' ...................... , .... " , . . . . . . . . . . . .. 2-154

CHAPTER 3 - CMOS Memories

RAMs
MCM14505 64 x 1 Static ................................ , ................ 3-3
MCM14537 256 x 1 Static ...................... ,....................... 3-1 2
MCM14552 64 x 4 Static .................................... ,.:........ 3-20
MCM145101 256 x 1 Static ...................... , .. , ................... , 3-27
MCM146504 4K x 1 Static ............ , ....... , .. , .............. ,........ 3-31-
MCM146508,6518 1K x 1 Static .......................... , ..... ,.,............ 3-32

ROM
MCM14524 256 x 4 ..................................... ,.............. 3-36
Table of Cont~nts (continued)

CHAPTER 4 - Bipolar Memories

TTL RAMs
MCM93415 1024 xl ............. '........................................ 4-3
. MCM93425 1024 xl ....... ; . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 4- 7

TTL PROMs
MCM5303/5003,
5304/5004 64 x 8 ..................................................... 4-11
MCM7620,7621 512 x 4 .................................................... 4-15
MCM7640, 7641,
7642,7643 512 x 8 and 1024 x 4 ....................................... 4-19
MCM7680,7681 1024 x 8 ................................................... 4-23
MCM7684,7685 2K x 4 ..................................................... 4-27
MECL Memories General Information .................................... 4-31
MECL RAMs
MCM10143 8 x 2 ...................................................... . 4-34
MCM10144 256 xl ........... '........................................ . 4-39
MCM10145 16 x 4 .................................................... . 4-41
MCM10146 1024 xl .................................................. . 4-43
MCM10147 128 xl .......................................... : ........ . 4-45
MCM10148 64 xl .................................................... . 4-47
MCM10152 256 xl 4-49

MECL PROMs
MCM10139 32 x 8 ......................................... '. .. . . . . . . . .. 4-51
MCM10149 256 x 4 ..................................................... 4-55

CHAPTER 5 - Memory Subsystems

Board-Level "
MMS1102 32K, 16K, or 8K x 18 or 16 Add-In Memory, .................... 5-3
MMS1110 16K x 16 LSI-11. Add-In Semiconductor Memory ................ 5-5
MMS1117 PDP-ll Unibus Compatible RAM .............................. 5- 7
MMS1118 16K x 18 PDP-11 Add-In Semiconductor Memory ............... 5-9
MMS3418 28K x 18 Semiconductor Memory ............................ 5-11
MMS68102 16K x 8 Nonvolatile Semiconductor Memory .................. 5-15
MMS68103 16K x 8 Semiconductor Memory for M6800 Systems .......... 5-17
MMS68104 16K x 8 Semiconductor Memory for MEK6800 D2 Kit ......... 5-19
MMS80810 32K x 8 Semiconductor Memory for 8080A Systems .......... 5-23

CHAPTER 6 - MECHANICAL DATA .................... : ....................... 6-1

 · Alphanumeric Index
Device Page Device Page
MCM21 L 14 ............................... 2-3 MCM7684 .............................. 4-27
MCM66L41 ............................. 2-66 MCM7685 .............................. 4-27
MCM25A32 ............................ 2-78 MCM10139 ............................ 4-51
MCM27A08 ............................ 2-84 MCM10143 ............................ 4-34
MCM27A 16 ............................ 2-90 MCM 10144 ............................ 4-39
MCM68A 10 ............................ 2-74 MCM10145 ............................ 4-41
MCM68A30A .......................... 2-132 MCM10146 ............................ 4-43
MCM68A308 .......................... 2-137 MCM10147 ............................ 4-45
MCM68A316A ..... . . . . . . . . . . . . . . . . . . .. 2-142 MCM10148 ............................ 4-47
MCM68A316E ......................... 2-146 MCM10149 ............................ 4-55
MCM68A332 .......................... 2-150 MCM10152 ............................ 4-49
MCM68A364 .......................... 2-154 MCM14505 .............................. 3-3
MCM68A 708 ........................... 2-95 MCM 14524 ............. .,............. 3-36
MCM68A 764 .......................... 2-101 MCM14537 ............................ 3-12
MCM68B 10 ............................ 2-74 MCM14552 ............................ 3-20
MCM68B30A .......................... 2-132 MCM66700 ........................... 2-118
MCM68B308 .......................... 2-137 MCM66710 ........................... 2-118
MCM68B364 .......................... 2-154 MCM66714 ........................... 2-118
MCM2114 ................................ 2-3 MCM66720 ........................... 2-118
MCM211.5A .............................. 2-8 MCM66730 ........................... 2-118
MCM2125A .............................. 2-8 MCM66734 ........................... 2-118
MCM2147 ..................... '.' ......... 2-9 MCM66740 ........................... 2-118
MCM2532 .............................. 2- 78 MCM66750 ........................... 2-118
MCM2708 ............................... 2-84 MCM66751 ........................... 2-118
MCM2716 .............................. 2-90 MCM66760 ........................... 2-118
MCM4027A ............................ 2-14 MCM66770 ........................... 2-118
MCM4096 .............................. 2-24 MCM66780 ............................ 2-118
MCM4116A ............................ 2-32 MCM66790 ........................... 2-118
MCM4516 .............................. 2-39 MCM68708 ............................ 2-95
MCM5003 .............................. 4-11 MCM68764 ........................... 2-101
MCM5004 .............................. 4-11 MCM93415 ...... ; ....................... 4-3
MCM5303 .............................. 4-11 MCM93425 .............................. 4- 7
MCM5304 .............................. 4-11 MCM145101 ........................... 3-27
MCM6604A ............................. 2-43 MCM146504 ........................... 3-31
MCM6605A ............................ 2-52 MCM 146508 ........................... 3-32
MCM6641 ................•............. 2-66 MCM146518 ........................... 3-32
MCM6664 .............................. 2-69 MMS1102 ................................ 5-3
MCM6670 ............................. 2-112 MMS1110 ................................ 5-,5
MCM6674 ............................. 2-112 MMS 1117 ....... ; ........................ 5-7
MCM6810 .............................. 2-74 MMS1118 ........... : .................... 5-9
MCM7620 .............................. 4-15 MMS3418 .............................. 5-11
MCM7621 .............................. 4-15 MMS68102 ............................ 5-15
MCM7640 .............................. 4-19 MMS68103 ............................ 5-17
MCM7641 .............................. 4-19 MMS68104 ............................ 5-19
MCM7642 .............................. 4-19 MMS80810 ............................ 5-23
MCM7643 .............................. 4-19 TMS27A16 ............................ 2-106
MCM7680 .............................. 4-23 TMS2716 ............................. 2-106
MCM7681 .............................. 4-23
 SELECTOR
GUIDES
II
CROSS-REFERENCE

1-1
_. -_ .._._----_ .._. __ ._---- ------_._-.
 MEMORIES SELECTION GUIDE
I

NOTES
Boldface denotes industry standard part numbers.
Operating temperature ranges -
MOS: OOC to 70°C
CMOS: -40°C to 85°C and -55°C to +125°C
ECL: Consult individual data sheets
TIL: Military, -55°C to +125°C; Commercial, O°C to 70°C.

FOOTNOTES
ss Second source
1 MOS power supplies -
Three +12, ±5 V
One +5 V
All MOS outputs are three-state exp,ept the 6570 and 6580 series which are open-collector.
2 Character generators include shifted and unshifted characters, ASCII, alphanumeric control,
math, Japanese, British, German, European, and French symbols.

1-2
MEMORIES SELECTION GUIDE (continued)

RAMs II
Number
Access Time Number Second
Organization Part Number of Power
(ns max) of Pins Source
Supplies1

MOS DYNAMIC RAMs

4096 x 1 MCM4096-6 250 3 16 ss
4096 x 1 MCM4096-16 300 3 16 ss
4096 x 1 MCM4096-11 350 3 16 ss
4096 x 1 MCM4027A-2 150 3 16 ss
4096 x 1 MCM4027A-3 200 3 16 ss
4096 x 1 MCM4027A-4 250 3 16 ss
4096 x 1 MCM6604A 350 3 16
4096 x 1 MCM6604A-2 250 3 16
4096 x 1 MCM6604A-4 300 3 16
4096 x 1 MCM6605A 300 3 22
4096 x 1 MCM6605A-2 200 3 22
16.384 x 1 MCM4116A-15 150 3 16 / ss
16.384 x 1 MCM4116A-20 200 3 16 ss
16.384 x 1 MCM4116A-25 250 3 16 ss
16.384 x 1 MCM4116A-30 300 3 16 ss
16.384 x 1 MCM4516A-15* 150 1 16 ss
65.536 x 1 MCM6664A-15* 150 1 16 ss

MOS STATIC RAMs

128 x'8 MCM6810. 450 1 24
128 x 8 MCM68A10 360 1 24
128 x 8 MCM68B10 250 1 24
1024 x 4 MCM2114-20 200 1 18 SS
1024)( 4 MCM2114-25 250 1 18 ss
1024)( 4 MCM2114-30 300 1 18 ss
1024)( 4 MCM2114-45 450 1 18 ss
1024)( 4 MCM21L14-20 200 1 18 ss
1024)( 4 MCM21L14-25 250 1 18 ss
1024)( 4 MCM21L14-30 300 1 18 ss
1024)( 4 MCM21 L 14-45 450 1 18 ss
1024)( 1 MCM2115A 45 1 16
1024)( 1 MCM2125A 45 1 16
4096 x 1 MCM6641-20 200 1 18 ss
4096 x 1 MCM6641-25 250 1 18 ss
4096 x 1 MCM6641-30 300 1. 18 ss
4096 x 1 MCM6641-45 450 1 18 ss
4096 x 1 MCM66L41 -20 200 1 18 ss
4096 x 1 MCM66L41 -25 250 1 18 ss
4096 x 1 MCM66L41 -30 300 1 18 ss
4096 x 1 MCM66L41-45 450 1 18 ss
4096 x 1 MCM2147-55* 55 1 18 ss
4096 x 1 MCM2147-70* 70 1 18 ss
4096 x 1 MCM2147-85* 85 1 18 ss I
*To be introduced.
See Notes on Page 1-2.

1-3
•
MEMORIES SELECTION GUIDE (continued)

Number
Access Time Number Second
Organization Part Number of Power
\ (ns max) of Pins Source
Supplies

CMOS STATIC RAMs

64 x 1 MCM14505 180** 1 14
256 x 1 MCM14537 700** 1 16
64 x 4 MCM14552 700** 1 24
(

256 x 4 MCM145101-1 450 1 22 ss

256 x 4 MCM145101-3 650 1 22 - ss
256 x 4 McM145101-8 800 1 22 ss
4096 x 1 MCMJ46504 450 1 18 ss
1024 x 1 MCM14650S* 460 1 16 ss
1024 x 1 MCM14650S-1 * 300 1 16 ss
1024 x 1 McM14651S* 460 1 18 ss
1024 x 1 MCM14651S-1* 300 1 18 ss
**Typical access time @ VOO = 10 Vdc.

Access Time
Organization Part Number Output
(ns max)

ECl BIPOLAR RAMs

8 x2 , MCM10143 15 EClOutput 24
256 x 1 MCM10144 26 EClOutput 16 ss
16 x 4 MCM10145 15 EClOutput 16 ss
1024 x 1 MCM10146 29 EClOutput 16 ss
128 x 1 MCM10147 15 EClOutput 16 ss
·16 x 4 MCM10148 15 EClOutput 16
256 x 1 MCM10152 15 EClOutput 16 ss

TTL BIPOLAR RAMs

256 x 4 MCM93412* 45 Open-Collector 22 ss
256 x 4 MCM93422* 45 Three-State 22 ss
1024 x 4 MCM93415* 45 Open-Collector 16 ss
1024 x 4 MCM93425* 45 Three-State 16 ss
*To be introduced.
See Notes on Page 1 -2.

J-4
 •
MEMORIES SELECTION GUIDE (continued)

EPROMs
Number
Access Time Number Second
Organization " Part Number of Power
(ns max) of Pins Source
Supplies I

MOS EPROMs
1024 x 8 MCM2708 450 3 24 ss
1024 x 8 MCM27A08 300 3 24 5S

1024 x 8 MCM68708 450 3 24 S5

1024 x 8 MCM68A708 300 3 24
2048 x 8 TMS2716 450 3 24 55
2048 x 8 TMS27A16 300 3 24 ss
2048 x 8 MCM2716* 450 1 24 ss
2048 x 8 MCM27A16* 350 1 24 ss
4096 x 8 MCM2532* 450 1 24
8192 x 8 MCM68764* 450 1 24 S5

PROMs
Access Time
Organization Part ~umber Output
(ns max)

Eel PROMs
32 x 8 MCM10139 25 EClOutput
256 x 4 MCM10149 30 EClOutput

TTL PROMs
64 x 8 MCM5003/5303 125 Open-Collector 24 S5
64 x 8 MCM5004/5304 125 2K Pull-Up 24 ss
512 x 4 MCM7620 70 Open-Collector 16 ss
512 x 4 MCM7621 70 Three-State 16 ss
512 x 4 MCM7640 70 Open-Collector 24 5S
512 x 4 MCM7641 70 Three-State 24 S5

1024 x 4 MCM7642 70 Open-Collector 18 5S

1024 x 4 MCM7643 70 Three-State 18 S5

1024 x 8 MCM7680 70 Open-Collector 24 55

1024 x 8 MCM7681 70 Three-State 24 5S

2048 x 4 MCM7684* 70 Open-Collector 18 55

2048 x 4 MCM7685* 70 Three-State 18 5S

*To be introduced.
See Notes on Page 1 -2.

1-5
I
MEMORIES SELECTION GUIDE (continued)

ROMs
Number
Access Time Number Second
o rga nization Part Number
(ns max)
of Power
of Pins Source
Supplies

MOS STATIC ROMs

Character Generators2
128 x (7 x 5) MCM6670 350 1 18
128 x (7 x 5) MCM6674 350 1 18
128 x (9 x 7) MCM66700 350 1 24 ss
128 x (9 x 7) MCM66710 350 1 24 ss
128 x (9 x 7) MCM66714 350 1 24 ' ss
128 x (9 x 7) MCM66720 350 1 24 ss
128 x (9 x 7) MCM66730 350 , 1 24 ss
128 x (9 x 7) MCM66734 350 1 24
128 x (9 x 7) MCM66740 350 1 24 ss
128 x (9 x 7) MCM66750 350 1 24 ss
128 x (9 x 7) MCM66760 350 1 24 ss
128 x (9 x 7) MCM66770 350 1 24
128 x (9 x 7) MCM66780 350 1 24
128 x (9 x 7) MCM66790 350 1 24

Binary ROMs
1024 x 8 MCM68A30-8 ' 350 1 24
1024 x 8 MCM68A308-7 350 1 24
2048 x 8 MCM68A316-91 350 1 24
1024 x 8 MCM68B30A 250 1 24 ss
1024 x 8 MCM68A30A 350 1 24 ss
1024 x 8 MCM68B308 250 1 24 ss
1024 x 8 MCM68A308 350 1 24 ss
2048 x 8 MCM68A316E 350 1 24 ss
2048 x 8 MCM68A316A 350 1 24 ss
4096 x 8 MCM68A332 350 1 24 ss
4096 x 8 MCM68A332-2* 350 1 24
8192 x 8 MCM68A364* 350 1 24 ss
8192 x 8 MCM68A364-3* 350 1 24
8192 x 8 MCM68B364-3* 250 1 24

CMOS ROM
I 256 x 4 I MCM14524 1200 16
*To be introduced.
See Notes on Page 1 -2.

1-6
MEMORY SYSTEMS
For most purposes, memory systems are as unique and individualistic as is the variety of
equipment in which they are used. There are, however, some computer systems - micro-
II
computers and minicomputers - whose widespread acceptance results in the use of large
numbers of memory systems of a specific architecture. Some of these have been identified,
resulting in the standard, inventoried systems described below. Due to large-volume
requirement and broad-based sales, these systems represent excellent values.

ADD-IN SYSTEMS FOR MICROCOMPUTERS

Organization
16K x 9 8K x 9
Application 32K x 8 Parity 16K x 8 Parity 8K x 8
Option Option
For 6800 Systems
--r--- - - - - - f - - -
Dynam ic RAMs
Standard MMS68100 MMS68100-1
Non-Volatile MMS68102A MMS68102 M MS68102A1 MMS68102-1
for 02 Kit MMS68104
Pseudo-Static RAMs MMS68103A MMS68103 M MS68103A1 MMS68103-1

For 8080A Systems

Dynamic RAMs MMS80810 MMS80810-1
---------,---- ---

ADD-IN SYSTEMS FOR MINICOMPUTERS

Organization
Application 32K x 18 16Kx18 12K x 18 8K x 18
64K x 18 48K x 18 4K x 16
32K x 16" 16Kx16* 12K x 16* , 8K x 16"
For LSI-1112/23
and MMS1102-34PC MMS1102-32PC MMS1102-31PC
PDP-11/03.123 MMS1102-34' MMS1102-32* MMS11 02-31 •

LSI-11 MMS1110* MMS1110-1* MMS1110-2* MMS1110-3*

For General
Automation MMS1600-32* MMS1600-16*
16/110,161220 MMS 1600-32P MMS1600-16P

For PDP-11 /05/

10/35/40/45/
50/55/60
Access Time
390 ns MMS1117-58PC MMS117-56PC MMSll17-54PC MMS1117-52PC
360 ns MMS1117-48PC MMS 117 -46PC MMS1117-44PC MMS1117-42PC
290 ns MMSll17-38PC MMSl17-36PC MMS1117-34PC MMS1117-32PC

For PDP-11 /04

and 11/34 MMS1118 MMS1118-1 MMS1118-2

For PDP-11s
with "MF11 L" MMS1118L* MMS1118L-1* MMSll18L-2*
Backplane

MODULES FOR GENERAL-PURPOSE APPLICATIONS

Dynamic RAMs
128K)( 18 bits MMS3418

1-7
I THE O.FFICIAL MOS MEMORY
CROSS-REFERENCE
From Motorola
APRIL 1979

MOTOROLA'S
ORGANIZATION ACCESS TIME NO.OF POWER MOTOROLA PIN·TO·PIN
PART NUMBER DESCRIPTION Ins max) PINS SUPPLIES REPLACEMENT
AMD
Am2716 2048 X 8 EPROM 450 24 +5 V MCM2716
Am4044 4096 Xl SRAM 200450 18 +5V MCM66L41
Am9016 16,384 X 1 DRAM 150-300 16 +12, ±5 V MCM4116A
Am9114 1024 X 4 SRAM 200450 18 +5V MCM2114
Am91L14 1024 X 4 SRAM 200450 18 +5V MCM'21L14
Am9124 1024 X 4 SRAM 200-450 18 +5V MCM2114
Am9147 4096 Xl SRAM 55·85 18 +5 V MCM2147
Am92088 1024 X 8 SRAM 350 24 +5 V MCM68A308
Am9217 2048 X 8 SROM 350 24 +5 V MCM68A316A
Am9218 2048 X 8 SROM 350 24 +5 V MCM68A316E
Am9232 4096 X 8 SROM 350 24 +5 V MCM68A332
Am9708 1024 X 8 EPROM 450 24 +12, ±5 V MCM68708
AMI
S2114 1024 X 4 SRAM 200450 18 +5 V MCM2114
S2114L 1024 X 4 SRAM 200450 18 +5 V MCM21 L14
S21.47 4096 Xl SRAM 70·100 18 +5 V MCM2147
S4264 8192 X 8 SROM 350 24 +5 V MCM68A364
S5101 256 X 4 SRAM 450-800 22 +5 V MCM145101
S6508 1024 X 1 SRAM 300460 16 +5 V MCM146508
S6518 1024 Xl SRAM 300460 18 +5 V MCM146518
S6810 128 X 8 SRAM 250-450 24 +~V MCM6810
S6830 1024 X 8 SROM 350 24 +5 V MCM68A30A
S6831 A 2048 X 8 SROM 350 24 +5 V . MCM68A316A
S68318 2048 X 8 SROM 350 24 +5 V MCM68A316E
FAIRCHI·LD
F16K 16,384 X 1 DRAM 150-300 16 +12, ±5 V MCM4116A
2114 1024 X 4 SRAM 200450 18 +5 V MCM2114
F2708 1024 X 8 EPROM 450 . 24 +12, ±5 V MCM2708
F27081 1024 X 8 EPROM 300 24 +12,±5V MCM27A08
2716 2048 X 8 EPROM 450 24 +5 V MCM2716
3508 1024 X 8 SROM 350 24 +5 V MCM68A308
F3516E 2048 X 8 SROM 350 24 +5 V MCM68A316E
FM4027 4096 X 1 DRAM 120·250 16 +12, ±5 V MCM4027A
4096 4096 X 1 DRAM 250·350 16 +12, ±5 V MCM4096
F68810 128 X 8 SRAM 250-450 24 +5 V MCM68810
F688308 1024 X 8 SROM 250·350 24 +5 V MCM688308
F68708 1024 X 8 EPROM 450 24 +12, ±5 V MCM68708
FUJITSU
M82147 4096 Xl SRAM 70-100 18 +5 V MCM2147
M8M2716 2048 ~ 8 EPROM 450 24 +5 V MCM2716
MB4044 4096 X 1 SRAM 200450 18 +5 V MCM6641
M88114 1024 X 4 SRAM 200450 18 +5 V MCM2114
M88116 16,384 X 1 DRAM 150-300 16 +12, ±5 V MCM4116A
M88224 4096 X 1 DRAM 250-350 16 +12, ±5 V MCM4096
M88227 4096 X 1 DRAM 120·250 16 +12, ±5 V MCM4027A
M88308 1024 X 8 SROM 350 24 +5 V MCM68A308
M88518H 1024 X 8 EPROM 450 24 +12,±5V MCM2708
GENERAL INSTRUMENT
R03-8316A 2048 X 8 SROM 350 24 +5 V MCM68A316A
R03-9316 2048 X 8 SROM 350 24 +5 V MCM68A316E
R03-9332A 4096 X 8 SROM 350 24 +5 V MCM68A332
R03-93648 8092 X 8 SROM 350 24 +5V MCM68A364
HITACHI
HM462716 2048 X 8 EPROM 450 24 +5V MCM2116
HM435101 256 X 4 SRAM 450·800 22 +5V MCM145101
HM462708 1024 X 8 EPROM 450 24 +12, ±5 V MCM2708
HM468A10 128 X 8 SRAM 350 24 +5V MCM6.8A10
HM46830 1024 X 8 SROM 350 24 +5 V MCM68A30A·
HM4704L 4096 X 1 DRAM 150-250 16 +12. ±5 V MCM4027A
HM4716 16.384 X 1 DRAM 150-300 16 +12, ±5V MCM4116A
HM472114A 1024 X 4 SRAM 200450 18 +5 V MCM21L14
HM4847 4096 X 1 SRAM 55-85 18 +5V MCM2147

1-8
 MOTOROLA'S
II
ORGANIZATION ACCESS TIME NO.OF POWER MOTOROLA PIN-TO-PIN
PART NUMBER DESCRIPTION (ns max) PINS SUPPLIES REPLACEMENT
INTEL
2104A 4096 X 1 DRAM 120-250 16 +12, ± 5 V MCM4027A
2114 1024 X 4 SRAM 200-450 18 +5 V MCM2114
2114L 1024 X 4 SRAM 200-450 18 +5 V MCM21 L14
2117 16,384 X 1 DRAM 150-300 16 +12, ±5 V MCM4116A
2147 4096 Xl SRAM 70-100 18 +5V MCM2147
2308 1024 X 8 SROM 350 24 +5V MCM68A308
2316A 2048 X 8 SROM 350 24 +5V MCM68A316A
2316E 2048 X 8 SROM 350 24 +5 V MCM68A316E
2708-1 1024 X 8 EPROM 300 24 +12, ±5 V MCM27A08
2708 1024 X 8 EPROM 450 24 +12, ±5 V MCM2708
2716 2048 X 8 EPROM 450 24 +5 V MCM2716
2716-1 2048 X 8 EPROM 350 24 +5 V MCM27A16
2716-2 2048 X 8 EPROM 350 24 +5 V MCM27A16
5101 256 X 4 SRAM 450-800 22 +5V MCM145101
INTERSIL
D2114 1024 X 4 SRAM 200-450 18 +5 V MCM2114
MK4027 4096 X 1 DRAM 150-250 16 +12, ±5 V MCM4027A
IM6508 1024 Xl SRAM 300-460 16 +5 V MCM146508
IM6508-1 1024 Xl SRAM 300-460 18 +5,V MCM146518
IM7027 4096 X 1 DRAM 120·250 16 +12, ±5 V MCM4027A
IM7114 1024 X 4 SRAM 200-450 18 +5 V MCM21 L14
IM7116 16,384 X 1 DRAM 150·300 16 +12, ±5 V MCM4116A
IM7141 4096 Xl SRAM 200-450 18 +5 V MCM6641
IM7141L 4096 Xl SRAM 200-450 18 +5 V MCM66L41
ITT
ITT4027 4096 X 1 DRAM 120·250 16 +12, ±5 V MCM4027A
ITT4116 16,384 X 1 DRAM 150·300 16 +12, ±5 V MCM4116
MIC
MIC2316E 2048 X 8 SROM 350 24 +5 V MCM68A316E
MIC2332 4096 X 8 SROM 350 24 +5V MCM68A332
MOSTEK
MK2708 1024 X 8 EPROM 450 24 +12, ±5 V MCM2708
MK2716 2048 X 8 EPROM 450 24 +5 V MCM2716
MK4027. 4096 X 1 DRAM 120-250 16 +12,±5V MCM4027A
MK4096 4096 X 1 DRAM 250·350 16 +12, ±5 V MCM4096
MK4104 4096 X 1 DRAM 200-450 18 +5 V MCM6641
MK4114 1024 X 4 SRAM 200-450 18 +5 V MCM2114
MK4116 16,384 X 1 DRAM 150·300 16 +12, ±5 V MCM4116A
MK30000 1024 X 8.SROM 350 24 +5 V MCM68A308
MK31000 2048 X 8 SROM 350 24 +5 V MCM68A316A
MK32000 4096 X 8 SROM 350 24 +5V MCM68A332
MK34000 2048 X 8 SROM 350 24 +5 V MCM68A316E
MK36000 8192 X 8 SROM 350 24 +5 V MCM68A364
MK36000-4 8192 X 8 SROM 250 24 +5V MCM688364
NATIONAL
MM2114 1024 X 4 SRAM 200·450 18 +5 V MCM2114
MM2147 4096 Xl SRAM 55-85 18 +5 V MCM2147
MM2708 1024 X 8 EPROM 450 24 +12, ±5 V MCM2708
MM2716 2048 X 8 EPROM 450 24 +5 V MCM2716
MM5235 8192 X 8 SROM 350 24 +5 V MCM68A364
MM5257 4096 Xl SRAM 200-450 18 +5 V MCM6641
MM5257L 4096 Xl SRAM 200·450 18 +5 V MCM66L41
MM5290 16,384 X 1 DRAM 150·300 16 +12, ±5 V MCM4116A
NEC/EA
IlPD414A 4096 X 1 DRAM 150·250 16 +12, ±5 V MCM4027A
IlPD414 4096 X 1 DRAM 250·350 16 +12, ±5 V MCM4096
IlPD416 16,384 X 1 DRAM 150·300 16 +12, ±5 V MCM4116A
IlPD2114L 1024 X 4 SRAM 200-450 18 +5 V MCM21 L14
IlPD2147 4096 Xl SRAM 55-85 18 +5 V MCM2147
IlPD2716 2048 X 8 EPROM 450 24 +5 V MCM2716
IlPD4104 4096 Xl SRAM 200-450 18 +5 V MCM66L41
IlPD5101 256 X 4 SRAM 450·800 22 +5V MCM145101
IlPD6508 1024 Xl SRAM 300-460 16 +5 V MCM146508
EA2308/8308 1024 X 8 SROM 350 24 +5 V MCM68A308
IlPD or
EA2316A/8316A 2048 X 8 SROM 350 24 +5 V MCM68A316A
IlPD or
EA2316E/8316E 2048 X 8 SROM 350 24 +5 V MCM68A316E
EA2708 1024 X 8 EPROM 450 24 +12,±5V MCM2708
IlPD or EA2716 2048 X 8 EPROM 450 24 +5 V MCM2716

1~9
I ORGANIZA'TlON
MOTOROLA'S
ACCESS TIME NO.OF POWER MOTOROLA PIN·TO·PIN
PART NUMBER DESCRIPTION (ns max) PINS SUPPLIES REPLACEMENT
NITRON
NC6570 128 X (9 X 7) SROM 350 24 +5 V MCM66700
NC6571 128 X (9 X 7) SROM 350 24 +5 V MCM66710
NC6572 128 X (9 X 7) SROM 350 24 +5V MCM66720
NC6573 128 X (9 X 7) SROM 350 24 +5V MCM66730
NC6574 128 X (9 X 7) SROM 350 24 +5 V MCM66740
NC6575 128 X (9 X 7) SROM 350 24 +5V MCM66750
NC6832 2048 X 8 SROM 550 ,24 +12,-+5V MCM6832
SIGNETICS
2607 1024 X 8 SROM 350 24 +5 V MCM68A308
2608 1024 X 8 SROM 350 24 +5 V MCM68A3OA
2609 128 X (9 X 7) SROM 350 24 +5 V MCM66700
2660 4096 X 1 DRAM 120-250 ·16 +12, ±5 V MCM4027A
2614 1024 X 4 SRAM 200450 18 +5 V MCM21L14
261.6 2048 X 8 SROM 350 24 +5 V MCM68A316E
2633 4096 X 8 SROM 350 24 +5 V MCM68A332
2664 8192 X 8 SROM 350 24 +5 V ( MCM68A364
2690 16,384 X 1 DRAM 250-350 16 +12,±5V MCM4116A
2708 1024 X 8 EPROM 450 24 +12, ±5 V MCM2708
2716 2048 X 8 EPROM 450 24 +5 V MCM2716
4027 4096 X 1 DRAM 150-250 16 +12, ±5 V MCM4027A
5101 256 X 4 SRAM 450-800 ,22 +5 V MCM145101
SYNERTEK
SY2114 1024 X 4 SRAM 200450 18 +5 V MCM21 L14
SY2147 4096 X 1 SRAM 55-85 18 +5 V MCM2147
SY2316A 2048 X 8 SROM 350 24 +5 V MCM68A316A
SY2316B 2048 X 8 SROM 350 24 +5 V MCM68A316E
SY2716 2048 X 8 EPROM 450 24 +5 V MCM2716
SY5101 256 X 4 SRAM 450-800 22 +5 V MCM145101
-.-
TEXAS INSTRUMENTS
,TMS 2516 2048 X 8 EPROM 450 24 +5 V MCM2716
TMS 2708 1024 X 8 EPROM 450 24 +12, ±5 V MCM2708
TMS 2716 2048 X 8 EPROM 450 24 +12, ±5 V TMS 2716
TMS 4027 4096 X 1 DRAM 120-250 16 +12, ±5 V MCM4027A
TMS4044 4096 X 1 SRAM 200-450 18 +5 V MCM6641
TMS 4045 1024 X 4 SRAM 200450 18 +5 V MCM2114
TMS 4116 16,384 X 1 DRAM 150-300 16 +12, ±5 V MCM4116A
TMS 4700 1024 X 8 SROM 350 24 +5 V MCM68A308
TMS 4732 4096 X 8 SROM 350 24 +5 V MCM68A332

Part Number Guide---------------------...:.----------

Directly 6800
G,",,;o P'~P~7""O' - 450 m MPU com~ 1m)V,,,'oo

/68~
MCM21 L14P45

//-~
Motorola MOS Lo~wer Package Type Motorola MOS Access Time Designator
Memory Prefix Version P = Plastic Memory Prefix No Letter = ;;;, 450 ns
L = Side Bl'!!ze A = ';;;350 ns
C = Cerdip Frit-Seal Ceramic B = ';;;250 ns

1-10
 NMOS Memories
RAM, EPROM, ROM II

2-1
2-2
 ® MOTOROLA
MCM2114
MCM21L14

4096-BIT STATIC RANDOM ACCESS MEMORY

MOS
The MCM2114 is a 4096-bit random access memory fabricated IN-CHANNEL, SILICON-GATE)
with high density, high reliability N-channel silicon-gate technology.
For ease of use, the device operates from a single power supply,
is directly compatible with TTL and DTL, and requires no clocks
or refreshing because of fully static operation. Data access is par-
ticularly simple, since address setup times are not required. The
4096·BIT STATIC
RANDOM ACCESS
MEMORY
II
output data has the same polarity as the input data.
The MCM2114 is designed for memory applications where
simple interfacing is the design objective. The MCM2114 is as-

~
sembled in 18-pin dual-in-line packages with the industry standard
pin-out. A separate chip select (8) lead allows easy selection of

~ ~ ~ ~ p~snc
an individual package when. the three-state outputs are 0 R-tied.
PSUFFIX
The MCM2114 series has a maximum current of 100 mAo Low
power versions (i.e., MCM21 L14 series) are available with a maxi-
ij PACKAGE
CASE 707
mum current of only 70 mAo
• 1024 Words by 4-Bit Organization

)~'X
• Industry Standard 18-Pin Configuration
• Single +5 Volt Supply
• No Clock or Timing Strobe Required
• Fully Static: Cycle Time = Access Time
CERAMIC PACKAGE
• Fully TTL/DTL Compatible
CASE 680
• Common Data Input and Output
• Three-State Outputs for OR-Ties
• Low Power Version Available PIN ASSIGNMENT

'r~l"
MAXIMUM ACCESS TIME/MINIMUM CYCLE TIME A6 Vcc
MCM2114-20 MCM2114-30 A5 2 17 A7
200 ns 300 ns
MCM21L14-20 MCM21 L 14-30 A4 3 16 A8
MCM2114-25 MCM2114-45
250 ns 450 ns A3 4 15 A9
MCM21 L14-25 MCM21L14-45

'L
AO 14 1/01

15 Al 13 1/02
A9
Vec = Pin 18 12 1/03
A2
A4
Vss=Pin9
Memory Array S 11 1/04
A5 Row
A6
1
Select
64 Row
, 64 Columns
VSS 9 -----.J 10 IN
17
A7 BLOCK DIAGRAM
16
A8

14
/101
13
1102
PIN NAMES

AO-A9 Address Input

W Write Enable
S Chip Select
1101-1/04 Data I nputlOutput
Vee Power (+5 V)
VSS Ground

2-3
 MCM2114, MCM21 L 14

ABSOLUTE MAXIMUM RATINGS (See Note 1)

Rating Value Unit
This device contains circuitry to protect the
Temperature Under Bias -10to+80 °c inputs against damage due to high static voltages
Voltage on Any Pin With Respect to VSS -0.5 to +7.0 Vdc or electric fields; however, it is advised that
normal precautions be taken to avoid applica·
DC Output Current 5.0 mA

I
tion of any voltage higher than maximum rated
Power Dissipation 1.0 Watt voltages to this high-impedance circuit.
Operating Temperature Range o to +70 °c
Storage Temperature Range -65 to +150 °c
Note: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted
to RECOMMENDED OPERATING CONDITIONS. Exposure to
higher than recommended voltages for extended periods of time could
affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(T A =0° to 70°C, Vee =5.0V ±5%, unless otherwise noted.)

RECOMMENDED DC OPERATING CONDITIONS

MCM2114 MCM21 L 14
Parameter Symbol Min Nom Max Min Nom Max Unit
Input Load Current III 10 10 }1A
(All Input Pins, Yin = 0 to 5.5 V)
I/O Leakage Current IILOI 10 10 }1A
(S= 2.4 V, VIIO'=O.4 V to VCC)
Power Supply Current ICCl 80 95 65 mA
(Vin ~ 5.5,11/0 = 0 mA, T A = 25 0 C)
Power Supply Cur.rent ICC2 100 70 mA
(Vin = 5.5 V, 11/0 = 0 mA, TA = OoC)
I nput Low Voltage VIL -0.5 0.8 -0.5 0.8 V
Input High Voltage VIH 2.0 6.0 2.0 6.0 V
Output Low Current 10L 2.1 6.0 2.1 6.0 mA
VOL =O.4V
Output High Current 10H -1.4 -1.0 -1.4 -1.0 mA
VOH = 2.4 V
Output Short Circuit Current lOS (2) 40 40 mA

Note: 2. Duration not to exceed 30 seconds.

CAPACITANCE
(f = 1 .0 MHz, T A = 25°C, periodically sampled rather than 100% tested.)

Characteristic Symbol Max Unit

Input Capacitance (V in = 0 V) Cin 5.0 pF
Input/Output Capacitance (VI/O = 0 V) CliO 5.0 pF

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and tem'perature unless otherwise noted.)

Input Pulse Levels . . . 0.8 Volt to 2.4 Volts

Input Rise arid Fall Times .. 10 ns
Input and Output Timing Levels 1.5 Volts
Output Load. 1 TTL Gate and CL = 100 pF

2-4
MCM2114, MCM21 L 14

AC OPERATING CONDITIONS AND CHARACTERISTICS

Read (Note 3). Write (Note 4) Cycles

RECOMMENDED AC OPERATING CONDITIONS (TA 0·0 to 70°C, Vee = 5.0 V ± 5%)

MCM2114-20 MCM2114-25 MCM2114-30 MCM2114-45
MCM211.14-20 MCM21 L 14-25 MCM21 L 14-30 MCM21 L 14-45
Parameter Symbol Min Max Min Max Min Max Min Max Units

II
Read Cycle Time tRC 200 250 300 450 ns

Access Time tA 200 250 300 450 ns

---_._---------
Chip Selection to Output Valid 100 120 ns
tso 70 85
Chip Selection to Output Active tsx 20 20 20 20 ns

Output 3·State From Oeselection tOTO 60 70 80 100 ns

Output Hold From Address Change tOHA 50 50 50 50 ns

Write Cycle Time twe 200 250 300 450 ns

Write Time tw 120 135 150 200 ns

Write Release Time tWR 0 0

---_._.._-_._._-----_.
Output 3-State From Write tOTW 60 70 80 100
Data to Write Time Overlap tow 120 135 150 200 ns
-----------~-

Data Hold From Write Time tOH 0 0 0 0 ns

Notes: 3. A Read occurs during the overlap of a low S and a high W.

4. A Write occurs during the overlap of a low S and a low W.

READ CYCLE TIMING (Note 5) WRITE CYCLE TIMING (Notes 6 and 7)

- - - - - twe -----.-j

Address
__JI~------------------------JI'----_
Il.ddress
__J~____- - - -__ -----------+--JI'------

DOllt ------------~---__1~===~
Note: 5. W is high for a Read cycle.

Notes: 6. If the S low transition occurs simultaneously with the

W low transition, the output buffers remain in a
high-impedance state.
7. IN must be high during all address transitions.
WAVEFORMS
Waveform Input Output
Symbol

MUST BE WILL BE
VALID

CHANGE WILL CHANGE

~ FROM H TO L FROM H TO L

CH"'NGE WILL CHANGE

-.!llll7 FROM LTD H FROM L TO H

~ON'T CARE CHANGING

~ ANY CHANGE
PERMITTED
STATE
UNKNOWN

==>- HIGH
IMPEDANCE

2-5
MCM2114, MCM21 L 14

TYPICAL CHARACTERISTICS

SUPPL Y CURRENT versus SUPPLY VOLTAGE SUPPL Y CURRENT versus AMBIENT TEMPERATURE
80 75

70
~
;;{ ;;{
E
75
E ............

~
..............

- I
........

--
65 .........
a:
I'......

-
::>
u 70

--
~
~ ~ .............
~
~ 65
k-- fo- i
~
60

--
~
...............
55

-'-'-'

60 50
4.5 4.75 5.0 5.25 5.5 o 20 40 60 80
Vee, SUPPLY VOLTAGE (VOLTS) TA, AMBIENT TEMPERATURE (Oe)

OUTPUT SOURCE CURRENT versus OUTPUT VOLTAGE OUTPUT SINK CURRENT versus OUTPUT VOL TAGE
8.0 9.0

7.0
1\

1\ 8.0
I
6.0
\
\ 7.0

!
I ,

\ /
;;{
\ «
6.0

I
E 5.0
E

Iw
u ~
f-
Z
a:
a:
::>
u
5.0
/

/
a: 4.0
""z
\
::>
0
CJ)
u;

~
~
4.0

~
:i:
E
3.0 \
\ 0
~

3.0
V
2.0 \
\
2.0

/
I
1.0 \ I
\ 1.0

I
o
1.0 2.0 3.0 4.0

'"
VOH, OUTPUT VOLTAGE (VOLTS)
5.0 6.0
o
o 0.1 0.2 0.3 0.4
VvL, OUTPUT VOlTAGE (VO LTS)
0.5 0.6

2-6
MCM2114, MCM21 L 14

NORMALIZED ACCESS TIME versus TEMPERATURE TYPICAL ACCESS TIME versus TEMPERATURE

1.0
/
170
v
/
! 0.95
/
--
160
/
- ;::
:E

en
/" /
§ 0.90 .... v
:E
;:: /v
« ~ 150
CI

~ 0.85
.... V « ./
V
« V
:J. V

•
~ 140 L
Z
:J.
0.80
~
- ----t-o
0.7 5 130
o 20 40 60 80 20 40 60 80 90
TA, TEMPERATURE (DC) TA, TEMPERATURE (DC)

MCM2114/MCM21 L14 BIT MAP

PIN 18
PIN 1 Vee
D o
1023 l1li(: 1008 1023 l1li(: 1008 1023 III: 1008 1023 lilt 1008
1007 1007 1007 1007

1/° 3 (PIN NO. 12) 1/° 4 (PIN NO.l1) 1/° 1 (PIN NO. 14) 1/° 2 (PIN NO. 13)

16 16 16 16
15 lilt ~ 15 III: 0 15 l1li(: 0 15 III: 0

To determine the precise location on the die of a word in memory, reassign address numbers to the address pins as
in the table below. The bit locations can then be determined directly from the bit map.

REASSIGNED REASSIGNED
PIN NUMBER ADDRESS NUMBER PIN NUMBER ADDRE-SS NUMBER
A6 6 Al
2 A5 7 A2
3 A4 15 AS
4 A3 16 AS
5 AD 17 A7

2-7
 ® MOTOROLA MCM2115A
MCM2125A
Product Previe'W'
MOS
(N·CHANNEL, SILICON·GATE)

1024 X 1 STATIC RAM

II The MCM2115A and MCM2125A families are high-speed, 1024 words

by one-bit random-access memories fabricated using HMOS, high-per-
formance N-channel silicon-gate technology. Both open collector (MCM
2115A) and three-state output (MCM2125A) are- available. The devices
1024-BIT STATIC
RANDOM ACCESS
MEMORY

use fully static circuitry throughout and require no clocks or refreshing

to operate. Data out has the same polarity as the input data.
Access times are fully compatible with the industry-produced 1 K
Bipolar RAMs, yet offer 20% to 50% reduction in power over their Bipolar
equ ivalents.
All inputs and outputs are directly TTL compatible. A seperate chip L SUFFIX
select allows easy selection of an individual device when outputs are CERAMIC PACKAGE
CASE 690
OR-tied.
• Organized as 1024 Words of 1 Bit
•
•
•
Single +5 V Operation
Maximum Access Time = 45 ns and 70 ns
low Operating Power Dissipation
.,.".
1J"Yt~ll ~ ~. ~
1 C SUFFIX
FRIT SEAL
CERAMIC PACKAGE
CASE 620
BLOCK DIAGRAM

WORD 32 X 32
DRIVER ARRAY PIN ASSIGNMENT

S 1~ 16 Vec
AO ~ 16 0
SENSE AMPS
CONTROL
A1 h14 W
AND
LOGIC
a 4 13 Ag
WRITE A2

A3 ~ 12 AS

A4 6 ~ 11 A7

ADDRESS
a ~ 10 A6
DECODER Vss 8 ~ 9 AS

PIN NAMES
A . . . . . . . . . . . . . . . . Address
D . . . . . . . . . . . . . . Data input
SiND Q ... " ......... Data Output
S .............. Chip Select
V CC . . . . . . . . . . . +5 V Supply
TRUTH TABLE VSS . . . . . . . . . . . . . " Ground
OUTPUT OUTPUT W. . . .. " " " . " . " . Write Enable
INPUTS 2115A FAMILY 2126A FAMILY
S W D Q Q MODE
This device contains circuitry to protect the
H X X H Hi-Z NOT SELECTED inputs against damage due to high static volt-
L L L H Hi-Z WRITE "0" ages or electric fields; however, it is advised that
L L H H Hi-Z WRITE"1" normal precautions be taken to avoid applica-
L H X Data Out Data Out READ tion of any voltage ·higher than maximum ratl;d
voltages to this high irnpl!dance circuit.

This is advance information and specifications are subject to change without notice.

2-8
 ® MOTOROLA MCM2147

Advance InforIllation
MOS
4096-BIT STATIC RANDOM ACCESS MEMORY (N-CHANNEL, SILICON-GATE),
The MCM2147 is a 4096-bit static random access memory
organized as 4096 words by l-bit using Motorola's N-channel sil icon-
gate MOS technology_ It uses a design approach which provides the
simple timing features associated with fully static memories and
the reduced standby power associated with sllmi-static and dynamic
memories_ This means low standby power without the need for
4096-BIT STATIC
RANDOM ACCESS
MEMORY
II
clocks, nor reduced data rates due to cycle times that exceed access
times_
E controls the power-down feature_ It is not a clock but rather C SUFFIX
FRIT-SEAL
a chip select that affects power consumption_ In less than a cycle
CERAMIC PACKAGE
time after E goes high, deselect mode, the part automatically reduces also available
its power requirements and remains in this low-power standby mode
as long as E remains high_ This feature results in system power
savings as great as 85% in larger systems, where most devices are
deselected_ The automatic power-down feature causes no perfor-
mance degradation.
The MCM2147 is in an 18 pin dual in-line package with the
industry standard pinout. It is TTL compatible in all respects_ The
data out has the same polarity as the input data. A data input and
a separate three-state output provide flexibility and allow easy
OR-ties. P SUFFIX
PLASTIC PACKAGE
• Fully Static Memory - No Clock or Timing Strobe Required CASE 707

• Single +5 V Supply
• High Density 18 Pin Package
• Automatic Power-Down PIN ASSIGNMENT
• Directly TTL Compatible-All Inputs and Outputs
______ r - - -
• Separate Data I nput and Output
AO 0 18 VCC
• Three-State Output
Al 17 A6
• Access Time - MCM2147-55 = 55 ns max
MCM2147-70 = 70 ns max A2 16 A7

MCM2147-85 = 85 ns max A3 4 15 A8
MCM2147-100 = 100 ns max
A4 14 A9

A5 13 Al0
BLOCK DIAGRAM
Q 12 All
AO
W 8 [ 11 D
VCC: Pin 18
Al [ 10 E
VSS 9
A2 • Memory Array
VSS ~ Pin 9

A6
17
Row
Select • 64 Row
PIN NAMES
A7
16 • 64 Columns

Address Input
AO-All
15
A8
w Write Enable
Chip Enable
11
D Q D Data Input
Q Data Output

VCC Power (+5 V)

VSS Ground

TRUTH TABLE

E W Mode Output Power

H X Not Selected High Z Standby
L Write High Z Active
A3 A4 A5 A9Al0All
H Read Data Out Active

This is advance information and specifications are subject to change without notice.

2-9
 MCM2147

ABSOLUTE MAXIMUM RATINGS (See Note 1)

Rating Value Unit This device contains circuitry to protect the
Temperature Under Bias -10 to +85 °c inputs against damage due to high static voltages
Voltage on Any Pin With Respect to VCC -0.5 to +7.0 Vdc or electric fields; however, it is advised that
normal precautions be taken to avoid applica-
DC Output Current 20 mA
tion of any voltage higher than maximum rated
Power Dissipation 1.0 Watt voltages to this high-impedance circuit.

II Operating Temperature Range

Storage Temperature Range
o to +70
-65to+150

Note: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM

RATINGS are exceeded. Functional operation should be restricted
°c
°c

to RECOMMENDED OPERATING COND·ITIONS. Exposure to

higher than recommended voltages for extended periods of time could
affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS (TA = 0 to 70 0 C, VCC = 5.0 V ± 5% unless otherwise noted.)
MCM2147-55 MCM2147-70 MCM2147-85 MCM2147-100
Parameter Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit
I nput Load Current IlL - 0.01 10 - 0.01 10 - 0.01 10 - 0.01 10 IJ.A
(All Input Pins, Vin = 0 to 5.5 V)
Output Leakage Current IOL - 0.1 50 - 0.1 50 ~
0.1 50 - 0.1 50 IJ.A
(E = 2.0 V, V out = 0 to 5.5 V)
Power Supply Current ICC1 - 120 170 - 100 150 - 95 130 - 90 110 mA
(E = V I L, Outputs Open, T A = 25 O C)
Power Supply Current ICC2 - - 180 - - 160 - - 140 - - 120 mA
(E = VIL, 'Outputs Open, T A = OoC)
Standby Current ISB - 15 30 - 10 20 - 15 25 - 10 20 mA
(E = VIH)
Input Low Voltage VIL -0.3 - 0.8 -0.3 - 0.8 -0.3 - 0.8 -0.3 - 0.8 V
Input High Voltage VIH 2.0 - 6.0 2.0 - 6.0 2.0 - 6.0 2.0 - 6.0 V
Output Low Voltage VOL - - 0.4 - - 0.4 - - 0.4 - - 0.4 V
tlOL = 8.0 mAl
Output High Voltage VOH 2.4 - - 2.4 - - 2.4 - - 2.4 - - V
(IOH = -4.0 mAl
0
TYPical values are for T A = 25 C and VCC = +5.0 V.

FIGURE 1 - OUTPUT LOAD

CAPACITANCE
(f = 1.0 MHz, T A = 25 0 C, periodically sampled rather than 100% tested.) Vee
Characteristic Symbol Max Unit
Input Capacitance (V in =0 V) Cin 5.0 pF 510
Output Capacitance (V out = 0 V) Cout 10 pF
Q -----.~-------.
Capacitance measured with a Boonton Meter or effective capacitance calculated
30 pF
lilt 300 ;::;;: (Including
from the equation: C = IlV' scope and jig)

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature unless otherwise noted.)

Input Pulse Levels . . . . . . . o Volt to 3.5 Volts

Input Rise and Fall Times .. 10 ns
Input and Output Timing Levels . . 1.5 Volts
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1
MCM2147

AC OPERATING CONDITIONS AND CHARACTERISTICS, Read, Write Cycles (TA = 0 to 70 0 e, Vec = 5.0 V ± 5%)

Parameter
Address Valid to Address Don't Care
(Cycle Time When Chip Enable is Held Active)
Chip Enable Low to Chip Enable High
Symbol
tAVAX

tAVOV
MCM2147-55
Min
55

-
Max
-

55
MCM2147-70
Min
70

-
Max
-

70
MCM2147-85 MCM2147-100
Min
85

-
Max
-

85
Min
100

-
Max

100
-
Unit
ns

ns
II
Address Valid to Output Valid (Access) tELOV1* - 55 - 70 - 85 - 100 ns
Chip Enable Low to Output Valid (Access) tELOV2* - 65 - 80 - 95 - 110 ns
Address Valid to Output Invalid tAVOX 10 - 10 - 10 - 10 - ns
Chip Enable Low to Output Invalid tELOX 10 - 10 - 10 - 10 - ns
Chip Enable High to Output High Z tEHOZ 0 40 0 40 0 40 0 40 ns
Chip Selection to Power-Up Time tpu 0 - 0 - 0 - 0 - ns
Chip Deselection to Power-Down Time tPD 0 30 0 30 0 30 0 30 ns
Address Valid to Chip Enable Low (Address Setup) tAXEL 0 - 0 - 0 - 0 - ns
Chip Enable Low to Write High tELWH 45 - 55 - 70 - 80 - ns
Address Valid to Write High tAVWH 45 - 55 - 70 - 80 - ns
Address Valid to Write Low (Address Setup) tAVWL 0 - 0 - 0 - 0 - ns
Write Low to Write High (Write Pulse Width) tWLWH 35 - 40 - 55 - 65 - ns
Write High to Address Don't Care tWHAX 10 - 15 - 15 - 15 - ns
Data Valid to Write High tDVWH 25 - 30 - 45 - 55 - ns
Write High to Data Don't Care (Data Hold) tWHDX 10 - 10 - 10 - 10 - ns
Write Low to Output High Z tWLOZ 0 30 0 35 0 45 0 50 ns
Write High to Output Valid tWHOV 0 - 0 - 0 - 0 - ns

*tELOVl is access from chip enable when the 2147 is deselected for at least 55 ns prior to this cycle. tELOV2 is access from chip enable for
o ns < deselect time < 55 ns. If deselect time = 0 ns, then t E LOV = tAVOV.

TIMING PARAMETER ABBREVIATIONS TIMING LIMITS

I II
t X X X X The table of timing values shows either a minimum or
,;,n,1 n,m, "om whkh ;n"~" ;, d,';n,d-.J a maximum 'Iimit for each parameter. Input requirements
transition direction for first signal are specified from the external system point of view.
signal name to which interval is defined Thus, address setup time is shown as a minimum since the
transition direction for second signal system must supply at least that much time (even though
most devices do not require it). On the other hand,
The transition definitions used in this data sheet are: responses from the memory are specified from the device
H = transition to high point of view. Thus, the access time is shown as a maxi-
L = transition to low mum since the device never provides data later than
V = transition to valid that time.
X = transition to invalid or don't care
Z = transition to off (high impedance)
 MCM2147

READ CYCLE TIMING 1

ie Held Low)
ADDRESS
§e---::-------- tAVAX

l-----V,H
----------- ='AV~:~----~·
- ~------ VI L

II
Q (Data out)-------P-r-ev-io-u-s-D-a-t-a-V-a""iid---<:rn"O"'l:'T"!:"1.L~---------D-a-t-a-v-a-1i - d - - - - - - - - V OH
---------------------~~~~JI'~-------------------------~-VOL

READ CYCLE TIMING 2

---1 _tAVEL

ADDRESS y. X Xx i:>(lJ. Address Valid

tELEH ~

~:~~
tELQV -tEHQZi
--tELQX-.j
VOH
Q (Data out) - - - - - - - - - - - HI Z ~ Data Valid )-HI Z- VOL

VCC
:~~--u-~-:~r= ~1...L.oL.&J,.l~---~-t-...JPD [

Supply
Current

NOTE: ViI is high for Read Cycles,

WRITE CYCLE TIMING

~----------------tAVAX----------------~

--~Ir-----------------------------------~v-------VIH
ADDRESS __-JI'-_______________________________-JI'-_______ VIL

~-------tELWH------------~

I,........,...,,....,..........,....,....,....,...,....,...,,....,.......,....,. VIH
.E
~~~~------------------------~~~~~~~~. .~ VIL

twLQZ 1".\ tWHQV

Q (Data out)XXXXXXXXX y"";,""H,...e,...li,...~e.,..~d.,...:~"X"t:'''lM<'..,.....,.."'l('''lI:~ HI Z -----f~_-.-_

"""""""""""''''''''''''''''''''''''''''i}"'''';''"'ta''''' VOH
- ~ - 7 VOL
Data out = Data in

WAVEFORMS '
Waveform Input Output
Symbol

MUST BE WILL BE
VALID VALID

CHANGE WILL CHANGE

~ FROM H TO L FROM H TO L

'CHANGE WILL CHANGE

~ FROM L TO H FROM L TO H

DON'T CARE CHANGING

~ ANY CHANGE
PERMITTED
STATE
UNKNOWN

==>-- HIGH
IMPEDANCE

2-12
MCM2147

FIGURE 2 - AVERAGE DEVICE DISSIPATION

DEVICE DESCRIPTION versus MEMORY SIZE

The MCM2147 is produced with a high-performance

MaS technology which combines on-chip substrate bias ICC
generation with device scaling to achieve high speed.
The speed-power product of this process is about four
times better than earl ier MaS processes.
This gives the MCM2147 its high speed, low power and
ease-of-use. The low-power standby feature is controlled
with the E input. E is not a clock and does not have to
be cvcled. This allows the user to tie E directly to system
addresses and use the Iine as part of the normal decoding
logic. Whenever the MCM2147 is deselected, it auto-
matically reduces its power requirements.

SYSTEM POWER SAVINGS

The automatic power-down feature adds up to signi-
ficant system power savings. Unselected devices draw low
standby power and only the active devices draw active IS8 L-.J--:":-:-:----::':-::,.---------:-:-:'
4K 8K 16K 32K 64K
power. Thus the average power consumed by a device MEMORY SIZE IN WORDS
declines as the system size increases, asymptotically
approaching the standby power level as shown in Figure 2.
The automatic power-down feature is obtained without
any performance degradation, since access time from chip FIGURE 3 - PC LAYOUT
enable is ,;;;; access time from address valid. Also the fully
Gnd
static design gives access time equal cycle time so multiple Vee r---s:;Tk---'
read or write operations are possible during a single select ~ ~ _ _Decouple,
_ _ _ _ _ ..J
period. The resultant data rates ar.e 14.3 MHz and 18 MHz
for the MCM2147-70 and MCM2147-55 respectively.

DECaUPLING AND BOARD LAYOUT

--- -- --- -- -- ---
-- - -- - - --
CONSIDERATIONS
The power switching characteristic of the MCM2147
requires careful decoupling. It is recommended that a

~ ~~ ~~
0.1 /-IF to 0.3 /-IF ceramic capacitor be used on every

~
other device, with a 22 /-IF to 47 f.1F bulk electrolytic
decoupler every 16 devices. The actual values to be used
will depend on board layout, trace widths and duty cycle.
Power supply gridding is recommended for PC board
layout. A very satisfactory grid can be developed on
a two-layer board with vertical traces on one side and
horizontal traces on the other, as shown in Figure 3.
If fast drivers are used, terminations are recommended
on input signal Iines to the MCM2147 because significant
reflections are possible when driving their high impedance
inputs. Terminations may be required to match the
impedance of the line to the driver.

2-13
 ® MOTOROLA MCM4027A

4096-BIT DYN~MIC RANDOM ACCESS MEMORY MOS

(N·CHANNEL, SILICON·GATE)

II The MCM4027A is a 4096 x 1 bit high-speed dynamic Random

Access Memory. It has smaller die size than the MCM4027 pro-
viding improved speed selections. The MCM4027 A is fabricated
using Motorola's highly reliable N-channel sil icon-gate technology.
By multiplexing row and column address inputs, the MCM4027 A
4096-BIT DYNAMIC
RANDOM ACCESS
MEMORY
requirp.s only six address lines and perm its packaging in Motorola's
standard 16-pin dual-in-line packages. Complete address decoding is
done on chip with address latches incorporated.
All inputs are TTL compatible, and the output is 3-state TTL
compatible. The MCM4027 A incorporates a one-transistor cell
design and dynamic storage techniques, with each of the 64 row
addresses requiring a refresh cycle every 2.0 milliseconds.

• Maximum Access Time '= 120 ns - MCM4027AC1

150 ns - MCM4027 AC2 C SUFFIX
200 ns - MCM4027 AC3 FRIT-SEAL PACKAGE
CASE 620
250 ns - MCM4027AC4
• Maximum Read and Write Cycle Time =
320 ns - MCM4027AC1, C2
375 ns - MCM4027 AC3, C4
• Low Power Dissipation - 470 mW Max (Active) PIN ASSIGNMENT
27 mW Max (Standby)
VSB 1 (r:-v- 16 VSS
• 3-State Output for OR-Ties
D,~ 2 [ ~ 15 CAS
• On-Chip Latches for Address, Chip Select, and Data In
• Power Supply Pins on Package Corners for Optimum Layout WE ~ 14 D out

• Industry Standard 16-Pin Package RAS 4 13 cs

• Page-Mode Capability AO 12 A3

• Compatible with the Popular 2104/MK4096/MCM6604 A2 11 A4

• Second Source for MK4027 A1 10 AS

VDO 8 I ~ 9 Vce

TRUTH TABLE

Inputs Data Out

Cycle Power Ref Function
RJ(S CAS ~ m Previous Interim Present
L L L L Valid data High Imp. Input data Full-operating Yes Write cycle
L L L H Valid data High Imp. Valid data (cell) Full-operating Yes Read cycle
L L H X Valid data High Imp. High Imp. Full-operating Yes Deselected-refresh
L H X X Valid data Valid data Valid data Reduced operating Yes RAS only-refresh
H L X X Valid data High Imp. High Imp. Standby No Standby-output disabled
H H X X Valid data Valid data Valid data Standby No Standby-output valid
H = High, L = Low, X = Don't Care

2-14
MCM4027A

BLOCK DIAGRAM

E Write
Clocks
1
RAS Clocks
1
I
! i Data In
~~ata In

II
Buffer

~
Address
Clocks

! i
pLJ CAS
Clocks

I
~ Reset
J L
Data

•
Chip Select
'--
~
Enable
1
Data Out
Buffer
~
Out

Input Buffer

A5
+ -f---- Dummy Cells

A4 Address -f---- Memory Array

A3 Buffers
Row
A2
(6)
Decoder 64 Sense Refresh Amplifiers
I- 1-of- 2
Data Bus
A1 Rowand (1-of-64) Data In/Out GaHng
Select
1---+--
AO ~
Colul'nn

-f-----
•
I Memory
I
Array •
I
I
-r-- I Dummy Cells I
I T
L-1 Column Decoder
(1-of-32)

+ i f 1-

OPERATING CHARACTERISTICS

ADDRESSING DATA OUTPUT -',

The MCM4D27 A has six address inputs (AD-A5) and In order to simplify the memory system designed and
two clock signals designated Row Address Strobe (~) reduce the total package count, the MCM4D27 A contains
and Column Address Strobe (CAS). At the beginning of an input data latch and a buffered output data latch. The
a memory cycle, the six low ,order address bits AD through state of the output latch and buffer at the-end of a mem-
A5 are strobed into the chip with RAS to sele~~ one of ory c\(cle will depend on the type of memory cycle per-
the 64 rows. The row address strobe also initiates the tim- formed and whether the chip is selected or unselected for
ing that will enable the 64 column sense amplifiers. After that memory cycle,
a specified hold time, the row address is removed and the A chip will be unselected during a memory cycle if:
six high order address bits (A6-A 11) are placed on the (1) The chip receives both RAS and CAS signals,
address pins. This address is then strobed into the chip but no Chip Select signal.
with CAS. Two of the 64 column sense amplifiers are (2) The chip receives a CAS signal but no RAS
selected by A 1 through 'A5. A one of two data bus select signal. With this condition, the chip will be
is accomplished by AD' to complete the data selection. unselected regardless of the state of Chip
The Chip Select (CS) is latched into the port along with Select input.
the column addresses. If, during a read, write, or read-modify-write cycle,

2-15
 MCM4027A

the chip is unselected, the output buffer will be in the INPUT/OUTPUT LEVELS
high impedance state at the end of the memory cycle. All of the inputs to the MCM4027 A are TTL-compatible,
The output buffer will remain in the high impedance state featuring high impedance and low capacitance (5 to 7 pF).
until the chip is selected for a memory cycle. The three-state data output buffer is TTL-compatible and
For a chip to be selected during a memory cycle, it has sufficient curren~ sink capability. (3.2 mA) to drive
must receive the following signa~s: RAS, CAS, and Chip two TTL loads. The output buffer also has a separate

FI
Select. The state of the output latch and buffer of a VCC pin so that it can be powered from the same supply
seleCted chip during the following type of memory cycles as the logic being employed.
would be: .
REFRESH
(1) Read Cycle - On the negative edge of CAS,
the output buffer will unconditionally go to a In order to maintain valid data, each of the 64 internal
high impedance state. It will remain in this rows of the MCM4027 A must be refreshed once every 2 ms.
state until access time. At this time, the out- Any cycle in which a RAS signal occurs accomplishes a
put latch and buffer will assume the logic refresh operation. Any read, write, or read-modify-write
state of the data read from the selected cell. cycle will refms h an entire internally selected row. How-
This output state will be maintained until the ever, it a wr;t", or read-modify-write cycle is used to per-
chip receives the next CAS signal. form a refresh cycle the chip must be deselected to pre-
vent writing data into the selected cell. The memory can
(2) Write Cycle - If the WE input is switched to a also be refreshed by employing only the RAS cycle. This
logic 0 before the CAS transition, the output refresh mo~e will not shorten the refresh cycle time; how-
latch and buffer will be switched to the state ever, the system standby power can be reduced by approx-
of the data input at the end ofthe access time. imately 30%.
This logic state will be maintained until the If the RAS only refresh cycles are employed for an ex-
chip receives the next CAS signal. tended length of time, the output buffer may eventually
lose data and assume the high impedance state. Applying
(3) Read-Modify-Write - Same as read cycle.
CAS to the chip will restore activity of the output buffer.

POWER DISSIPATION
DATA INPUT Since the MCIVI4027A is a dynClmic RAM, its power
Data to be written into a selected storage cell of the drain will be extremely small during the time the chip is
memory chip' is first stored in the on-chip data latch. unselected.
The gating of this latch is performed with a combination The power increases when the chip is selected and
of the WE and CAS signals. The last of these signals to most of this increase is encountered on the add~ess
make a negative transition will strobe the data into the strobe edge. The circuitry of the MCM4027A is largely
latch. If' the WE input is switching to a logic b in the dynamic so power is not drawn during the whole time
beginning of a write cycle, the falling edge of CAS strobes the strobe is active. Thus the dynamic power is a function
the data into the latch. The data setup and hold times of the operating frequency rather than the active duty
are then referenced to the negative edge of CAS. cycle.
If a read-modify-write cycle is being performed, the In a memory systeM, the CAS signal must be supplied
WE input would not make its negative transistion until to all the memory chips to ensure that the outputs of
after the CAS signal was enabled. Thus, the data would the unselected chips are switched to the high impedance
not be strobed into th.e latch until the negative transistion state. Those chips that do not receive a RAS signal will
of WE. The data setup and hold times would now be ref- not dissipate any power on the CAS edge except for that
erenced to the negative edge of the WE signal. The only required to turn off the chip outputs. T,hus, in order to
other timing constraints Tor a write-type-cycle is that both ensure minimum system power, the RAS signal should be
the CAS and WE signals remain in the logic 0 state for' a decoded so that only the chips to be selected receive' a
sufficient time to accomplish the permanent storage of RAS signal. If the RAS signal is decoded, then the chip
the data into the selected cell. select input of all the chips can be set to a logic 0 state.

Circuit diagrams external to or containing Motorola products are included as a means of illustration only. Complete information
sufficient for construction purposes may not be fully illustrated. Although the information herein has been carefully checked and is believed
to be reliable, Motorola assumes no responsibility for inaccuracies. Information herein does not convey to the purchaser any license under
the patent rights of Motorola or others.
The information contained herein is for guidance only, with no warranty of any type, expressed or implied. Motorola reserves the right
to make any changes to the information and the product(s) to which the information applies and to discontinue manufacture of the
product (s) at any time.

2-16
MCM4027A

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted.)
RECOMMENDED OPERATING CONDITIONS (Referenced to VSS = Ground)
Parameter Symbol Min Typ Max Unit Notes
Supply Voltage VOO 10.8 12.0 13.2 Vdc 2
VCC VSS 5.0 VOO Vdc 3

II
VSS 0 0 0 Vdc 2
VBB -4.5 -5.0 -5.5 Vdc 2
Logic 1 Voltage, RAS, CAS, WRITE VIHC 2.4 5.0 7.0 Vdc 2,4
Logic 1 Voltage, all inputs except RAS, CAS, WR ITE VIH 2.2 5.0 7.0 Vdc 2,4
Logic 0 Voltaga, all inputs VIL -1.0 0 0.8 Vdc 2,4

DC CHARACTERISTICS (VOO = 12 V ~ 10% VCC =5 0 V ± 10% VBB = -5 0 V ± 10%, VSS =0 V, T A = 0 to 70 0 C.) Notes 1,5
Characteristic Symbol Min Typ Max Units Notes
Average VOO Power Supply Current 1001 35 mA 6
VCC Power Supply Current ICC mA 7
Average VBB. Power Supply Current IBB 250 /lA
Standby VOO Power Supply Current 1002 2 mA 9
Average VOO Power Supply Curtent during 1003 25 mA 6
"RAS only" cycles
Input Leakage Current (any input) II(L) 10 /lA 8
Output Leakage Current 10(L) 10 /lA 9,10
Output Logic 1 Voltage @ lout = -5 mA VOH 2.4 Vdc
Output Logic 0 Voltage @ lout = 3.2 mA VOL 0.4 Vdc

NOTES 1 throu!lh 11:

1. T A is specified for operation at frequencies to tRC;;' tRC(min). 6. Current is proportional to cycle rate. 1001 (max) is measured
Operation at higher cycle rates with reduced ambient temperatures at the cycle rate specified by tRC(min).
and higher power dissipation is permissible provided that all ac 7. ICC depends on output loading. Ouring readout of high level
parameters are met. data V CC is connected th rough a low impedance (135 51 typ) to
2. All voltages referenced to VSS. Data Out. At all other times ICC consists of leakage currents only.
3. Output voltage will swing from VSS to VCC when enabled, 8. All device pins at 0 volts except VSS which is at -5 volts and
with no output load. For purposes of maintaining data in standby the pin under test which is at +10 volts.
mode, VCC may be reduced to VSS without affecting refresh 9. Output is disabled (high-impedance) and RAS and CAS are
operations.or data retention. However, the VOH(min) specifica- both at a logic 1. Transient stabilization is required prior to
tion is not guaranteed in this mode. measurement of this parameter.
4. Device speed is not guaranteed at input voltages greater than
10.0V,;;VO ut ';;+10V.
TTL levels (0 to 5 v).
11. Effective capacitance is calculated from the equation:
5. Several cycles are required after power-up before proper
device operation is achieved. Any 8 cycles which perform refresh C = ~~ with ~V = 3 volts.
are adequate for this purpose.
EFFECTIVE CAPACITANCE (Full operating voltage and temperature range, periodically sampled rather than 100% tested) Note 11
Characteristic Symbol Max Unit
I nput Capacitance (AO-A5), Dill' CS Cin(EFF) 5.0 pF
RAS, CAS, WRITE 10.0
Output Capacitance Cout{EFF) 7.0 pF

ABSOLUTE MAXIMUM RATINGS (See Notes 1 and 2)

Rating Symbol Value Unit
Voltage on Any Pin Relative to VSS' Vin, V out -0.5 to +20 Vdc
Operating Temperature Range TA o to +70 °c
Storage Temperature Range -65 to +150 °c This device contains circuitry to protect the
Tstg
inputs against damage due to high static volt-
Output Current (Short Circuit) lout 50 mAdc
ages or electric fields; however. it is advised that
• (Vss - Vaa > 4.5 V) normal precautions be taken to avoid applica-
tion of any voltage higher than maximum rated
NOTE: Permanent device damage may occur if ASSOLUTE MAXIMUM RATINGS
voltages to this high impedance cirCUit.
ARE EXCEEDED. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages
for extended periods of time could affect device reliability. VSS must be applied
prior to VCC and VDD. VSS must also be the last power supply switched off.

2-17
 MCM4027A

AC OPERATING CONDITIONS AND CHARACTERISTICS

. (Read, Write, and Read-Modify-Write Cycles)

RECOMMENDED AC OPERATING CONDITIONS (VDD = 12 V, 10%, Vcc = 5.0 V! 10%, Vss = -5.0 V,: 10%, Vss ~ 0 V,

•
TA = 0 to 70 0 C,) Notes 1,5, 12,18

MCM4027AC1 MCM4027AC2 MCM4027AC3 MCM4027AC4

Parameter Symbol Min Max Min Max Min Max Min Max Units Notes
Random Read or Write Cycle Time 'RC 320 320 375 375 ns 13
Read Write Cycle Time RWC 320 320 375 375 ns 13
Page Mode Cycle Time PC 160 170 225 285 ns 13
Access Time From Row Address Strobe 'RAC 120 150 200 250 ns 14.16
Access Time From Column Address Strobe 'CAC 80 100 135 165 ns 15.16
Output Buffer and Turn-Off Delay 'OFF 35 40 50 60 ns
Row Address Strobe Precharge Time 'RP 100 100 120 120 ns
Row Address Strobe Pulse Width 'RAS 120 10.000 150 10.000 200 10.000 250 10.000 ns
Row Address Strobe Hold Time 'RSH 80 100 135 165 ns
Column. Address Strobe Pulse Width 'CAS' 80 100 135 165 ns
Column Address Strobe Hold Time 'CSH 120 150 200 250 ns
Row to Column Strobe Lead Time 'RCD 15 40 20 50 25 65 35 85 ns 17
Row Address Setup Time 'ASR 0 0 0 0 ns
Row Address Hold Time 'RAH 15 20 25 35 .ns
Column Address Setup Time 'ASC -5 -10 ·10 ·10 ns
Column Address Hold Time 'CAH 40 45 55 75 ns
Column Address Hold Time Referenced to RAS 'AR 80 95 120 160 ns
Chip Select Setup Time 'CSC 0 -10 ·10 ·10 ns
ChlQSelect Hold Time 'CH 40 45 55 75 ns
Chip Select Hold Time Referenced to RAS 'CHR 80 95 120 160 ns
Transition T,,\1e Rise and Fall 'T 3 35 3 35 3 50 3 50 ns 18
Read Command Setup Time 'RCS 0 0 0 0 ns
Read Command Hold Time 'RCH 0 0 0 0 ns
Write Command Hold Time 'wCH 40 45 55 75 ns
Write Command Hold Time Referenced to ~ 'WCR 80 95 120 160 ns
Write Command Pulse Width 'WP 40 45 55 75 ns
Write Command to Row Strobe Lead Time 'RWL 50 50 70 85 ns
Write Command to Column Strobe Lead Time 'CWL 50 50 70 85 ns
Data In Setup Time 'DS 0 0 0 0 ns 19
Data," Hold Time 'DH 40 45 55 75 ns 19
Data," Hold Time Referenced to RAS 'DHR 80 95 120 160 ns
Column to Row Strobe Precharge Time 'CRP 0 0 0 0 ns
Column Precharge Time 'CP 60 60 80 110 ns
Refresh Period 'RFSH 2 2 2 2 ms
Write Command Setup Time 'WCS 0 0 0 0 M

CAS to ~ Delay 'CWD 60 60 80 90 ns 20

RAS to ~ Delay 'RWD 100 110 145 175 ns 20
Data Out Hold Time 'DOH 10 10 10 10 /is

NOTES 12 through 20: 18.VIHC(min) or VIH(min) and VIL(max) are reference levels for
measuring timing of input signals. Also, transition times are
12. AC measurements assume tT = 5 ns.
measured between VIHC or VIH and VIL.
13. The specifications for tRc(min) and tRwc(min) are used only
19.These parameters are referenced to CAS leading edge in
to indicate cycle ·time at which proper operation over the fuji
random write cycles and to WRITE leading edge in delayed write
temperature range (O°C .;; T A .;; 70 0 C) is assured.
or read-modify write cycles.
14.Assumes that tRCD';; tRCO(max).
20. twcs, tCWO. and tRWO are not restl ictive operating para-
15.Assumes that tRCO '" tRCO (max). meters. They are included in the data sheet as electrical charac-
16. Measured with a load circuit equivalent to 2 TTL loads and terisitcs 'only: If twcs ;;, twcS(min), the cycle is an early write
100 pF. cycle and Data Out will contain the data written into the selected
17 .Operation within the tRCO(max) limit insures that tRAC(max) cell. If tCWD ;;, tCWD(min) and tRWO ;;, tRWO(min), the cycle is
can be met. tRCO(max) is specified as a reference point only; if, a read-write cycle and Data Out will contain data read from the
tRCO is greater tha:1 the specified tRco(max) limit, then access selected cell. If neither of the above sets of conditions is satisfied,
time is controlled exclusively by tCAC. the condition of Data Out (at access time) is indeterminate.

2-18
MCM4027A

READ CYCLE TIMING

II
---------tRC

tRAS-------~

V1HC
RAS
VIL

14------------+---tCSH---------~
---~----~I-tCAS-----

VIHC
--------~------~~I
CAS
VIL

VIH
ADDRESSES
VIL

VIHC
WRiTE VIL

VIH
CS
VIL

tCAC-----~

D out VOH
VOL
----- tRAC------~

2-19
 MCM4027A

II WRITE CYCLE TIMING

~----------------------tRC----~~------------~

VIHC
RAS
VIL
~_ _ _ _ _~=t;:~=t=tRSH---
.----~4-----+-tCAS------~

VIHC
CAS VIL

VIH
ADDRESSES
VIL

~--~------tCWL--------~1

VIH
Din
VIL

VIH
CS
VIL

I
DOH
VOH
D out Open
VOL
tRAC

2-20
MCM4027A

READ-MODIFY·WRITE TIMING

~-----------------------------tRWC----------------------------~

~------------------------tRAS----------------------~

RAS VIHC
VIL

----~~--~----------tCAS----------------~

VIHC
CAS
VIL

VIH
ADDRESSES
VIL

VIHC
WRITE
VIL

VIH
C§
VIL

VOH
Dout
VOL
tRAC

VIH
Din
VIL

RAS ONLY REFRESH TIMING

ADDRESSES

VOH --------------------------------------------~---------------------
Dout
VOL --------------------------------------------------------------------

2-21
MCM4027A

PAGE MOpE READ CYCLE

~------------------------tRAS---------------------~-----g
VIHC-
RAS
-
tRSH~
VIL
tRP
teAs tCRP
VIHC'-
CAS
VIL -

DOut

PAGE MODE WRITE CYCLE

VIH-
Addresses V I L-

DOUT

2-22
MCM4027A

Row Address A5 A4 A3 A2 A 1 AO
Column Address A5 A4 A3 A2 Al AO

Column Addresses

•
Rows A A A A A A
5 4 3 2 1 0 Hex
203E H L L L L L 20
2030 202E 2020 201 E 2010 200E 2000 H L L L L H 21
L H H H H H IF
L H H H H L 1E
H L L L H L 22
H L L L H H 23
L H H H L H 10
L H H H L L lC
H L L H L L 24
H L L H L H 25
L H H L H H 18
L H H L H L lA
H L L H H L 26
H L L H H H 27
L H H L L H 19
183E 1830 182E 1820 181 E 1810 180E 1800 L H H L L L 18
283E 2830 282E 2820 281 E 2810 280E 2800 H L H L L L 28
H L H L L H 29
L H L H H H 17
L H L H H L 16
H L H L H L 2A
H L H L H H 28
L H L H L H 15
L H L H L L 14
H L H H L L 2C
H L H H L H 20
L H L L H H 13
L H L L H L 12
H L H H H L 2E
H L H H H H 2F
L H L L L H 11
103E 1030 102E 1020 101 E 1010 100E 1000 L H L L L L 10
303E 3030 302E 3020 301 E 3010 300E 3000 H H L L L L 30
H H L L L H 31
L L H H H H OF
L L H H H L OE
H H L L H L 32
H H L L H H 33
L L H H L H 00
L L H H L L OC
H H L H L L 34
H H L H L H 35
L L H L H H 06
L L H L H L OA
H H L H H l_ 36
H H L H H H 37
L L H L L H 09
083E 0830 082E 0820 081 E 0810 080E 0800 L L H L L L 08
383E 3830 382E 3820 381 E 3810 380E 3800 H H H L L L 38
H H H L L H 39
L L L H H H 07
L L L H H L 06
H H H L H L 3A
H H H L H H 36
L L L H L H 05
L L L H L L 04
H H H H L L 3C
H H H H L H 3D
L L L L H H 03
L L L L H L 02
H H H H H L 3E
H H H H H H 3F
L L L L L H 01
003E 0030 002E 0020 001 E 0010 OOOE 0000 L L L L L L 00
<0 ..JJ:::t...J...JII...J...JIJ:..J...JJ:I...J ...JII...J...JII..J...JII...J..JII..J ...JII...J...JJ:I...J...Jl:I...J...JII...J ..JII...J..JII..J...JII....J-III...J

IB <- II..J...JII...J...JII...J..JII...J...J I I..J....J:C 1:'...J...J I I ..J..J:t I...J...J II...J..JII..J..JIl:...J...JII...J...J II..J....JII..J...JII...J...JII...J...J

! <N I I-, -'I I-, -'I I-, -'I I-, -' I I-, -'I I-, -'I I-, ...JIIII...J...J...J..J

~ <'" I I-, -'I I-, -' I I-, -'I I...J...J...J...J....J...J...J...J

~ <~
o
II: <Ill I
I I-, -' I
I -'
I -' ...J...J....J...J...J...J...J...J

...J...J...J...J...J...J...J...J
0
Pin 1
.,.. w~ou~mm~W~~~NM~O w~Ou~mmOOW~~~NM~O w~Ou~mmoow~~~NM~O w~ou~mmOOW~~VNM~O
__ oooooooooooooooo
1: MMMMMMMMMMMMMMMM NNNNNNNNNNNNNNNN --~~~_~~~~~~_~

MCM4027A BIT ADDRESS MAP

2-23
 ® MOTOROLA MCM4096

Advance InforIllation
MOS
(N-CHANNEL, SILICON-GATE)

I 4096-BIT DYNAMIC RANDOM ACCESS MEMORY

The MCM4096 is a 4096-bit, high-speed dynamic Random Access

Memory designed for high-performance, low-cost applications in
mainframe and buffer memories and peripheral storage_ Organized as
4096-BIT DYNAMIC
RANDOM ACCESS
MEMORY

4096 one-bit words and fabricated using Motorola's highly reliable

N-channel silicon gate technology, this device optimizes speed,
power, and density tradeoffs.
By multiplexing row and column address input, the MCM4096
requires only six address lines and permits packaging in Motorola's
standard 16-pin dual in-line packages. Complete address decoding is
done on chip with address latches incorporated.
All inputs are TTL compatible, and the output is 3-state TTL
compatible. The MCM4096 Incorporates a one-transistor cell design CERAMIC PACKAGE
and dynamic storage techniques, with each of the 64 row addresses CASE 690
requiring a refresh cycle every 2.0 milliseconds.
• Organized as 4096 Words of 1 Bit

-
~ - -I
• Maximum Access Time = 250 ns - MCM4096L6, C6
300 ns - MCM4096L 16, C16 I I
350 ns - MCM4096L 11, Cll 16 .

• Minimum Read and Write Cycle Time = 1 C SUFFIX

FRIT-SEAL
375 ns - MCM4096L6, C6 CERAMIC PACKAGE
425 ns -- MCM4096L16, C16 CASE 620
500 ns -.: MCM4906L 11, Cll
• Low Power Dissipation
445 mW Maximum (Active)
19 mW Maximum 'Standby)
PIN ASSIGNMENT
• 3-State Output
• On-Chip Latches for Address, Chip Select, and Data In
• Power Supply Pins on Package Corners for Optimum Layout vss 11~ 16 VSS
• Standard 16-Pin Package Din 2 I 15 CAS
• Compatible with the Popular 2104/MK4096/4027/MCM6604/
MCM6604A
WE 3 I 14 D out

RAS 4 I 13 CS
AO 5 I 12 A3

A2 6 I 11 A4
ABSOLUTE MAXIMUM RATINGS (See Note 1)
A1 7 I 10 A5
Rating Symbol Value Unit
Voltage on Any Pin Relative to VSB* Vin, V out -0.5 to +20 Vdc
VDD 8 I 9 VCC

Operating Temperature R,mge TA o to +70 °c

Storage Temperature Range T stg -55 to + 150 °c
Output Current (Short Circuit) lout 50 mAde
*(VSS -VDD;;;' 4.5 V)
This device cont<;ins circuitry to protect the
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS inputs against damage due to high static volt-
are exceeded. Functional operation should be restricted to RECOMMENDED ages or electric fields; however. it is advised that
OPERATING CONDITIONS. Exposure to higher than recommended voltages normal precautions be taken to' avoid applica-
for extended periods of time could affect device reliability. At power turn-on, tion of any voltage higher than maximum rated
the VBS supply must come up before or coincident with VDD. voltages to this high impedance circuit.

This is advance information and specifications are subject to change without notice.

2-24
MCM4096

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted.)

RECOMMENDED OPERATING CONDITIONS (Referenced to Vss = Ground)

4096-6 4096-16 4096-11

Parameter Symbol Min Max Min Max Min Max Unit Notes

II
Supply Voltage VDD 11.4 12.6 11.4 12.6 11.4 12.6 Vdc 1
VCC VSS VDD VSS VDD VSS VDD Vdc 1,2
VSS 0 0 0 0 0 0 Vdc 1
VSS -4.5 -5.5 -4.5 -5.5 -4.5 -5.5 Vdc 1
Logic 1 Voltage, RAS, CAS, WRITE VIHC 2.7 7.0 2.7 7.0 3.0 7.0 Vdc 1,3
Logic 1 Voltage, all inputs except RAS, CAS, WRITE VIH 2.4 7.0 2.4 7.0 2.4 7.0 Vdc 1,3
Logic 0 Voltage, all inputs VIL -1.0 0.8 -1.0 0.8 -1.0 0.8 Vdc 1,3
0
DC CHARACTERISTICS (V DO = 12 V ± 10%, Vee = 5.0 V ± 10%, VBB = ·-5.0 V ± 10%, VSS =0 V, TA = 0 to 70 e)

4096-6 4096-16 4096-11

Characteristic Symbol Min Max Min Max Min Max Units Notes
Average VDD Power Supply Current IDDl - 35 - 30 - 25 mA 4
VCC Power Supply Current ICC - - - - - - mA 5
Average VSS Power Supply Curent ISS - 75 - 75 - 75 IlA
Standby VDD Power Supply Current IDD2 - 1.5 - 1.5 - ,1.5 mA 7
Average VDD Power Supply Current during "RAS only" cycles IDD3 - 25 - 22 - 18 mA 4
Input Leakage Current (any input) IIL(L) - 5 - 5 - 5 IlA 6
Output Leakage Current IO(L) - 10 - 10 - 10 IlA 7,8
Output Logic 1 Voltage @ lout = -5 mA VOH 2.4 - 2.4 - 2.4 - Vdc 2
Output Logic 0 yotlage @ lout = 3.2 mA VOL - 0.4 - 0.4 - 0.4 Vdc

NOTES:
1. All voltages referenced to VSS. VSS must be applied before and remov~d after other supply voltages.
2. Output voltage will swing from VSS to VCC if VCC " VDD -4 volts. If VCC ;;. VDD -4 volts, the output will swing from VSS to a voltage
somewhat less than VDD.
3, Device speed is not guaranteed at input voltages greater than TTL levels (0 to 5 V).
4. Current is proportional to cycle rate; maximum current is measured at the fastest cycle rate.
5. ICC depends upon output loading. The VCC supply is connected to the output buffer only.
6. All device pins at 0 volts except VSS which is at -5 volts and the pin under test which is at +10 volts.
7. Output is disabled (open-circuit) and RAS and CAS are both at a logic 1.
8.0V';;V out ,,+10V.

EFFECTIVE CAPACITANCE (Full operating voltage and temperature range periodically sampled rather than 100% tested.)
Characteristic Symbol Max Unit
Input Capacitance (AO-A5) Din, CS Cin(EFF) 10 pF
RAS, CAS, WRITE 7.0
Output Capacitance Cout(EFF) 8.0 pF

2-25
 MCM4096

AC OPERATING CONDITIONS AND CHARACTERISTJCS

(Read, Write, and Read-Modify-Write Cycles)

RECOMMENDED AC OPERATING CONDITIONS (NOTES 13 and 15)

I
o
(V DD = 12 V ± 10%, vee = 5.0 V ± 10%, VB B = - 5.0 V ± 10%, V 55 = 0 v, T A = 0 to 70 e)
MCM4096-6 MCM4096-16 MCM4096~11
Parameter Symbol Min Max Min Max Min Max Units Notes
Random Read or Write Cycle Time tRC 375 - 425 - 500 - ns 9
Access Time from Row Address Strobe tRAC - 250 - 300 - 350 ns 9,11
Access Time from Column Address St~obe tCAC - 140 - 165 - 200 ns 10,11
Output Buffer and Turn-Off Delay tOFF 0 65 0 80 0 100 ns
Row Address Strobe Precharge Time tRP 115 - 125 - ·150 - ns
Row Address Strobe Pulse Width tRAS 250 10,000 300 10,000 300 10,000 ns
Column Address Strobe Pulse Width tCAS 140 - 165 - 200 - ns 10
Row to Column Strobe Lead Time tRCL 60 110 80 135 100 150 ns 12
Row Address Setup Time tASR 0 - 0 - 0 - ns
Row Address Hold Time tRAH 60 - 80 - 100 - ns .
Chip Select Hold Time tCH 100 - 100 - 100 - ns
Transition Time (Rise and Fall) tT 3.0 50 3.0 50 3.0 50 ns 13
Read Command Setup Time tRCS 0 - 0 - 0 - ns
Read Command Hold Time tRCH 0 - 0 - 0 - ns
Write Command Hold Time tWCH 110 - 130 - 150 - ns
Write Command Pulse Width twp 110 - 130 - 150 - ns
Column to Row Strobe Lead Time tCRL -40 +40 -50 +50 -50 +50 ns
Write Command to Column Strobe Lead Time tCWL 110 - 130 - 150 - ns
Data in Setup Time tDS 0 - 0 - 0 - ns 14
Data in Hold Time tDH 110 - 130 - 150 - ns 14
Refresh Period tRFSH - 2.0 - 2.0 - 2.0 ms
Modify Time tMod 0 10 0 10 0 10 J).s
Data Out Hold Time tDOH 10 - 10 - 10 - J).s

NOTES:
9. Assumes that tRCL + tT';; tRCL(max).
10. Assumes that tRCL + tT;;;' tRCL (max).
11. Measured with a load circuit equivalent to 1 TTL load and 100 pF.
12. Operation within the tRCL (max) limit ensures that tRAC (max) can be met. tRCL (max) is specified as a reference point only; if tRCL
is greater than the specified tRCL (max) limit, then access time is controlled exclusively by tCAC.
13. VIHC (min) or VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transistion times are measured
between VIHcor VIH and VIL.
14. These parameters are referenced to CAS leading edge in random write cycles and to WRITE leading edge in delayed write or read-modify-
write cycles.
15. After the application of supply voltages or after' extended periods of operation without clocks, the device must perform a minimum of
eight initialization cycles (any valid memory cycle containing both RAS and CAS) prior to normal operation.

2-26
MCM4096

READ CYCLE TIMING

V1HC
tAR
tRAS

"I
tRC

"I
•
RAS I
VIL

tCAS

V1HC
CAS
VIL

VIH
ADDRESSES
V1L

VIHC
WRITE
VIL

VIH
CS
VIL

tCAC

°out VOH
VOL
tRAC

2-27
 MCM4096

WRITE CYCLE TIMING

tRC--------------------~

I V I HC

VIL
-----++--.....:..:=~~
t C A S - - - - - - ' r---t(.~ •• ------I

A,DDRESSES VIH
VIL

VIH
Din
VIL

VIH
CS
VIL

,c:c~
VOH
D out Open
VOL
tRAC

2-28
MCM4096

READ-MODIFY-WRITE TIMING

-- tRWC -------------~I
.1
~---------------------- tRAS --- .1

VIHC

II
RAS
VI L

VIHC
CAS
VIL

tCAH

ADDRESSES

1 ;-1_
1.--_ _ _ _------:- -tRWD--------------

' - - - - - - - - - tCWD ---------~T"

VIHC
WRITE
VIL

VIH
CS
VIL

tCAC
tOFF
VOH
Dout Open
VOL
-tRAC

VIH
Din
VIL

RAS ONLY REFRESH TIMING

f ~. tRC ~

V~~:~---------t-A-S-"~'"AM~A~-----.-~J-
ADDRESSES VIH _ _ Row Address
VIL

D out

2-29
MCM4096

BLOCK DIAGRAM

E Write
Clocks
I
RAS Clocks
1
I
1t Data In
Buffer
~ataln

~
Address
Clocks

1 i
p~ ~
CAS
Clocks

,I Reset
J I
Data

~
Data Out

Chip Select
- r---1} Enable Buffer
Out

-II nput Buffer

A5
+ -f--- Dummy Cells

A4 Address -f---- Memory Array

A3 Buffers

.
Row
(6)
A2 Decoder
64 Sense Refresh Amplifiers
I- 1·of· 2
Data Bus
A1 Rowand (1·of·64) Data In/Out _Gating
"
Select
Column
AO ~
I Memory Array I
-f-- I I
r-r-- I Dummy Cells I
I I

Y1 Column Decoder
(1·of·32)

i r I
OPERATING CHARACTERISTICS

ADDRESSING DATA OUTPUT

The MCM4096 has six address inputs (AO-A5) and In order, to simplify the memory system designed and
two clock signals designated Row Address Strobe (R"AS) reduce the total package count, the MCM4027 contains
and Column Address Strobe (CASL At the beginning of an input data latch and a buffered output data latch. The
a memory cycle, the six low order address bits AO through state of the Qutput latch and buffer at the end of a mem-
A5 are strobed into the chip with RAS to select one of ory cyCle will dep~nd on the type of memory cycle per-
the 64 rows. The row address strobe also initiates the tim- formed and whether the chip is selected or unselected for
ing that will .enable the 64 column sense amplifiers. After that memory cycle.
a specified hold time, the row address is removed and the A chip will' be unselected during a memory cycle if:
six high order address bits (A6-A 11) are placed on the (1) The chip receives both RAS and CAS signals,
address pins. This address is then strobed into the chip but no Chip Select signal.
with CAS, Two of the 64 column sense amplifiers are (2) The chip receives a CAS signal but no RAS
selected by A 1 through A5. A one of two data bus select signal. With this condition, the chip will be
is accomplished by AO to complete the data selection. unselected regardless of the state of Ch ip
The Chip Select (CS) is latched into the port along with Select input,
the column addresses. If, during a read, write, or read-modify-write cycle,

2-30
MCM4096

the chip is unselected, the output buffer will be in the INPUT/OUTPUT LEVELS
high impedance state at the end of the memory cycle. All of the inputs to the MCM4096 are TTL·compatible,
The output buffer will remain in the high impedance state featuring high impedance and low capacitance (5 to 7 pF).
until the chip is selected for a memory cycle. The three-state data output buffer is TTL-compatible and
For a chip to be selected during a memory cycle, it has sufficient current sink capability (3.2 mAl to drive
-- -- --
must receive the following signals: RAS, CAS, and Chip two TTL loads. The output buffer also has a separate

II
Select. The state of the output latch and buffer of a VCC pin so that it can be powered from the same supply
selected chip during the following type of memory cycles as the logic being employed.
would be:
REFRESH
(1) Read Cycle - On the negative edge of CAS,
the output buffer will unconditionally go to a In order to maintain valid data, each of the 64 internal
high impedance state. It will remain in this rows of the MCM409,6 must be refreshed once every 2 ms.
state until access time. At this time, the out· Any cycle in which a RAS signa~ occurs accomplishes a
put latch and buffer will assume the logic refresh operation. Any read, write, or read-modify-write
state of the data read from the selected cell. cycle will refresh an entire internally selected row. How·
This output state will be maintained until the ever, if a write or read-modify-write cycle is used to per-
chip receives the next CAS signal. form a refresh cycle the chip must be deselected to pre-
vent writing data into the selected cell. The memory can
(2) Write Cycle - If the WE input is switched to a also be refreshed by employing only the RAS cycle. This
logic 0 before the CAS transition, the output refresh mode will not shorten the refresh cycle time, how·
latch and buffer will be switched to the state ever the system standby power can be reduced by approx·
of the data input at the end of the access time, imately 30%.
This logic state will be maintained until the If the RAS only refresh cycles are employed for an ex·
chip receives the next CAS signal. tended length of time, the output buffer may eventually
lose data and assume the high impedance state, Applying
(3) Read·Modify·Write - Same as read cycle.
CAS to the chip will restore activity of the output buffer.

POWER DISSIPATION
DATA INPUT
Since the MCM4096 is a dynamic RAM, its power
Da,ta to be written into a selected storage cell of the drain will be extremely small during the time the chip is
memory chip is first stored in the on·chip data latch. unselected.
The gating of this latch is performed with a combination The power increases when the chip is selected and
of the WE and CAS signals. The last of these signals to most of this increase is encountered on the address
make a negative transition will strobe the data into the strobe edge. The circuitry of the MCM4027 is largely
latch. If the WE input is switching to a logic 0 in the dynamic so power is not drawn during the whole time
beginning of a write cycle, the falling edge of CAS strobes the strobe is active. Thus the dynamic power is a function
the data into the latch. The data setup and hold times of the operating frequency rather than the active duty
are then referenced to the negative edge of CAS, cycle.
If a read-modify-write cycle is being performed, the In a memory system, the CAS signal must be supplied
WE input would not make its negative transistion until to all the memory chips to ensure that the outputs of
after the CAS signal was enabled. Thus, the data would the unselected chips are switched to the high impedance
not be strobed into the latch until the negative transistion state. Those chips that do not receive a RAS signal will
of WE. The data setup and hold times would now be ref· not dissipate any power on the CAS edge except for that
erenced to the negative edge of the WE signal. The only required to turn off the chip outputs. Thus, in order to
other timing constraints for a write-type-cycle is that both ensure minimum system power, the RAS signal should be
the CAS and WE signals remain in the logic 0 state for a decoded so that only the chips to be selected receive a
sufficient time to accomplish the permanent storage of ~ signal. If the 'RAS' signal is decoded,tthen the chip
the data into the selected cell. select input of all the chips can be set to a logic 0 state.

2-31
 ® MOTOROLA MCM4116A

16,384-BIT DYNAMIC RANDOM ACCESS MEMORY

MOS
The MCM4116A is a 16,384-bit, high-speed dynamic Random (N-CHANNEL)

I Access Memory designed for high-performance, low-cost applications

(n mainframe and buffer memories and peripheral storage. Organized
as 16,384 one-bit words and fabricated using Motorola's highly
rei iable N-channel double-polysil icon technology, this device
optim izes speed, power, and density tradeoffs.
16,384-BIT DYNAMIC
RANDOM ACCESS
MEMORY
By muliplexing row and column address inputs, the MCM4116A
requires only seven address lines and permits packaging in Motorola's
standard 16-pin dual in-line packages. This packaging technique

'6~_11
allows high system density and is compatible with widely avail-

_ _
able automated test and insertion equipment. Complete address
decQding is done on chip with address latches incorporated.
All inputs are TTL compatible, and the output is 3-state TTL
compatible. The data output of the MCM4116A is controlled by the
column address strobe and remains valid from access time until the
column address strobe returns to the high state. This output scheme L SUFFIX ,
allows higher degrees of system design flexibility such as common CEAAMIC PACKAGE 16
input/output operation and two dimensional memory selection by CASE 690 ,
decoding both row address and column address strobes.
C SUFFIX
The MCM4116A incorporates a one-transistor cell design and FAIT-SEAL PACKAGE
dynamic storage techniques, with each of the 128 row addresses CASE 620
requiring a refresh cycle every 2 milliseconds.

• Flexible Timing with Read-Modify-Write, RAS-Only Refresh,

PIN ASSIGNMENT
and Page-Mode Capability
• Industry Standard 16-Pin Package
• 16,384 X 1 Organization
• ± 10% Tolerance on All Power Supplies
• All Inputs are Fully TTL Compatible WRITE 14 D out
• Three-State Fully TTL-Compatible Output
RAS 4 13 A6
• Common I/O Capability When Using "Early Write" Mode
AO 12 A3
• On-Chip Latches for Addresses and Data In
• Low Power Dissipation - 462 mW Active, 20 mW Standby (Max) A2 11 A4

• Fast Access Time Op'tions: 150ns- MCM4116AL-15,AC-15 A1 10 A5

200 ns - MCM4116A L-20, AC-20
VDD 8 9 Vee
250 ns - MCM4116A L-25, AC-25
300 ns - MCM4116A L-30, AC-30
• Easy Upgrade from 16-Pin 4K RAMs PIN NAMES
• Pin Compatible with 2117, 2116, 6616, pPD416, and 4116 AO-A6 Address Inputs
CAS Column Address St~obe

Din Data In
D out Data Out
ABSOLUTE MAXIMUM RATINGS (See Note 1) RAS Row Address Strobe
WRITE Read/Write Input
Rating Symbol Value Unit VBB Power (-5 V)
VCC Power (+5 V)
Voltage on Any Pin Relative to VBB Vin.Vout -0.5 to +20 Vdc
VDD Power (+12 V)
Operating Temperature Range TA o to +70 °c VSS Ground

Storage Temperature Range T stg -65 to +150 °c

Power Oissipation Po 1.0 W
This device contains circuitry to protect the
Data Out Current lout 50 mA inputs against damage due tb high static volt-
NOTE 1: Permanent device damage may occur if ABSOLUTE MAXIMUM RAT- ages or electric fields; however. it is advised that
normal precautions be taken to avoid applica-
INGS are exceeded. Functional operation should be restricted to RECOM-
tion of any voltage higher than maximum rated
MENDED OPERATING CONDITIONS. Exposure to higher than recom-
voltages to this high impedance circuit.
mended voltages for extended periods of time could affect device reliability.

2-32
MCM4116A

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted.)
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit Notes
Supply Voltage VOO 10.8 12.0 13.2 Vdc 1

VCC 4.5 5.0 5.5 Vdc 1,2

VSS 0 0 0 Vdc 1

VSS -4.5 -5.0 -5.5 Vdc 1

-

II
Logic 1 Voltage, RAS, CAS, WRITE VIHC 2.7 7.0 Vdc 1
Logic 1 Voltage, all inputs except RAS, CAS, WRITE VIH 2.4 - 7.0 Vdc 1
Logic 0 Voltage, all inputs VIL -1.0 - 0.8 Vdc 1

12·V '10% VCC - 50 V ~ 10% VSS" -50 V' 10%, VSS = 0 V, T A = 0 to 70 C.1
D
DC CHARACTERISTICS 1Voo c

Characteristic Symbol Min Max Units Notes

Average VOO Power Supply Current 1001 - 35 mA 4
VCC Power Supply Current ICC - - mA 5
Average VSS Power Supply Current ISS1,3 - 200 J.!.A
,Standby Vas Power Supply Current ISS2 - 100 J.!.A

Standby VDO Power Supply Current 1002 - 1.5 mA 6

Average VOO Power Supply Current during 1003 - 27 mA 4
"RAS only" cycles
Input Leakage Current (any Input) I ilL! - 10 J.!.A
Output Leakage Current IO(L! - 10 J.!.A 6,7
Output Logic 1 Voltage @ lout - -5 mA VOH 2.4 - Vdc 2
Output Logic 0 Voltage @ lout = 4.2 mA VOL - 0.4 Vdc

NOTES:
1 All voltages referenced to VSS' VBB must be applied before and removed after other supply voltages.
2 Output voltage will swing from VSS to V CC under open circuit conditions. For purposes of maintaining data In power down mode, V CC
may be reduced to VSS without affecting refresh oparations. VOH(min) .pecification is not guaranteed in this mode.
3. Several cycles are required after power up before proper device operation i. achieved. Any B cycles which perform refresh are aclequate
4. Current is proportional to cycle rate; maximum current i. measured at the fastest cycle rate
5. ICC depends upon output loading. The VCC supply is connected to the output buffer only
6. Output is disabled (open·circuit) and RAS and CAS are both at a logic 1.
,7 D V 0;; V out ... + 5.5 V lQ,t
B, Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation' C = Av

BLOCK DIAGRAM

_VDD
WRITE

Clock
Generator
l
I
J
Write
Clocks
J _VCC
_VSS
-VBB
No.1
1
Multiplexed •I l
Data
In I
Data In
(Din)
Clock
Generator
, Buffer J

~~ H
~
Clock
Gene'rator
No.2
II ~ Latch
Release
Data
Out
Buffer
I
Data Out
(Dout)

~ Dummy Cells
A6
--~
I
A5 I Memory Array 1-of-2
I
Mux Data
A4 128 _ 8us
Address Row
A3 Input ~ Decoder
r-;v'
Row
Lines
128 - Sense - Refresh Amps :===: Select
Buffers 1 :128 Data ~
A2 (7) I InlOut
A1 I Memory Array
I
AD Dummy Cells
~

- __ 64-Column ___

~
Select Lines

====i Column Decoders

Switch I A1-A6 )j 1·of·64
I
AD

2-33
 MCM4116A

AC OPERATING CONDITIONS AND CHARACTERISTICS (See Notes 3, 9, 14)

(Read, Write, and Read-Modify-Write Cycles)
RECOMMENDED AC OPERATING CONDITIONS
(VOO=12V±10% VCC=50V+10%
- -
VSS=-50V+10% vss=ov TA=Ot070 0 C)
MCM4116A-15 MCM4116A-20 MCM4116A-25 MCM4116A-30
Parameter Symbol Min Max Min Max Min Max Min Max Units Notes
Random Read or Write Cycle Time tRC 375 - 375 - 410 - 480 - ns
Read Write Cycle Time tRWC 375 - 375 - 515 - 660 - ns
Access Time from Row Address Strobe tRAC - 150 - 200 - 250 - 300 ns 10,12

I Access Time from Column Address Strobe

Output Suffer and Turn-off Oelay
Row Address Strobe Precharge Time
Row Address Strobe Pulse Width
Column Address Strobe Pulse Width
tCAC
tOFF
tRP
tRAS
tCAS
-
0
-100.
150
90
90
50
-
10,000
10,000
-
0
120
200
135
135
50
-
10,000
10,000
-
0
150
250
165
165
60
-
10,000
10,000
-
0
180
300
200
200
60
-
10,000
10,000
ns
ns
ns
ns
ns
11,12
17

Row to Column Strobe Lead Time tRCO 20 60 25 65 35 85 60 100 ns 13

Row Address Setup Time tASR 0 - a - 0 - 0 - ns
Row Address Hold Time tRAH 20 - 25 - 35 - 60 - ns
Column Address Setup Time tASC -10 - -10 - -10 - -10 - ns
Column Address Hold Time tCAH 45 - 55 - 75 - 100 - ns
Column Address Hold Time tAR 105 - 120 - 160 - 200 - ns
Referenced to RAS
Transition Time (Rise and Fall) tT 3.0 35 3.0 50 3.0 50 3.0 50 ns 14
Read Command Setup Time tRCS 0 - 0 - 0 - 0 - ns
Read Command Hold Time tRCH 0 - 0 - 0 - 0 - ns
Write Command Hold Time tWCH 45 - 55 - 75 - 100 - ns
Write Command Hold Time tWCR 105 - 120 - 160 - 200 - ns
Referenced to RAS
Write Command Pulse Width twp 45 - 55 - 75 - 100 - ns
Write Command to Row Strobe Lead Time tRWL 60 - 80 - 100 - 180 - ns
Write Command to Column Strobe tCWL 60 - 80 - 100 - 180 - ns
Lead Time
Oata in Setup Time tos 0 - 0 - 0 - , 0 - ns 15
Oata in Hold Time tOH 45 - 55 - 75 - 100 - ns 15
Data in Hold Time Referenced to RAS tDHR 105 - 120 - 160 - 200 - ns
Column to Row Strobe Precharge Time teRP -20 - -20 - -20 - -20 - ns
RAS Hold Time tRSH 100 - 135 - 165 - 200 - ns
Refresh Period tRFSH - 2.0 - 2.0 - 2.0 - 2.0 ms
WR ITE Cqmmand Setup Time twcs -20 - -20 - -20 - ~20 - ns
CAS to WRITE Delay tCWD 70 - 95 - 125 - 180 - ns 16
RAS to WRITE Delay tRWD 120 - 160 - 210 - 280 - ns 16
CAS Precharge Time (Page mode cycle only) tcp 60 - 80 - 100 - 100 - ns
Page Mode Cycle Time tpc 170 - 225 - 275 - 325 - ns
CAS Hold Time tCSH 150 - 200 - 250 - 300 - ns

Parameter Symbol Typ Max Units Notes

NOTES: (continued) Input Capacitance (AO-A5), Din 4.0 5.0 pF 9
C'1
9. AC measurements assume tT = 5.0 ns. ------ pF
Input Capacitance RAS, CAS, WRITE C'2 8.0 10 9
10. Assumes that tRCD + tT';; tRCD (max). Output Capacitance (Dout) Co 5.0 7.0 pF 7,9
11. Assumes that tRCD + tT;;' tRCD (max).
12. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
13. Operation wit'hin the tRCO (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD
is greater than the specified tRCO (max) limit, then access time is controlled exclusively by tCAC.
14. V I HC (min) or V I H (min) and V, L (max) are reference levels for measuring timing of input signals .. Also, transistion times are measured
between V,HC or V,H and V,L.
15. These parameters are referenced to CAS leading edge in random write cycles and to WR ITE leading edge in delayed write or read-modify-
write cycles.
16. twcs, tCWD and tRWO are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only: If
twcs ;;. twcs (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the
entire cycle; If tcwo ;;. tcwo (min) and tRWO .. tRWO (min), the cycle is a read-write cycle and the data out wil.1 contain data read from
the selected cell; If neither of the above sets of conditions is satisfied the condition of the da~a out (at access time) is indeterminate.
17. Assumes that tCRP > 50 ns.

2-34
MCM4116A

READ CYCLE TIMING

~-------------- tRC ------------.,j

VIHC---------~I ~---------tAR

VIL_

II
VIH-
ADDRESSES
VIL_

tRCS

VIHC-

I----
WRITE
VIL_
tCAC-

tRAC-------~

VOH- Valid
°out HiZ
vOL- Data

WRITE CYCLE TIMING

~-------------tRC --------------~
~----------------tRAS

RAS VIHC-
V IL _

14---...:...----- tRS H ------.~

~-------~--+tCSH-------~
--~~-~-- tCAS----~

VIHC-
CAS
V _
IL

V IH -
ADDRESSES
VIL -

VIHC~
WRITE
VIL_

H-
Din
VIL_

tDHR

VOH-
D out HiZ
VO L -

2-35
 MCM4116A

READ-WRITE/READ-MODIFY-WRITE CYCLE

~ _______________________________ tRWC ____________~----------~------~

~----------------------~------tRAS

I ~----~----- tRSH --------------------~~

~----------------~-----+-tCSH------------------------~
---~~It__-----'------ tCAS --------------------~

ADDRESSES

D out

RAS ONLY REFRESH TIMING

Note: CAS = VIHC, WRITE = Don't Care

~ 'AJ~=
rr'AAH
VIH_ Row
ADDRESSES VIL_ Address

VOH-
--------------------------------- HiZ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

2-36
MCM4116A

PAGE MODE READ CYCLE

RAS
~------------------------.----tRAS------------------~--~

1'-----:--------1 f - - -
tRSH
tRP
II
tCAS tCRP
CAS VIHC
VIL

V 1H
Addresses
VIL

VOH
DO ut V aL --------'--

Write

PAGE MODE WRITE CYCLE

RAS

CAS

Add resses Vv I H
IL

2-37
MCM4116A

MCM4116A BIT ADDRESS MAP

Row Address A6 A5 A4 A3 A2 Al AO Pin 8

Column Address A6 A5 A4 A3 A2 Al AO

Rows DLL 76 118

Column Addresses

He~ Dec A6 A5 A4 A3 A2 Al AO

1 0 1
.....
ID 1 0 1
..... 77 119

16 30 0 0 1 0 1 1 0
17 31 0 0 1 0 1 1
14 28 0 0 1 0 1 0 0
15 29 0 0 0 1 0 1
12 26 0 0 0 0 1 0
13 27 0 0 0 0 1 1
10 24 0 0 0 0 0 0
11 25 0 0 1 0 0 0
IE 22 0 0 1
IF 23 0 0 1
o = potential well filled 1 = potential well filled lC 20 0 0 1 0 0
with electrons with electrons
10 21 0 0 1 0 1
lA 18 0 0 1 0 1
1B 19 0 1 1 0 1
18 16 0 1 1 0 0 0
19 17 0 0 0 0 1
OE 14 0 0 1 0
OF 15 0 a .1
OC 12 0 1
00 13 0 1 0 1
OA 10 0 0 1 0
OB 11 0 0 1
08 0 0 0 0 0
09 0 1 0 0
06 0 0 0 1
07 0 0 1 1
04 0 0 1 0 ,

05 0 0 0 0 0 1
.....
~ § § § ~ § 88 § 8~ g 02 2 0 0 0 0 1 0
03 0 0 0 0 0 1
"'. LL

~ ~
8 It>

~ ~
0 S 0 0 ..... 00 0 0 0 0 0 0 0
(; 0 0 0 0 0
01 0 0 0 0 0 0 1
8 0 S 8 g :g 8 .....
~ ~
LL
0 ~ M
LL
.....
.....
~ M
ID (f; N
0

~
~ :;:
~ ~ 000 0
-
~ o
a: !;l
0 0 000

~ 0 0

~ 0 o 0 o 0 <:) 0

~ 000

Dpin16

2-38
 ® MOTOROLA MCM4516

Produ.ct Previe""
MOS
(N·CHANNEL, SILlCON·GATE)

16,384-BIT
16,384cBIT DYNAMIC RAM
DYNAMIC RAM
The MCM4516 is a 16,384-bit, high-speed, dynamic Random-Access
Memory. Organized as 16,384 one-bit words and fabricated using HMOS
high-performance, N-channel, silicon-gate technology. This new breed of
5-volt only dynamic RAM combines high performance with low cost and
improved reliability.
By multiplexing row- and column-address inputs, the MCM4516 re-
quires only eight address lines and permits packaging in standard 16-pin
dual-in-line packages. Complete address decoding is done on chip with
address latches incorporated. Data out is controlled by CAS allowing
L SUFFIX
for greater system flexibility.
CERAMIC PACKAGE
All inputs and outputs, including clocks, are fully TTL compatible. CASE 690
The MCM4516 incorporates a one-transistor cell design and dynamic
storage techniques. In addition to the RAS-only refresh mode, refresh

Ir'WM~~
control function available on pin 1 provides automatic and self-refresh
modes.
• Organized as 16,384 Words of 1 Bit 16 U I
• Single +5 Volt Operation 1 C SUFFIX
FR IT-SEAL
• Fast 120 ns Operation
CERAMIC PACKAGE
• Low Power Dissipation: CASE 620
200 mW Maximum (Active)
20 mW Maximum (Standby)
• Three-State Data Output
• Internal Latches for Address and Data Input PIN ASSIGNMENT
• Early-Write Output Capability
• 64K Compatible 128-Cycle, 2 ms Refresh
• - Control on Pin 1 for Automatic and Self Refresh
REFRESH 1 ~~16 VSS

0 2 16 CAS
• RAS-only Refresh Mode
• CAS Controlled Output Providing Latched or Unlatched Data Vii 3 I 14 Q

• Upward Pin Compatibility from the 16K RAM (MCM4116) RAS 4 I 13 A6

to the 64K RAM (MCM6664) AO 6 I 12 A3

A2 6 I 11 A4
A1 7 I 10 A5

VCC 8 I 9 N/C

OUTPUT BUFFER TRUTH TABLE

Internal
Early Write CAS Refresh Control (CAS Internal) Output Buffer
This device contains circuitry to protect the
H X X (X) Hi·Z inputs against damage due to high static volt-
X H X (X) Hi-Z ages or electric fields; however, it is advised that
L L L (H) Maintains Previous normal" precautions be taken to avoid applica-
tion of any voltage higher than maximum rated
Data
voltages to this high impedance circuit.
L L H (L) Active
This is advance information and specifications are subject to change without notice.

2-39
 MCM4516

PIN ASSIGNMENT COMPARISON

MCM4116 MCM4516 MCM6664

VBB 16 VSS REFRESH 16 VSS REFRESH 16 VSS

0 15 CAS 0 15 CAS D 15 CAS

W 14 Q W 14 Iii 14

II
3 3 Q Q

AAS 4 13 A6 AAS 4 13 A6 RAS 4 13 A6

AO 12 A3 AO 12 A3 AO 12 A3

A2 11 A4 A2 11 A4 A2 11 A4
A1 10 A5 A1 10 A5 A1 10 A5

8 VCC 8 N/C 8 9 A7
VDO VDD Vec

PIN'VARIATIONS ON-CHIP REFRESH FEATURES/BENEFITS

PIN NUMBER MCM4116 MCM4516 ~ Reduce System Refresh Controlier Design Problem

VBB (-5 V) REFRESH REFRESH Reduce System Parts Count

8 VDD (+12 V) VCC VCC (+5 V) Reduce System Noise Increasing System Reliability
9 VCC (+5 V) N/C A7
Reduce System Power During Refresh

READ CYCLE TIMING

V ,HC -. ------,1
V __
,L

_~~----_r--tRSH--------H~

V,HC--------~+_--------__--~ 14------+- tCAS -------t~

CAS

V ,HC
I 'ReS ~
WRITE ~-
V ,L tCAe

V OH -
~ tRAC

-
14- tOFF
HI-Z
J- Valid Data
D out
V OL -

Motorola reserves the right to make changes to any products herein to improve reliability, function or design. Motorola does not assume any liability arising
out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

2-40
MCM4516

WRITE CYCLE TIMING

VIHC------~
.. ---- tAR 4 tRAS --------~ --'r-~----"""__

~-~--tRSH-----,~
~-----------~--~ tCSH
-~~ __~----tCAS 14-----~- tCRP
VIHC------------~---------~-~

VIH-
ADDRESSES
VIL_

DSC-
Valid Data

VOH-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - H I·Z
VOL-

READ-WRITE/READ-MODIFY-WRITE CYCLE TIMING

tRWC----------------------~

~------------------------tRAS
VIHC-
RA.:'
VIL_
. .----~---tRSH ------------~~
~-------------r_----~- tCSH
----e~~-~------tCAS
VIHC- -----r~------~~~
CAS

ADDRESSES

tOFF

2-41
 MCM4516

SELF REFRESH MODE (Battery Backup)

(CAS I, Addresses, Data-In, and Write are Don't Care)

RAS

• AUTOMATIC PULSE REFRESH CYCLE

(CAS', Addresses, Data-tn, and Write are Don't Care)

RAS
14-------_' tRC + tRP

tRFD ~----~~---------- tFRD

fCAS controls the output data. If CAS remains low the previous output will rem<)in valid.
h igh·impedance state.

RAS-ONLY REFRESH CYCLE

(Data-in and Write are Don't Care CAS is HIGH'
~---------- tRC + tRP -----------.t

tRAS ------I~ JIe------=:!L

tRAH

ADDRESSES, AO-A5

2-42
 ® MOTOROLA MCM6604A

4096-BIT DYNAMIC RANDOM ACCESS MEMORY MOS

(N-CHANNEL, SILICON-GATE)

•
The MCM6604A is a 4096-bit, high-speed, dynamic Random
Access Memory designed for high-performance, low-cost applications
in mainframe and buffer memories and peripheral storage_ Organized 4096-BIT DYNAMIC
as 4096 one-bit words and fabricated using Motorola's highly reliable RANDOM ACCESS
N-channel silicon gate technology, this device optimizes speed, MEMORY
power, and density tradeoffs_
By multiplexing row and column address inputs, the MCM6604A
requires only six address lines and permits packaging in Motorola's
standard 16-pin dual in-line packages_ Complete address decoding
is done on chip with address latches incorporated.
All inputs are TTL compatible, and the output is 3-state TTL
compatible. The· MCM6604A incorporates a one-transistor cell
design and dynamic storage techniques, with each of the 64-row
addresses requiring a refresh cycle every 2.0 milliseconds.
L SUFFIX
• Organized as 4096 Words of 1 Bit CERAMIC PACKAGE
• Maximum Access Time = 250 ns - MCM6604AL2, C2 CASE 690

300 ns - MCM6604AL4, C4
350 ns - MCM6604AL, C
• Minimum Read and Write Cycle Time =
375 ns - MCM6604AL2, C2
425 ns - MCM6604AL4, C4
500 ns - MCM6604AL, C
• Low Power Dissipation
500 mW Typical (Active) FRIT-SEAL
18 mW Typical (Standby) CERAMIC PACKAGE
CASE 620
• 3-State Output
• On-Chip Latches for Address, Chip Select, and Data In
• Power Supply Pins on Package Corners for Optimum Layout
• Standard 16-Pin Package
• Compatible with the Popular 2104/MK4096/4096/4027/MK4027 PIN ASSIGNMENT

ves 16 VSS

Din 15 CAS
ABSOLUTE MAXIMUM RATINGS (See Note 1) WE 14 °out
Rating Synlbol Value Unit RAS' 4 13 CS
Voltage on Any·Pin Relative to VBB* Vin, V out -0.3 to +20 Vdc
AO 12 A3
Operating Temperature Range TA o to +70 °c
A2 6 11
Storage Temperature Range T stg -65 to +150 °c A4

Output Current (Short Circuit) lout 50 mAdc Al 10 A5

*(VSS -VDD;;' 4.5 V) VOO S 9 VCC

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS

are exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages
This device contains circuitry to protect the
for extended periods of time could affect device reliability. VBB must be inputs against damage due to high static volt-
applied prior to VCC and VOD. VBB must also be the last power supply ages or electric fields; however, it is advised that
switched off. normal precautions be taken to avoid applica-
tion of any voltage higher than maximum rated
voltages to this high impedance circuit.

2-43
 MCM6604A
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating. voltage and temperature range unless otherwise noted.)

RECOMMENDED OPERATING CONDITIONS (Referenc~to VSS = Ground)

Parameter Symbol Min Nom Max Unit
Supply Voltage Voo 11.4 12.0 12.S Vdc
Vee 4.5 5.0 5.5 Vdc
VBB -4.5" -5.0 -5.5 Vdc
Input High Voltage An, CS, Din VIH 2.4 - 5.0 Vdc
2.7 - 5.0
RAS, CAS, WE
Input Low Voltage All Inputs VIL -1.0 - 0.8 Vdc

II
DC CHARACTERISTICS (VDD = 12 V ±5%, Vec = 5.0 V ± 10%, VBB = -5.0 V ± 10%, VSS = 0 V, TA = 0 to 70°C)
Characteristic Symbol Min Typ Max Unit
Input Current, Any Input lin - - 10 Jl.A
(V in = 0 to 7.0 VI
Output High Voltage VOH 2.4 - - Vdc
1I0=:-5.0mAI
Output Low Voltage VOL - - 0.4 Vdc
(10 = 2.0mA)
Output Leakage Current ILO - - 10 Jl.A
(Output Disabled by Cs Input)
Average Supply Current, Active Mode 100A - 38 50 mA
(Tcyc(WI = minI ICCA - 20 100 Jl.A
IBBA - - 75 Jl.A
Supply Current, Standby Mode 100S - 1.3 2.0 mA
ICCS - - 10 Jl.A
- - Jl.A
IBBS 75

EFFECTIVE CAPAC IT ANCE (Full operating voltage and temperature range, periodically sampled rather than 100% tested.)
Characteristic Symbol Max Unit
Input Capacitance AO-A5 Cin(EFF) 10 pF
RAS, CAS, Din; WE, Cs 7.0
Output Capacitance Cout(EFF) 8.0 .pF

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Read, Write, and Read-Modify-Write Cycles)

RECOMMENDED AC OPERATING CONDITIONS(VDD = 12 V ±5%, VCC = 5.0 V ± 10%, VBB = -5.0 V ± 10%, TA = 0 to 70 0 C)
MCM6604AL,C MCM6604AL2, C2 MCM6604AL4, C4
Parameter Symbol Min Max Min Max Min Max Unit
Random Read or Write Cycle Time tRC 500 - 375 - 425 - ns
Row Address Strobe Pulse Width tRAS 350 10,000 250 10,000 300 10,000 ns
Row Address Strobe Hold Time tRSH 200 - 140 - 170 - ns
Row Address Strobe Precharge Time tRP . 150 - 125 - 125 - ns
Row to Column Strobe Lead Time (Note 1) tRCL 110 150 70 1.10 90 130 ns
Column Adaress Strobe Pulse Width tCAS 200 10,000 140 10,000 170 10,000 ns
Column to Row Strobe Lead Time tCRL -50 +50 -40 +40 -50 +50 ns
Address Setup Time tAS 0 - 0 - 0 - ns
Address Hold Time tAH 100 - SO - 80 - ns
RAS Address Release Time tAR 250 - 170 - 210 - ns
Read Command Setup Time tRCS 0 - 0 - 0 - ns
Read Command Hold Time tRCH 100 - SO - 80 - ns
Write Command to Column Strobe Lead Time tCWL 200 - 140 - 170 - ns
Write Command Hold Time (Note 2) tWCH 150 - 110 - 130 - ns
Write Command Pulse Width twp 200 - 140 - 170 - ns
Data In Setup Time tDS 0 - 0 - 0 - ns
Data In Hold Time tDH 150 - 110 - 130 - ns
Refresh Period tREF - 2.0 - 2.0 - 2.0 ms

1. If tRCL is greater than the maximum recommended value shown in this table,
tcyC and tRAC will increase by the amount that tRCL exceeds ·the value shown.
2. 1he Write Command Hold Time is important only when normal random write cycles are
being performed. During a read·write or a read·modify·write cycle, the limiting parameter
is the Write Command Pulse Width.

2-44
MCM6604A

AC CHARACTERISTICS itT ~ tr ~ tf ~ 10 ns, Load = 1 MC74HOO Series TTL Gate, CUEFF) = 50 pF)

MCM6604AL, C MCM6604AL2, C2 MCM6604AL4, C4

Characteristic Symbol Max Max Max Unit
Access Time from Row Address Strobe tRAC 350 250 300 ns

•
(110 ns .;; tRCL + IT .;; 150 ns for MCM6604AL, C)
( 70 ns';; tRCL + tT';; 110 ns for MCM6604AL2, C2)
( 90 ns'; tRCL + tT';; 130 ns for MCM6604AL4, C4)
Access Time from Column Address StrObe tCAC 200 140 170 ns
Output Buffer Turn-Off Delay totl 100 65 85 ns

READ CYCLE TIMING

~-----------------------tRC------------------------~

CAS

Address

Data
Out

~--------------tRAC------------~

~ ~ Don't Car~

2-45
 MCM6604A

II WRITE CYCLE TIMING

~-----------------------tAC------------------------~
~----------------tRAS--------------~

RAS

CAS

Address

toff
I,.----------~------~-- VOH
Data Data Stable from Previo~s _~~______..(I Output Follows
Out -------+-- Cycle (or Disabled) Data Input

--------------tRAC--------------~
~ = Don't Care

2-46
MCM6604A

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Read-Modify-Write Cycle)

RECOMMENDED AC OPERATING CONDITIONS(VDD = 12 V ±5%, VCC = 5.0 V ± 10%, VSS = -5.0 V ± 10%, TA = a to 70 0 C)
Note: Parameters not listed are the same 35 for a RSlld or Write Cycle.
MCM6604AL. C MCM6604AL2, C2 MCM6604AL4, C4
Parameter Symbol Min Max Min Max Min Max Unit
Read-ModifY-Write Cycle Time
Row Address Strobe Pulse Width
Column Address Strobe Pulse Width
RAS Hold Time
tRWC
tRWRAS
tRWCAS
tRWL
700
550
400
200
-
10,000
10,000
-
515
390
280
140
-

10,000
10,000
-
595
470
340
170
-
10,000
10,000
-
ns
ns
ns
ns
II
MOdify Time tMOD a 10,000 0 10,000 a 10,000 ns

READ - MODIFY - WRITE TIMING

~---------------------------tRWC------------------------~

~-------------------tRWRAS----------------~~1

~-------tRWCAS------~

Data In

-~-f-tMOD

~---------------------------------VOH
Dilta
Out --------+0. . Data Stable from Previous
Cycle (or Disabled) -t,,()pe,n-(I Data Valid

I'----------------------------------VOL
~----------tRAC----------~

~ = Don't Care

2-47
 MCM6604A

-RAS ON'l Y REFRESH TIMING

'--'---~--'--~-'-"'.'''~-'''--------'-----------'---------------------'---,

1 - - - - - - - - - - - : - - tRC - - - - - - - - -

~----------- VIL

II Address

VOL
D out
--------------------------------- Open-------------------------------------

~ ~ Don't Care

,---------------------------------------------,----------------------------~
.'----'-------------
BLOCK DIAGRAM
-,-
WATTE ~------,--,--
-----------------
Write
Clocks

1
Data In
Buffer
~taln

Clucks

p CM
Clocks

----- --~ -----r-+---

Reset Data
-- ~
CAS

J-
Data Out Out

-[C"" s,'~, ~h)

Enable Buffer
\
-,--- ......
Input Buffer

r- 1
A5 -f---- Dummy Cells

A4 Address f-f---- Memory Array

A3

A2

Al
Buffers
(6)

Rowand
Column
Row
Decoder

(1-of-64)
--------,---
64 Sense Refresh Amplifiers
Data In/Out Gating
-
- 1·of,2
Data Bus
Select
AO ~ +I
f-t---e I Memory Array
I I
f-t-- I Dummy Cells I
I J

Y t
Column Decoder
(1-of-32)

i JI
'------

L--,

2-48
MCM6604A

OPERATING CHARACTERISTICS

DATA OUTPUT of WE. The data setup and hold times would now be ref-
In order to simplify the memory system design and erenced to the negative edge of the WE signal. The only
reduce the total package count, the MCM6604A contains other timing constraints for a write-type cycle is that both
an input data latch and a buffered output data latch. the CAS and WE signals remain in the logic 0 state for a
The state of the output latch and buffer at the end of a sufficient time to accomplish the permanent storage of

•
memory cycle will depend on the type of memory cycle the data into the sel ected cell.
performed and whether the chip is selected or unselected
for that memory cycle.
INPUT/OUTPUT LEVELS
A chip will be unselected during a memory cycle if: All of the inputs to the MCM6604A are TTL com-
(1) The chip receives both RAS and CAS signals, patible, except RAS, CAS, and WE. The latter control
but no Chip Select signal. inputs require a slightly higher input voltage, V,H = 2.7 V
(2) The chip receives a CAS signal but no RAS minimum, which can be met with memory address buffers
signal. With this condition, the chip will be such as the MC3459.
The inputs feature high impedance and low capacitance
unselected regardless of the state of Chip
« 10 pF) characteristics which will minimize the driver
Select input.
requirements in a memory system. The three-state data
If, during a read, write, or read·modify-write cycle, output buffer is TTL compatible and has sufficient current
the chip is unselected, the output buffer will be in the
sink capability (2 mAl to drive one high-speed TTL load.
high impedance state at the end of the memory cycle. The
The output buffer also has a separate VCC pin so that it
output buffer will remain in the high impedance state
can be powered from the same supply as the logic being
until the chip IS selected for a memory cycle.
employed.
For a chip to be selected during a memory cycle, it
must receive the following signals: RAS, CAS, and Chip
Select. The state of the output latch and buffer of a
REFRESH
selected chip dUring the following type of memory cycles In order to ensure or maintain valid data, each of the
would be:
64 internal rows of the MCM6604A must be refreshed
(1) Read Cycle - On the negative edge of CAS, once every 2 ms. Any read, write, or read-modify-write
the output buffer will unconditionally go to a cycle will refresh an entire internally selected row. How-
high impedance state. It will remain in this
ever, if a write or read-modify-write cycle is used to
state until access time. At this time, the output
perform a refresh cycle, the chip must be deselected.
latch and buffer will assume the logic state
The MCM6604A can also be refreshed by employing
of the data read from the selected cell. This
output state will be maintained until the chip only the RAS cycle. This refresh mode will not shorten
receives the next CAS signal. the refresh cycle time; the minimum switching time for
(2) Write Cycle - If the WE input is switched RAS still holds. However, the system standby power can
to a logic 0 .before the CAS transition, the be reduced by approximately 30%. It should also be noted
output latch and buffer will be switched to that, regardless of the type of refresh cycle employed, all
the state of the data input at the end of the of the minimum and maximum timing restrictions includ-
access time. This logic state will be maintained ing address setup and hold times must be observed.
until the chip receives the next CAS signal.
(3) Read-Modify-Write - Same as a read cycle.
TIMING CONSIDERATIONS
DATA INPUT The timing of HAS and CAS as well as their timing re-
Data to be written into a selected storage cell of the lationships must be understood by the designer in order to
memory chip is first stored in the on-chip data latch. The obtain maximum performance in a system. The RAS and
gatingof this latch is performed with a combination of the CAS clocks have minimum and maximum pulse widths,
WE and CAS signals. The .last of these signals to make a tRAS (tRWRAS) and tCAS (tRWCAS). respectively. These
negative transition will strobe the data into the latch. If clock limits must not be violated to ensure proper device
the WE input is switched to a logic 0 at the beginning of operation and data integrity. Once a cycle has been ini-
a write cycle, the falling edge of CAS strobes the data tiated by driving RAS and/or CAS low, it must not be
into the latch. The data setup and hold times are then aborted prior to fulfilling the minimum clock signal pulse
referenced to the negative edge of CAS. width(s). Also, a new cycle cannot be initiated until the
If a read-modify-write cycle is being performed, the minimum precharge time, tRP, has been met.
WE input would not make its negative transistion until The read access time (tACC) is a function of the row to
after the CAS signal was enabled. Thus, the data would column strobe lead time (tRCL), the CAS transistion from
not be strobed into the latch until the negative transition high to low (tfL and the access time from column address

2-49
 MCM6604A

strobe (tCAC) as noted in the following equation: that CS does not have to be valid until the leading edge of
(1 ) CAS. Since the memory device does not have to.be selected
tACC = tRCL + tf + tCAC
at the start of a memory cycle, the system decode time
If the tRCL + tf time is less than or equal to the speci- for CS does not enter into the system access time.
fied tRCL maximum limit, then the device access time The minimum overlap of RAS and CAS during a memo

•
becomes: ory cycle is defined by tRSH. A minimum overlap is reo
tACC = tRAC (access time from the leading quired to keep the write control logic on for a sufficient
(2)
edge of RAS) time to ensure adequate charge or discharge of the selected
storage capacitor during a write cycle.
Note from the ac electrical characteristics that tRAC
The termination of the RAS and CAS down time is de·
is specified for a given timing skew of tRCL; for the
fined by tCR L. This parameter defines the maximum lead
MCM6604AL, the tRAC is 350 ns maximum for 110 ns';;;; (-) or lag (+) time that the trailing edge of CAS can have
tRCL + tf';;;; 150 ns. The 40 ns variation in the falling edge with respect to the trailing edge of RAS. Note that for a
of CAS, for a given tRAC maximum, is given to allow for memory system requiring minimum cycle time, CAS may
system timing skew in the generation of CAS. This will lead RAS by the specified amount, although CAS cannot
ensure minimum system access time since the timing skew lag RAS. This restriction must be placed on tCR~
of CAS has been accounted for at the device. minimum cycle time since tRSH would be violated; CAS
The gating of chip select (CS) is also designed to mini- can lag RAS for the specified maximum time provided the
mize system access time. Note from the timing diagrams minimum tRSH time is not violated.

Circuit diagrams utilizing Motorola products are included as a means IS believed to be entirely reliable. However, no responsibility is
of illuStrating typical semiconductor applications; consequently, assumed for inaccuracies. Furthermore, such information does not
complete information sufficient for construction purposes is not 'convey to the purchaser of the semiconductor devices described any
necessarily given. The information has been carefully checked and license under the patent rights of Motorola Inc. or others.

2-50
 sC')
FIGURE 1 - VDD AND VSS LAYOUT FOR TWO-SIDED PC BOARD MCM6604A
S
C)
C)

Voo ~
l>
J...
A='j" 10 J.lF
VSS

Voo

B =
J...
'j' 100J.lF

VSS

Solid lines denote

component side
, I\) of PC board.
,0,
, --L

!Voo

Vss

II
 ® MOTOROLA MCM660SA

4096-BIT DYNAMIC RANDOM ACCESS MEMORY

MOS
The MCM6605A is a 4096-bit high-speed dynamic Random Access (N-CHANNEL, SILICON-GATEI

PI Memory designed for high-performance, low-cost applications in

mainframe and buffer memories 'and peripheral storage_ Organized
as 4096 one-bit -words, these memories are fabricated using selective
oxidation N-channel silicon gate technology to optimi,ze device
speed, power and density tradeoffs.
4096-BIT DYNAMIC
RANDOM ACCESS
MEMORY
All address and control inputs are TTL compatible except for
a single high-level clock (Chip Enable). Complete address decoding
is done on chip and address latches are incorporated for ease of use.
Refresh of the entire memory can be accomplished by sequentially
cycling through addresses AO-A4 (32 cycles) a maximum of every

~
2.0 milliseconds. ~~--:;-----
The MCM6605A uses a three-transistor memory cell to simplify
internal sense amplifier requirements. Output data is inverted with
respect to input data. The outputs are 3-state TTL configuration and ; I ,... L SUFFIX
require no external sense amplifier. Outputs are in the high impedance
CERAMIC PACKAGE
(floating) state when either the Chip Enable is in the low state or the CASE 677
Chip Select is in the high state.
• Organized as 4096 Words of 1 Bit
L1, P1 L2,P2 L, P
• Maximum Access Time = 150 ns 200 ns 300 ns

• Minimum Read Cycle Time = 290 ns 360 ns 470 ns

• Minimum Write Cycle Time = 390 ns 490 ns 590 ns

• Minimum Read Modify Write

Cycle Time = 390 ns • 490 ns 590 ns CASE 708

• Low Power Dissipation

335 mW Typical (Active)
2.6 mW Typical (Standby with Refresh) PIN ASSIGNMENT
• Easy Refresh - Only 32 Cycles Every 2.0 ms
• TTL Compatible
• 3-State Output Vee 22 VDD
A3 21 Al
• Address Latches On Chip
Preset' 3 20 Al0
• Power Supply Pins on Package Cor,1ers Data In 4.----1~-...LJ.----,'1----.19 A9
for Layout Simplification
All 5 18 A8
• Typical Applications: Chip Enable 6 17 A7
Main Memory Data Out 7 16 A6
Buffer Memory Chip Select 8 '--_ _ _-'~~ 15 A5
Peripheral Storage A4 9 14 Read/Write
A210 13 AO

Vce 11 12 VSS

ABSOLUTE MAXIMUM RATINGS (See Note 1) 'See Applications Info.mation

Rating Symbol Value Unit

Voltage on Any Pin Relative to VBB Yin. V out -0.3 to +20 Vdc
Operating Temperature Range TA o to +70 °c
Storage Temperature Range T stg -65 to +150 °c This dev'ice contains circuitry to protect the
inputsagainst damagedue to high static voltages
or electric fields; however. it is advised that
NOTE1: Permanent device damage ,may occur if ABSOLUTE MAXIMUM RATINGS are ex- nor mal precautions be taken to avo id application
ceeded. Functional operation should be restricted to RECOMMENDED OPERAT- of any voltage higher than maKimum rated volt-
ING COND ITIONS. Expo~ure to higher than recommended voltages for extended ages to this high-impedance circuit_
periods of time could affect device reliability.

2-52
MCM6605A

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted.)

RECOMMf:NDED DC OPEHA'rlNG CONOI nONS (Referenced to Vss).

---.--. .------.----..-.---------.-.-.-----...... - -..··--,...-·-----..,.----r-----.. .·. -··-· r -
___________•____ ~_a_ra_m_e_te_r_ _ _ _ _ .__.. _ •

•
Symbol Min Nom Max Unit
Supply Voltage
I__-V..:O;..:O=---4--1-1-.4--~_1-2-+-- 12.6 Vdc

VCC 4.5 5.0 5.5 Vdc

t-------.-4------+-- .-----t----I
VSS 0 0 0 Vdc
~-V-B-B---+---5-.-25-----I--·---5--.0--r----4-.7-5--+--~
Vdc
.---- .--------1f--=-=--+------<~.------I__.----- . - -+--~
Logic Levels
_!_~~~~~Volta.~~~~in' R/W, CS) ____________+-___V.:..IH:...:-_~--3-.-0 .._ . 1---_ _ I---~'?_O_+_0_.6..-1f-_Vdc___l
Input LowVoltaye (An, 0in, R/W, CS) VIL -1.0' 0.8 Vdc
- - - - - - - - - -....-.. --f--.-.--....-._-+---I
Chip Enable High Voltage VCEH VOO - 0.6 VOO + 0.6 Vdc
----..- - - . - - - . - . - . - . - - - - - - . - - - - - - - - - - - - + - . . . . : = . - . : . . . - + . - - - - - I__-.-.....-f-----...-.......-.-t-----I
Chip Enable LowVoitage VCEL -1.0 0.8 Vdc

DC CHARACTERISTICS
------------------.•- - ._..._--.--.
C_ha~_ct_er_i~tic
•____
__ _.,..--_.--.-_ __.._
..
Symbo._I--I__M_in_ _+.-_T_y:,:p_-4-_ _
Max
.. ... --.--
Unit

Input Current (An, Oin' R/W, CS, Preset) 10 J.lA

(Vin ~ 0 to VOO + 1.0 V)
--..--..- - - -..-.--------------+----+---.---1f-------f----·10
Input Chip Enable Current liCE IJ.A
(Vi" ~ 0 to VOO + 1.0 V)
- - - + -..- - - - - 1 - - . - - . - . - - - 4 - - - - 1 - - - -
Output High Voltage VOH 2.4 Vec Vdc

.._----_.._----_ ..._-_._------_..__... _----

(10 ~ -100I'A)
--_._._ ---.. -----~----_+----4----
Output Low Voltage VOL VSS 0.45 Vdc

~.~~:~~---.---- ... --------.---.---.----f__..-.--... --~-----.-.-+----+.-

Output Leakage Current I LO 10 IJ.A

(Va ~ ~
V CE..::L_'.o_,_C_S_~._V_:I:..:.H_). - - - - - - - + - - - - - I - - . - - - 4 - - - - + - - - - . - - - r -
0.45 V to V CC, CE
Average Supply Current, Active Mode IOOA - 28 36 mA
(T cyc(W) min)0
~--!------I--o~65-·- ~i-:o----t---;nA

.__. _ - - - - - - - - - -
Supply Current, Standby Mode
ISBA

IOOS 1.0
100
20
IJ.A
IJ.A
(CE ~ 0.45 V) ICCS 10 /i A

IBBS 1.0 20 IJ.A

EFFECTIVE CAPAC IT ANCE (Test Circuit of Figure 1, full operating voltage and temperature range,
periotiically sampled rather than 100% tested)
-- Max Unit
Characteristic Symbol Min Typ
Input Capacitance (An, 0in, R/W, CS, Preset) Cin(EFF) - 4.0 5.0 pF
Chip Enable Capacitance CCE(EFF) - 25 30 pF
,-~-

Output Capacitance Cout(EFF) - 4.0 5.0 pF

~.

..2.-:.5.3._
 MCM6605A

FIGURE 1 - MEASUREMENT OF EFFECTIVE CAPACITANCE

r------,
R

51

I Tektronix'
567 or Equiv.
Effective capacitance is determined by comparing the rise time
of the voltage waveform at a particular pin to that measured with
known values of capacitance. Scope calibration points are deter·
mined by using the rise times obtained with the empty socket and
standard capacitor values as references.
The device under test (OUT) is inserted into the test socket
and normal operating power supplies applied. All input pins,
except that being measured, are grounded. The effective capaci·
tance of the desired pin can then be read directly from the scope.

Measurement
Pin R Input Pulse Level
CE 67 n 16 v 12 V
Input/Output lOOn 6.0 v 4.0V

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature unless otherwise noted.)
OPERATING MODES
Mode Control States Output
RIW CS
Active (CE = High)
Read Only H L Valid
Read/Write H -+L L Valid
Write Only L L Valid
Read Refresh H-+L L-+H Valid -+ Floating
Refresh Only L H Floating
Chip Disable (Unselec~ed) H H Floating
Standby (CE = Low) X X Floating

X = Don't Care

RECOMMENDED AC OPERATING CONDITIONS (Read Write and Read Modify Write Cycles)
Parameter Symbol Min Max Unit
Address Setup Time tAS 0 - ns
Address Hold Time tAH 60 - ns
CE Pulse Transition Time tr 10 100 ns
CE Off Time MCM6605A L,P/ L2,P2 tSB 120 - ns
MCM6605AL 1,P1 90 -
Chip Select Delay Time tCSD - 70 ns
Chip Select Hold Time tr.!>H 0 - ns
Read Write Delay Time tRWD - 70 ns
Read Write Hold Time tRWH 0 - ns
Time Between Refresh tREF - 2.0 ms

2-54
MCM6605A

AC CHARACTER ISTICS
[All timing with tT = 20 ns; Load = 1 TTL Gate (MC74HOO Series), CL = 50 pF (effective))

READ CYCLE (R!W = V1H CS = VIL)

MCM6605AL,P MCM6605AL 1,P1 MCM6605AL2,P2
CharaL1:eristic SVmbol Min Max Min Max Min Max Unit
Read Cycle Time
Chip Enable On Time
Chip Enable to Output Delay
Read Access Time
tcyc(R)
tCE
tco
tacc
470
310
-

-
-
2000
280
300
290
160
-
-
-

2000
130
150
360
200

-
-
2000
-

180
200
ns
ns
ns
ns
II
READ CYCLE TIMING

1 4 - - - - - - - - tcyc(R) - - - - - - - - - . - ,

Stable Address
Address

~~ - Don't Care

2-55
 MCM6605A

WRITE CYCLE (R/W = VIL CS = VIL)

REFRESHCYCLEJ~/W=VI~_C_S_=_V~I.~H~)_____-._____._~~~~~T7~~~~~~~~~~77~--~

I Chip Enable On Ti~--­

Read·Write Release Time
- - - - - - - . - - - - - . - - - - - -..----f-.~:..:-+_::~_+---+__:_::::_1--_+__:_::_:__+--+_-_l
Write Puis,! W~~. ____....__.________._____.____+--.:.=--_+-=.::...-+__
ns
ns
ns
ns
Read-Write to Chip Enable Separation Time ns
- - - - - - - - - - - - - - -..--------------.-.-+----'--'-='--4-----I----I----+--::c::--.-t----+----:::-:--+----t
Data Delay Time' too 70 70 70 ns
O-;;t;-Hold Ti':;-;--~------'---"-- tDH 50 20 50 ns
_____ ._. _ _ _ _ _._ _ _.___._____ ._ _ _ _ _ _ _ _ _ _ _ _ _._L...._ _ _ _ _ _ _ .__ '-__._ _ '--_ _ _ _ ._ _ .,.__._L--_ _ _
-----.-'----~-

*If a write pulse (tW) is employed on the R/W line during a write cycle, then the input data setup time is measured from the
leading edge of the write pulse. The tDS time is the same as that of the read-modify-write cycle.

WRITE AND REFRESH CYCLE TIMING

f--._-- tcyc(WI -----.----------.-l

Address I Stable Address

Data In

~ - Don't Care.

2-56
MCM6605A

READ-MODIFY-WRITE (R/W = VI H ....VIL CS = VIL)

READ REFRESH (See Note 1)
MCM6605AL.P MCM6605AL 1.Pl MCM6605AL2.P2
Characteristic Symbol Min Max Min Max Min Max Unit
Read-Modify-Write Cycle Time teyc(R/W) 590 - 390 - 490 - ns
Chip Enable On Time tCE 430 2000 260 2000 330 2000 ns
Read-Write Release Time IRWR 410 2000 240 2000 310 2000 ns
Write Pulse Width
Data Setup Time
Data Hold Time
Read-Write 10 Chip Enable Separation Time
Chip Enable to Output Delay
tw
tDS
tDH
tRC
ICO
210
0
50
0
-
-
.-
_.
--

280
160
0
20

-
0
-
-
.-

130
160
0
50
0
-
-
-
--

-
180
ns
ns
ns
ns
ns
II
Read Access Time lace - 300' -- 150 - 200 ns

Note 1: A read refresh cycle is possible by bri nging CS high after outpul data
is valid and then bringing R /W low to the write posilion.

READ MODIFY WRITE TIMING

Chip Enable

VCEL

VIH

Chip Select

VIL

V IH

Read/Write

VIL

VIH
2.6 V
Data In Din'Stable
1.2 V
VIL

VDH '._----------4- - - - - - - --
Data Out - - - - - - . k - - - - Floating •

VOL ~"------------ - - - -

~~ - Don't Care

2-57
 MCM6605A

TYPICAL CHARACTERISTICS CURVES

FIGURE 2 - ACCESS TIME versus Voo FIGURE 3 - ACCESS TIME versus AMBIENT TEMPERATURE

.5 1.5

I ~
wI. 3
::;;
4

2"- _.-
w1.3
:;;
>=1.2
1.4

" .... ........ C/O

1. C/O
.1
~1.1
« t'-.
~~
::; o. 9
~
«
.0

O. 8
r-- too-
- ~ 1.0
::! 0.9
«
~ 0.8
1--"1""" - I--I--
I--

2: O. 7 2: 0.7

O. 6 -- 0.6
5 0.5
O. 8.0 9.0 10 11 12 13 14 15 16 17 18 -10 10 w w w ~ ~ m w u
Voo , SUPPLY VOLTAGE (VOLTS) TA, AMBIENT TEMPERATURE

FIGURE 4 - 100 SUPPLY CURRENT versus VOO FIGURE 5 - 100 SUPPL Y CURRENT versus CYCLE TIME
2 -- 0,---

t;;; 2. 0 ·t- ~- r---- 9 --- t-. - ~~ ----- j-'

~ 1. 8 B

Gl 6 f - - I--
~ ~ I
,-- 7 tSB" mint--
>-
~
V
4 f----- 1-. 6
1.
I
~1. 2 r----
~
. - f---- '---- 5
~
8' 0 V
4
~
I
:3« o. 8 ~ 1--. 3

~ 0 6t--·
../ 2
'\
.... ,
V
2: O. 4-""" .--r----- --- 1--- 1 tCE" ~in f---
...::.:....,
,0280 9.0 10 11 12 13 14 15 16 17 18 1.0 10 100
Voo, SUPPL Y va LTAGE (VOLTS) tcye, CYCLE TIME (~s)

FIGURE 6 -100 SUPPLY CURRENT

versus AMBIENT TEMPERATURE FIGURE 7 - REFRESH TIME versus AMBIENT TEMPERATURE
1. 0 100a

8
f""'-.. t--
-- r-- r--
-
- - - 1---- t - - -

~ 10 a
~
~
~

",
7 -- .............
~
a::
w
6 a::
2:
5 w 10

4 ~
3 --I--- :E
>= 1.0

.1
2 --~

g
0 O. 1
-10 10 20 30 40 50 60 70 80 .90 -10 10 w w w ~ ~ m w 90
TA, AMBIENT TEMPERATU RE (DC) TA, AMBIENT TEMPERATU RE (OCI

2-58
MCM6605A

TYPICAL SUPPLY CURRENT TRANSIENT WAVEFORMS

FIGURE 8 - CHIP ENABLE VOLTAGE

14

II
12

10
f 1\
B.O

6.0

4.0

2.0
\
-2.0
o 100 200 300 400 500
I, TIME Insl

FIGURE 9 - iOO SUPPLY CURRENT FIGURE 10 - iCC SUPPLY CURRENT

°R=tIT
12 0

1
I-
10 0

80 I .5 o~-
;:;;
I-
o I-~t= !
--1-- ~-
-,-I ~ 1

""a:
w
a:
::::l
0
It \
I ""a: 0 )
a:
::::l
I" i -Ll
u 0 u 0
~ Ir~ J \ >-
I I I
~ 2
0
\r---..,
~ -1
0

U ~ -2
1 i I

:~!
0
~ '1
i
-3 i
-2 0

-4 0
0 100 200 300 400 500
0
-4 0
1
I 100
i
200 300
l
400 500
I, TIME Ins) I, TIME Ins)

FIGURE 11 - iBB SUPPLY CURRENT FIGURE 12 - iCE SUPPLY CURRENT

80 --,---- 0 l
I
60 0

'1 40 1 20
I-
~ I-
Z IA
~ 20
.A .\,~
W
a:
a:
0
1\ j
a:
G 0
.A ._
... ::::l
u 0
>-
'I' V
~

~ ( i
~ -2 0 ~ -1 0
~ IV
~ -40 ~-2 0
,I !

~I
-60 -3
I
I
-80 -4 00
o 100 200 300 400 500 100 200 300 400 500
t, TIME Ins) t, TIME Ins)

2-59
 MCM6605A~

BLOCK DIAGRAM

Al0A9A8 A7 A6 A5 AOA2A4
20 1918 1716 15 1310 9

I Qj
c:
.:i
aN
~~
en
Qj
c:
..J
QjN
<AM

en~-
iii iii

Row
Decode
Al 21 And
Sit
Sense
A3
Line
Select

Qj Qj
c: c:
..J ..J
QjN
~~
en
<AM
~-
en
Iii Iii'
Bit

Data In 40-----+1 7 Data Out

Chip 8 0 - - - - - - - - - . 4 . - - - - - - - - 1 - - - - - - - < 1 1 " " " ' 1

Select

All VSS ~ Pin 12

VSS= Pin 1
VCC~Pinll

FUNCTIONAL DESCRIPTION
The MCM6605A 4096-bit dynamic RAM uses a three decoder selects one of these 128 bit sense Iines for read
transistor storage cell in an inverting cell configuration. and write operations. During the ¢2 signal, the data on
The single high-level clock (Chip Enable) starts an internal this selected bit sense line is Exclusive ORed with the state
three-phase clock generator which controls the read and of the appropriate data control cell to supply the correct
write functions of the device. The ¢1 signal, which is high output data. After this data is received by the external
when CE is low (standby mode). preconditions the nodes system, CE may be brought low to the standby position.
in the dynamic RAM in preparation for a memory cycle. This assumes that the R/W signal is held high to prevent
The 1>2 signal, which comes on as CE goes high, is the read an internal cp3 being generated.
control and transfers data from storage onto bit sense To perform a write or refresh operation, CE is brought
lines. The 1>3 signal, which comes after 1>2 only during a high and everything is identical to a read operation up
write or refresh cycle, transfers data from the bit sense until the 128 bit sense lines are charged with the selected
lines back into storage. The ¢3 signal occurs only if the columns of stored data. When R/W is brought low (if it is
R/W input is low. . not already there), a 1>3 signal is generateq after cp2 is over.
To perform a read cycle, CE is brought high to The ¢3 signal takes the data from the 128 bit sense lines
initiate a cp2 signal and latch the input addresses. The and returns it to the 128 storage locations it came from.
column decoders select one column in each of the four Because of the design of the memory array, this (/)2-</>3,
storage quadrants (see the block diagram) and transfers read-write operation inverts the data. Therefore, one extra
data from storage onto the 128 bit sense lines. The row row of memory cells, called data control cells, is used to

2-60
MCM6605A

keep track of the polarity of stored .data in order to be VCC- Output buffer supply. This supply goes only to
able to correctly recover it. During the write operation, the data output buffer and draiNs current only when
the input data is Exclusive ORed with these control cells driving an output load high.
before being stored in the array. A refresh cycle does not Preset - This pin should be tied to ground. During devir..e
modify any of the bit sense lines, but simply returns the testing Preset can be used to preset the data control cells
data (now inverted) into storage. to a logic zero. One 200 ns, 12 V pulse will set all 32 cells
All timing signals for the MCM6605A are specified simultaneously. Preset has no system use; its only purpose

II
around these operations. The following is a brief descrip- is to ensure a good logic level in the control cells after
tion of the input pins and relevant timing requirements. first power up. In system use, this good logic level will
Chip Enable - CE is a single high level clock which ini- come naturally after the first few refresh cycles.
tiates all memory cycleli. CE can remain low as long as
desired for specific applications as long as the 2.0 ms re- APPLICATIONS INFORMATION
fresh requirements are met. Power Supplies
Chip Select - This signal controls only the I/O buffers. The MCM6605A is a dynamic RAM which has essentially
When CS is high, the input is disconnected and the output zero power drain when in the standby (CE low) mode.
is in the 3·state high-impedance state. A refresh cycle is, When operating, the VDD supply may experience transients
therefore, a write cycle with CS high. CS has no critical in the order of 100 rnA for a short time (Figure 9). The
timing with respect to any other signal except that there VBB supply, which has very low dc drain while operating,
is a finite delay between activation and data out. may see transients of about 40 mA during the edges of CEo
Therefore, appropriate bypassing of both supplies is recom-
Read/Write - When high, R/W inhibits the internal 1{)3
mended. This bypassing has been simplified by the location
signal, thereby keeping the memory from writing. When
of the power supply pins on the corners of the package.
RIW is low, a 1{)3 will occur soon a,fter 1{)2 is finished. For a
The Vec line supplies only the input leakage of a
read cycle, R/W should be high within tRWD of CE to
insure that a 1{)3 does not start. The only timing require- TTL load on Data Out and should never exceed about
100 JlA, presenting little bypassing requirement.
ment on the RIW input for writing is a minimum write
pulse defined as the overlap of CS, CE, and R/W. Refresh Power dissipation for a system of N chips is much,
cycles require that CS be high to inhibit the input buffer lower than N times the 335 mW typical dissipation for a
before a 1{)3 occurs. Thus CS should be high within tCSD full speen operating chip. This is bec.ause the unselected
for a refresh cycle, or before R/W goes low for a read- rows in a memory array card are operating in the standby
refresh cycle. mode of near zero dissipation. This zero standby power is
actually unachievable because of the requirements for
Data In _. The input data must be valid for a sufficient refresh. Therefore, power dissipation for an array of
time to override the data stored on the selected bit sense N X M chips operating at 11 cycle time, tREF refresh
line. It must remain valid for the "write pulse" defined increment, and max(mum CE down time between cycles is:
under ReadIWrite. Signals on the Din pin are ignored
when either CS.or R/W is high, or CE is low.
PD "'" M(~?O ns) 335 mW + (N-1) (M)(-~) 335mW
Data Out - Output data is inverted from input data and is 11 ns tREF IlS
valid tacc after CE goes high. The data will remain valid
as long as CE is high and CS remains low. With either CE For a 550·ns-cycle·time, 64 k by 16 system (16 by 16
low or CS high, the output is in a high-impedance state. chip array) with refresh at 2.0 ms, the approximate power
The data output is initially precharged high when CE goes dissipation is:
high and is then either discharged to ground or left high
depending on the stored data. This precharging followed P
D
"'" 16 (490) 335 + (15) (16)
550 -
(~)
2000
335
by valid data occurs regardless of the state of the R/W
input, making the write cycle actually a read-write cycle. "'" 4775 mW + 630 mW = 5.4 W
The output will also try to precharge during a refresh cycle A similar one megabyte system, eight bytes wide, would
but will be kept at high impedance by the CS being high. have a dissipation of only 24 W. If the low standby
If CS is originally low and is then brought high (within power capability were not used, olier 600 W would
the tCSD specification) the output may start to precharge be dissipated.
before being cut off and returned to high impedance.
Addresses - The addresses are latched when CE goes high, Refresh
and may be removed after an appropriate hold time. The MCM6605A is refreshed by performing a refresh (or
VSS - Circuit ground. write) cycle on each of the 32 combinations of the least
significant address bits (AO-A4) within a 2.0 ms time
Vee _. The reverse bias substrate supply. Forward biasing period. (A5-A 11 must remain constant at proper logic
this supply with 'respect to VSS will destroy the memory levels.) This refresh can be done in a burst mode (32 cycles
device. starting every 2.0 ms) or in a distributed mode where one
VDO - Positive supply voltage. cycle is done every 62.5 IlS.

2-61
 MCM6605A

A refresh abort can be accomplished by treating a data bus buffering transceivers and the memory array
refresh cycle as a read-modify-write cycle with CS" high. (which consists of 16 MCM6605As) organized into two
This type of cycle can be aborted any time until the R/W rows of 4K bytes each.
signal has been brought low to allow a ¢3 clock to begin. The third section of the block diagram comprises
refresh and control logic for the memory system. This
Non-Volatile Storage logic interfaces the timing of the refresh handshaking with
In many digital systems, it is extremely important to the microprocessor (MPU) clock circuitry. It handles

I retain data during emergencies such as power failure. requests for refresh, the generation of refresh addresses,
Unfortunately, however, most random access read/write the synchronization of a Power Fail signal, the multiplexing
semiconductor memories such as the MCM6605A are of the external Memory Clock with the internal clock
volatile. That is, if power is removed from the semicon- (used during standbY), and the generation of a -5 V supply
ductor memory, stored information'~s lost. Therefore, on the board using a charge,pump method.
non-volatility for a specified period of time becomes highly The refresh control logic is illustrated in Figure 14. It
desirable· -. as a necessity to maintain irreplaceable infor- handles the refreshing of the memory during both operating
mation or as a convenience to avoid the time cOnsuming and standby modes. The timing for this logic is given in
and troublesome task of having to reload the memory. Figure 15. Figure 16 gives the memory timing for the
The extremely low standby power dissipation of the standby mode only. Decoding of the memory clock (CEA
MCM6605A makes it ideal for main memory applications and CEB) and the circuitry to synchronize the Power Fail
requiring battery backup for non-volatility. For example, signal are shown in Figure 17, with the timing given in
the MCM6605A can be employed in an 8K byte non- Figure 18.
volatile main memory system application for micropro- The memory device clock (CEA and CEB) during stand-
cessors. The memory system can be partitioned into three by is· created by a .monostable multivibrator (MC14528)
major sections as illustrated in Figure 13. The first section and buffered from the memory array by three MC14503
contains the address buffers and the Read/Write and Chip buffers in parallel. This clock is multiplElxed with the
Select decoding logic. The second section consists of the Memory Clock by use of the three-state feature of the

FIGURE 13 - NON-VOLATILE MEMORY SYSTEM BLOCK DIAGRAM

r--------------------------------,
Address Buffers and Decoding Logic Refresh and Power Fall LogiC

BAO AO

A4

Refresh Addresses
AO A4
AO A4
Address Refresh Addresses
Buffers
AS
Refresh
CMOS Request
All
Refresh/Power Fail
GSA Logic Refresh
Grant
BAIS
To
Memory
Array CEA CEB
R/W

VMA Buffers

Memory Memory Clock

Clock
_ _ _ _ _ _ _ _ _ _ _ """"""
r-----------------
I
_~L

I
DO 1~.---------------,--DoutO
I
I I
,.......- - - - - - - - - - - - - - - ' - Do ut 7
I Data I
BK x 8 Memory Array
I Transceivers
1----------------,-. 0 inO
I
16 MCM660SA
2 Rows x 8 Columns
I
I 07" t------------~. Din7
I
I
L ______________ 3~~~~~=~~
. .
____ _ _____ ...JI

2-62
MCM6605A

MC14503. The Memory clock (used during normal opera- FaIT signal change states just prior to or during a refresh
tion) is translated to 12 V levels by use of an MC3460 cycle. The trailing edge of the 500 ns monostable clears
Clock Driver. Decoding of the CEA and CEB signals (j.e., the MC14027 flip-flop, enabling the second flip-flop in the
clocking only the memory bank addressed) to conserve package. The state of Power Fail and Power Fail is applied
power is accomplished by the logic within the MC3460. to the K and J inputs of this second flip-flop and is syn-
Since the Power Fail signal will occur asynchronously chronized by clocking with Memory Clock_ The outputs
with both the Memory Clock and the refreshing operation of this flip-flop, labeled Bat and Bat, lock the system into
(Refresh Clock), it is necessary to synchronize the Power
FaTI signal to the rest of the system in order to avoid
aborting a memory access cycle or a refresh cycle. An
MC14027 dual flip-flop is used as the basic synchronization
device. The leading edge of Hie Refresh Clock triggers a
the refresh mode and multiplex in the internal clock for
standby operation when Bat = "1". The voltage to logic
not required for the refresh only mode of operation is
removed to conserve power.
By using CMOS for the refresh logic and capacitance
II
3 p.s monostable multivibrator which is used as a refresh drivers, and a low current refresh oscillator, the standby
pretrigger. The trailing edge of this pretrigger triggers a current required for the 8K byte system is extremely
500 ns monostable which creates the CE pulse during small, as noted in Table 1. This low standby current
standby operation. The 3 p.s pretrigger signal is used to requirement can be easily supplied for several days with
set half of the MC14027 flip-flop, the output of which, standard type +12 V batteries. For more detailed informa-
®, then inhibits a changeover from the standby to the tion on this sytem and a large mainframe memory system,
see Application Notes AN-732 and AN-740.
operating modes (or vice versa). This logic prevents
the system from aborting a refresh cycle should the Power

FIGURE 14 - REFRESH CONTROL LOGIC

12 V
100 pF 221 k 1%

t 1/,13 MC14049
0.022 !JF lN4148

i 0.
5
~BVBto
Refresh Addresses MZ4625
~ ____ ~A~ ______ ~

- Ref
Al A2 A3 - 1/2 MC14049
100 k
+5.0 V

475 k 1%

100 k

Refresh Grant

Ba, ------------------------~

FIGURE 15 - REFRESH TIMING

Bus 4>1

Bus 4>2

Occurs Every 64"s

Refresh Request --------,~7.%0~~7.~~~~~~~I---------------

RefreSh Grant

Memory Clock

I22LL2l Don't Care

2-63
MCM6605A

FIGURE 16 - MEMORY TIMING IN STANDBY MODE

o 32/lS 64 /lS

Refresh Clock

A = First 4K Byte

____~n~______________~n~_______
"RefreSh Address Counter Incremented
B = Second 4K Byte
CE A • CEB

CS A . CSB "1" - - - - - - - - - - - - - - - - - - -........- - - - - - - - - - - - -

R/WA. R/WB "0" - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

FIGURE 17 - POWER FAIL LOGIC AND CHIP ENABLE DRIVER

12 V
MC14503
5 11 • 5 11 •
520 pF 82 pF r---~
1% I
T1 T2 T1 T2

o Q~-----------------6

Refr.,h Clock
112 MC14528 1/2 MC1452B
3 !,S 500 ns

6 6

12 V
12 V

Q Bat
Q
113 MC14049
112 MC 14027 112 MC14027

114 MC14001 CE B

12 v Q 6 1------+-------__

1 •

1/S-MC7407 12 V

1/4 MC3302
22 k

12 V

22k

MC3460

- - - - - - - - - - - - - - - - - - - - - - - -____~ ASel
A

----------------------------~ BSer
B
Memory Clock

+5V ___~-.....J

2-64
MCM6605A

FIGURE 18 - POWER UP/DOWN SYNCHRONIZATION

1.0j.1s 2.0j.1s 3.01'5 4.01'5

\'--------
-11\\..._____

II
500 n. Mono.table _ _ _ _ _ _ _ _ _ _ _ _ _ _

7;~n:b~~B _ _ _ _ _ _ _ _ _ _ _ _ _ _ _~;---\\..._ _ ___

Clock Input ® "---I

Inhibit ® -.-l \\...____
I No Power Fail signal changes will be I
~ recognized dUring this time. --------,

TABLE 1 - STANDBY MODE CURRENT ALLOCATION

Circuit Section Typical Current Circuit diagrams utilizing MOTorola products are included as a means
of illustrating typical semiconductor appl icatians; consequently.
+12 V Current (VOO) for 16 MCM6605A's 5 mA complete information 5ufflcient for construction purposes IS not
necessarily given. The Information has been carefully checked and
Charge Pump 3mA
15 believed to be entirely reliable However, no responsibility IS
Comparator 2 mA assumed for InaccuraCies. Furthermore, such Information does not
convey to the purchaser of the semiconductor devices described any
Capacitance Orivers 4mA 'Icense under the patent rights of Motorola I nco or others
Total 14mA

2-65
 ® MOTOROLA
MC'M66'41
MCM66L41

4096-BIT STATIC RANDOM ACCESS MEMORIES MOS

The MCM6641 series 4096 X 1-bit random access memory is (N-CHANNEL, SILICON-GATE)

II fabricated with high density, high rei iabil ity N-channel sil icon-
gate technology. For ease of use, the device operates from a single
5-volt power supply, is directly compatible with TTL and DTL,
and requires no clocks or refreshing because of fully static operation.
4096"BIT STATIC
RANDOM ACCESS MEMORIES
The fully static operation allows chip selects to be tied low further
simplifying system timing. Data access is particularly simple, since
address setup times are not required. The output data has the same
polarity as the data input.
The MCM6641 is designed for memory appl ications where simple
interfacing is the design objective, and is assembled in 18 pin dual
in-I ine packages with the industry standard pin-outs.
• Single±10%+5VSupply
PIN ASSIGNMENT
• Fully Static Operation-No Clock, Timing Strobe, Pre-Charge,
or Refresh Required
• Industry Standard 18-Pin Configuration 18

• Fully TTL Compatible 17

16
• Common Data Input and Output Capability
15
• Three-State Outputs for OR-Tie Capability
14
• Power Dissipation MCM6641 Less Than 550 mW (Maximum) 13
MCM66L41 Less Than 385 mW (Maximum)
12
• Standby Power Dissipation Less Than 125 mW (Typical) 11
• Plug-in Replacement for TMS4044 10

MAXIMUM ACCESS TIME/MINIMUM CYCLE TIME

-- MCM6641-20
MCM66L41-20
200 ns
MCM6641-30
MCM66L41-30
300 ns

MCM6641-25 MCM6641-45
250 ns 450 ns
MCM66L41-25 MCM66L41-45

BLOCK DIAGRAM PIN NAMES

AO------~~-r------. _ _ _ _ VSS Address Input

AO--Al1
A 1 ______..... ~.,.__.

D Data Input
A2 _ _ _ _...J""O,....--; Memory Array ---VCC
Row Q Data Output
64 Row
A8 - - - - - . . . . 1 .... - - - . Select Ch ip Select
64 Columns
A7 • VCC Power Supply (+ 5 V)
A6-----....I ...~-. Ground
VSS
W Write Enable
Q

TRUTH TABLE
w-_........-..... S W D a Mode
5 H X X HI-Z Not Selected
L L HI-Z Write "0"
L 'L H HI-Z Write "1"
A3 A4 A5AllAl0A9 L H X Output data Read
MCM6641, MCM66L41

ABSOLUTE MAXIMUM RATINGS (See Note 1)

Rating Value Unit This device contains circuitry to protect the
Temperature Under Bias -10 to +80 °c inputs against damage due to high static voltages
Voltage on Any Pin With Respect to VSS -0.5 to +7.0 Vdc or electric fields; however, it is advised that
normal precautions be taken to avoid applica·
DC Output Current 20 mA
tion of any voltage higher than maximum rated

II
Power Dissipation 1.0 Watt voltages to this high-impedance circuit.
Operating Temperature Range o to +70 °c
Storage Temperature Range -65 to + 150 °c

Note: 1. Permanent device damage may occur if ABSOLUTE MAX IMUM

RATINGS are exceeded. Functional operation should be restricted
to RECOMMENDED OPERATING CONDITIONS. Exposure to
higher than recommended voltages for extended periods of time could
affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Vec = 5.0 V ± 10%, T A = 0 to +70 0 C)

RECOMMENDED DC OPERATING CONDITIONS

MCM6641 MCM66L41
Parameter Symbol Min Typ Max Min Typ Max Unit
Input Load Current III - - 10 - - 10 IlA
(All Input Pins, Vin =0 to 5.5 V)
Output Leakage Current IILOI - - 10 - - 10 IlA
(S = 2.4 V, Vin = 0.4 to Vee)
Power Supply Current ICC - 80 100 - 55 70 mA
(VCC = 5.5 V, lout = a mA, TA = OoC)
Input Low Voltage VIL -0.5 - 0.8 -0.5 -- 0.8 V
Input High Voltage VIH 2.0 - 6.0 2.0 - 6.0 V
Output Low Voltage VOL - 0.15 0.4 - 0.15 0.4 V
IOL = 2.1 mA
Output High Voltage VOH 2.4 - - 2.4 V
10H = 1.0 mA
OutP:.Jt Short Circuit Current IOS(2) - - 40 - - 40 mA
.
TYPical values are at VCC ... 5.0 V, T A = 25 ° C
Note: 2. Duration not to exceed 30 seconds.

CAPACITANCE
(f = 1.0 MHz, T A = 25 0 C, periodically sampled rather than 100% tested.)

Characteristic Symbol Max Unit

Input Capacitance (Vin = 0 V) 5.0 pF

Output Capacitance (V out =0 V) Cout 10 pF

STANDBY OPERATION
(Typical Supply Values)

Device Supply Operating Standby Max Standby Power

MCM6641 VCC +5 V +2.4 V 225 mW
MCM66L41 VCC +5 V +2.4 V 150mW

The MCM6641 series is offered in an 18-pin dual-in-line ceramic (JL suffix) and plastic (NL suffix) packages designed for insertion in mounting-
hole rows on 300-mil centers. The series is designed for operation from OOC to 70°C.

2-67
 MCM6641, MCM66L41

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature unless otherwise noted.)

Input Pulse Levels . . . . . . . . . . . . . . . . 0.8 Volt to 2.0 Volts

Input Rise and Fall Times . . . . . . . . . 10 ns
Input and Output Timing Levels 1.5 V01ts
Output Load . . . . . . . . . . . . . . . . . . . . . . . 1 TTL Gate and CL = 100pF

I AC OPERATING CONDITIONS AND CHARACTERISTICS

Read (Note 3), Write (Note 4) Cycles

RECOMMENDED AC OPERATING CONDITIONS (TA = 0 to 70 0 C, VCC = 5.0 V ± 10%)

MCM6641-20 MCM6641-25 MCM6641-30 MCM6641-45

MCM66L41-20 MCM66L41-25 MCM66L41-30 MCM66 L41-45
Parameter Symbol Min Max Min Max Min Max Min Max Units
Read Cycle Time tRC 200 - 250 - 300 - 450 - ns
Access Time tA - 200 - 250 - 300 - 450 ns
Chip Selection to Output Valid tso - 70 - 85 - 100 - 120 ns
Chip Selection to Output Active tsx 10 - 10 - 10 - 10 - ns
Output 3-State From Oeselection tOTO 1- 40 - 60 - 80 - 100 ns
Output Hold From Address Change tOHA 50 - 50 - 50 - 50 - ns
Write Cycle Time twc 200 - 250 - 300 - 450 - ns
Write Time tw 100 - 125 - 150 - 200 - ns
Write Release Time tWR 0 _. 0 - 0 - 0 - ns
Output 3-State From Write tOTW - 40 - 60 - 80 - 100 ns
Data to Write Time Overlap tow 100 - 125 - 150 - 200 - ns
Data Hold From Write Time tOH 0 - 0 - 0 - 0 - ns

READ CYCLE TIMING ,(Note 5) WRITE CYCLE TIMING (Note 6)

~-----------tRC----------~ I~-----------twc----------~

~----------tA--------~
Address
-+__ ______ --~--------------------~,-----
Address __ J~ ____________________ ~

Dout------------------~----_4ESc=====~

Notes: A Read occurs during the overlap of a low S and a high W.

4. A Write occurs during the overlap of a low S and a low W.
5. W is high for a Read cycle.
6. If the S low transition occurs simultaneously with the W low
transition, the output buffers remain in a high impedance rate.

2-68
 ® MOTOROL.A MCM6664

[-------.-----p-r-~·duct
Previevv
------_.. _--_.- .--~--------------

MOS

•
(N-CHANNEL, SILICON-GATE)

65,536-BIT
DYNAMIC RAM
65,536-BIT DYNAMIC RAM
The MCM6664 is a 65,536 bit, high-speed, dynamic Random-Access
Memory. Organized as 65,536 one-bit words and fabricated using HMOS
high-performance N-channel silicon-gate technology. This new breed of
5-volt only dynamic RAM combines high performance with low cost and
improved reliability.
By multiplexing row- and column-address inputs, the MCM6664 re-
quires only eight address lines and permits packaging in standard 16-pin
dual-in-line packages. Complete address decoding is done on chip with
L SUFFIX
address latches incorporated. Data out is controlled by CAS allowing CERAMIC PACKAGE
for greater system flexibility_ CASE 690
All inputs and outputs, including clocks, are fully TTL compatible.

J'_
The MCM6664 incorporates a one-transistor cell design and dynamic
storage techniques. In addition to the RAS-only refresh mode, refresh
control function available on pin 1 provides automatic and self-refresh
modes.
• Organized as 65,536 Words of 1 Bit 1 C SUFFIX
• Single +5 V Operation FRIT-SEAL
CERAMIC PACKAGE
• Fast 150 ns Operation CASE 620

• Low Power Dissipation

250 mW Maximum (Active)
30 mW Maximum (Standby)
• Three-State Data Output
• Internal Latches for Address and Data Input
PIN ASSIGNMENT
• Early-Write Output Capability
• 16K Compatible 128-Cycle, 2 ms Refresh
REFRESH q~ 16 vss
• Control on Pin 1 for Automatic and Self Refresh
D 2 15 CAS
• RAS-only Refresh Mode
W 3( 14 Q
• CAS Controlled Output Providing Latched or Unlatched Data
RAS 4 ~13 A6
• Upward Pin Compatible from the 16K RAM (MCM4116)
AD 5 ~12 A3

A26 11 A4
A17 ~10 A5

Vee 8 ~ 9 A7
-------------_._------_._-------------'

OUTPUT BUFFER TRUTH TABLE

Internal
Early Write CAS Refresh Control (CAS Internal) Output Buffer
This device contains circuitry to protect the
H X X (X) Hi-Z inputs against damage due to high static volt-
X H X (X) Hi-Z ages or electric fields; however, it is advised that
- (H) normal precautions be taken to avoid applica-
L L L Maintains Previous
tion of any voltage higher than maximum rated
Data
Voltages to this high impedance circuit.
L L H (L) Active
This is advance informatIon and specifications are subject to change without notice.

2-69
 MCM6664

BLOCK DIAGRAM

+- Vcc
+-Vss
i
r---
PruchtJruc
Sltnw Amplifier
Clock

II i1I
AO ---+

Al-.... 16.384·8" M.morv ~ 16,384·811 MI!nlory ~RAS

Array 0 Array
~
---+
~ 8. (3
+-00
A2 ~ ~ ::i
3
:::
CD
c
j
(')
, __ Write. Vi
A3 ---+
l 1/211 of 1281 11211 01 1~81 ::::
0

[
f Column Decoder Column Dltcoder
[
A4-.... [ ~ i + - REFAES'H
~
g- ~
A5 ---+ ii
§ ~ 4 - - Data In. 0

16,384·811 Memory
a 16.384-811 Memory £
Array N Array
A6-.... lID - - . . Output Data. a
1I
~
A7 ---+ 0
~
8.
Precharge ~
~nse Amplifier Sense Amplifier
Clock

4116 TO 6664 COMPARISON

MCM4116

VSS 16 VSS
PIN VARIATIONS
0 2 15 CAS

W 3 14 a PIN NUMBER MCM4116 MCM6664

~ 4 13 A6
1 VBS (-5 V) REFRESH
AO 12 A3 VOO (+12 V)
8 Vee (+5 V)
A2 6 11 A4 9 VCC (+5 V) A7
A1 10 A5

VOO 8 9 VCC

MCM6664

~ 1 16 VSS
On-Chip Refresh FeatureslBenefits
0 2 15 CAS
Vi 3 14 a Reduce System Refresh Controller Design Problem

FiAS 4 13 A6 Reduce System Parts Count

AO 5 12 A3 Reduce System Noise Increasing System Reliability
A2 6 11 A4 Reduce System Power During Refresh
A1 7 10 AS

VCC 8 9 A7

2-70
MCM6664

READ CY~LE TIMING

tRC

RAS
VIHC-
VIL-
tAR
---, tRAS

II
tCSH
tRSH

tCAS

VIH-
ADDRESSES VIL_

LtCAC-l J
D out
V9 H - ___________________ 'RAe~. ~:';: ~_t_O_F-F
HI Z {
VOL-

WRITE CYCLE TIMING

ADDRESSES

VOH-______________________________________
Dout VOL- HiZ

2-71
 MCM6664

SELF REFRESH MODE (Batt.ry Backup)

(CAS', Addr.....; Dlta-In, Ind Write Ir. Don't Care)

II tFBR

AUTOMATIC PULSE REFRESH CYCLE

(CAS', Addresses, Data-In, and Write are Don't Care)

tRC+tRP _ __

tRFD~~----~__-------------tFRD~--·--------~

1~ controls the output data. If CAS remaons low the previous output will remain valid. When CAS IS brought high, the output
wIll assume a high·impedance state.

RAS-ONLY REFRESH CYCLE

(Data-in and Write are Don't Care, CAS is HIGH)

~------------------tRC+tRP------------------~

ADDRESSES,
AO-AS

2-72
MCM6664

READ-WRITE/READ-MODIFY-WRITE CYCLE

RAS

CAS
VIHC-
VIL_

V1HC_
tAR
"I
tCSH
tRWC
tRAS

tRSH

tCAS
•
VIL_

VIH_
ADDRESSES
VIL_

D out

2-73
 MCM6810
® MOTOROLA
1.0 MHz

MCM68AIO
1.5 MHz

MCM68B10
2.0 MHz

128 X 8-BIT STATIC RANDOM ACCESS MEMORY

II The MCM6810 is a byte-organized memory designed for use in

bus·organized systems. It IS fabricated with N-channel silicon·gate
technology. For ease of use, the device operates from a single power
supply, has compatibility with TTL and DTL, and net'!ds no
MOS
IN-CHANNEL, SILICON-GATE I

128 X 8-BIT STATIC

RANDOM ACCESS
clocks or refreshing because of static operation.
The memory is compatible with the M6800 Microcomputer
MEMORY
Family, providing random storage in byte increments. Memory
expansion IS provided through mUltiple Chip Select inputs.
P SUFFIX
• Organized as 128 Bytes of 8 Bits PLAsTIC PACKAGE
• Static Operation CASE 709

~
• Bidirectional Three-State Data Input/Output
• Six Chip Select Inputs (Four Active Low, Two Active High)
• Single 5· Volt Power Supply L SUFFIX
CERAMIC PACKAGE.
• TTL Compatible
CASE 716
• Maximum Access Time = 450 ns - MCM6810
360 ns - MCM68A 10
PIN ASSIGNMENT
250 ns - MCM688 10
24

23

22
ORDERING INFORMATION
4 21

Speed Device Temperature Range 20

1.0 MHz MC681OP, L o to 700C 6 19

MC6810CP, CL -40 to +85 0 C 18

17
MIL-STD-8838 MC6810BJCS -55 to +125 0 C
MIL-STD-883C MC6810CJCS 16

1.5 MHz MC68Al0P, L o to +70 o C 10 15

14
-40 to +85 0 C
11
MC68Al0CP, CL
12 13
2.0 MHz MC68Bl0P, L o to +700C
M6800 MICROCOMPUTER FAMILY MCM6810 - RANDOM ACCESS MEMORY
BLOCK DIAGRAM BLOCK DIAGRAM
r------,

Data
Bus

Memory Address
and Control

Address Data
Bus Bus

2-74
MCM6810, MCM68A10, MCM68B10

MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage VCC -0.3 to +7.0 Vdc
This device contains circuitry to protect
Input Voltage Vin -0.3 to +7.0 Vdc the inputs against damage due to high
Operating Temperature Range TA TL to TH °c static voltages or electric fields; however.
o to 70 it is advised that normal precautions be

II
-40 to 85 taken to avoid application of any voltage
higher than maximum rated voltages to
-55to125
this' high impedance circuit.
Storage Temperature Range T stg -65 to +150 °c
Thermal Resistance 8JA 82.5 °C/W

ELECTRICAL CHARACTER ISTICS IV cc ~ 5.0 V "5%. VSS ~ O. T A ~ TL to TH unless otherwise noted)

Characteristic Symbol Min Typ Max Unit

Input Current (An. R/W. CS n • CS n ) lin 2.5 MAdc
a
(Vin ~ to 5.25 V)
Output High Voltage VOH 2.4 Vdc
(lOH ~ -205 MA)
Output Low Voltage VOL 0.4 Vd('
(IOL ~ 1.6 mAl
Output Leakage Current (Three·State) ITSI 10 }JAde
(CS ~ 0.8 V or CS ~ 2.0 V. V out ~ 0.4 V to 2.4 V)
Supply Current 1.0 MHz ICC 80 mAde
(VCC ~ 5.25 V. all other pins grounded) 1 5.2.0 MHz 100
Input Capacitance (An. R/W. CS n . CS n ) e ,n 7.5 pF
(Vin ~ O. T A ~ 25 0 C. f ~ 1.0 MHz)
Output Capacitance (On) Cout 12.5 pF
(V out ~ O. TA ~ 25 0 C. f ~ 1.0 MHz. CS(/) ~ 0)

RECOMMENDED DC OPERATING CONDITIONS

r Parameter I Symbol I Min

1 Nom
1 Max , Unit
[ Input High Voltage
I VIH I 2.0 I I 5.25 I Vdc
r Input Low Voltage 1 VIL 1 -0.3
1 J 0.8 [ Vdc

BLOCK DIAGRAM

2 00
AO 23 3 01
AI 22 02
A2 21 03
A3 20 6 04
A4 19 05
A5 18 06
A6 17 07
Cs5 15
Cs4 14
eS3 13
CS2 12
Cs1 11

eso 10

2-75
 MCM6810, MCM68A10, MCM68B10

FIGURE 1 - AC TEST LOAD

5.0 V
AC TEST CONDITIONS
AL:2.5k
Condition Value
Input Pulse Levels 0.8 V to 2.0 V Test Point o-....~_-+l...
I-~ MMD6150

II
~ ~, or Equiv
Input Rise and Fall Times 20 ns
Output Load See Figure 1 130 pF' ... ~ 11.7 k
~, MMD7000
~, or Equiv

• I nc I udes J i9 Capacitance
. AC OPERATING CONDITIONS AND CHARACTERISTICS
READ CYCLE (VCC = 5.0 V' 5%, VSS = 0, TA = TL to TH unless otherwise noted.)
MCM6810 MCM68A10 MCM68B10
Characteristic Symbol Min Max Min Max Min Max Unit
Read Cycle Time tcydR) 450 - 360 - 250 - ns
Access Time tacc - 450 - 360 - 250 ns
Address Setup Time tAS 20 - 20 - 20 - ns
Address Hold Time tAH 0 - 0 - 0 - ns
Data Delay Time (Read) tDDR - 230 - 220 - 180 ns
Read to Select Delay Time tRCS 0 - 0 - 0 - ns
Data Hold from Address tDHA 10 - 10 - 10 - ns
Output Hold Time tH 10 - 10 - 10 - ns
Data Hold from Read tDHR, 10 80 ,10 60 10 60 ns
Read Hold from Chip Select tRH 0 - 0 - 0 - ns

READ CYCLE TIMING

~------------------------tcyc(R)------------------------~

~--------------tacc--------------~~~I

2.0 V
Address
0.8 V

CS

~------tDDR------~

0.8 V

R/W

Data QlJt ------------.c

~ = Don't Care
Note: CS and Cs can be enabled for consecutive'
read cycle. provided ·A/W remeln. at V I H.

2-76
MCM6810, MCM68A 10, MCM68Bl0

WRITE CYCLE (VCC = 5.0 V ± 5%, VSS = 0, T A ~ TL to TH unless otherwise noted.)

MCM6810 MCM68Al0 MCM68810

Characteristic Symbol Min Max Min Max Min Max Unit
Write Cycle Time tcyclW) 450 - 360 - 250 - ns
Address Setup Time tAS 20 - 20 - 20 - ns

•
Address Hold Time tAH 0 - 0 - 0 - ns
Chip Select Pulse Width tcs 300 - 250 - 210 - ns
Write to Chip Select Delay Time twcs 0 - 0 - 0 - ns
Data Setup Time (Write) tDSW 190 - 80 - 60 - ns
Input Hold Time tH 10 -- 10 - 10 _. ns
Write Hold Time from Chip Select tWH 0 -

WRITE CYCLE TIMING

AddreSS~8V

~
2.0 V

tAS

2.0 V
CS _____________ ~~~~~J

CS --------...1..,..,,,.....,...,....,.,...,..,.
0.8 V

R/W
0.8 V

Data In ~~~~~.~~~~-D-atal-nSt-able---tH~~~~~~~~~~~~~~~~~
Wffi - Don'tCare Note CS and CS can be enabled for consecutive write cycles
provided R/W is strobed to V I H before or coincident
with the Address change, and remains high for time tAS

2-77
 ® MOTOROLA
MCM2532
MCM25A32

Advance InforIllation
MOS
(N·CHANNEL. SILICON-GATE)
4096 X 8-BIT UV ERASABLE PROM

II The MCM2532/25A32 is a 32,768-bit Erasable and Electrically

Reprogrammable PROM designed for system debug usage and similar
applications requiring nonvolatile memory that could be reprogram-
med periodically. The transparent window in the package allows the
4096 X 8-BIT
UV ERASABLE PROM

memory content to be erased with ultraviolet light.

For ease of use, the device operates from a single power supply
and has a static power-down mode. Pin·for·pin mask programmable
ROMs are available for large volume production runs of systems
initially using the MCM2532.
• Single +5 V Power Supply
• Organized as 4096 Bytes of 8 Bits FRIT-SEAL PACKAGE
• Automatic Power-Down Mode (Standby) CASE 623A

• Fully Static Operation (No Clocks) L SUFFIX SIDEBRAZE CERAMIC PACKAGE

ALSO AVAILABLE - CASE 716
• TTL Compatible During both Read and Program
• Maximum Access Time = 450 ns MCM 2532
350 ns MCM25A32
• Pin Compatible with MCM68A332 Mask Programmable ROMs PIN ASSIGNMENT

24
2 23
3 22
MOTOROLA'S PIN COMPATIBLE EPROM FAMILY 4 21
(INDUSTRY STANDARD PINOUTS) 5 20
6 19
7 18
8 17
64K
9 16
A7 Vee 24 32K
16K 10 15
A6 23 Vee 24
8K 11 14
A5 A9 22 A8 23 24
12 13
A4 21 A9 22 e 23 24
5 A3 20 Vpp 21 22 23
6 A2 19 E/Progr 20 21 22
Al A" 18 AlO 19 20 21
Ao 0°7 17 All 18 19 20
000 DOs 16 0°7 17 18 19 *PIN NAMES
1----- ----~-- -------
10 0°1 DOS lS 0°6 16 17 Progr 18 A ... . Address
11 0°2 D~ 14 DOS 15 16 17
0°7 DQ . . . . . . . . Data Input/Output
12 Vss 003 13 0°4 14 15 006 16
E/Progr ., Dual Function Enable
MCM68764 003 13 14 DOS 15 (Power-down/program Pulse)
MCM2532 13 0°4 14
VCC . . . . . . . . . . . +5 V Supply
MCM2716 003 13
Vpp . . .. +25 V Program Voltage
MCM2708 VSS . . . . . . . . . . . . . . Ground

*New Industry standard nomenclature

This is advance information and specifications are subject to change without notice.

2-78
MCM2532, MCM25A32

PIN NUMBER BLOCK DIAGRAM

9-11, Data Input/Output
Mode 13-17 12 20 21 24 DOO-D07
DQ VSS E/Progr Vpp VCC
Read Data out VSS VIL Ot05 V VCC
Output Disable Hi-Z VSS VIH o to 25 V VCC
Standby Hi-Z VSS VIH o to 5 V VCC

II
Program Data in VSS Pulsed VPPH VCC
VIH to VIL
Program Verify Data out VSS VIL o to 5 V VCC
Program Inhibit Hi-Z VSS VIH VpPH VCC

ABSOLUTE MAXIMUM RATINGS (1)

Rating Value Unit
Temperature Under Bias -10 to +80 oC
Storage Temperature -65 to +125 oC
All Input/Output Voltages with
Respect to VSS +6 to -0.3 Vdc
Vpp Supply Voltage with Respect to VSS +28 to -0.3 Vdc

NOTE 1: Permanent device damage may occur if ABSOLUTE

MAXIMUM RATINGS are exceeded. Functional opera-
tion should be restricted to RECOMMENDED OPERA-
TING CONDITIONS. Exposure to higher than recom-
mended voltages for extended periods of time could
affect device reliability.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Fully operating voltage and temperature range unless otherwise noted)

RECOMMENDED DC READ OPERATING CONDITIONS (T A = 0 0 to +70 0 C)

Parameter Symbol Min Nom Max Unit

Supply Voltage* MCM2732 VCC 4.75 5.0 5.25 Vdc
MCM27A32 4.5 5.0 5.5 Vdc
VPP 0 5.0 VCC +0.6 Vdc
Input High Voltage VIH 2.2 - VCC +1.0 Vdc
Input Low Voltage VIL -0.1 - 0.65 Vdc

READ OPERATION DC CHARACTERISTICS

Characteristic Condition Symbol Min Typ Max Unit

Address and E Input Sink Current Vin = 5.25 V lin - - 10 J1.A
Output Leakage Current V out = 5.25 V ILO - - 10 J1.A
VCC Supply Current* (Standby) E = VIH ICC1 - 10 25 mA
VCC Supply Current* (Active) E = VIL ICC2 - 50 160 mA
Vpp Supply Current* VPP = 5.85 V IpP1 - - 400 J1.A
VPP = 0 V - - 0 J1.A
Output Low Voltage IOL = 2.1 mA VOL - - 0.45 V
Output High Voltage IOH = -400J1.A rVOH 2.4 - - V

"VCC must be applied simultaneouslY or prior to Vpp. VCC must also be switched off simultaneously with or after Vpp. With Vpp connected
dire~tlY to Vee during the read operation, the supply current would be the sum of IpP1 and ICC. The additional 0.6 V tolerance on Vpp
makes it possible to use a driver circuit for switching the Vpp supply from Vce in Read mode to +25 V for programming. Typical values are
for T A = 25 0 e and nominal supply voltages. .

2-79
 MCM2532, MCM25A32

CAPACITANCE
(f = 1.0 MHz, T A = 25 0 C, periodically sampled rather than 100% tested)

Characteristic Symbol Typ Max

Input Capacitance (Vin = 0 V) 4.0 6.0
Output Capacitance (V out = 0 V) Cout 8.0 12

Capacitance measured with a Boonton Meter or effective capacitance calc"lated from the equation: C = 16t/6V.

II (T A
AC READ OPERATING CONDITIONS AND CHARACTERISTICS
= 0 to +70 0 C, VCC and Vpp = 5.0 V (± 10% MCM25A32, ±5% MCM2532) unless otherwise noted)

Input Pulse Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0.65 Volt to 2.2 Volts

Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ns
Input and Output Timing Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 0.8/2.0 Volts
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 1 TTL Gate and CL = 100 pF

MCM27A32 MCM2732
Characteristic Symbol Min Max Min Max Unit
Address Valid to Output Valid IE/Progr = VIL) tAVOV - 350 - 450 ns
E to Output Valid tELOV - 350 - 450 ns
E to Hi-Z Output tEHOZ 0 100 0 100 ns
Data Hold from Address IE = VIL) tAXOX 0 - 0 - ns

READ MODE TIMING DIAGRAMS IE = VIL)

A (Address) Address Valid

__.~~.k:::-----_'AXQXj, _.
o (Data Out) ~ Qo,,",V,"d ~

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that
normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.

2-80
MCM2532, MCM25A32

STANDBY MODE

A (Address) Address Valid New Address Valid

•
E (PD/Progr) Active Mode

tEHOZ

o (Data Out) Output Valid I\-----Hi-Z - - - - - - . . . . . . ( Output Valid

DC PROGRAMMING CONDITIONS AND CHARACTERISTICS

(T A = 0 to +70 0 C)

RECOMMENDED PROGRAMMING OPERATION CONDITIONS

Parameter Symbol Min Nom Max Unit

Supply Voltage VCC, VPPL 4.75 5.0 5.25 Vdc
VPPH 24 25 26 Vde
Input High Voltage for Data VIH 2.2 - VCC +1 Vde
--
Input Low Voltage for Data VIL -0.1 - 0.65 Vde

-Vee must be applied simultaneously or prior to Vpp. Vee must also be switched off simultaneously with or after Vpp. The device must
not be inserted into or removed from a board with Vpp at +25 V. Vpp must not exceed the +26 V maximum specifications'.

PROGRAMMING OPERATION DC CHARACTERISTICS

Characteristic Condition Symbol Min Typ Max Unit

Address and E/Progr Input Sink Current Yin = 5.25V/0.45 V III - - 10 )lAde
V~ Supply Current E/Progr = V II IpP1 - - 400 )lAde
Vpp Programming Pulse Supply Current E/Progr = VIH IpP2 - - 30 mAdc
VCCSupply Current ICC - - 160 mAde

AC PROGRAMMING OPERATING CONDITIONS AND CHARACTERISTICS

Characteristic Symbol Min Max Unit

Address Setup Time tAVEL 2.0 - )lS

Vpp Setup Time tpHEL 0 - ns

Data Setup Time tDVEL 2.0 - )lS

Address Hold Time tEHAX 2,0 - )lS

Vpp to Enable Low Time tpLEL 0 - ns

Data Hold Time tEHOZ 2.0 - )lS

Vpp Hold Time tEHPL 0 - ns

Enable (Program) Active Time tFI FI-I 1* 55 ms
Enable (E/Progr) Pulse Transition Time tT(PEI 5 - ns
Vpp Rise and Fall Time from 5 to 25 V tR, tF 0.5 2 )lS'

-If shorter than 45 ms (min) pulses are used, the same number of pulses should be applied after the specific data has been verified.

2-81
 MCM2532, MCM25A32

PROGRAMMING OPERATION TIMING DIAGRAM

~-------IProgram

VIH

A (Address)

VIL

II o or Q
VOH/VIH

(Data)
VOL/VIL
Hi-Z

VIH --------------------~--------~
E/Progr (PD/Progr)

VIL

VpPH ~~~~~~~~~~~-----------------------+~L

Vpp

VPPL L...l~~~.¥.-l~"'-X..x..»

PROGRAMMING INSTRUCTIONS Multiple MCM2532s may be programmed in parallel

with the same data by connecting together like inputs and
After the completion of an ERASE operation, every applying the program pulse to the E/Progr inputs. Dif-
bit in the device is in the "1" state (represented by ferent data may be programmed into multiple MCM2532s
Output High). Data are entered by programming zeros connected in parallel by using the PROGRAM INHIBIT
(Output Low) into the requir'ed bits. The yvords are mode. Except for the E/Prugr: pin, all like inputs may be
addressed the same way as in the READ operation. A common.
programmed "0" can only be changed to a "1" by ultra- PROGRAM VERIFY for the MCM2532 is the read
violet light erasure. operation.
To set the memory up for PROGRAM mode, the Vpp
READ OPERATION
input (pin 21) should be raised to +25 V. The V CC supply
After access time, data is valid at the outputs in the
voltage is the same as for the READ operation. Program-
READ mode.
ming data is entered in 8-bit words through the data out
(DQ) terminals while E/Progr is high. Only "D's" vyill be ERASING INSTRUCTIONS
programmed when "O's" and "1 's" are entered in the data The MCM2532/25A32 can be erased by exposure to
word. high intensity shortwave ultraviolet light, with a wave-
After address and data setup, a 50 ms program pulse length of 2537 angstroms. The recommended integrated
(V IH to V ILl is applied to the E/Progr input. A program dose (i.e., UV-intensity X exposure time) is 15 Ws/cm 2 .
pulse is applied to each address location to be program- As an example, using the "Model 30·000" UV-Eraser
med. Locations may be programmed individually, sequen- (Turner Designs, Mountain View, CA 94043) the ERASE-
tially, or at random. The maximum program pulse width time is 36 minutes. The lamps should be used without
is 55 ms; therefore, programming must not be attempted shortwave filters and the MCM2532/25A32 should be
with a dc signal applied to the E/Progr input. positioned about one inch away from the UV-tubes. \

2-82
MCM2532, MCM25A32

TIMING PARAMETER ABBREVIATIONS TIMING LIMITS

I II
t X X X X The table of timing values shows either a minimum or
,;'"" ",me "om wh;,h ;n""" ;, d.';n.d-.J a maximum limit for each parameter. Input requirements
transition direction for first signal are specified from the external system point of view.

•
signal name to which interval is defined Thus, address setup time is shown as a minimum since the
transition direction for second signal system must supply at least that much time (even though
most devices do not require it). On the other hand,
The transition definitions used in this data sheet are: responses from the memory are specified from the device
H = transition to high point of view. Thus, the access time is shown as a maxi-
L = transition to low mum since the device never provides data later than
V = transition to valid that time.
X = transition to invalid or don't care
Z = transition to off (high impedance)

WAVEFORMS
Waveform Input Output
Symbol

MUST BE WILL BE
VALID VALID

CHANGE WILL CHANGE

~ FROM H TO L FROM H TO L

CHANGE WILL CHANGE

Q7Z7 FROM L TO H FROM L TO H

DON'T CARE CHANGING

~ ANY CHANGE
PERMITTED
STATE
UNKNOWN

HIGH
=:)- IMPEDANCE

2-83
 ® MOTOROLA
MCM2708
MCM27A08

1024 X 8 ERASABLE PROM

The MCM270S/27AOS is an S192-bit Erasable and Electrically

MOS

•
Reprogrammable PROM designed for system debug usage and
similar applications requiring nonvolatile memory that could be (N-CHANNEL, SILICON-GATE)
reprogrammed periodically. The transparent window on the package
allows the memory content to be erased with ultraviolet light. 1024 X a·BIT
Pin-for-pin mask-programmable ROMs are available for large volume UV ERASABLE PROM
production runs of systems initially using the MCM270S/27 AOS.

• Organized as 1024 Bytes of S Bits

• Static Operation
• Standard Power Supplies of +12 V, +5 V and - 5 V
• Maximum Access Time = 300 ns - MCM27AOS
450 ns - MCM2708

• Low Power Dissipation

FRIT·SEAL PACKAGE
• Chip-Select Input for Memory Expansion CASE 623A

• TTL Compatible
• Three-State Outputs
• Pin Equivalent to the 2708
• Pin-for-Pin Compatible to MCM65308, MCM6S30S or 2308
Mask-Programmable ROMs
CERAMIC PACKAGE
CASE 716

PIN CONNECTION DURING READ OR PROGRAM

Pin Number
Mode
9-11,13-17 12 18 19 20 21 24
Read D out VSS VSS VDD VIL Vaa Vee
Program Din VSS Pulsed VDD VIHW Vaa Vee PIN ASSIGNMENT
VIHP
24
23
ABSOLUTE MAXIMUM RATINGS (1)
22
Rating Value Unit
4 21
Operating Temperature o to +70 °c
20
Storage Temperature -65 to +125 °e
6 19
VOO with Respect to Vaa +20 to -0.3 Vdc
18
Vce and VSS with Respect to VBB +15 to -0.3 Vdc
17
All Input or Output Voltages with Respect to Vaa during Read +15 to -0.3 Vdc
16
CSIWE Input with Respect to Vaa during Programming +20 to -0.3 Vdc
10 15
Program Input with Respect to Vaa +35 to -0.3 Vdc
11 14
Power Dissipation 1.8 Watts
12 13
Note 1:
Permanent device damage may occur if
ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should
be restricted to RECOMMENDED OP-
ERATING eo'NOITIONS. Exposure to
higher than recommended voltages for
extended periods of time could affect
device reliability.

2-84
MCM2708, MCM-27 A08

BLOCK DIAGRAM

Data Output
00-07

Y Gating
•
AO-A9

Memory
Matrix
(64x128)

DC READ OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted.)

RECOMMENDED DC READ OPERATING CONDITIONS

Parameter Symbol Min Nom Max Unit
Supply Voltage VCC 4.75 5.0 5.25 Vdc
VOO 11.4 12 12.6 Vdc
VSS -5.25 -5.0 -4.75 Vdc
Input High Voltage VIH 3.0 - VCC + 1.0 Vdc
Input Low Voltage VIL VSS - 0.65 Vdc
READ OPERATION DC CHARACTERISTICS
Characteristic Condition Symbol Min Typ Max Unit
Address and CS Input Sink Current Vin ~ 5.25 Vor Vin ~ VIL lin - 1 10 JlA
Output Leakage Current V out ~ 5.25 V, CS/WE ~ 5 V ILO - 1 10 JlA
VOO Supply Current
I Worst-Case Supply Currents 100 - 50 65 mA
VCC Supply Current I (Note 2) All Inputs High ICC - 6 10 mA
V SS Supply Current
I CS/WE ~ 5.0 V, T A ~ DoC ISS - 30 45 mA
Output Low Voltage IOL ~ 1.6 mA VOL - - 0.45 V
Output High Voltage IOH ~ -100 JlA VOH1 3.7 - - V
Output High Voltage IOH~-1.0mA VOH2 2.4 - - V
Power Oissipation (Note 2) TA ~ 70°C Po - - 800 mW

Note 2:
The total power dissipation is specified at 800 mW. It is not calculable by summing the various current (100, ICC, and ISS) multiplied by
their respective voltages, since current paths exist between the various power supplies and VSS. The 100, ICC, and ISS currents should be
used to determine power supply capacity only.

Vss must be applied prior to VCC and VOO. VSS must also be the' last power supply switched off.
 MCM2708, MCM27 A08

AC READ OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted.)
(All timing with tr = tf = 20 ns, Load per Note 3)

I C haractaristlc
Alldress to Output Delay
Chip Select to Output Delay
Symbol
tAO
tco
Min
-
-
MCM27A08
Typ
220
60
Max
300
120
Min
-
-
MCM270B
Typ
280
60
Max
450
120
Unit
ns
ns
Data Hoill from Address tDHA 0 - - 0 - - ns
Data Hold from Deselection tDHD a - 120 0 - 120 ns

CAPACITANCE (periodically sampled rather than 100% tested)

Characteristic Condition Symbol Typ Max Unit
Input Capacitance Vin = 0 V. TA = 25°C Cin 4.0 6.0 pF
(f = 1.0 MHz)
Output Capacitance V out =0 V. TA = 25 0
C Cout 8.0 12 pF
(f = 1.0 MHz) - .. ,

Note 3:
Output L.oad = 1 TTL. Gate and CL. = 100 pF (Includes Jig Capacitance)
Timing Measurement Reference L.evels: Inputs: 0.8 V and 2.8 V
Outputs: 0.8 V and 2.4 V

AC TEST LOAD

'Includes Jig Capacitance

"For VOH1

READ OPERATION TIMING DIAGRAM

Address

Output Valid
(Low Impedance)

2-86
MCM2708, MCM27 A08

DC PROGRAMMING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted.)

RECOMMENDED PROGRAMMING OPERATING CONDITIONS

Supply Voltage
Parameter

Input High Voltage for All Addresses and Data

Symbol
VCC
VOD
Vee
Min
4.76
11.4
-6.26
3.0
Nom
6.0
12
-5.0
-
Max
6.26
12.6
-4.75
VCC + 1.0
Unit
Vdc
Vdc
Vdc
Vdc
II
VIH
Input Low Voltage (except Program) VIL VSS - 0.65 Vdc
CS/WE Input High Voltage (Note 4) VIHW 11.4 12 12.6 Vdc
Program Pulse Input High Voltage (Note 4) VIHP 25 - 27 Vdc
Program Pulse Input Low Voltage (Note 5) VILP VSS - 1.0 Vdc

Note 4: Referenced to VSS.

Note 6: VIHP-VIL.P =,25Vmin.

PROGRAMMING OPERATION DC CHARACTERISTICS

Characteristic Condition Symbol Min Typ Max Unit
Address and CS/WE Input Sink Current Vin = 5.25 V III - - 10 !JAde
Program Pulse Source Current IIPL - - 3.0 mAdc
Program Pulse Sink Current IIPH - - 20 mAde
VDO Supply Current Worst-Case Supply Currents 100 - 50 65 mAde
V CC Supply Current ,All Inputs High ICC - 6 10 mAde
Vee Supply current CS/WE = 5 V, TA = Ooc lee - 30 45 mAde

. AC PROGRAMMING OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature unless otherwise noted.)

Characteristic Symbol Min Max Unit

Address Setup Time tAS 10 - !JS
CS/WE Setup Time tcss 10 - !JS
Data Setup Time tDS 10 - ps
Address Hold Time tAH 1.0 - ps
CS/WE Hold Time tCH 0.5 - ps
Data Hold Time tDH 1.0 - ps
Chip Deselect to Output Float Delay tDF 0 120 ns
Program to Read Delay tDPR - 10 ps
Program Pulse Width tpw 0.1 1.0 ms
Program Pulse Rise Time tpR 0.5 2.0 ps
Program Pulse Fall Time tPF 0.5 2.0 ps

2-87
 MCM27D8, MCM27 AD8

PROGRAMMING OPERATION TIMING DIAGRAM

I 14-------------1 of N Program Loops - - - - - - - - - - _ M - - READ-

(After N
Program
Loops)

t CH ----+--+--
Note 6

VIH
Address Address 0

VIH
Data Out
Data
Valid

t DH --+--+.0---
tDS

Program
Pulse

VIL-------J

Note 6: The CS/WE transition must occur after the Program Pulse transition and before the Address Transition.

Motorola reserves the right to make changes to any products herein to improve reliability, function or design. Motorola does not assume any liability arising
out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

2-88
MCM27oa, MCM27 AOa

PROGRAMMING INSTRUCTIONS
1. All 8192 bits should be programmed with a 0.2 ms
program pulse width.
After the completion of an E RASE operation, every
bit in the device is in the "1" state (represented by
Output High). Data are entered by programming zeros
(Output Low) into the required bits. The words are
addressed the same way as in the READ operation. A
programmed "0" can only be changed to a "1" by ultra-
The minimum number of program loops:

N = TPto. tal = 100 ms = 500. One program loop

tpw 0.2 ms
II
consists of words 0 to 1023.
violet light erasure.
2. Words 0 to 200 and 300 to 700 are to be pro-
To set the memory up for programming mode, the
grammed. All other bits are "don't care". The
eS/WE input (Pin 20) should be raised to +12 V. Pro-
program pulse width is 0.5 ms. The minimum
gramming data is entered in 8-bit words through the
100
data output terminals (DO to 07). number of program loops, N = "Q.5 = 200. One
Logic levels for the data lines and addresses and the
program loop consists of words 0 to 1023. The
supply voltages (Vee, VOO, Vas) are the same as for the
data entered into the "don't care" bits should be
READ operation.
all 1s.
After address and data setup one program pulse per
address is applied to the program input (Pin 18). A pro- 3. Same requirements as example 2, but the EPROM is
gram loop is a full pass through all addresses. Total now to be updated to include data for words 850
programming time, TPtotal = N x tpw ~ 100 ms. The to 880. The minimum number of program loops is
required number of program loops (N) is a function of the the same as in the previous example, N = 200. One
program pulse width (tpW), where: 0.1 ms ~ tpw ~ program loop consists' of words 0 to 1023. The data
1.0 ms; correspondingly N is: 100 ~ N ~ 1000. There entered into the "don't care" bits should be all ls.
must be N successive loops through all 1024 addresses. It Addresses 0 to 200 and 300 to 700 must be reo
is not permitted to apply more than one program pulse in programmed with their original data pattern.
succession to the same address (i .e., N program pulses to
an address and then change to the next address to be pro- ERASING INSTRUCTIONS
grammed). At the end of a program sequence the CS/WE
falling edge transition must occur before the first address The MCM270S/27 AOS can be erased by exposure to
transition, when changing from a PROGRAM to a READ high intensity shortwave ultraviolet light, with a wave·
cycle. The program pin (Pin 18) should be pulled down length o~ 2537 A. The recommended integrated dose (i.e.,
to V I LP with an active device, because this pin sources a UV·intensity x exposure time) is 12.5 Ws/cm 2 . As an
small amount of current (IIPL) when CS/WE is at VIHW example, using the "Model 30-000" UV-Eraser (Turner
(12 V) and the program pulse is at V I LP' Designs, Mountain View, CA94043) the E RASE·time is
30 minutes. The lamps should be used without shortwave
EXAMPLES FOR PROGRAMMING filters and the MCM270S/27 AOS should be positioned
Always use the TPtotal= NxtpW ~ 100 ms relationship. about one inch away from the UV-tubes.

2-89
 ® MOTOROLA
MCM2716
MCM27A16
Advance InforIllation
.MOS
2048 X 8-BIT UV ERASABLE PROM

II The MCM2716/27A16 is a 16,384-bit Erasable and Electrically

Reprogrammable PROM designed for system debug usage and similar
applications re'quiring nonvolatile memory that could be reprogram-
med periodically. The transparent window on the package allows the
(N-CHANNEL, SILICON-GATE)

2048 X 8·BIT
UV ERASABLE PROM

memory content to be erased with ultraviolet light.

For ease of use, the device operates from a single power supply
and has a static power-down mode. Pin-for-pin mask programmable
ROMS are available for large volume production runs of systems
initially using the MCM2716/27A16.

• Single ± 10% 5 V Power Supply

• Automatic Power-down Mode (Standby)
• Organized as 2048 Bytes of 8 Bits FRIT-SEAL PACKAGE
CASE 623A
• Low Power Dissipation
• TTL Compatible During Read and Program
• Maximum Access Time = 450 ns MCM2716
350 ns MCM27A 16
• .Pin Equivalent to Intel's 2716
• Pin Compatible to MCM68A316E Mask Programmable ROMs
CE RAMIC PACKAGE
CASE 716

PIN NUMBER

9-11,
Mode 13-17 12 18 20 21 24 PIN ASSIGNMENT

DO VSS E/Progr G Vpp VCC

Read Data out VSS VIL VIL Vee Vee

Output Disable HiZ VSS Don't Care VIH Vec Vee

4
Standby HiZ VSS VIH Don't Care Vee Vec

Program Data in VSS Pulsed VIH VIHP VCC

VIL to VIH

Program Verify Data out VSS VIL VIL VIHP VCC

Program I nh ibit HiZ VSS VIL VIH VIHP VCC 10

11
ABSOLUTE MAXIMUM RATINGS (1) 12
Rating Value Unit
Temperature Under Bias -10 to +80 °C·
Storage Temperature -65 to{) +125 °e *PIN NAMES
All Input or Output Voltages with Respect to VSS during Read + 6 to -0.3 Vdc A '" Address
Vpp Supply Voltage with Respect to VSS +28 to -0.3 Vdc DO . . . . Data Input/Output
E/Progr . . . . Chip Enable/Program
NOTE 1: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are G .... Output Enable
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages
for extended periods of time could affect device reliability. • New industry standard nomenclature

ThiS IS advance Information and speCifications are subject to change wl~hout notice.

2-90
MCM2716, MCM27 A 16

BLOCK DIAGRAM

Data I nput/Output
DaO-Da7

Y Gating
II
AO-Al0

Memory
Matrix
(128 x 128)

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted)

RECOMMENDED DC READ OPERATING CONDITIONS (TA = 00 to +70 0 C)

Parameter Symbol Min Nom Max Unit
Supply Voltage' MCM2716 VCC 4.75 5.0 5.25 Vdc
MCM27A16 4.5 5.0 5.5
Vpp VCC - 0.6 5.0 VCC + 0.6
Input High Voltage VIH 2.0 - VCC + 1.0 Vdc
Input Low Voltage VIL -0.1 - 0.8 Vdc

READ OPERATION DC CHARACTERISTICS

Characteristic Condition Symbol Min Typ Max Unit
Address, G and E/Progr Vin = 5.25 V lin - - 10 IJA
Input Sink Current
Output Leakage Current V out= 5.25 V, G = 5.0 V ILO - - 10 IJA
VCC Supply Current' (Standby) E/Progr = VIH, G = VIL ICCl - 10 25 mA
VCC Supply Current' (Active) G = E/Progr = VIL ICC2 - 57 100 mA
Vpp Supply Current' Vpp = 5.85 V IPPl - - 5.0 mA
Output Low Voltage IOL = 2.1 mA VOL - - 0.45 V
-
Output High Voltage IOH = -400 IJA VOH 2.4 - - V
'VCC must be applied simultaneously or prior to Vpp. VCC must alsobe switched off simultaneously with or after Vpp. With Vpp connected
directly to VCC during the read operation, the supply current would be the sum of IpPl and ICC. The additional 0.6 V tolerance on Vpp
makes it possible to use a driver circuit for switching the Vpp supply pin from VCC in Read mode to +25 V for programming. Typical values
are for T A = 25 0 C and nominal supply voltages.

CAPACITANCE

Characteristic This device contains circuitry to protect the

Input Capacitance (Vin = 0 V) inputs against damage due to high static voltages
or electric fields; however, it is advised that
Output Capacitance (V out - 0 V)
normal precautions be taken to avoid applica-
Capacitance measured with a Boonton Meter or effective capacitance calculated from the tion of any voltage higher than maximum
. IAt rated voltages to this high-impedance circuit.
equation: C = 15:V-

2-91
 MCM2716, MCM27A16

AC OPERATING CONDITIONS AND CHARACTERISTICS

(TA - 0 to +70o e. vee - 5.0 V ± 10% unless otherwise noted.)

Input Pulse Levels . . . • . . . . . . . . . . . . 0.8 Volt to 2.2 Volts Input and Output Timing Levels . . . • • . . . . . . . • . 2.0 Volts
Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . 20 ns Output Load. , • . . . . • • • . . . . . • . . . . . . • . See Figure 1
MCM27A16 MCM2716
Characteristic Condition Symbol Min Max Min Max Units
Address Valid to Output Valid E/Progr = G = Vil tAvmi - 350 - 450 ns
E/Progr to Output Valid (Nota 2) - 350 - 450 ns

I
tELOV
Output Enable to Output Valid E/Progr" VIL tGLOV - 120 - 120 ns
E/Progr to Hi Z Output tEHOZ 0 100 0 100 ns
Output Disable to Hr Z Output E/Progr = V Il tGHOZ 0 100 0 100 ns
Data Hold from Addrass E/Progr = G = VIL tAXDX 0 - 0 - ns

FIGURE 1 - AC TEST LOAD

S'OV

1f1
AL=2.2k

T.lt Point
MMDS1S0
'100 pF 6 k or Squiv
MMD7000
or Eql!iv
... .,.
READ MODE TIMING DIAGRAMS 'Includes Jig Capacitance
(Chip Enable = V I L)

Address

Output Valid

STANDBY MODE
(Output Enable = VIL)
Standby Mode (Chip Select = V I L)

Address

E/Progr
Standby Mode Active Mode

t-----_r_ tE LQV
(Note 2)

Data Out Output Valid Output Valid

NOTE 2: tE LQV is referenced to E/Progr or stable address, whichever occurs last.

2-92
MCM2716, MCM27A16

DC PROGRAMMING CONDITIONS AND CHARACTERISTICS

(TA = 0 to +70 0 e, vee = 5.0 V ± 10%)

RECOMMENDED PROGRAMMING OPERATING CONDITIONS

Paramater Symbol Min Nom Max Unit
Supply Voltage Vee 4.75 5.0 5.25 Vdc
Vpp 24 25 26 Vdc
Input High Voltage for Data VIH 2.2 - Vee + 1 Vdc

II
Input Low Voltage for Data VIL -0.1 - 0.8 Vdc
*VCC must be applied slmulataneously or prior to Vpp. VCC must also be sWitched off simultaneously with or after Vpp. The device must not
be inserted into or removed from a board with Vpp at +25 V. VPP must not exceed the +26 V maximum specifications.

PROGRAMMING OPERATION DC CHARACTERISTICS

Charactaristic Condition Symbol Min Typ Max Unit
Address, G and E/Progr Input V in = 5.25 V 10.45 III - - 10 I.IAde
Sink Current
VPP Supply Current E/Progr = V I L IpPl - - 5.0 mAde
VPP Programming Pulse E/Progr = V I H IpP2 - - 30 mAde
Supply Current
VCC Supply Current ICC - - 100 mAde

AC PROGRAMMING OPERATING CONDITIONS AND CHARACTERISTICS

Characteristic Symbol Min Max Unit

Address Setup Time tAVEH 2.0 - I.IS
Output Enable High to Program Pulse tGHEH 2.0 - I.IS
Data Setup Time tDVEH 2.0 - I.IS
Address Hold Time tELAX 2.0 - I.IS
Output Enable Hold Time tELGL 2.0 - I.IS
Data Hold Time tELQZ 2.0 - I.IS
Output Disable to Hi Z Output tGHQZ 0 120 ns
Output Enable to Valid Data (E/Progr = VIL) tGLQV - 120 ns
Program Pulse Width tEHEL 45 55 ms
Program Pulse Rise Time tPR 5 - ns
Program Pulse Fall Time tpF 5 - ns

PROGRAMMING OPERATION TIMING DIAGRAM

----Program--

l --tEL-AX -----.

T I

E/Progr

2-93
 MCM2716, MCM27A16

PROGRAMMING INSTRUCTIONS The PROGRAM VERIFY mode with VPP at 25 V

is used to determine that all programmed bits were
After the completion of an ERASE operation, every correctly programmed.
bit in the device is in the "1" state (represented by
READ OPERATION
Output High). Data are entered by programming zeros
After access time, data is valid at the outputs in the
(Output Low) into the required bits. The words are
READ mode. With stable system addresses, effectively
addressed the same way as in the READ operation. A
faster access time (120 ns) can be obtained by gating the
programmed "0" can only be changed toa "1" by ultra-
data onto the bus with a low Output Enable input (VI L).
violet light erasure.
A high level Output Enable input (VIH) puts the
To set the memory up for PROGRAM mode, the VPP

I input (pin 21) should be raised to +25 V. The VCC supply

voltage is the same as for the READ operation and G is
at VIH. Programming data is entered in 8-bit words
through the data out (DO) terminals. Only' "'a's" will be
programmed when "0'5" and "1 's" are entered in the
MCM2716 in the Output Disable mode with outputs in
the high impedance state. This mode allows two or more
devices to have outputs OR-tied together on the same data
bus. Only one of the MCM2716s in this configuration
should have output enable at V I L to prevent contention
on the data bus.
data word.
The Standby mode is available to reduce active power
After address and data setup, a 50 ms program pulse
dissipation from 525 mW to 132 mW. The outputs are
(VIL to VIH) is applied to the E/Progr input. A program
in the high impedance state when the E/Progr input
pulse is applied to each address location to be program-
pin is high (VIH) independent of the Output Enable input.
med. Locations may be programmed individually, sequen-
tially, or at random. The maximum program pulse width
ERASING INSTRUCTIONS
is 55 ms; therefore, programming must not be attempted
with a de signal applied to the E/Progr input.
The MCM2716/27A16 can be erased by exposure to
Multiple MCM2716s may be programmed in parallel
high intensity shortwave ultraviolet light, with a wave-
with the same data by connecting together like inputs and
length of 2537 A. The recommended integrated dose
applying the program pulse to the E/Progr inputs. Dif·
(i.e., UV-intensity X exposure time) is 15 Ws/cm 2 . As an
ferent data may be programmed into multiple MCM2716s
example, using the "Model 30-000" UV·Eraser (Turner
connected in parallel by using the PROGRAM INHIBIT
Designs, Mountain View, CA 94043) the ERASE-time is
mode. Except for the E/Progr pin, all like inputs (includ-
36 minutes. The lamps should be used Without shortwave
ing Output Enable) may be common.
filters and the MCM2716/27 A 16 should be positioned
about one inch away from the UV·tubes.

TIMING 'PARAMETER ABBREVIATIONS TIMING LIMITS

I II
t X X X X The table of timing values shows' either a minimum or
,;,,,' ",m, "om wh;,h ,""'", ;, d,fiood-' a maximum limit for each parameter. Input requirements
transition direction for first signal are specified from the external system point of view.
signal name to which interval is defined Thus, address setup time is shown as a minimum since the
transition direction for second signal system must supply at least that much time (even though
most devices do not requi re it). On the other hand
The transition definitions used in this data sheet are: responses from the memory are specified from the devic~
H = transition to high point of view. Thus, the access time is shown as a maxi·
L = transition to low mum since the device never provides data later than
V = transition to valid that time.
X = transition to invalid or don't care
Z = transition to off (high impedance)

WAVEFORMS
Waveform Input Output
Symbol

MUST BE WILL BE
VALID VALID

CHANGE WJLL CHANGE

~ FROM H TO L FROM H TO L

CHI\NGE WILL CHANGE

-.llZlZ7 FROMLTOH FROM L TO H

DON'T CARE CHANGING

~ ANY CHANGE
PERMITTED
STATE
UNKNOWN

~
HIGH
IMPEDANCE

2-94
 ® MOTOROLA
MCM68708
MCM68A708

1024 X a ERASABLE PROM MOS

The MCM68708/68A708 is a 8192-bit Erasable and Electrically (N-CHANNEL, SILICON-GATE)
Reprogrammable PROM designed for system debug usage and
1024 X a-BIT
similar applications requiring nonvolatile memory that could be
reprogrammed periodically. The transparent window on the package
allows the memory content to be erased with ultraviolet light.
Pin-for-pin mask-programmable ROMs are available for large volume
production runs of systems initially using the MCM68708/68A708.
uv ERASABLE PROM

II
• Organized as 1024 Bytes of 8 Bits
• Fully Static Operation
• Standard Power Supplies of + 12 V, +5 V and - 5 V
• Maximum Access Time = 300 ns - MCM68A708
450 ns - MCM68708
• Low Power Dissipation
• Chip-Select Input for Memory Expansion
• TTL Compatible
• Three-State Outputs
PIN ASSIGNMENT
• . Pin Equivalent to the 2708
• Pin-for-Pin Compatible to MCM65308, MCM68308 or 2308
Mask-Programmable ROMs

• Bus Compatible to the M6800 Family

PIN CONNECTION DURING READ OR PROGRAM

Pin Number
Mode
9-11,13-17 12 18 19 20 21 24
10
Read D out VSS VSS VDD VIL VSS Vce
11
Program Din VSS Pulsed VDD VIHW VSS Vec
12
VIHP

M6800 MICROCOMPUTER FAMIL Y MCM68708/68A708 READ ONLY

BLOCK DIAGRAM MEMORY BLOCK DIAGRAM

Memory
Data Bus
Matrix
(1024 x 8)

Address Data Memory Address

Bus Bus and Control

2-95
MCM68708, MCM68A708

BLOCK DIAGRAM

Oeta Output
00-07 ABSOLUTE MAXIMUM RATINGS1
Rating Value Unit
Operating. Temperature o to ~70 °c
Storage Temperature -65 to +125 uc
VOO with Respect to Vaa +20 to -0.3 Vdc
VCC and VSS with Respect to Vaa +15 to -0.3 Vdc
All Input or Output Voltages with +15 to -0.3 Vdc
Respect to Vaa during Read
CS/WE Input with Respect to Vaa +20 to -0.3 Vdc
during Programming
Y Gating
Program Input with Respect to Vaa +35 to -0.3 Vdc
Power Dissipation 1.8 Watts

AO-A9
Note 1:
Permanent device damage may occur if AaSOLUTE MAXIMUM
Memory RATINGS are exceeded. Functional operation should be restricted
Matrix
to RECOMMENDED OPERATING CONDITIONS. Exposure to
(64x128)
higher than recommended voltages for extended periods of time
could affect device reliability.

DC READ OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted.)

RECOMMENDED DC READ OPERATING CONDITIONS

Parameter Symbol Min Nom Max Unit
Supply Voltage VCC 4.75 5.0 5.25 Vdc
VDD 11.4 12 12.6 Vdc
Vaa -5.25 -5.0 -4.75 Vdc
Input High Voltage VIH VSS +2.0 _. Vee Vdc
Input Low Voltage VIL VSS -0.3 - VSS +O.s Vdc
READ OPERATION DC CHARACTERISTICS
Characteristic Condition Symbol Min Typ Max Unit
Address and CS Input Sink Current Yin ~ 5.25 V or Yin ~ VIL lin - 1 10 IlA
Output Leakage Current V out ~ 5.25 V. CS/WE ~ 5 V ILO - 1 10 IlA
VOO Supply Current
I Worst-Case Supply Currents 100 - 50 65 mA
Vce Supply Current J (Note 2) All Inputs High ICC - 6 10 mA
Vaa Supply Current
I CS/WE ~ 5.0 V. TA ~ OOC laa - 30 45 mA
Output Low Voltage IOL; 1.6 mA VOL - - VSS +0.4 V
Output High Voltage IOH; -100 IlA VOH VSS +2.4 - - V
Power Dissipation (Note 2) TA ~ 700 C Po - - BOO mW

Not82:
The total power dissipation is specified at 800 mW. It is not calculable by summing the various currents (100. ICC. and laa) multiplied by
their respective voltages. since current paths exist between the various power supplies and VSS. The IDO. ICC. and laa currents should be
used to determ ine power supply capacity only. '

Vaa must be applied prior to VCC and VDO. Vaa must also be the last power supply switched off.

2-96
MCM68708, MCM68A708

AC READ OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted.)
(All timing with tr = tf = 20 ns, Load per Note 3)

Address to Output Delay

Chip Select to Output Delay
Data Hold from Address
Characteristic Symbol
tAO
tco
Min
-
-
10
MCM68A708
Typ
220
60
-
Max
300
120
-
Min
-
-
10
MCM68708
Typ
280
60
-
Max
450
120
-
Unit
ns
ns
ns
II
tDHA
Data Hold from Deselection tDHD 10 - 120 10 - 120 ns

CAPACITANCE (periodically sampled rather than 100% tested)

Characteristic Condition Symbol Typ Max Unit
I nput Capacitance Vin=OV,TA=2?oC Cin 4.0 6.0 pF
(f = 1.0 MHz)
Output· Capacitance V out = 0 V, TA = 25°C Cout 8.0 12 pF
(f = 1.0 MHz)

Note 3:
Output Load = 1 TTL Gate and C L = 100 pF (Includes Jig Capacitance)
Timing Measurement Reference Levels: Inputs: 0.8 V and 2.8 V
Outputs: 0.8 V and 2.4 V

ACTESTLOAD

Test Point o--'-~~---i'lJ-"""

MMD6150
100 pF • ;;;:~ or EqU1V
24 k
MMD7000
or Equ iv

• Includes Jig Capacitance

READ OPERATION TIMING DIAGRAM

Address

'Output Valid
(low Impedance)

2-97
 MCM68708, MCM68A708

DC PROGRAryiMING CONDITIONS AND CI:iARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted.)

II
RECOMMENDED PROGRAMMING OPERATING CONDITIONS
Parameter Symbol Min Nom Max Unit
Supply Voltage VCC 4.75 5.0 5.25 Vdc
VDD 11.4 12 12.6 Vdc
VBB -5.25 -5.0 -4.75 Vdc
Input High Voltage for All Addresses and Data VIH 3.0 - VCC + 1.0 Vdc
Input Low Voltage (except Program) VIL VSS - 0.65 Vdc
CS/WE Input High Voltage (Note 4) VIHW 11.4 12 12.6 Vdc
Program Pulse Input High Voltage (Note 4) VIHP 25 - 27 Vdc
Program Pulse Input Low Voltage (Note 5) VILP VSS - 1.0 Vdc

Note 4: Referenced to VSS.

Note 5: VIHP--VILP ~ 25Vmin.

PROGRAMMING OPERATION DC CHARACTERISTICS

Characteristic Condition Symbol Min Typ Max Unit
Address and CS!WE Input Sink Current Vin ~ 5.25 V III -- -_.. 10 IlAde
Program Pulse Source Current IIPL --- - 3.0 mAde
Program Pulse Sink Current IIPH -- _.- 20 mAde
V DO Supply Current Worst-Case Supply Currents IDD - 50 65 m.Ade
V CC Supply Current All Inputs High ICC - 6 10 mAde
V BB Supply current CS/WE ~ 5 V. TA"' OoC I?B - 30 45 mAde

AC PROGRAMMING OPERATING CONDITIONS AND CHARACTERISTICS

(Full operatirg voltage and temperature unless otherwise noted.)

Characteristic Symbol Min Max Unit

Address Setup Time tAS 10 -- IlS
CS/WE Setup Time tcss 10 -- IlS
Data Setup Time tDS 10 - IlS
Address Hold Time tAH 1.0 -- IlS

CS/WE Hold Time tCH 0.5 - IlS

Data Hold Time tDH 1.0 - 115

Chip Deselect to Ouptut Float Delay tDF 0 120 ns

Program to Read Delay tDPR - 10 IlS
Program Pulse Width tpw 0.1 1.0 ms
Program Pulse Rise Time tPR 0.5 2.0 IlS
Program Pulse Fall Time tpF 0.5 2.0 IlS

2-98
MCM68708, MCM68A708

PROGRAMMING OPERATION TIMING DIAGRAM

1--------------, of N Program Loops --------------t-- READ---

(After N
Program
Loops) II
t CH ---r--+--
Note 6

VIH
Address Address 0

tAH_

VII-;i
Data Out
Data
Valid

tDS
t DH --.1---+-_-

t PR - - - I - - 1 - - - - - - t PW - - - + - - 1 - - - - t PF

VIHP

Program
Pulse

VI L - - - - - - - - '

Note 6: The CS/WE transistion must occur after the Program Pulse transition and before the Address Transistion.

Motorola reserves the right to make changes to any products herein to improve reliability, function or design. Motorola does not assume any liability arising
out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others

2-99
 MCM68708, MCM68A708

PROGRAMMING INSTRUCTIONS
1. All 8092 bits should be programmed with a 0.2 ms
program pulse width.
After the completion of an ERASE operation, every

I bit in the device is in the "1" state (represented by

Output High). Data are entered by programming zeros
(Output Low) into the required bits. The words are
addressed the same way as in the READ operation. A
programmed "0" can only be changed to a "1" by ultra-
The minimum number of program loops:

N = TPtotal = 100 ms = 500.

tpw 0.2 ms
One program loop

consists of words 0 to 1023.

violet light erasure.
2. Words 0 to 200 and 300 to 700 are to be pro-
To set the memory up for programming mode, the
grammed. All other bits are "don't care". The
CS/WE input (Pin 20) should be raised to +12 V. Pro-
program pulse width is 0.5 ms. The minimum
gramming data is entered in 8-bit words through the
100
data output terminals (DO to 07). I number of program loops, N = 0:5 = 200. One
Logic levels for the. data lines and addresses and the
program loop consists of words 0 to 1023. The
supply voltages (Vee, VOO, VBB) are the same as for the
data entered into the "don't care" bits should be
READ operation.
all 1s.
After address and data setup one program pulse per
address is applied to the program input (Pin 18). A pro- 3. Same requirements as example 2, but the EPROM is
gram loop is a full pass through all addresses. Total now to be updated to include data for words 850
programming time, TPtotal = N x' tpw ~ 100 ms. The to 880. The minimum number of program loops is
required number of program loops (N) is a function of the the same as in the previous example, N = 200. One
program pulse width (tPW). where: 0.1 ms ,.;; tpw ,.;; program loop consists of words 0 to 1023. The data
1.0 ms; correspondingly N is: 100";; N ,.;; 1000. There entered into the "don't care" bits should be all 1s.
must be N successive loops through all 1024 addresses. It Addresses 0 to 200 and 300 to 700 must be reo
is not permitted to apply more than one program pulse in programmed with their original data pattern.
succession to the same address (i.e., N program pulses to
an address and then change to the next address to be pro- ERASING INSTRUCTIONS
grammed). At the end of a program sequence the CS/WE
falling edge transition must occur before the first address The MCM68708/68A70B can be erased by exposure to
transition, when changing from a PROGRAM to a READ high intensity shortwave ultraviolet light, with a wave-
cycle. The program pin (Pin 18) should be pulled down length of 2537 A. The recommended integrated dose (i.e.,
to V I LP with an active device, because this pin sources a UV-intensity x exposure time) is 12.5 Ws/cm 2. As an
small amount of current (IIPL) when CS/WE is at VIHW example, using the "Model 30-000" UV-Eraser (Turner
(12 V) and the program pulse is at V I LP' Designs, Mounta.in View, CA 94043) the ERASE-time is
30 minutes. The lamps should be used without shortwave
EXAMPLES FOR PROGRAMMING filters and the MCM6870B/68A70B should be positioned
Always use the TPtotal = N x tpw ~ 100 ms relationship. about one inch away from the UV-tubes.

2-100
 ® MOTOROLA
MCM68764
MCM68A764
Advance InforIllation
MOS
(N-CHANNEL, SILICON-GATE)

•
8192 X 8-BIT UV ERASABLE PROM 8192 X 8-BIT
The MCM68764/68A764 is a 65,536-bit Erasable and Electrically UV ERASABLE PROM
Reprogrammable PROM designed for system debug usage and similar
applications requiring nonvolatile memory that could be reprogram-
med periodically or for replacing 64K ROMs for fast turnaround
time: The transparent window on the package allows the memory
content to be erased with ultraviolet light.
For ease of use, the device operates from a single power supply
and has a static power-down mode. Pin-for-pin mask programmable
ROMs are available for large volume production runs of systems
initially using the MCM68764/68A764. FRIT-SEAL PACKAGE
CASE 623A
• Single +5 V Power Supply
• Automatic Power-down Mode (Standby) with Chip Enable
• Organized as 8192 Bytes of 8 Bits
• Low Power Dissipation
• Fully TTL Compatible L SUFFIX
• Maximum Access Time = 450 ns MCM68764 CERAMIC PACKAGE
350 ns MCM68A764 CASE 716

• Standard 24-Pin DIP for EPROM Upgradability

• Pin Compatible to MCM68A364 Mask Programmable ROM
PIN ASSIGNMENT

MODE SE LECTION
PIN NUMBER
9-11,
Mode 13-17, 12 20 24
DQ ENpp 4
Vss VCC
Read Data out VSS VIL VCC
Output Disable Hi-Z VSS VIH VCC
Standby Hi-Z VSS VIH VCC
Program Data in VSS Pulsed VCC
VILPto VIHP
10
11
12

ABSOLUTE MAXIMUM RATINGS (1)

Rating Value Unit
Temperature Under Bias -10 to +80 °c
Storage Temperature -65 to +125 °c *PIN NAMES
All Input or Output Voltages with Respect to VSS during Read + 6 to -0.3 Vdc A . . . . Address
Vpp Supply Voltage with Respect to VSS +28 to -0.3 Vdc DQ . . . . Data Input/Output
ENpp . . . . Chip Enable/Program
NOTE 1: Permanent device damage may occur if ABSOLUTE MAX IMUM RATINGS are
G .... Output Enable
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages
for extended periods of time could affect device reliability. • New industry standard nomenclature

This is advance information and specifications are subject to change without notice.

2-101
MCM68764, MCM68A764

. BLOCK DIAGRAM

Data I nput/Output
DOO-D07
VCC--' .-. ~ __
VSS--' -- ~ -- -----

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted)

RECOMMENDED DC READ OPERATING CONDITIONS (T A = 00 to +70 0 C)

Parameter Symbol Min Nom Max Unit
Supply Voltage* MCM68764 VCC 4.75 5.0 5.25 Vdc
MCM68A764 4.5 5.0 5.5
Input High VOltage VIH 2.0 - VCC +1.0 Vdc
Input Low Voltage VIL -0.1 - 0.8 Vdc

READ OPERATING DC CHARACTERISTICS

Characteristic Condition Symbol Min Typ Max Unit

Address Input Sink Current Yin = 5.25 V lin - - 10 jJA
Output Leakage Current V out = 5.25 V ILO - - 10 jJA
E/Vpp Input Sink Current E/Vpp = VIL IEL - - 10 J.1A
EIVpp = VIH IEH = IpL - - 200 J.1A
EIVpp = VIHP IpH - - 30 mA
VCC Supply Current (Active) I:IVpp = VIL ICC1 - - 160 mA
VCC Supply Current (Standby) ~IVpp = VIH ICC2 - - 25 mA
Output Low Voltage IOL = 2.1 mA VOL - 0.1 0.45 V
Output High Voltage IOH = -400!J. A VOH 2.4 4.0 - V

CAPACIT ANCE

Characteristic This device contains circuitry to protect the

Input Capacitance (V in = 0 V) inputs against damage due to high static voltages
or electric fields; however, it is advised that
Output Capacitance (V out =·0 V)
normal precautions be taken to avoid applica·
Capacitance measured with a Boonton Meter or effective capacitance calculated from the tion of any voltage higher than maximum
I"A t rated voltages to this high·impedance circuit.
equation: C = AV'

2-102
MCM68764, MCM68A764

DC PROGRAMMING CONDITIONS AND CHARACTERISTICS

(T A ; 0 to +70 0 e, Vee; 5.0 V ± 5%)

RECOMMENDED PROGRAMMING OPERATING CONDITIONS

Parameter Symbol Min Nom Max Unit
Supply Voltage Vee 4.75 5.0 5.25 Vdc
Input High Voltage for All Addresses and Data VIH 2.0 - Vee + 1 Vdc
Input Low Voltage for All Addresses and Data VIL -0.1 - 0.8 Vdc

•
Program Pulse Input High Voltage VIHP 24 25 26 Vdc
Program Pulse Input Low Voltage VILP 2.0 Vee 6.0 Vdc

PROGRAMMING OPERATION DC CHARACTERISTICS

Characteristic Condition Symbol Min Typ. Max Unit
Address Input Sink Current Vin ; 5.25 V III - - 10 J,JAdc
Program Pulse Current (Vpp - 25 V) IpH - - 30 mAde
Vpp Programming Pulse Current (Vpp ; 5 V) IPL; IEH - - 200 J,JA
VCC Supply Current lec - - 160 mAdc

AC PROGRAMMING OPERATING CONDITIONS AND CHARACTERISTICS

Characteristic Symbol Min Max Unit

Address Setup Time tAVPH 2.0 - J1s
Data Setup Time tDVPH 2.0 - J1s
Chip Enable to Valid Data tELQV 450 - ns
ehip Disable to Data In tEHDV 2.0 - J1s
Program Pulse Width" tpHPL 1.0 55 ms
Program Pulse Rise T,ime tPR 0.5 2.0 J1s
Program Pulse Fall Time tpF 0.5 2.0 J1s
"The minimum programming time is twice the programming time after successful verification of the programmed pattern, but maximum
programming time is 55 ms.

PROGRAMMING OPERATION TIMING DIAGRAM

ADDRESS ".4095 ADDRESS 0

DATA DATA OUT

tpF tELOV
 MCM68764, MCM68A764

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted)

•
Input Pulse Levels . . . . . . .. 0.8 Volt to 2.2 Volts Input Timing Levels . 1 Volt and 2 Volts
Input Rise and Fall Times .. . . . . . . 20 ns Output Timing Levels .. 0.8 Volt to 2 Volts
Output Load ... . . 100 pF + 1 74 Series TTL Load

.MCM68A764 MCM687134
Characteristic Condition Symbol Min Max Min Max Units
Address Valid to Output Valid E; VIL tAVOV - 350 - 450 ns
E to Output Valid tELOV - 350 - 450 ns
E to Hi-Z Output tEHOZ 0 100 0 100 ns
Data Hold from Address E"-VIL tAXDX 0 - 0 - ns

READ MODE TIMING DIAGRAM

ADDRESS ADDRESS VALID

ElVpp

tEHQZ

HI·Z HI·Z
OUTPUT------------------~ DATA VALID

.2-104
MCM68764, MCM68A764

PROGRAMMING INSTRUCTIONS READ OPERATION

After access time, data is valid at the outputs in the
After the completion of an ERASE operation, every Read mode. A single input (E/vpp) enables the out·
bit in the device is in the "1" state (represented by puts and puts the chip in active or standby mode. With
Output High). Data are entered by programming zeros E/Vpp = "0" the outputs are enabled and the chip is
(Output Low) into the required bits. The words are in active mode, with E/Vpp = "1" the outputs are
addressed the same way as in the READ operation. A tristated and the chip is in standby mode. During stand-
programmed "0" can only be changed to a "1" by ultra- by mode, the power dissipation is reduced from 880 mW
violet light erasure. to 132 mW.

•
To set the memory up for Program Mode, the E/Vpp Multiple MCM68764 may share a common data bus
input (Pin 20) should be between +2.0 and +6.0 V, with like outputs OR-tied together. In this configuration
which will tristate the outputs and allow data to be set- the E/Vpp input should be high on all unselected MCM
up on the DQ terminals. The VCC voltage is the same as 68764s to prevent data contention.
for the Read operation. Only "a's" will be programmed
when "a's" and" 1 's" are entered in the 8-bit data word.
After address and data setup, 25 volt programming ERASING INSTRUCTIONS
pulse (V,H to V,HP) is applied to the E/Vpp input. A
program pulse is appl ied to each address location to be The MCM68764 can be erased by exposure to high
programmed. Locations may' be programmed indivi- intensity shortwave ultraviolet Iight, with a wavelength
dually, sequentially, or at random. The maximum pro- of 2537 angstroms. The recommended integrated dose
gram pulse width is 55 ms and the maximum program (i.e., UV-intensity X exposure time) is 15 Ws/cm 2 .
pulse amplitude is 26.0 V. As an example, using the "Model 30-000" UV-Era-
Multiple MCM68764s may be programmed in parallel ser (Turner Designs, Mountain View, CA 94043) the
by connecting like inputs and applying the program ERASE-time is 36 minutes. The lamps should be used
pulse to the E/Vpp inputs. Different data may be pro' without shortwave filters and the MCM68764 should
grammed into multiple MCM68764s connected in paral- be positioned about one inch away from the UV-tubes.
lel by selectively applying the programming pulse only
to the MCM68764s to be programmed.

TIMING PARAMETER ABBREVIATIONS TIMING LIMITS

I II
t X X X X The table of timing values shows either a minimum or
,;gn,' oem, hom which ;ot",,1 ;, d,fln,d..J a maximum limit for each parameter. Input requirements
transition direction for first signal are specified from the external system point of view.
signal name to which interval is defined Thus, address setup time is shown as a minimum since the
transition direction for second signal system must supply at least that much time (even though
most devices' do not require it). On the other hand,
The transition definitions used in this data sheet are: responses from the memory are specified from the device
H = transition to high point of view. Thus, the access time is shown as a maxi-
L = transition to low mum since the device never provides data later than
V = transition to valid that time.
X = transition to invalid or don't care
Z = transition to off (high impedance)

WAVEFORMS
Waveform Input Output
Symbol

MUST BIc WILL BE

VALID VALID

CHANGE WILL CHANGE

~ FROM H TO L FROM H TO L

CHI\NGE WILL CHANGE

..fllZZ7 FROMLTOH FROMLTOH

DON'T CI\RE CHI\NGING

~ ANY CHANGE
PERMITTED
STATE
UNKNOWN

=r HIGH
IMPEDANCE
® MOTOROLA
IMS2716 -
TMS27A16

2048 X 8 ERASABLE PROM

MOS
The TM,S2716 and TMS27A16 are 16,384-bit Erasable and (N-CHANNEL, SILICON-GATE)
Electrically Reprogrammable PROMs designed for system debug
usage and similar applications requiring nonvolatile memory that 2048 X 8-BIT
could be reprogrammed periodically, The transparent window on the UV ERASABLE PROM
package allows the memory content to be erased with ultraviolet
light, The TMS2716 is pin compatible with 2708 EPROMs, allowing
easy memory size doubling,

• Organized as 2048 Bytes of 8 Bits

• Fully Static Operation (No Clocks, No Refresh)
• Standard Power Suppl ies of + 12 V, + 5 V, and -- 5 V
• Maximum Access Time = 300 ns - TMS27 A 16
450 ns - TMS2716 FRIT-SEAL PACKAGE
CASE 623A
• Chip-Select Input for Memory Expansion
• TTL Compatible - No Pull-up Resistors Required
• Three-State Outputs for OR-Tie Capability
• The TMS2716 is Pin Compatible to MCM2708 and
MCM68708 EPROMs
CERAMIC PACKAGE
CASE716

BLOCK DIAGRAM
PIN ASSIGNMENT
Data Input/Output
24
DOD-D07
23

22
21

20
19
Program Enable' (E)
18

17

16
1D 15
Y Gating
11 14
12 13

PIN NAMES
AD-A10

AO-Al0 ,Address Inputs

DOO-OOl Data Input (Program) or
Memory Matrix
Output (Read)
(128 X 128)
(E) , _ Program Enable
S , , , ,Chip Select
(Progr) , , , _Program Pulse
VBB ' , , ,-5 V Power Supply
Vee, , , ,+5 V Power Supply
V DO " + 12 V Power Supply
VSS ' , , ,Ground

2:-106
TMS2716, TMS27A16

ABSOLUTE MAXIMUM RATINGS (1)

Rating Value PIN CONNECTION DURING
Unit
READ OR PROGRAM
Operating Temperature o to +70
Storage Temperature -65 to + 125 Pin Number

VDD with Respect te V88 +20 to -0.3 Vdc 9-11,

•
Mode 13-17 18 24
VCC and VSS with Respect to V88 +15 to -0.3 Vdc
All Input or Output Voltage with Respect to VBB During Read Read D out VIL 0' VCC
+15to-0.3 Vdc
VIH
(E!lnput with Respect to VBB During Programming +20 to -0.3 Vdc
Program Din Pulsed VIHW
Program Input wrth Respect to V 8B + 35 to -0.3 Vdc
VIHP
Power Dissipation 1.8 Watts

NOTE 1 Permanent device damage may if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommenderl voltages for
extended periods of time could affect device reliability.

DC READ OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted)

RECOMMENDED DC READ OPERATING CONDITIONS

Parameter Symbol Min Nom Max Unit
Supply Voltage TMS2716 VCC 4.75 5.0 5.25 Vdc
VDD 11.4 12 12.6 Vdc
VBB -5.25 -5.0 -4.75 Vdc
TMS27A16 VCC 4.5 5.0 5.5 Vdc
VDD 10.8 12 13.2 Vdc I

V8B -5.5 -5.0 -4.5 Vdc

I nput High Voltage VIH 2.2 -- Vec + 10 Vrlc
Input Low Voltage VIL VSS - 0.65 Vdc

READ OPERATING DC CHARACTERISTICS

Characteristic Condition Symbol Min Typ Max Unit
Address Input Sink Current Vin ~ VCCmax or Vin ~ VIL I in 1 10 j1A
Output Leakage Current V out = VCCmax and S = 5 V ILO 1 10 j1A
VOD Supply Current Worst-Case Supply Currents 100 65 mA
V CC Supply Current All Inputs High ICC 12 mA
V BB Supply Current (E) = S.O V, TA = OoC 45 mA
IBB
Output Low Voltage IOL = 1.6 mA VOL 0.45 V
Output High Voltage IOH = -100 j1A VOHl 3.7 V
Output High Voltage IOH=-1.0mA VOH2 2.4 V

VBB must be applied prior to VCC anrl VDD. VBB must also be the last power supply switched off.

CAPACITANCE (periodically sampled rather than 100% tested)

Characteristic Condition Symbol Typ Max Unit
Input Capacitance Vin = 0 V, T A = 25°C Cin 4.0 6.0 pF
(f = 1.0 MHz!
Output Capacitance V out =0 V, T A = 25°C Cout 8.0 12 pF
(f = 1.0 MHz!

_________...___________2::1 OZ._
 TMS2716, TMS27 A 16

AC READ OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature"range unless otherwise noted)
(All timing with tr = tf = 20 ns, Load per Note 2)

TMS2716 TMS27A16
Characteristic Symbol Min Max Min Max Unit

II
Address to Output Delay tAVQV - 450 - 300 ns
Chip Select to Output Delay tSLQV - 120 - 120 ns
Data Hold from Address tAXQZ 10 - 10 - ns
Data Hold from Deselection tSHQZ 10 120 10 120 ns
NOTE 2: Output Load = 1 TTL Gate and CL = 100 pF !Includes Jig Capacitance)
Timing Measurement Reference Levels - Inputs: 0.8 V and 2.8 V
AC TEST LOAD
Outputs: 0.8 V and 2.4 V
oDV

MMD6150
or Equ,v
100 pF • 37 k"
MMD1000
ur EllUIV

'Includes Jig Capacitance

"ForVOH

TIMING PARAMETE R ABBR EVIATIONS TIMING LIMITS

;;gn" nom, hom wh;,h ;nt"", ;; d,"ned..J

transition direction for first signal
t
I II
X X X X The table of timing values shows either a minimum or
a maximum iimit for each parameter. Input requirements
are specified from the external system point of view.
signal name to which interval is defined Thus, address setup time is shown as a minimum since the
transition direction for second signal system must supply at least that much time (even though
most devices do not require it). On the other hand,
The transition definitions used in this data sheet are: response:; from the memory are specified from the device
H = transition to high point of view. Thus, the access time is shown as a maxi·
L = transition to low mum since the device never provides data later than
V = transition to valid that time.
X = transition to invalid or don't care
Z = transition to off (high impedance)

READ OPERATION TIMING DIAGRAM

Address Valid

Chip Select, S

~--..j...tSHQZ

Data Out, Q Output Valid

(Low Impedance)

2-108
TMS2716, TMS27A16

DC PROGRAMMING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted)

RECOMMENDED PROGRAMMING OPERATING CONDITIONS

Parameter Symbol Min Nom Max Unit

•
Supply Voltage Vee 4.75 5.0 5.25 Vdc
VDD 11.4 12 12.6 Vdc
VBB -5.25 -5.0 -4.75 Vdc
Input High Voltage for Data VIHD 3.8 - Vec+ 1 Vdc
Input Low Voltage for Data VILO VSS - 0.65 Vdc
Input High Voltage for Addresses VIHA 3.8 - VCC + 1 Vdc
I nput Low Voltage for Addresses VILA VSS - 0.4 Vdc
Program Enable (E) Input High Voltage (Note 3) VIHW 11.4 12 12.6 Vdc
Program Enable (E) Input Low Voltage (Note 3) VILW=VCC 4.75 5.0 5.25 Vdc
Program Pulse Input High Voltage (Note 3) VIHP 25 - 27 Vdc
Program Pulse Input Low Voltage (Note 4) VILP VSS - 1.0 Vdc

NOTE 3: Referenced to VSS.

NOTE 4: VIHP - VILP = 25 V min.

PROGRAMMING OPERATION QC CHARACTERISTICS

Characteristic Condition Symbol Min Typ Max Unit-
Address Input Sink Current Yin = 5.25 V III - - 10 liAdc
Program Pulse Source Current IIPL - - 3.0 mAde
Program Pulse Sink Current IIPH - - 20 mAde
VOD Supply Current Worst-Case Supply Currents IDO - - 65 mAde
VCC Supply Current All Inputs High ICC - - 15 mAdc
(E)=5V,TA=OoC
VBB Supply current lAB - - 45 mAde

AC PROGRAMMING OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature unless otherwise noted)

Characteristic Symbol Min Max Unit

Address Setup Time tAVPH 10 - liS
(E) Setup Time tEHPH 10 - liS
Data Setup Time tDVPH 10 - liS
Address Hold Time tpLAX 1.0 - liS

(E) Hold Time tPLEL 0.5 - liS

Data Hold Time tPLDX 1.0 - liS

Program to Read Delay tELQV - 10 liS

Program Pulse Width tpHPL 0.1 1.0 ms

Program Pulse Rise Time tpR 0.5 2.0 liS

Program Pulse Fall Time tPF 0.5 2.0 liS

Motorola reserves the right to make changes to any products herein to improve reliability, function or design. Motorola does not assume any liability arising
out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.
 TMS2716, TMS27A16

PROGRAMMING OPERATION TIMING DIAGRAM

II Program
Enable, (E)
1 + - - - - - - - - - - - - - 1 of N Program Loops -------,--------1+-- READ-
(After N
Program
Loops)

tpLEL

tEHPH Note 5

VIHA

Address 0

VILA
-----?
tAVPH tPLAX-

VIHD
Data Out
Valjd

tDVPH tPU)X

tPR tpHPL- tpF

Program
Pulse, P

VILP------~

NOTE 5: This Program Enable tranistion must occur after the Program Pulse transition and before the Address Transition,

WAVEFORM DEFINITIONS
Waveform Input Output Waveform Inp'Jt Output
Symbol Symbol

DON'T CARE CHANGING

MUST BE WILL BE
VALID VALID ~ ANY CHANGE
PERMITTED
STATE
UNKNOWN
CHANGE WILL CHANGE
~ FROM H TO L FROMHTOL
~
HIGH
IMPEDANCE
CHANGE
~
WILL CHANGE
FROM L TO H FROMLTOH

2-110
TMS2716, TMS27A16

PROGRAMMING INSTRUCTIONS EXAMPLE FOR PROGRAMMING

Always use the TPtotal = N X tPHPL ~ 100 ms

II
After the completion of an E RASE operation, every bit relationship.
in the device is in the "1" state (represented by Output 1. All 16,384 bits should be prograrnmed with a 0.2 ms
High). Data are entered by programming zeros (Out· program pulse width.
put Low) into the required bits. The words are addressed The minimum number of program loops:
the same way as in the READ operation. A programmed
"0" can only be changed to a "1" by ultraviolet light N = TPtotal = 100 rns = 500.
tPHPL 0.2 ms
erasure.
To set the memory up for programming mode, the One program loop consists of words 0 to 2047.
VCC(E) input (Pin 24) should be raised to +12 V. Pro- 2. Words 0 to 200 and 300 to 700 are to be pro-
gramming data is entered in 8-bit words through the data grammed. All other bits are "don't care". The' program
output terminals (DOO to D07). pulse width is 0.5 ms. The minimum number of program
The VDD and VBB supply voltages are the same as for loops, N = 100/0.5 = 200. One program loop consists of
the READ operation. words 0 to 2047. The data entered into the "don't care"
After address and data setup, one program pulse per bits should be all 1s.
address is applied to the program input. A program loop is 3. Same requirements as example 2, but the EPROM is
a full pass through all addresses. Total programming time/ now to be updated to include data for words 850 to 880.
address, TPtotal = N X tPHPL ~ 100 ms. The required The minimum number of program loops is the same as in
number of program loops (N) is a function of the program the previous example, N = 200. One program loop consists
pulse width (tPHPL! where: 0.1 ms";;;; tPHPL .,;;;; 1.0 ms; of words a to 2047. The data entered into the "don't
correspondingly, N is: 100 .,;;;; N .,;;;; 1000. There must be care" bits should be all 1s. Addresses 0 to 200 and
N successive loops through all 2048 addresses. It is not 300 to 700 must be reprogrammed with their original
permitted to apply more than one program pulse in data pattern.
succession to the same address (i.e., N program pulses to ERASING INSTRUCTIONS
an address and then change to the next address to be
programmed). At the end of a program sequence the The TMS2716/27A16 can be erased by exposure to
Program Enable (E) falling edge transition must occur high intensity shortwave ultraviolet light, with a wave-
before the first address transition; when changing from length of 2537 A. The recommended integrated dose (i.e.,
a PROGRAM to a READ cycle. The program pin should UV-intensity X exposure time) is 12.5 Ws/cm 2 . As an
be pulled down to VILP with an active device, because example, using the "Model 30-000" UV-Eraser (Turner
this pin sources a small amount of current (II pLl when Designs, Mountain View, CA 94043) the ERASE-time is
(E) is at VIHW (12 V) and the program pulse is at VI LP. 30 minutes. The lamps should be used without shortwave
filters and the TMS2716/27A16 should be positioned
about one inch away from the UV-tubes.

2-111
 ® MOTOROLA
MCM6670
MCM6674

MOS
128c X 7 X 5 CHARACTER GENERATOR IN-CHANNEL, SILICON GATE)

II The MCM6670 is a mask-programmable horizontal-scan (row

select) character generator containing 128 characters in a 5 X 7
matrix. A 7-bit address code is used to select one of the 128 available
characters, and a 3-bit row select code chooses the appropriate row
to appear at the outputs. The rows are sequentially displayed,
128c >.< 7 x5
HORIZONTAL-SCAN
CHARACTER GENERATOR

providing a 7-word sequence of 5 parallel bits per word for each

character selected by the address inputs.
The MCM6674 is a preprogrammed version of the MCM6670. L SUFFIX
The complete pattern of this device is contained in this data sheet. CERAMIC PACKAGE

• Fully Static Operation

• TTL Compatibility
• Single ± 10% + 5 Volt Power Supply
• 18-Pin Package
• Diagonal Corner Power Supply Pins
• Fast Access Time, 350 ns (max)

ABSOLUTE MAXIMUM RATINGS (See Note 11

, Rating Symbol Value Unit
P SUFFIX
Supply Voltage VCC -0.3 to +7.0 Vdc PLASTIC PACKAGE
CASE 707
I nput Voltage Vin -0.3 to +7.0 Vdc

Operating Temperature Range TA o to + 70 °c

Storage Temperature Range T stg ·-65 to +150 °c
NOTE 1 Permanent device damage may occur if ABSOLUTE MAXIMUM RA TINGS are ex- PIN ASSIGNMENT
ceeded. Functional operation should be restricted to RECOMMENDED OPERAT-
I NG· CONDI TI ONS. Exposure to higher than recommended voltages for extended
periods of time could affect device reliability.
18
17
16
4 15
BLOCK DIAGRAM
14
13
12 DO
AO 7
12.
A1 6 13 D1
A2 5 8 11
Memory Row
A3 4 D2
Matrix Decode 10
A4 3
15 D3
A5
A6
D4

11 10 8,
RS1 RS2 RS3 This device contains circuitry to protect the
VCC ~.Pin 18 inputs against damage due to high static volt-
Gnd ~ Pin 9 ages or electric fields; however, it is advised that
17 normal precautions be taken to avoid applica-
CS tion of any voltage higher than maximum rated
voltages to this high impedance circuit.

2-112
MCM6670, MCM6674

DC OPERATING CONDITIONS AND CHARACTERISITCS

(Full operating voltage and temperature range unless otherwise noted.)

RECOMMENDED DC OPERATING CONDITIONS

Parameter Symbol Min Nom Max Unit
Supply Voltage
Input High Voltage
Input low Voltage
. VCC
VIH
4.5
2.0
-0.3
5.0
-
5.5
5.25
0.8
Vdc
Vdc
Vdc
Vll ~-

DC CHARACTERISTICS

II
Characteristic Symbol Min Typ Max Unit
Input Current lin - - 2.5 /lAde
(V in = 0 to 5.25 V)
Output High Voltage VOH 2.4 - VCC Vdc
UOH = -205 /lA)
Output low Voltage VOL - - 0.4 Vdc
(IOl = 1.6 mAl
Output leakage C\!i!:ent (Three-State) IlO - - 10 /lAde
(CS = 2.0 V or CS = 0.8 V, Vout = 0.4 V to 2.4 V)
Supply Current ICC - - 130 mAde
(VCC = 5.25 V, TA = OoC)

CAPACITANCE (T A = 25 0 C, f = 1.0 MHz)

Characteristic
Input Capacitance
Output Capacitance

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted.!

AC TEST lOAD

5.0 V

R L =2.5k
AC TEST CONDITIONS
Condition Value Test Paint o-........ _>---+-....~--+ MMD6150
Input Pulse levels 0.8 V to 2.0 V .... ~r ar Equiv

Input Rise and Fall Times 20 ns

30 pF ;::r: 11.7 k
U MMD7000
Output load 1 TTL Gate and Cl = 30 pF
, ar Equiv

AC CHARACTERISTICS
Characteristic Symbol Min Max Unit
Cycle Time 1cyc 350 - ns
Address Access Time tacc(A) - 350 ns
Row Select Access Time tacc(RS) • - 350 ns
ChiP Select to Output Delay tco - 150 ns

2-113
 MCM6670, MCM6674
TIMING D'lAGRAM

tcyc .. I
tacc(A)

~ ~
Address 2.0 V
... 0.8 V
I
I

I
tacc(RS)
"
RS
2.0 V
0.8 V K
II CS ~~- /L 2.0 V

~----tco
"
0.8 V
X X X X X XVv0~

vX>
~XXX~~~~ '" 0.8 2_0~ Xy
V ~XR0
X )()( xx x XX\t0/>

x 2.4 V
Data Out
~ ~~~~ k: 04 V
Data Valid K¢~x)()(;W

~ = Don't Care

CUSTOM PROGRAMMING FOR MCM6670

By the programming of a single photomask, the cus- as VOH; the dots left blank will be at VOL. RO is always
tomer may specify the content of the MCM6670. En- programmed to be blank (VOL). (Blank formats appear at
coding of the photomask is done with the aid of a com- the end of this data sheet for your convenience; they are
puter to provide quick, efficient implementation of the not to be submitted to Motorola, however.)
custom bit pattern while reducing the cost of implemen- 2. Convert the characters to hexadecimal coding treat-
tation. ing dots as ones and blanks as zeros, and enter this i nfor-
Information for the custom memory content may be mation in the blocks to the right of the character font
sent to Motorola in the following forms, in order of format. The information for 04 must be a hex one or
preference: zero, and is entered in the left block. The information for
1. Hexadecimal coding using IBM Punch Cards (Fig- 03 thru DO is entered in the right block, with 03 the
ures 3 and 4). most significant bi~ for the hex coding, and DO the
2. Hexadecimal coding using ASCII Paper Tape Punch least significant.
(Figure 5). 3. Transfer the hexadecimal figures either to punched
Programming of the MCM6670 can be achieved by cards (Figure 3) or to paper tape (Figure 5).
using the following sequence: 4. Transmit this data to Motorola, along with the
1. Create the 128 characters in a 5 x 7 font using customer name, customer part number and revision, and
the format shown in Figure 1. Note that information at an indication that the source device is the MCM6670.
output 04 appears in column one, 03 in column two,
5. Information should be submitted on an organiza-
thru DO information in column five. The dots filled in
tional data form such as that shown in Figure 2.
and programmed as a logic "1" will appear at the outputs

FIGURE 1 - CHARACTER FORMAT

Character Numbe{CrJ.f!IJfJ1t3&(l./f'r/{) Character NumberC-Cfl.5~/f7£f\ IAlPrJ{)

ROW SELECT
MSB LSB HEX MSB LSB HEX
TRUTH TABLE

RS3 RS2 RSl OUTPUT RO 00000 0 0 RO 0 0000 o 0

0 0 0 RO Rl OO~DD 0 tf Rl 131 18lt81181131 I F
0 0 1 Rl R2 0~018J0 0 A R2 181 0000 / 0
0
0
1
1
0
1
R2
R3
R3 181 0 0 0 t8I I R3 ~ DODO / 0
1 0 0 R4
R418100 018:1 I R41:81 ~1:8I00 I c
1 0 1 R5 R5 ~ I~H~ IE1I81 F R5 ~ DODD / 0
1
1
1
1
0
1
R6
R7
R6 !8lDOOI8l R6 181 DODO I 0
R7 ~DoDI8I R7 t8I 18It8118lt81 f F
D4 D3 DO D4 D3 DO

2-114
MCM6670, MCIV!6674

FIGURE 2 - FORMAT FOR PROGRAMMING GENERAL OPTIONS

ORGANIZATIONAL DATA
MCM6670 MOS READ ONLY MEMORY

Customer:
Motorola Use Only
Company
Ouote; _ _ _ __
Part No.
Part No.
Originator
Specif. No .
PhoneNo _ _ _ _ _ _ _ _.________

Chip·Select Options: Active Low No·Connect

Active High
1 a
CS D o D

FIGURE 3 - CARD PUNCH FORMAT

Columns Column 10 on the first card contains either a zero or

1·9 Blank a one to program 04 of row RO for the first character.
10·25 ·Hex coding for first character Column 11 contains the hex character for 03 thru DO.
26 Slash (I) Columns 12 and 13 contain the information to program
27·42 Hex coding for second character R1. The entire first character is coded in columns 10thru
43 Slash (I) 25. Each card contains the coding for four characters;
44-59 Hex coding for third character 32 cards are required to program the entire 128 characters.
60 Slash (I) The characters must be pro{jiammed in sequence from
61-76 Hex coding for fourth character the first character to the last in order to establish proper
77·78 Blank addressing for the part. Figure 3 provides an illustration of
79-80 Card number (starting 01; thru 32) the correct format.

FIGURE 4 - EXAMPLE OF CARD PUNCH FORMAT

(First 12 Characters of MCM6670P4)

00000000011000000000000001110001010101010111110101010101000111101010101010000010
123451 11910"»nu~~n~~~~nnu~an~~~~nnM~.V.H~flU~~~UU"H~~~~~~~»~~ ~~~U~~"~""ronnnu~~n~n.

111 I 11 11111111111111111111111111111111111111 11 1 11 I 1 111 1111111 111111111111111 1111

22222222222222222222222222222222222222222222222222222222222222222222222222222222
3333333333333333333333333333333333333333333333333333 3 3 3 3 3 3 3 3 3 3 3 3 3 333333333333333
4~444444444444444444444444444444444444444444441414141414144444444444444444444444

55555555555555555555555555555555555555555555555H5555555555555555555555555555555
66666666666 61s 6 6 6 6 6 6 6 6661666616666666666 6 6 6 6 6 6 6 6 6 6 6 6 6 6 666 616 6 6 6 6 6 6 6 6 666 6666166 66
717 17 7 17 7 17 171717771717717 717 17 7 717 17 7 7 77 7 7 7 7 7 7 7 7 7 7 7 7 1 7 7 7 7 7 7 7 7 1 7 1 7 7 7 7 7 7 7 7 7 77 7777
1188888888888888888888888888888888 8 888888888888888888888888888888888888888888888
9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 99 9 S 1 9 9 9 9 9 £ 9 9 .~ 9 9 9 9 9 9 9 9 9 9 9
I 2 3 4 5 6'7 a 9 10 11121~ 14 IS 16 17 tl 1'20212221242S2S212121l(1 3132331435363131394041424344454647 4849SJ~1 ~i~3~ 555651:>9 ~',S:)' ~. ~~ ;~; :',c ~'~: ~o;: 7213 N 151& n 111110
GLOBE S-' STANDARD FORM

2-115
 MCM6670, 'MCM6674

FIGURE 5 - PAPER TAPE FORMAT

Frames
Leader Blank Tape start of data entry. (Note that the tape cannot begin with
1 to M Allowed for customer use (M ,;;;; 64) a CR and/or LF, or the customer identification will be
M+l,M+2 CR; LF (Carriage Return; Line Feed) assumed to be programming data.)
M + 3 to M + 66 First line of pattern information Frame M + 3 contains a zero or a one to program D4

II (64 hex figures per line) of row RO for the first character. Frame M + 4 contains
M + 67, M + 68 CR;LF the hex character for D3 thru DO, completing the pro·
M + 69 to Remaining 31 lines of hex figures, gramming information for RO. Frames M + 5. and M + 6
M + 2114 each line followed by a Carriage Re· contain the information to program R 1. The entire first
turn and Line Feed character is coded in Frames M + 3 thru M + 18. Four
Blank Tape complete characters are programmed with each line. A
Frames 1 to M are left to the customer for internal total of 32 lines program all 128 characters (32 x 4).
identification, where M ';;;;64. Any combination of alpha· The characters must be programmed in sequence from the
numerics may be used. This information is terminated first character to the last in order to establish proper
with a Carriage Return and Line Feed, delineating the addressing for the part.

FIGURE 6 - MCM6674 PATTERN

~
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

..... ..... .....

A6 ... A4 D4 DO D4. DO D4 ... DO D4. . DO D4. DO D4 DO D4. DO 04 DO D4 DO D4 DO D4 DO D4 DO D4 DO D4 . DO D4 DO D4 DO

.....
RO 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000
••••• ••••• •••••
.....
00.00 0000. 0.000 00000 0 •••0 00.00 00000 00000 00.00 00000 0 ••• 0 0.'.0
• 000. '0000 00.00 0000' 00.00 aooo • 0000' .000. 0'000 DO.OC 00000 00.00 .0.0. 00.00 aooo. .000.

..... ..... ..... ..... .....

.000. '0000 00.00 0000. 000.0 •• 0 •• 000.0 .000. •••• 0 00080 00000 00.00 0 ••'0 0.000 ' . 0 ' . .000.
000 .000. • 0000 00.00 0000. 0 •••• .oao. • 0.00 oaooa aOBO. 00.00 aoao • .oaoa
• 000. 110000 00.00 0000. 00.00 •• 0 •• • • 000 0.0.0 00.0 • 000.0 00000 0' •• 0 .0.0. 0.000 ..0 •• .DOO.

..... ..... ..... .....

.000. • 0000 .000 •

.....
OD.OD 0000. OOO.D • 0000 0,0.0 DODO' 00.00 00000 00.00 o • • IID DO'OO .000 • .DDO.
.0000

.....
R7 000011 00'000 " 0•• 0000 • 00000 OOoOD OD.OD DOooO 0 ••• 0 0 ••• 0

..... .....
RO 00000 00000 OODOo oDOoO 00000 00000 00000 00000 00000 'ODoOo 00000 00000 OOOOD 00000 00000 00000

.....
0".0 0'.'0 0 ••• 0 o ••• D OODOO D••• O 0000. 00.00 D••• O 0'•• 0
• ODO • • O.D. • ODO. .OOD. ooao • 0000. • 000. aoao. • ODO •

.....
'0110. 0.0.0 .000. 00.00 .000. .000 • .0.0 •

..... ..... ..... ..... .....

• 000 • • O.D. .000. .OOD. • 0.0. 000.0 D.o.o DODoa 0.0.0 0 ••• 0 • OODO • 000' .0.0• .000 • • 000 .. .0.0 •
001
.ODO •
• 0 •••
• 000.
.0 •••
.0.0.
••• 0. • • • 0B aoao. 0.0.0 aoaoo 0 •••0 0.000 • •• 0. • ••0 • aOIl • • .0 •••
aooo • • 000. aoaOB :~:§: '000.
aooo.
• • 000
80000 g:8:8 0000.
DODO.
0.0.0
aooo •
00'00
00.00
00.00
00000
• 000 •
.000 •
.000 •
• 000.
.0.0.
aoao.
aOBO.
.0.0•
.000.
• 000.
R7 0 ••• 0 0 ••• 0 0 ••• 0 0 •••0 00000 •• 0 •• 0000. 00.00 00.00 0 ••• 0

010
AO 00000
00000
00000
00000
00000
00000
oODOD
00000
00.00
OO.DO
00.00
ooaoo
00.00
00000
00000
0.0.0
0.0.0
0.0.0
00000
00000
00000
.....
00000

.....
0.0.0
080ao
0.0.0
0.0.0
00000
00.00
0 ••••
.0.00
0 ••• 0
00.0.
•••• 0
00000
• • 000
• • 00.
000.0
00800
0.000
00000
08000
.0.00
.0.00
.0.0.
oaooo
oaooo aoooo
00000
0 • • 00
0 • • 00

oOOOD
00000
000.0
00.00
8:888
8~~88
00000
0.000
00.00
OOO.D
oooao
000.0
00000

..... .....
00.00
aoao. ooaOD
0 •••0
O ••• D
00000
00 ODD
00.00
00.00
00000
DODOD
00000
00000
0 • • 00
0 • • 00
00000

.....
DOoOO
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
00000
0000.
000.0
00.00
0 •.000

..... .....
.00 • • .00.0 000 DO 00.00 .0.0. 00.00 0.000 00000 0 • • 00 .0000
A7 00000 00.00 00000 0.0.0 00.00 ODD • • 0 • • 0. 00000 000.0 0.000 00.00 00000 .0000 DODOD 0 • • 00 00000
AO 00000 00000 00000 00000 00000 DOooo 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000

.....
0 ••• 0 00.00 0 ••• 0 0 ••• 0 000.0 00 • • 0 0 ••• 0 0 ••• 0 00000 0.1100 000'0 00000 0.000 0 ••• 0

.....
.000. 0 • • 00 .000. • 000. 00 • • 0 .0000 oaDOO 0000 • .OOD. .000. 0 • • 00 0 • • 00 00.00 00000 00.00 .00D.

.....
0000.
8~~~~ gg~~~ ~~8:B ~~~~: 8~~g8 g~~88 ~~888 ~~~~~
.00 • • 00.00 •••• 0 .0Do.· 000.0
011 .0.0. 00.00 DODO_ :~~~g 88~~g 0 •••0 0000. 000.0
• • DO. 000.0 00.00
88g~~
OO.DO • 0000 DODO. 0000 • .000 • 0.000 .000. 0 • • 00 0 • • 00 o.DOO
.oooa

..... ..... .....

• 000. 00.00 .0000 .OOD' 000.0 .000 • .0000 .000. 0 • • 00 0.000 00.00 00000 00.00 00000
R7 0 ••• 0 0 ••• 0 0 ••• 0 DOo.O 0 ••• 0 0 ••• 0 .0000 0 ••• 0 0 • • 00 00000 .0000 Doo.O 00000 O.oDO 00.00

AO 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 oOLlOO 00000 00000
0 ••• 0 00.00 •••• 0
0.00.
0 •• '0 •••• 0 0 •••• .000. 0 ••• 0 0000 • .oooa .0000 .000 • • 000. 0 ••• 0
0.0.0

.....
.ODO. .000. 0.00' .0000 • 0000 .0000 .000 • 00.00 0000. .00.D .0000 . . 0 ••. • • 00.

.....
.00D.
0000. • OOD. 0.00. .0000 0'00 • .0000 .0000 .0000 .000. 00.00 0000. .0.00 .0000 .0.0• • 0.0.
100 .0.0 • .0Do.

.....
.000. 0 ••• 0 0.008
0 • • 0.
:8:8: • 000.
0.00.
0.00,
:88§B
.000.
DilDO •
0.00.
• • • 00
.0000
.0000
• • • 00
:8888
.00 • •
.000.
.000 •
.000.
00.00
oO.oD
0000.
0000.
.000.
• • 000
.0.00
.0000
.0DOD .000 •
• 00 • •
• 000.
.000.
.000.
.000. 00'00 .00.0 .000D .000 • • 000. .000.
A7 D••• o .000. •••• D 0 ••• 0 ••••0 .0000 D•••• • 000. 0 ••• 0 0 ••• 0 .000. .000 • • 00D. O• • • D

18881 :8g8: .....

AO 00000 00000 00000 OoooD 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000
:~~~~
0 ••• 0 •••• 0
~~~~~
.000 •
:888: • 000. 0 •••0
~88g8 D• • • O 00.00
888gg
~~5~g
.0.0.
• 000. • 000. .000 • • 000 • 0000 • 0.000 000.0 0.0.0

..... .....
• 000. eooo • aODO. • 0000 .000 • • 000. .000 • 0.0.0 0.0.0 DOO.O 0.000 0.000 000.0 .000. 00000
101 •••• 0 • 000 • •••• 0 0 ••• 0 ooaoo .000 • 0.0.0 .000 • 00.00 00.00 00.00 0.000 00.00 000.0 00000 00000
0.0.0
8~~~8
• 0000 .0.0 • aO.OD 0000. 00.00 00.00 0.000 0.000 000.0 00080 00000 00000
A7
80000
• 0000
.00.0
o • • D.
.00.D
.000.
.000.
o ••• D
OO.DO
OO.oD
:888:
0 ••• 0 00.00
•• 0 ••
• 000.
.000.
.000.
00.00
00.00
• 0000 0.000
0 ••• 0
DODO •
DDoOD
DOo.O
0 ••• 0
00000
00000
00000

AO 00000 00000 00000 00000 00000 00000 00000 00000 LJoODO 00000 00000 00000 00000 00000 00000 00000

.....
00 • • 0 0 ••• 0 .0000 00000 0000. 00000 000.0 o •• rJ. 00.00 0000. .0000 0 • • 00 Quoau 000 DO 00000
00 • • 0
DO.oO
DODO.
D ••••
.0000
.0 •• 0
00000
0 ••• 0
DODD.
0 •• 0.
000 DO
0 ••• 0
00.0.
00.00
.00 • •
.00 • •
:8888
.0 •• 0
00000
0 • • 00
00000
0000.
.0000
.00.0
00.00
00.00
00000
• • 0.0
DOC 00
.0•• 0
00000
0 ••• 0
110 000.0 .000. • • 00. .000. .00 • • • 000. 0 ••• 0 0 •• 0. • • 00 • ooaoo 0000. ao.oo 00.00 RO.o • • • 00. aooo.
R7
00000
00000
00000
0 ••••
00000
00000
.000.
• • 00.
.0."0
•.0000
.000.
0 ••• 0
.000 •
.00 • •
0 •• 0.
• 0000
0 ••• 0
00.00
00.00
00.00
0000.
.000.
0 ••• 0
.000.
.000.
.000.
~8:gg
0 ••• 0
0000.
.000'
0 ••• 0
..000
.0.00
.00.0
00.00
Oo.OD
0 ••• 0
:8:8:
.D.O •
.000.
.000 •
• 000.
.000.
.000.
0 ••• 0

.....
00000

.....
AO DOooo 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000 00000
.0•• 0 0 •• 0. 00000 00000 001100 00000 00000 00000 00000 .000. 00000 000.0 Oo.OD 0.000 0.000 0.0.0
• • 00. • 00 • • 00000 00000 00.00 00000 00000 00000 00000 .000. 000 DO 00.00 00.00 00.00 .oao • .0.0.

.....
.000. .000. .0•• 0 0 •••• .000. • 00D. .000 • .000 • .000. 00.00 00.00 DO.OO 000.0 0.0.0
111 • • 00. .00 • • ..00. 80000 00.00 .Oooe .000. .000. o.oaG 0 •••• oooao 0.000 00000 000.0 00000 .0.0.
0 •• 0. .0000 .000. DDoDo
8~~~8
.0•• 0 0 ••• 0 00.00 .000. .0.0. DODO. 00'00 00.00 DO.OO 00.00 0.0.0
.ODOO 0000. .0000 0000. 00.0. .OD • • 0.0.0 .0aoD .000. 0.000 00.00 00.00 oo.oc 00000 .0.0.
A7 .0000 0000. • 0000 •••• 0 000.0 0 •• 0 • 00.00 0.0.0 .000. o ••• D 000.0 00.00 0.000 ODDOo 0.0.0

2-116
MCM6670, MCM6674

The formats below are given for your convenience in preparing character information for MCM6670 programming. THESE
FORMATS ARE NOT TO BE USED TO TRANSMIT THE INFORMATION TO MOTOROLA. Refer to the Custom Pro·
gramming instructions for detailed procedures.

Character Number _ __ Character Numbe'r _ __ Character Number _ __ Character Number _ __

II
MSB LSB HEX MSB LSB HEX MSB LSB HEX MSB LSB HEX

ROOOOOO 0 0 RO 00000 tJ 0 RO 00000 0 0

R100000 Ri 00000 Rl00oo0
R200000 R200000 R200000
R300000 R3DOOOO R300000
R400000 R400000 R400000
R500000 R500000 R5DOOOo
R600000 R600000 R600000
R700000 R700000 R700000
0403 DO D4 D3 DO D4 D3 DO D4 D3 DO

Character Number _ __ Character Number _ __ Character Number _ __ Character Number _ _.._ _

MSB LSB HEX MSB LSB HEX MSB LSB HEX MSB LSB HEX

ROOOOOO 0 0 HO 00000 0 0 RO 00000 0 0

R100000 R100000 Rlo0000
R200000 R200000 R200000
R300000 R300000 R300000
R400000 R400000 R400000
R500000 R500000 R500000
R600000 R600000 R600000 '1,
R700000 R700000 R700000 j
D4 D3 DO D4 D3 DO D4 D3 DO

Character Number _ _ _ _ Character Number _ __ Character Number _ _ .__ Character Number _ _ _ _ _ _

MSB LSB HEX MSB LSB HEX MSB LSB HEX MSB LSB HEX

ROOOOOO 0 0 RO 00000 0 0
RO 010000 o 0
R100000 R100000 Rl00000
R200000 R200000 R200000
R300000 R300000 R300000
R400000 R400000 R400000
R500000 R500000 R500000
R600000 R600000 R600000
R700000 R700000 R700000
D403 DO 04 D3 DO D4 D3 DO

Character Number _ __ Character Number _ __ Character Number _ __ Character Number _ _ _ _

MSB LSB HEX MSB LSB HEX MSB LSB HEX MSB LSB HEX

ROOOoOO tJ 0 o 0 RO 00000 0 0 RO 00000 0 0

R100000 R100000 Rl00000
R200000 R200000 R200000
R300000 R300000 R~ 00000
R400000 R400000 R400000
R500000 R500000 R500000
R60 000 R600000 R600000
R700000 R700000 R700000
0403 DO 0403 DO 04 D3 DO D4 D3 DO

2-117
 ® MOTOROL.A
MCM66700 MCM66710
MCM66714 MCM66720
MCM66730 MCM66734
MCM66740 MCM66750
',,> 8192-BIT READ ONLY MEMORIES
ROW SELECT CHARACTER GENERATORS MCM66751 MCM66760
The MCM66700 is a mask-programmable 8192-bit horizontal-scan MCM66770 MCM66780
II (row select) character generator. It contains 128· chqracters in"
a 7 X 9 matrix, and has the capabil ityof shifting certain characters
that normally extend below the baseline such as j, y, g, p, and
q. Circuitry is supplied 'internalry to effectively lower the whole
matrix for this type of character-a feature previously requiring
MCM66790

external circuitry.
A seven-bit address code is used to select one of the 128 available MOS
characters. Each character is defined as a specific combination of
IN-CHANNEL, SILICON-GATE)
logic 1s and Os stored in a 7 X 9 matrix. When a specific four-bit
binary row select code is applied, a word of seven parallel bits appears
at the ouq~ut. The rows can be sequentially selected, providing 8K READ ONLY MEMORIES
a nine-word sequence of seven parallel bits per word for each HORIZONTAL-SCAN
character selected by the address inputs. As the row select inputs CHARACTER GENERATORS
are sequentially addressed, the devices will automatically place WITH SHIFTED CHARACTERS
the 7 X 9 character in one of two preprogrammed positions on
the 16-row matrix, with the positions defined by the four row
select inputs. Rows that are not· part of the character are
automatically blanked.

~CSUFFIX
The devices listed are preprogrammed versions of the MCM66700.
They contain various sets of characters to meet the requirements
of diverse applications. The complete patterns of these devices
are contained in this data sheet.
• Fully Static Operation
,~~!:~:~",
1 .
'ACKAG'
CASE 623
• Fully TTL Compatible with Three-State Outputs
• CMOS and MPU Compatible, Single ± 10% 5 Volt Supply
• Shifted Character Capability
(Except MCM66720, MCM66730, and MCM66734)
• Maximum Access Time = 350 ns
• 4 Programmable Chip Selects (0, 1, or X)
• Pin-for-Pin Replacement for-the MCM6570,
Including All Standard Patterns
24
.
4' 1
PSUFFIX
PLASTIC PACKAGE
CASE7M

AO 15
PIN ASSIGNMENT
A1 16
A2 12 24
Memory
A3 11 Address Matrix Row 23
Decode (8064) Decode
A4 9 3 22
A5 4 21
A6 4
20
6 19
18
Shift 8 17
Control
Matrix 9 16
BLOCK (128) 10 15
DIAGRAM 11 14

Vcc=Pin2 12 13

VSS = Pin 13

2-118
MCM66700 Series

ABSOLUTE MAXIMUM RATINGS (See Note 1, Voltages Referenced to VSS)

Rating Symbol Value Unit
Supply Voltages VCC -0.3 to 7.0 Vdc
Input Voltage Vin -0.3 to 7.0 Vdc
Operating Temperature Range TA o to + 70 uc
Storage Temperature Range T stg -55 to + 125 °c
NOTE 1: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher-than-recommended voltages for
extended periods of time could affect device reliability.
II
DC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature range unless otherwise noted)

RECOMMENDED DC OPERATING CONDITIONS (Referenced to VSS)

Parameter Symbol Min Nom Max Unit
Supply Voltage VCC 4.5 5.0 5.5 Vdc
Input Logic "1" Voltage VIH 2.0 - Vce Vdc
Input Logic "0" Voltage VIL -0.3 - 0.8 Vdc

DC CHARACTERISTICS
Characteristic Symbol Min Typ Max Unit
Input Leakage Current IIH - - 2.5 pAdc
(VIH ~ 5.5 Vdc, VCC ~ 4.5 Vdc)
Output Low Voltage (Blank) VOL 0 - 0.4 Vdc
(IOL ~ 1.6 mAdc)
Output High Voltage (Dot) VOH 2.4 - - Vdc
(IOH ~ -205 pAdc)
Power Supply Current ICC - - 80 mAdc
Power Dissipation Po - 200 440 mW

CAPACITANCE (Periodically sampled rather than 100% tested)

Input Capacitance Cin 4.0 7.0 pF
(f ~ 1.0 MHz)
Output Capacitance C out 4.0 7.0 pF
(f ~ 1.0 MHz)

This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that
normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.

2-119
 I
\

MCM66100 Series

AC OPERATING CONDITIONS AND CHARACTERISTlqS

(Full operating voltage and temperature range unless otherwise noted)

ACTEST LOAD

5.0 V

I AC TEST CONDITIONS
Test Point o-......~~--44....
__~ MMD6150
... ,., or Equiv

130 pF ;::~
Condition Value 11.7 k , . MMD7000
,,, or Equiv
Input Pulse Levels 0.8 V to 2.0 V
Input Rise and Fall Times 20 ns
Output Load 1 TTL Gate and CL = 130 pF

AC CHARACTERISTICS
Characteristic Symbol Typ Max Unit
Address Access Time tacc(A) 250 350 ns
Row Select Access Time tacc(RS) 250 350 ns
Chip Select to Output Delay tco 100 150 ns

TIMING DIAGRAM

1..- - - - - - - - tacc(A) - - - - - - - - 1...

Address 2.0 V
0.8 V

1 4 - - - - - - tacc(RS)'------~••

2.0 V
RS
0.8 V

2.0 V

tco-----~.

0.8 V

Data Out 2.4 V

Data Valid
0.4 V

. ~ = Don't Care

2-120
MCM66700 Series

MEMORY OPERATION (Using Positive Logic)

Most positive level = 1, most negative level = O.
Address can be programmed to occupy either of the two positions
To select one of the 128 characters, apply the appro- in a 7 X 16 matrix. (Shifted characters are not available
priate binary code to the Address inputs (AO through A6). on MCM66720, MCM66730, or MCM66734.)

II
Row Select Output
To select one of the rows of the addressed character For these devices, an output dot is defined as a logic 1
to appear at the seven output lines, apply the appropriate level. and an output blank is defined as a logic 0 level.
binary code to the Row Select inputs (RSO through RS3).
Programmable Chip Select
Shifted Characters The MCM66700 has four Chip Select inputs that can
These devices have the capability of displaying charac- ~e programmed with a 1,0, or don't care (not connected).
ters that descend below the bottom Iine (such as lowercase A don't care must always be the highest chip select pin or
letters j, y, g, p, and q). Internal circuitry effectively drops pins. All standard patterns have Don't Care Chip Select-
the whole matrix for this type of character. Any character except MCM66751.

DISPLA Y FORMAT
Figure 1 shows the relationship between the logic uses of the shift option may require as much as the full
levels at the row select inputs and the character row at 7 X 16 array, or as little as the basic 7 X 9 array (when
the outputs. The MCM66700 allows the user to locate the no shifting occurs, as in the MCM66720).
basic 7 X 9 font anywhere in the 7 X 16 array. In addition, The MCM66700 can be programmed to be scanned
a shifted font can be placed anywhere in the same 7 X 16 either from bottom to top or from top to bottom. This is
array_ For example, the basic MCM66710 font is achieved through the option of assigning row numbers in
establ ished in rows R 14 through R6. All other rows are ascending or descending count, as long as both the basic
autornatically blanked. The shifted font is established in font and the shifted font are the same. For example, an
rows R11 through R3, with all other rows blanked. Thu~, up counter will scan the MCM6671 0 from bottom to top,
while anyone character is contained in a 7 X 9 array, the whereas an up counter will scan the MCM66714 from top
MCM66710 requires a 7 X 12 array on the CRT screen to to bottom (see Figures 7 and 8 for row designation).
contain both normal and descending characters. Other

FIGURE 1 - ROW SELECT INPUT CODE AND SAMPLE CHARACTERS FOR MCM66710 AND MCM66720

ROW SELECT
TRUTH TABLE MCM66710 MCM66720
RS3 RS2 RSl RSO OUTPUT
ROW ROW
0 0 0 0 RO NO. NO.
0 0 0 1 Rl
0 0 1 0 R2 0000000 R15 0000000 •••••• 0 RO 0000000
0 0 1 1 R3 • • • • • • 0 R14 0000000 .00000. Rl .0 • • • 00
.00000. R13 0000000 .00000. R2 • • 000.0
0 1 0 0 R4 • 00000. R12 0000000 .00lJoo • R3 .0000.0
0 1 0 1 R5 .00000. Rll .0.1II110Q •••••• 0 R4 • • 000.0
0 1 1 0 R6 •••••• 0 Rl0 • • 000.0 .000000 R5 .0 • • • 00
0 1 1 1 R7 .000000 R9 .0000.0 .000000 R6 .000000
1 0 0 0 RS .000000 RS .0000.0 .000000 R7 .000000
1 0 0 1 R9 .000000 R7 • • 000.0 .000000 RS .000000
1 0 1 0 Rl0 .000000 A6 .0 • • • 00 06 00 06 00
1 0 1 1 Rll
0000000 R5 .000000
0000000 R4 .000000
1 1 0 0 A12 0000000 R3 .000000
1 1 0 1 R13 0000000 R2 0000000
1 1 1 0 R14 0000000 Rl 0000000
1 1 1 1 R15 0000000 RO 0000000
06 00 06 00

2-121
MCM66700 Series

CUSTOM PROGRAMMING FOR MCM66700

By the programming of a single photomask, the custom- they are not to be submitted to Motorola, however.)
er may specify the content of the MCM66700. Encoding 2. Indicate which characters are shifted by filling
of the photomask is done with the aid of a computer to in the extra square (dot) in the top row, at the left
provide quick, efficient implementation of the custom bit (column S).
pattern while reducing the cost of implementation. 3. Convert the characters to hexadecimal coding
Information for the custom memory content may t-reating dots as 1s and blanks as Os, and enter this infor-
be sent to Motorola in the following forms, in order mation in the blocks to the right of .the character font
of preference: * format. High order bits are at the left, in columns Sand
1. Hexadecimal coding using IBM Punch Cards D3. For the bottom eight rows, the bit in Column S must
(Figures 3 and 4) be 0, so these locations have been omitted. For the top
2. Hexadecimal coding using ASCII Paper Tape Punch row, the bit in Column S will be 0 for an unshifted
(Figure 5) character, and 1 for a shifted character.
4. Transfer the hexadecimal figures either to punched
Programming of the MCM66700 can be achieved by cards (Figure 3) or to paper tape (Figure 5).
using the follow sequence: 5. Assign row numbers to the unshifted font. These
1. Create the 128 characters in a 7 X 9 font using the must be nine sequential numbers (values 0 through 15)
format shown in Figure 2. Note that information at assigned consecutively to the rows. The shifted font is
output D6 appears in column one, D5 in column two, similarly placed in any position in the 16 rows.
through DO information in column seven. The dots filled 6. Provide, in writing, the information indicated in
in and programmed as a logic 1 will appear at the outputs Figure 6 (a copy of Figure 10 may be used for this pur-
as VOH;the dots left blank will be at VOL. (Blank formats pose). Submit this information to Motorola together
appear at the end of this data sheet for your convenience; with the punched cards or paper tape.

FIGURE 2 - CHARACTER FORMAT FIGURE 3 - CARD PUNCH FbRMAT

Character Number
MSB
(C,,-"O"'. INI'W)
LSB HEX
Columns
1 - 10 Blank
11 Asterisk (*)
RIll 0000 0000 o 0

~
000 0000 00 12 - 29 Hex coding for first character
RI~
RIZ. DOD 0000 0 30 Slash (I)
R II 000 0000 0 31 - 48 Hex coding for second character
~I.i RIO 0181181 000121 I 49 Slash (I)
R If 1KI00 1KI0~0 "I A 50 - 67 Hex coding for third character
• R, 18!00 01800
!
68 Slash (I)
R 7 jgJoo tgJol8Io II A 69 - 76 Blank
R, 08181 000181 3 I 77 - 78 Card number (starting 01; through 43)
S 06 04 03 DO
79 - 80 Blank

Character Number( CtIstf-/tIIEJ'( """") Column 12 on the first card contains the hexadecimal
equivalent of column Sand D6 through D4 for the top row of the
MSB LSB HEX
RIJ 181 olia ~ ~~00 .Co first character. Column 13 contains D3 through DO. Columns 14
RIO 01810 oo~o z and 15 contain the information for the next row. The entire first

2 Rtl DI8!I8I I8!I8Io0 character is coded in columns 12 through 29. Each card contains

~
R. 01810 OOilO 22- the coding for three characters. 43 cards are required·to program the
R7 D~o OOIKIO 2.2- entire 128 characters, the last card containing only two characters.
l R6
RJ'
018118 ~18I00 3 G
01810 0000 2.0
The characters must be programmed in sequence from the first
character to the last in order to establish proper addressing for the
Rlf 01810 0000 2.0
R.5 1KI00 0000 1/-0 part. As an example, the first nine characters of the MCM66710
S 06 04 03 DO are correctly coded and punched in Figure 4.

*NOTE: Motorola can accept magnetic tape and truth table formats. For further information contact your local Motorola sales representative.

2-122
MCM66700 Series

FIGURE 4 - EXAMPLE OF CARD PUNCH FORMAT

(First 9 Characters of MCM66710)

,-::

II

ooooooooooollllllllooooooooooloooocooaooooololollolooDoonooololoialloooooooolooo
, 1 J 4 ~ I 1 • , ,. 'I 11 11 It n I, :' 11 It n I, 1111 ;, H a 1111 a If 11 )1 J1l~ ]) l' 31 It nu" H U '" c~,' () "c,
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 11 ,I 1 11 111 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 11 1 1 111 11 11 11 1 1 1 1 1 1 11 ill 1 1 r 1 1 11 1

2222222222222222222222222222221211221111221212222222 2 212 2 2222222222222;'; 22122222

)~" 11 Sl~' IS li~: ~ ~~ " " 51 ~J,. ~~ U" '.1 :.' '~1 ' J;' 1\ 1& " Ie ,1 II
II
3333 3 3 3 3 3 3 3 3 3 3 333331333333313331331133331133333333333333333331313133 j 333 3333 3 3 3 3

444 4 44 44 4 414 44 4 4 4 4 44 4141114 4 4 4 44444444444444441444444444144444444444444444444444

S S S S S S S S S S S S S S 5 5 5 5 5 5555555555555555555555555) 5 5 5 5 5 5 5 5 5 5 5 5 ~ 5 5 5 5 5 5 5 555555555555555
6 66 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 16 6 6 € 6 6 6 6 6 6 6 6 b 6 6 6 6 6 6 6 t 6 66 6 ~ 6 6

77 77 7 77 77 7 77 77 7 77 77 7 7 77 77 7 77 7 7 7 7 77 7 7 7 77 7 77 7 7 7 7777 7 7 77 7 7 7 77 77 77 7 77 7 77 7 77 7 77 17 7 7 7 7
a 88 8 8 8 8 8 8 818 8 8 8 8 8 8 8 8 8 6 8 8888888888888888888888888818888888818888888888888888 88888
99999999999999999999 9999999999999999999999999999999939999999999999 S 9 399999 999 999
1 1 1 , ~ , 1 • , !G :1 Ii II .& 1\ 'i 11 11 "I: 11 11:j l' IS Ii 1) 11 H l~ 11 ); lJ :. 11 H ]1 11 19 U 11 '1 U« H U "" c, la )1 Ii :.j Ij i\ ~, II !I ~, ~c " i: iJ 5' II )~ i' 6' i; '0 'I " I) ,( Ii ~~ :1 ", "' 0
OBE 1110 1 SUNOARD FCRM 5081

FIGURE 5 - PAPER TAPE FORMAT

Frames
start of data entry. (Note that the tape cannot begin
Leader Blank Tape with a CR and/or LF, or the customer identification will
1 to M Allowed for customer use (M ~64) be assumed to be programming data.)
M+1,M+2 CR; LF (Carriage Return; Line Frame M + 3 contains the hexadecimal equivalent of
Feed) column Sand 06 thru 04 for the top row of the first
M + 3 to M + 66 First line of pattern information
character. Frame M + 4 contains 03 thru ~O. Frames
(64 hex figures per line) M + 5 and M + 6 program the second row of the first
M + 67, M + 68 CR;LF
character. Frames M + 3 to M + 66 comprise the first line
M + 69 to M + 2378 Remaining 35 lines of hex figures, of the printout. The line is terminated with a CR and
each line followed by a Carriage LF.
Return and Line Feed
The remaining 35 lines of data are punched in sequence
Blank Tape
using the same format, each line terminated with a CR
Frames 1 to M are left to the customer for i nterna I and LF. The total 36 lines of data contain 36 x 64 or
identification, where M ~ 64. Any coml:,lination of alpha· 2304 hex figures. Since.18 hex figures are required to
numerics may be used. This information is terminated program each 7 x 9 character, the full 128 (2304 -:- 18)
with a Carriage Return and line Feed, delineating the characters are programmed.

FIGURE 6 - FORMAT FOR ORGANIZATIONAL DATA

ORGANIZATIONAL DATA
MCM66700 MOS READ ONLY MEMORY

Customer

Customer Part No. _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Rev.

Row Number for top row of non-shifted font

Row Number for bottom row of non-shifted font

Row Number for top row of shifted font

Programmable Chip Select information: 1 ~ Active High 0 ~ Active Low X ~ Don't Care (Not Connected)

CS1_ CS2_ CS3_ CS4_

2-123
 MCM66700 Series

FIGURE 7 - MCM66710 PATTE.RN

II

FIGURE 8 - MCM66714 PATTERN

.J • • O;JU:J •••••••
0000800 .o~.oo • •••••••
0000800 ::J:JC:O • • O •••••••
0000.00 OOCC;C::OO •••••••
ooaDaeo OO:J::J:;:OO •••••••
0000.00 co::oac:o •••••••
DoDO.Or: G:JOCC:OO •••••••
DODoaoc ;]000::00 •••••••
0 • • • 000 ;)CO~:;:JG= •••••••

2-124
MCM66700 Series

FIGURE 9 - MCM66734 PATTERN-

FIGURE 10 - MCM66720 PATTERN**

J080800
Cloaaaao
•••••••
ooeoaoo
:l......
,.1O::)aooo

a008COO
0 ••••• 0
a.CODOLJ
aOaUDlJ. aooo.oc aaocooo
:Joa0800 aoo.coo oeoooao aoooaco aoo;:]ooo
GGooac:J
Doo.ceo
0 • • • 000

oeo.ooo
ooaoooo
oaO:J80U

OOO[)OCO
OOCOOOO
JO~.OOO
:J:Jacoc:m
:J.C~COO
caOCCOD
O.::JOOOC
JU~!.lJ:"';t.:
TJCoaoU
~JU80C.C
U;J2::::::ao
LJD:J!::mao
••••••• oooacca DC.OoDD oaoaoo. 0000000 08000:::::0 00S:]08:::::
OOeoaoo oooaooa oaOOO.8 aooo •• e 0000000 oaOODOO c:::::COGao
Do.aorn
gg:g:gg ~~~:~~8 ~8~B~~~ ~~~~~~~ 8gg8~gg 'JOD.OOD nCOQII,~u
rl00.~-n~)

:..J • • • • • O 00000.0 ••••••• 0 ••••• 0 •••••••

aooooo. oeoo •• o aoooooo aoocoo. aooooo.
:JaOoDa. 080.080 aoocoeo aooooao ::::lCloOCa[)

~!~~~~~ ~~;;m imm ~~U~~i n~~~~i iii~~ii

oooaaoo 0 • • • 000 W• • OOOO • • • • • • •

:mo.ooo 0000.00 .00.00. • ••••••
~oo.oao oOGe.oo ::JO:::O •• O •••••••

i~iii~i ~~~~m i~~~m 1111111

2-125
 MCM66700 Series

FIGURE 11 - MCM66730 PA TTERNU

II

FIGURE 12 - MCM66740 PATTERN

2~126
MCM66700 Series

FIGURE 13 - MCM66750 PATTERN

II

MCM66751 - Same as MCM66750 except CS1 = 0, CS2 = 0, CS3 = X, and CS4 = X.

FIGURE 14 - MCM66760 PATTERN

2-127
MCM66700 Series

FIGURE 15- MCM66770 PATTERN

~j~~:~~§ ~,·~-· .·!.· ~c·:.·j~.~ .· ........

... ......
. ....-:.
-.•••• ~;_J

~,' ~, :. '~. ~.-':. ~,.:-'.

• ••!,'-.•~-
. :.-- : :-~~~~~~~
- -:-
......
;-
.:;::~:=.t
:-
.:.~;~.::.~
:-:

FIGURE 16 - MCM66780 PATTERN

2-128
MCM66700 Series

FIGURE 17 - MCM66790 PATTERN

II
IC':2C'JI .~~s:::.:: • ••••••• 0001000 0000000
.~:::JW::;. I::::::::::::;. ::-:;~:.:c::. 0010100 8000000
OICC::IO :.J.'-:;:-."~ :. ~::":-;=.c 0100010 ':)000000
1000001 0000000
:.;. 0000000 LJOOOC:JO

.......
c;c .~~. C::l --':1' :" ..• :-~::~: 0000000 0000000

..
~~.:::::::::. :1:- 0000000 fJ':]OOOOD
IC.;:::'-;c.:\..:. _::,::...:. , 0000000 000008,0

.......... .. ···....
.........
•
Ie,
"~'-~:·:-i.

,-:;: :.;
0000000 •••••••

~!!!!! IIIII11
., :IC

.....
_ .:'X'.:'~,-":
10:::.--::-
-':1:".' I:: ••• ::'::J ; ~:::-=.CJ

.. ·...... ....
..=:::::::-.:~
.' .c::c.=.~
--: -: -.~:
-::1 IC::C;CI: 1,- :1
~ .C~~'J:-:.: .' -
.: rar
==

.... ~-'-~ -'.~: :~. ~, ~~~~;i~

j~: ~~ a:::.:..::..:a{
-':.:_:"::::Cc.: a,,--,::':-,::,a;:.;
: •••• :-:r. • .;::~-:.: =:; a::J
a'J:::c::-:.:, ac:::::ca.::-l
r. •• U,:::,·~ .- •., ...
'." ".:'. ::::, ...•.•••. :.c.
C-.1 • • ::::r: :J • • • sa:l
r!~:~ • • ::(] l:::: • • CCC
.~2·.~2.~ , ;.rJ:~a::::: .(;:~:;:;.-
' ,~~

2-129
MCM66700 Series

MCM66700 Series MCM6570 Series

Pin Assignment Pin Assignment

MCM6570 Series MCM66700 Equivalent Description

23
MCM6571 MCM66710 ASC II, sh ifted
MCM6571A MCM66714 ASCII, shifted
MCM6572 MCM66720 ASCII
MCM6573 MCM66730 Japanese
MCM6573A MCM66734 Japanese
MCM6574 MCM66740 Math Symbols
MCM6575 MCM66750 Alphanumeric Control
MCM6576 MCM66760 British, shifted
MCM6577 MCM66770 German, shifted
MCM6578 MCM66780 French, shifted
MCM6579 MCM667110 European, shifted

APPLICATIONS INFORMATION

One important application for the MCM66700 series is serially out to the Z·axis where it modulates the raster
in CRT display systems (Figure 18). A set of buffer shift to form the character.
registers or random access memories applies a 7·bit The MCM66700 series require one power supply of
character code to the input of the character generator, +5.0 volts. When powering this device from laboratory
which then supplies one row of the character according or system powersupplies, it is important that the Absolute
to the count at the four row select inputs. As each row Maximum Ratings not be exceeded or device failure
is available, it is put into the TTL MC7495 shift registers, can result. Sor.le power supplies exhibit spikes or glitches
The parallel information in these shift registers is clocked on thei r outputs when the ac power'is switched on and off.

FIGURE 18 - CRT DISPLAY APPLICATION USING MCM66710

MC7495

~ Os 00 ~
6
~ MC
9 C1
8 C2
01 ~
0-3- OpO
3 0P1 02 ~
~ AO DO
17
4 0P2
7
~ A1 01
5
,OP3
10
03r-=-o--I
o---E. 18
Character
Code
0----!2-
~
A2
A3
A4
02
03
04
6
19
W 1 Os
MC7495
OO~
~
5 6
A5 05 MC
~ A6 06 ~ 9
C1 01 ~
RSO RS1 RS2RS3 8
C2
21 22 23 24 2
.roo

~
°PO
> 3 02
Op1
4
Op2
5 10 Z Axis
Dp3 03
Input
Preset
Control C1
Counters
C2

2-130
MCM66700 Series

The formats below are given for your convenience in preparing character information for MCM66700 programming.
THESE FORMATS ARE NOT TO BE USED TO TRANSMIT THE INFORMATION TO MOTOROLA. Refer to the Custom
Programming instructions for detailed procedures.

•
Character Number Character Number Character Number

MSB LSB HEX MSB LSB HEX MSB LSB HEX

R 0000 0000 R 0000 000 R 0000 0000

R DOD DODD R DOD DODO R DOD DODO
R 000 0000 R 000 0000 R 000 0000
R 000 0000 R ODD 0000 R ODD 0000
R ODD 0000 R ODD DODO R ODD 0000
R DOD DODO R DOD 0000 R 000 0000
R DOD ODD R DOD DOD R ODD DODD
R ODD DODD R ODD DODO R ODD DODD
R
S
ODD
06
0000
04 03 DO
R
S
000
06
0000
04 03 DO
R
S
ODD
06
0000
0403 00

Character Number Character Number Character Number _ _ _ _ _ _

MSB LSB HEX MSB LSB HEX MSB LSB HEX

R DoDO DODO R DODD 0000 R DODD 0000
R DOD 0000 DOD 0000 R ODD DODO
R ODD 0000 000 0000 R DOD 0000
R 000 0000 R ODD 0000 R DOD 0000
R DOD DODO R ODD DODD R ODD DODD
R DOD DODO R ODD DODO R DOD 0000
R DOD DOD DOD 0000 R ODD DODD
R ODD 0000 R ODD DODD R ODD DODD
R ODD DODD
DO
R ODD 0000 R ODD 0000
DO
-.J
S 06 0403 S 06 0403 DO S 06 0403

Character Number Character Number Character Number

MSB LSB HEX MSB LSB HEX MSB LSB HEX

R DODO 0000 R R DODO 0000
R DOD DODD R R ODD 0000
R 000 0000 R R 000 0000
R 000 0000 R R ODD 0000
R ODD DODD R R ODD 0000
R DOD 0000 R R DOD DODD
R 000 000 R R 000 DOD
R 000 DODO R R DOD DODO
R
S
DOD
06
0000
0403 DO
R
S 06 04 03 DO
R DOD
S 06
0000
0403 DO

2-131
 ® MOTOROLA MCM68A30A
MCM68B30A

1024 X 8-BIT READ ONLY MEMORY MOS

The MCM68A30A/MCM68B30A are mask-programmable byte- (N-CHANNEL, SIL ICON-GATE I

II organized memories designed for use in bus-organized systems_

They are fabricated with N-channel sil icon-gate technology_For
ease of use, the_ device operates from a single power supply, has
compatibility with TTL and DTL, and needs no clocks or
refreshing because of static operation_
1024 X 8-BIT
READ ONLY MEMORY

The memory is compatible with the M6800 Microcomputer

Family, providing read only storage in byte increments. Memory

~
expansion is provided through multiple Chip Select inputs. The
active level of the Chip Select inputs and the memory content are
CSUFFIX
defined by the customer.
~VtW -FRIT S~:S~P6~~KAGE
• Organized as 1024 Bytes of 8 Bits

~
• Static Operation
• Three-State Data Output
P SUFFIX
• Four Chip Select Inputs (Programmable) PLASTIC PACKAGE
• Single ±10% 5-Volt Power Supply CASE 709

• TTL Compatible
• Maximum Access Time = 350 ns - MCM68A30A
PIN ASSIGNMENT
250 ns - MCM68B30A

ABSOLUTE MAXIMUM RATINGS (See Note 11

Rating Symbol Value Unit

Supply Voltage VCC -0.3 to +7.0 Vdc

I nput Voltage -0.3 to + 7.0 Vdc

Operating Temperature Range o to + 70

Storage Temperature Range -65 to +150
10
NOTE 1 Permanent device damage may occur tfABSOLUTE MAXIMUMRATiNGSareex·
ceeded. Functional operation should be restricted to RECOMMENDED OPERAT 11
ING CONDITIONS. Exposure to higher than recommended voltages for extended 12
periods of time could affect device reliability

M6800 MICROCOMPUTER FAMIL Y MCM68A30A/MCM68B30A READ ON L Y

BLOCK DIAGRAM MEMORY BLOCK DIAGRAM

Memory
Matrix Data Bus
(1024 X 8)

Address Data Memory Address

Bus, Bus and Control

2-132
MCM68A30A, MCM68B30A

DC OPERATING CONDITIONS AND CHARACTERISTICS

I Full operating voltage and temperature range unless otherwise noted.)

RECOMMENDED DC OPERATING CONDITIONS

Parameter Symbol Min Nom Max Unit

•
Supply Voltage Vee 4.5 5.0 5.5 Vdc

Input High Voltage VIH 2.0 5.5 Vdc

I nput low Voltage Vil -0.3 0.8 Vdc

DC CHARACTERISTICS
Characteristic Symbol Min Typ Max Unit

Input Current lin - 2.5 !JAdc

IV ln - 0 to 5.5 VI

Outp"t High Voltage VOH 24 Vdc

UOH = -205!JA)
Output low Voltage VOL 0.4 Vdc
IIOl 1.6 mAl

Output leakage.Current (Threr Statel ILO 10 !JAdc

(CS = 0.8 V or CS = 2.0 V, V out = 0.4 V to 2.4 V)
Supply Current ICC 130 mAde
(VCC 0 5.5 V, TA = OOC)

CAPACITANCE If 1.0 MHz, T A 25 0 C. pel/odlcally sampled

rather than,l 00% tested I This device contains c/lcultry to protect the
Inputs against damage due to high static voltages
Symbol Max or electl/c fields. however, It IS advised that·
Charaoteristic Unit
normal precautions be taken to aVOid application
I nput Capacitance C ln 7.5 pF of any voltage higher than maximum rated volt
ages to this high-Impedance circuit
Output Capacitance Cout 12.5 pF

BLOCK DIAGRAM

AO 24
2 DO
A1 23
3 01
A2 22-
4 02
A3 21
Address 03
A4 20
Decode 04
AS 19
7 05
A6 18
A7 17 8 06
A8 16 9 07
A9 15

CS1 ' 10
CS2' 11
CS3' 13
CS4' 14
Vee ~ Pin 12
-Active level defined by the customer Gnd c Pin 1

2-133
MCM68A30A, MCM68B30A

AC OPERATING CONDITIONS AND CHARACTERISTICS

IFul1 operating voltage and temperature unless otherWise noted.)
IAII timing with tr = tf = 20 ns, Load of Figure 1)

MCM68A30AL MCM68830AL
Characteristic Symbol Min Max Min Max Unit
Cycle Time teyc 350 - 250 - ns
Access Time taee - 350 - 250 ns
Chip Select to Output Delay teo - 150 - 125 ns
Data Hold from Address tDHA 10 - 10 - ns
Data Hold from Deselection tDHD 10 150 10 125 ns

FIGURE 1 - AC TEST LOAD

5.0 V

R L =2.5k

..... MMD6150
or Equlv
~r
130 pF' :::f' 11.7 k
~r MMD7000
~, or Equlv

-Includes Jig Capacitance

TIMING DIAGRAM

t eve

tacc

~ ~~
Address 1'-2.0 V
1<-0.8 V

v- ~V?-XX~
cs >lXXXXXXXXXX'I ~ 2.0 V
~XXXXXXY

.. teo
0.8
"
cs ~ 0.8 V 2.0 V2 ~XX~
I-tDHD~
f-tDHA
2.4 V
Data Out
~X XXX~XXXXXX~~~~~ 0.4 V ~

2.;.134
MCM68A30A, MCM68B30A

CUSTOM PROGRAMMING
By the programming of a single photomask for the FIGURE 2 - BINARY TO HEXADECIMAL CONVERSION
MCM68A30A/MCM68B30A. the customer may specify Binary HexadeCimal
the content of the memory and the method of enabling Data Character

the outputs. 0
0
0
0
0
0
0
, ,
0

I nformation on the general options of the ,

,
II
0 0 0 2
MCM68A30A/MCM68B30A should be submitted on 0 0 , 3
,
an Organizational Oata form such as that shown in Figure 0
0 , 0
0 ,
0 4
5
3. ("No Connect" must always be the highest order Chip ,
Select pin(s),)
0
0 , 1
, 0
, 6
7
, 0 0 0 8
Information for custom memory content may be sent
to Motorola in one of four forms (shown in order of
, 0 0 1 9
1 0 1 0 A
preference) :
1 0 1 1 B
1. Paper tape output of the Motorola M6800 Software. 1 1 0 0

2. HexadeCimal coding using IBM Punch Cards.

1 1 0 , C
0
1 1 1 0 E
3. EPROM (MCM2708, MCM27A08, or MCM68708). 1 1 1 1 F

4. Hand·punched paper tape (Figure 3).

PAPER TAPE
IBM PUNCH CARDS
Included Ir1 the software packages developed for the The hexadeCimal equivalent (from Figure 2) may be
M6800 Microcomputer Family is the ability to produce placed on 80 column IBM punch cards as follows
a paper tape output for computerized mask generation.
Step Column
The assembler directives are used to control allocation
1 12 Byte "0" Hexadecimal equivalent for
of memory, to assign values for stored data, and fO!
outputs 07 thru 04 (07 = MS.B.)
controlling the assembly process. The paper tape must
2 13 Byte "0" Hexadeci mal equivalent for
specify the full 1024 bytes.
outputs 03 thru 00 (03 = MS. B.)
3 1475 Alternate steps 1 and 2 for consecutive
bytes.
4 77·80 Card number (starting 0001)

2-135
 MCM68A30A, MCM68B30A

FIGURE 3 - HAND·PUNCHED PAPER TAPE FORMAT

Frames bits 07 thru 04 of byte O. Frame M + 4 contains bits

Leader Blank Tape 03 thru DO. These two hex figures together program byte
1 to M Allowed for customer use (M ~64) O. Likewise, frames M + 5 and M + 6 program byte 1,
M+1,M+2 CR; LF (Carriage Return; Line while M + 7 and M + 8 program byte 2. Frames M + 3 to
M + 66 comprise the first line of the printout and program,

II
Feed)
M + 3 to M + 66 First line of pattern information in sequence, the first 32 bytes of storage. The line is
(64 hex figures per line) terminated with a CR and LF.
M+67,M+68 CR;LF Option B (2048 x 4)
M + 69 to M + 211 2 Remaining 31 lines of hex figures, Frame M + 3 contains the hexadecimal equivalent
each line followed by a Carriage of byte 0, bits 03 thru ~O. Frame M + 4 contains byte 1,
Return and Line Feed frame M + 5 byte 2, and so on. Frames M + 3 to M + 66
Blank Tape
sequentially program bytes 0 to 31 (the first 32 bytes).
Frames 1 to M are left to the customer for internal The line is terminated with a CR and LF.
identification, where M "64. Any combination of alpha· Both Options
numerics may be used. This information is terminated The remai ning 31 I ines of data are punched in sequence
with a Carriage Return and Line Feed, del ineating the using the same format, each line terminated with a CR
start of data entry. (Note that the tape cannot begin and LF. The total 32 lines of data contain 32 x 64 or
with a CR and/or LF, or the customer identification will 2048 characters. Since each character programs 4 bits of
be assumed to be programming data.) information, a full 8192 bits are programmed.
As an example, a printout of the punched tape for
Option A (1024 x 8) Figure 13 would read as shown in Figure 10 (a CR and
Frame M + 3 contains the hexadecimal equivalent of LF is implicit at ,he end of each line).

FIGURE 4 - FORMAT FOR PROGRAMMING GENERAL OPTIONS

ORGANIZATIONAL DATA
MCM68A30A/68B30A MOS READ ONL Y MEMORY

Customer: Motorola Use Only:

Company _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ Quote:

Part No. Part No.: _ _ _ _ _ _ _ _ _ _ __

Originator _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __ Specif. No.: _ _ _ _ _ _ _ _ _ __

Phone No. _ _ _ _ _ _ _ _ _ _ _ __

Chip Select Options: Active Active No Connect

High Low "Don't Care"

CSl 0 0 0
CS2 D D D
CS3 D 0 D
CS4 D D 0

2-136
® MOTOROLA MCM68A308
MCM68B308

MOS
1024 X 8-BIT READ ONLY MEMORY

•
(N-CHANNEL, SILICON-GATE)
The MCM68A308/MCM68B308 is a mask-programmable byte-
organized memory designed for use in bus-organized systems. It is
fabricated with N-channel sil icon-gate technology. For ease of use,
1024 X 8-BIT
the device operates from a single power supply, has compatibility
with TTL and DTL, and needs no clocks or refreshing because READ ONLY MEMORY
of static operation.
The memory is compatible with the M6800 Microcomputer
Family, providing read only storage in byte increments. Memory
expansion is provided through multiple Chip Select inputs. The
C SUFFIX
active level of the Chip Select inputs and the memory content
FRITSEAL
are clefined by the customer. PACKAGE
• Organized as 1024 Bytes of 8 Bits CASE 623

• Static Operation
• Three-State Data Output
• Mask·Programmable Chip Selects for
Simplified Memory Expansion
• Single ± 10% 5·Volt Power Supply
• TTL Compatible
• Maximum Access Time = 350 ns - MCM68A308
250 ns - MCM688308 P SUFFIX
• 350 mW Typical Power Dissipation PLASTIC PACKAGE
CASE 709

PIN ASSIGNMENT
MOTOROLA'S PIN COMPATIBLE ROM FAMILY
(Industry Standard Pinouts)

24

23

22

21
10
20
10 11
19
11 12
18
12
17

16
PIN NAMES
15
AO-A9 . Addr~ss Inputs
14
S1-S4. .. Chip Selects

00-07 . Data Output

MCM68A308
VCC . . . +5 V Power Supply

VSS . . Ground

2-137
 MCM68A308, MCM68B308

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted)
RECOMMENDED DC OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit

Supply Voltage VCC 4.5 5.0 5.5 Vdc
Input High Voltage VIH 2.0 - 5.5 Vdc

•
Input Low Voltage VIL -0.3 - 0.8 Vdc

DC CHARACTERISTICS

Characteristic Symbol Min Max Unit

Input Current I in - 2.5 /JAdc
(Vin ~ Oto·5.5 V)
Output High Voltage VOH. 2.4 - Vdc
(IOH ~ -205 /JA)
Output Low Voltage VOL - 0.4 Vdc
(IOL ~ 1.6 mAl
Output Leakage Current (Three-State) ILO - 10 /JAdc
(S ~ 0.8 V or S = 2.0 V, V out = 0.4 V to 2.4 VI
Supply Current ICC -- 130 mAdc
(VCC ~ 5.5 V, T A ~ OoC)

ABSOLUTE MAXIMUM RATINGS (See Note 1)

Rating Symbol Value Unit

Supply Voltage Vec -0.3to+7.0 Vdc
Input Voltage Vin -03 to +7.0 Vdc
Operating Temperature Range TA o to + 70 °c
Storage Temperature Range T stg -65 to + 150 °c

NOTE 1: Permanent device damage may occur

if ABSOLUTE MAXIMUM RATINGS are M6800 MICROCOMPUTER FAMILY
exceeded. Functional operation should be BLOCK DIAGRAM
restricted to RECOMMENDED OPERATING
CONDITIONS. Exposure to higher than recom-
mended voltages for extended periods of time'
could affect device reliability.

Addr.s. Data
Bus Bus

AO
9 00
A1 7
10 01
A2 6
11 02
A3
13 03
BLOCK A4 4 Address
Decode 14 04
DIAGRAM A5 3
15 05
A6
A7 1 16 06
17 07
A8 23
A9 22

S1' 20
S2' 18
S3' 21
19
.
S4' Vee = Pin 24

Active level defined by the user. VSS = Pin 12

2-138
MCM68A308, MCM68B308

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature unless otherwise noted.
All timing with tr ~ tf ~ 20 ns, Load of Figure 1)

MCM68A308 MCM68B308
Characteristic Symbol Min Max Min Max Unit

•
Cycle Time teye 350 - 250 - ns
Access Time taec - 350 - 250 ns
Chip Select to Output Delay tso - 150 -- 150 ns
Data Hold from Address tDHA 10 - 10 - ns
Data Hold from Deselection tDHD 10 150 10 150 ns

CAPACITANCE This device contains circuitry to protect

(f ~ 2.0 MHz, T A ~ 25 0 C, periodically sampled rather than 100% tested) the inputs against damage due to high static
voltages or electric fields; however, it is
I Characteristic
I Symbol Max
I Unit
advised that normal precautions be taken
I Input Capacitance
I Cin 7.5
J pF
to avoid application of any voltage higher

I Output Capacitance I C out 12.5

I pF than maximum rated
high-impedance circuit.
voltages to this

FIGURE 1 - AC TEST LOAD

50 V

Test Point 0--.....---1........---+01...

..--... MMD6150
..... ~r or Equlv

130 pF· ;::r: 11.7 k ~,

MMD7000
~, or Equiv

flnctudes Jig Capacitance

TIMING DIAGRAM

~r------------------------- tcyC - - - - - - - - - - - - - - - - - - - - - - - -__~

~------------------tacc----------------~~

Address 2.0 V
0.8 V

2.0 V
0.8 V

__- - - - - - - - - - - -
I~. tso ------------II-i

~ ~ Don't care

2-139
 MCM68A308, MCM68B308

CUSTOM PROGRAMMING
FIGURE 2 - BINARY TO HEXADECIMAL CONVERSION
By the programming of a single photomask for the
Binary Hexadecimal
MCM68A30S/MCM68B308, the customer may specify Data Character
the content of the memory and the method of enabling 0 0 0 0 0
the outputs. (A "no-connect" must always be the highest 0 p 0 1 1

II order chip-select(s).)

I nformation on the general options

MCM68A30S/MCM68B30S should be submitted on an
of

Organizational Data form such as that shown in Figure 4.

the
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
0
1

1
2
3
4
5
6
7
1 0 0 0 8
Information for customer memory content may be 1 0 0 1 9
1 0 1 0 A
sent to Motorola in one of four forms (shown in order
1 0 1 1 B
of preference): 1 1 0 0 C
1 1 0 1 D
1. Paper tape output of the Motorola M6800 Software. 1 1 1 0 E
2. Hexadecimal coding using IBM Punch Cards. 1 1 1 1 F

3. EPROM one MCM68A708 or equivalent.

IBM PUNCH CARDS
4. Hand punched paper tape (Figure 3).
The hexadecimal equivalent (from Figure 2) may be
placed on 80 column IBM punch cards as follows:
PAPER TAPE Step Column
I ncluded in the software packages developed for the 1 12 Byte "0" Hexadecimal equivalent for
M6800 Microcomputer Family is the ability to produce outputs Q7 thru Q4 (Q7 = M.S.B.)
a paper tape output for computerized mask generation. 2 13 Byte "0" Hexadecimal equivalent for
The assembler directives are u'sed to control allocation outputs Q3 thru QO (Q3 = M.S.B.)
of memory, to assign values for stored data, and for 3 14-75 Alternate steps 1 and 2 for consecutive
cantrall ing the assembly process. The paper tape must bytes.
specify the full 1024 bytes. 4 77-80 Cal'd number (starting 0001)

FIGURE 3 - HAND·PUNCHED PAPER TAPE FORMAT

Frames
Leader Blank Tape
1 toM Allowed for customer use (M';;; 64) with a CR and/or LF, or the customer identification will
M+1,M+2 CR; LF (Carriage Return; Line be assumed to be programming data.)
Feed) Frame M + 3 contains the hexadecimal equivalent of
M + 3 to M + 66 First line of pattern information bits Q7 thru Q4 of byte O. Frame M + 4 contains bits
(64 hex figures per line) Q3 thru QO. These two hex figures together program byte
M +.67, M + 68 CR;LF O. Likewise, frames M + 5 and M + 6 program byte 1,
M + 69 to M + 2112 Remaining 31 lines of hex figures, whrle M + 7 and M + 8 program byte 2. Frames-j'~VIF-'h",,",,"U-+----­
each line followed by a Carriage M + 66 comprise the first line of the printout and program,
Return and Line Feed in sequence, the first 32 bytes of storage. The line is
Blank Tape terminated with a CR and LF.
Frames 1 to M are left to the customer for internal The remaining 31 lines of data are punched in sequence
identification, where M ,;;; 64. Any combination of alpha- using the same format, each line terminated with a CR
. numerics may be used. This information is terminated and L F. The total 32 I ines of data contai n 32 x 64 or
with a Carriage Returri and line Feed, delineating the 204S characters. Since 'each character programs 4 bits of
start of data entry. (Note that the tape cannot begin information, a full 8192 bits are programmed.

2-140
MCM68A308, MCM68B308

FIGURE 4 - FORMAT FOR PROGRAMMING GENERAL OPTIONS

ORGANIZATIONAL DATA
MCM68308 MOS READ ONL Y MEMORY

Customer:

Company _________________________________

Part No.
Motorola Use Only:

Quote: ___________________

Part No.: __________________

•
Originator ________________________________ Specif. No.: __________________

Phone No. _______________________

Chip Select: Active Active No

High Low Connect

S1 0 0 D
S2 D 0 0
S3 0 D D
S4 D D D

2-141
 ® MOTOROLA
MCM68A316A

2048 X 8-BIT READ ONLY MEMORY

MOS
The MCM68A316A is a mask-programmable byte-organized

II memory designed for use in bus-organized systems. It is fabricated

with N-channel sil icon-gate technology. For ease of use, the device
operates from a single power supply, has compatibility with TTL
and DTL, and needs no clocks or refreshing because of fully
static operation.
(N-CHANNEL, SILICON-GATE)

2048 X 8-BIT
READ ONLY MEMORY

The memory is compatible with the M6800 Microcomputer

Family, providing read-only storage in byte increments. Memory
expansion is provided through multiple Chip Select inputs. The
C SUFFIX
active level of the Chip Select inputs and the memory content FRIT·SEAL PACKAGE
are defined by the user. CASE 623

• Fully Static Operation

• Three-State Data Output
• Mask-Programmable Chip Selects for
Simplified ":1emory Expansion
• Single ± 10% 5-Volt Power Supply
• TTL Compatible
• Maximum Access Time = 350 ns
• Plug-in Compatible with 2316A

CASE 709
ABSOLUTE MAXIMUM RATINGS (See Note 1)
Rating Symbol Value Unit
Supply Voltage VCC - 03to+70 Vdc
Input Voltage Vin -0.3 to +7.0 Vdc
Operating Temperature Range TA o to +70 °c PIN ASSIGNMENT
Storage Temperature Range T stg -65 to +150 °c
NOTE 1: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
.,
1 ( A7
2 ( A8
• Vee J24
QO 023
OPERATING CONDITIONS. Exposure to higher than recommended voltages
3 C A9 Ql 022
for extended periods of time could affect device reliability.
4C Al0 Q2 p21
5 C AO Q3 P20
M6800 MICROCOMPUTER FAMILY BLOCK OIAGRAM
6C Al Q4 p19

l Me6S00
Microprocessor
7 ( A2
8 ( A3
Q5 p18
Q6 )17
9( A4 Q7 )16
IMCM68A316AJ ).15
J Read Only
10 ( A5 51
IVIe-r"rlO ... 6 S
12 ( VSS 53 J13
1 Random

~
Access
Me":,ory I
PIN NAMES
I Interface

~ Adapter AD-AlD. · Address Inputs

Sl-S3 ... · Chip Selects

I QO-Q7 .. · Data Output

Interface

~ Adapter
Modem
I Vee ... · +5 V Power Supply
VSS . . . · Ground
Address Data
Bus Bus

2-142
MCM68A316A

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted)

RECOMMENDED DC OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit
Supply Voltage VCC 4.5 5.0 5.5 Vdc
5.5 Vdc

II
Input High Voltage VIH 2.0 -

Input Low Voltage VIL -0.3 - 0.8 Vdc

DC CHARACTERISTICS
Characteristic Symbol Min Max Unit
Input Current lin - 2.5 /lAdc
(Vin ~ 0 to 5.5 V)
Output High Voltage VOH 2.4 - Vdc
UOH ~ -205/lA)
Output Low Voltage VOL - 0.4 Vdc
(lOL ~ 1.6 mAl
Output Leakage Current (Three·State) ILO - 10 }JAdc
(S ~ 0.8 V or S ~ 2.0 V, V out ~ 0.4 V to 2.4 V)
Supply Current ICC - 130 mAdc
(VCC~5.5V,TA~00C)

This device contains circuitry to protect the

CAPACITANCE inputs against damage due to high static volt-
(f ~ 2.0 MHz, T A ~ 25°C, periodically sampled rather than 100% tested) ages or electric fields; however, it is advised that
normal precautions be taken to avoid applica-
Characteristic tion of any voltage higher than maximum rated
I nput Capacitance voltages to this high impedance circuit.

Output Capacitance
FIGURE 1-AC TEST LOAD
50 V

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature unless otherwise noted.
o---+-_>--........~-4 MM06150
All timing with tr = tf ~ 20 ns, Load of Figure 11 T est Po in t
or Equiv
Characteristic Symbol Min Max Unit
Cycle Time 350 - ns 130pF· 11.7k
tcyc MM07000
Access Time tacc - 350 ns or Equiv

Chip Select to Output Delay tso - 150 ns

Data Hold from Address tDHA 10 - ns
Data Hold from Deselection tH 10 150 ns
-Include'S Jig CdpcH. 1tance

AO 5
23 00
A1 6
22 01
A2 7
21 02
A3 8
Address
20 03
BLOCK A4 9
Oecode 19 04
DIAGRAM A5 10
18 05
A6 11
17 06
A7 1
16 07
A8 2
A9 3.
Al0 4

51" H>
52" 14
53" 13
Vee = Pin 24
• Active level defined by the user. Vss = Pin 12

2-143
 MCM68A316A

TIMING DIAGRAM

tcYc------------------------__~

~~----------------tacc----------------~~

2-144
MCM68A316A

CUSTOM PROGRAMMING

By the programming of a single photomask for the FIGURE 2 - BINARY TO HEXADECIMAL CONVERSION

MCM68316A, the customer may specify the content of Binary Hexadecimal

the memory and the method of enabling the outputs. Data Character
a a a 0 a

•
Information on the general options of the a a a 1 1
a a 1 0 2
MCM68A316A should be submitted on an Organizational
a a 1 1 3
Data form such as that'shown in Figure 3. a 1 a 0 4
a 1 0 1 5
Information for custom memory content may be sent 0 1 1 0 6
0 1 1 1 7
to Motorola in one of four forms (shown in order of
1 0 0 0 8
preference) :
1 0 0 1 9
1 0 1 0 A
1. Paper tape output of the Motorola M6800 Software. 1 0 1 1 8
1 1 0 0 C
2. Hexadecimal coding using I BM Punch Cards.
1 1 0 1 0
3. EPROM (TMS2716 or MCM2716). 1 1 1 0 E
1 1 1 1 F
4. Hand·punched paper tape.
"-----

IBM PUNCH CARDS

PAPER TAPE
The hexadecimal eq~ivalent (from Figure 2) may be
Included in the software packages developed for the
placed on 80 column IBM punch cards as follows:
M6800 Microcomputer Family is the ability to produce a
paper tape output for computerized mask generation. The Step Column
assembler- directives are used to control allocation of 1 12 Byte "0" Hexadecimal equivalent for
memory, to assign values for stored data, and for control- outputs 07 thru 04 (07 = M.S.B.)
ling the assembly process. The paper tape must specify the 2 13 Byte "0" Hexadecimal equivalent for
full 2048 bytes. outputs 03 thru 00 (03 = M.S.B.)
3 14-75 Alternate steps 1 and 2 for consecutive
bytes.
4 77-80 Card number (starting 0001)
Total number of cards (64)

FIGURE 3 - FORMAT FOR PROGRAMMING GENERAL OPTIONS

ORGANIZATIONAL DATA
MCM68A316A MOS READ ONL Y MEMORY

Customer:
Motorola Use Onl y:
Company ------------__________________________

Quote:
Part No.
Part No .. ______--'-_______________
Originator _______-----------------------------
Spec if. No.: ______________________
Phone No. ___________________________

Chip Select: 'Don't Care

Active High Active Low (No Connect)

o D D
o o D
o D D
*A don't care must always be the highest order Chip Select(s).

2-145
 ® MOTOROI.A MCM68A316E

MOS
2048 X 8 BIT READ ONLY MEMORY

•
(N~HANNEL. SILICON-GATE)

The MCM68A316E is a mask-programmable byte-organized

memory designed for use in bus-organized systems. It is fabricated
with N-channel silicon-gate technology. For ease of use, the device 2048 X 8 BIT
operates from asingle power supply, has compatibility with TTL and READ ONLY MEMORY
DTL, and needs no clocks orrefeshing because of static operation.
The memory is compatible with the M6800 Microcomputer
Family, providing read only storage in byte increments. Memory
expansion is provided through multiple Chip Select inputs. The C SUFFIX
active level of the Chip Select inputs and the memory content I=RIT·SEAL PACKAGE
CASE 623
are defined by the user.
• Fully Static Operation
• Three·State Data Output
• Mask-Programmable Chip Selects for
Simplified Memory Expansion
• Single ± 10% 5-Volt Power Supply
• TTL Compatible
• Maximum Access Time = 350 ns
• Plug-in Compatible with 2316E
P SUFFIX
• Pin Compatible with 2708 and MCM2716 EPROMs PLASTIC PACKAGE
CASE 709

PIN ASSIGNMENT
MOTOROLA's PIN COMPATIBLE ROM FAMILY
(Industry Standard Pinouts)

22
21

;20
19
24 18
23 17
22 16
21 15
20 14
10
19 13
11
18
12
17
16
PIN NAMES
15
AO-A10 . . . . ~ddress Inputs
14
S1 -S3 . . . . Chip Selects
13
00-07 . . . . Data Output
Vee . • . . + 5 V Power Supply
VSS . . . • Ground

2-146
MCM68A316E

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted)
RECOMMENDED DC OPERATING CONDITIONS
Parameter Symbol Min Typ Max Unit
Supply Voltage VCC 4.5 5.0 5.5 Vde
Input High Voltage VIH 2.0 - 5.5 Vde
Input Low Voltage VIL -0.3 - 0.8 Vde

•
DC CHARACTERISTICS
Characteristic Symbol Min Max Unit
Input Current lin - 2.5 /.lAde
(Vin = 0 to 5.5 V)
Output High Voltage VOH 2.4 - Vde
(lOH = -205 /.lA)
Output Low Voltage VOL - 0.4 Vde
(lOL = 1.6 rnA)
Output Leakage Current (Three·State) ILO - 10 /.lAde
(S = 0.8 V or S = 2.0 V, V out = 0.4 V to 2.4 V)
Supply Current ICC - 130 niAde
(VCC = 5.5 V, T A = OoC)

ABSOL.UTE MAXIMUM RATINGS (See Note 1)

Rating Symbol Value Unit

Supply Voltage VCC -0.3 to +7.0 Vde
Input Voltage Vin -0.3 to +7.0 Vde
Operating Temperature Range TA o to +70 °c
Storage Temperature Range T stg -65 to + 150 °c
NOTE1: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages
for extended periods of time could affect device reliability.

CAPACIT ANCE
(f = 2.0 MHz, T A = 25°C, periodically sampled rather than 100% tested)

Characteristic Symbol Max Unit

I nput Capacitance . 7.5 pF
Output Capacitance C out 12.5 pF

M6800 MICROCOMPUTER FAMIL Y

BLOCK OIAGRAM

Address Data
Bus Bus

AO 8
9 00
At 7
10 01
A2 6
11 02
A3
13 03
BLOCK A4 4 Address
Decode 14 04
DIAGRAM A5 3 15 05
A6
A7 16 06
1
17 07
A8 23
A9 22
Al0 19

51'
52'
53'
V'cc = Pin 24
• Active level defined by the user. Gnd = Pin 12

---~~~--
2-147
~------ -~
 MCM68A316E

FIGURE 1-AC TEST LOAD

50V
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise noted.
All timing with tr = tf = 20 ns, Load of Figure 1)
Test Point 0 -.....-1>---+1
.....
.._---. Unit
... 1r MMD6150
orEqulv
Cycle Time
Characteristic Svmbol
tcyc
Min
350
Max
- ns

II
130pFO;j=:; 11.7 k 11r MMD7000 Access T,me tacc - 350 ns

11r or Equlv
Chip Select to Output Delay tso - 150 ns
Data Hold from Address tDHA 10 - ns
Data Hold from Deselection tH 10 150 ns

·'Includes Jig Capacitance

TIMING DIAGRAM
This device contains circuitry to
protect the inputs against damage -.teye
due to high static voltages or elec· tacc
tric fields; however, it is advised
Addres,~
that normal precautions be taken
to avoid application of any vol·
~:3 ~ ~
tage higher than maximum rated
voltages to this high·impedance
circuit. 2.0 V
0.8 V

tso
2.0 v
0.8 v
f--tH:j
tOHA
f-
'~.4 V
Data Out 0.4 V

2-148
MCM68A316E

CUSTOM PROGRAMMING

. By the programming of a single photomask for the FIGURE 2 - BINARV TO HEXADECIMAL CONVERSION

MCM68A316E, the customer may specify the content of Binary Hexadecimal

•
Data Character
the memory and the method of enabling the outputs.
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
Information on the general options of the
0 0 1 1 3
MCM68A316E should be submitted on an Organizational
0 1 0 0 4
Data form such as that shown in Figure 3. ("No-Connect" 0 1 0 1 5
must always be the highest order Chip Select(s).) 0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
Information for custom memory content may be sent
1 0 0 1 9
to Motorola in one of three forms (shown in order of
1 0 1 0 A
preference) : 1 1
0 1 B
1 1 0 0 C
1. Paper tape output of the Motorola M6800 Software. 1 1 0 1 0
2. Hexadecimal coding using IBM Punch Cards. 1 1 1 0 E
1 1 1 1 F
3. EPROM (TMS2716 or MCM2716).

IBM PUNCH CARDS

PAPER TAPE
The hexadecimal equivalent (from Figure 2) may be
Included in the software packages developed for the
placed on 80 column IBM punch cards as follows:
M6800 Microcomputer Family is the ability to produce a
paper tape output for computerized mask generation. The Step Column
assembler directives are used to control allocation of 1 12 Byte "0" Hexadecimal equivalent for
memory, to assign values for stored data, and for control- outputs 07 thru 04 (07 = M.S.S-l
ling the assembly process_ The paper tape must specify the 2 13 Byte "0" Hexadecimal equivalent for
full 2048 bytes. outputs 03 thru 00 (03 = M.S_B_)
3 14-75 Alternate steps 1 and 2 for consecutive
bytes_
4 77-80 Card number (starting 0001)
Total number of cards (64)

FIGURE 3 - FORMAT FOR PROGRAMMING GENERAL OPTIONS

ORGANIZATIONAL DATA
MCM68A316E MOS READ ONL Y MEMORY

Customer:
Motorola Use Only:
Company -------------------------------------
Ouote: ________________________
Part No.
Part No.: __________________
Originator ________________________________

Specif. No.:
Phone No __________________________

Chip Select: Active Active No

High Low Connect

Sl D D D
S2 D D D
'S3 0 0 D

__2-1.5JL_
 ® MOTOROLA MCM68A332

4096 X a-BIT READ ONLY MEMORY MOS

The MCM68A332 is a mask-programmable byte-organized (N-CHANNEL, SILICON-GATE)

II memory designed for use in bl!s-organized systems. It is fabricated

with N-channel silicon-gate technology. For ease of use, the device
operates from a single power supply. has compatibility with TTL and
DTL. and needs no clocks or refreshing because of static operation.
4096 X a-BIT
READ ONLY MEMORY
The memory is compatible with the M6800 Microcomputer
Family. providing read only storage in byte increments. Memory
expansion is provided through multiple Chip Select inputs. The
active level of the Chip Select inputs and the memory content C SUFFIX
are defined by the user. FRITSEAL PACKAGE
CASE 624
• Fully Static Operation
• Three-State Data Output for OR-Ties
• Mask-Programmable Chip Selects for Simplified Memory
Expansion
• Single ±10% 5-Volt Power Supply
• Fully TTL Compatible
• Maximum Access Time = 350 ns
• Directly Compatible with 4732
• Pin Compatible with 2708 and 2716 EPROMs P SUFFIX
.' Preprogrammec MCM68A332-2 Available PLASTIC PACKAGE
CASE 709

PIN ASSIGNMENT
MOTOROLA'S PIN COMPATIBLE ROM FAMILY
24
(Industry Standard Pinouts)
23
22
4 21
20
6 19
18
24
8 17
23
16
22
15
21
20
10 12 13
19
11
18
'12
17
16 PIN NAMES

15 AO-A 11 . . . . Address Inputs

S , . . . Programmable
14
Chip Selects
13
00-07 . . . . Data Output
MCM68A308 V CC . . . . + 5 V Power Supply
VSS . . . . Ground

2-150
MCM68A332

AO
9 00
A1
10 01
A2 11 02
A3
13 03
BLOCK A4 4 Address
Decode 14 04
DIAGRAM A5 3 15 05
A6
16 06
A7
17 07
A8 23

II
A9 22
Al0 19
All 18

51' 20--
52' 21--
Vee = Pin 24
V55=Pin12
* Active level defined. by the user.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted)

RECOMMENDED DC OPERATING CONDITIONS

Parameter Symbol Min Typ Max Unit
Supply Voltage (Vee must be applied at least 100 "s before proper deVice operatIOn IS achleved.1 Vce 4.5 5.0 5.5 Vdc
Input High Voltage VIH 2.0 - 5.5 Vdc
Input low Voltage Vil -0.3 - 0.8 Vdc
--
DC CHARACTERISTICS
Characteristic Symbol Min Max Unit
I nput Current lin - 2.5 !lAdc
(Vin ~ 0 to 5.5 V)
Output High Voltage VOH 2.4 - Vdc
(lOH ~ -205 !lAI
Output low Voltage VOL - 0.4 Vdc
(IOl ~ 1.6 mAl
Output leakage Current (Three-State) IlO - 10 !lAdc
(S ~ 0.8 V Qr S = 2.0 V, V out ~ 0.4 V to 2.4 V)
Supply Current ICC - 80 mAdc
(Vee = 5.5 V, TA = OOCI

ABSOLUTE MAXIMUM RATINGS (See Note 1)

This device contains circuitry to
Rating Symbol Value Unit
protect the inputs against damage
Supply Voltage VCC -0.3 to +7.0 Vdc due to high static voltages or elec-
Input Voltage Vin -0.3 to +7.0 Vdc tric fields; however, it is advised
that normal precautions be taken
Operating Temperature Range TA o to +70 °c
to avoid application of any vol-
Storage Temperature Range T stg -65 to +150 °c tage higher than maximum rated
NOTE 1: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are voltages to this high-impedance
exceeded. Functional operation should be restricted to RECOMMENDED circuit.
OPERATING CONDITIONS. Exposure to higher than recommended voltages
for extended periods of time could affect device reliability.'

CAPACITANCE
(t = 1.0 MHz, T ~ = 25 0 C, periodically sampled rather than 100% tested)
Characteristic Symbol Typ
Input Capacitance Cin 5.0
Output Capacitance C out

M6800 MICROCOMPUTER FAMILY

BLOCK DIAGRAM

Address Data
Bus Bus

2-151
 MCM68A332

FIGURE l-AC TEST LOAD

5.0 V
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Full operating voltage and temperature unless otherwise noted.

TI MMD6150
All timing with tr = tf = 2'0 ns, Load of, Figure 1)

I
.Test Point Characteristic Symbol Min Max Unit
or equivalent
Cycle Time tcyc 350 - ns

'" "'1-1 ".H

MMD7000
or equivalent
Access Time
Chip Select to Output Delay
Data Hold from Address
tacc
tso
tDHA
-
--
10,
350
150
-
ns
ns
ns
Data Hold from Deselection tH 10 150 ns

• I ncludes jig capacitance

TIMING DIAGRAM

tcyc

tace

~
Address, A 2.0 V
1.0.8 V

Chip Select, S 2.0 V

0.8 V ~'

tso

Chip Select, S 0.4 V

0.8 V
__ tH~
:-tDHA

Output, Q
------------------------~------~(~~~:~~~~~--------~>~---------

Waveform Waveform Waveform

Symbol Input Output Symbol Input Output Symbol Input Ou~put

MUST BE
VALID
WILLBE
VALID ~ ::~;;H~~EE
PERMITTED
CHANGING:
STATE
UNKNOWN
=>- - HIGH
IMPEDANCE

2-152
MCM68A332

MCM68A332 CUSTOM PROGRAMMING FIGURE 2 - BINARY TO HEXADECIMAL CONVERSION

Hexadecimal
By the programming of a single photomask for the Binary Data Character
MCM68A332, ~he customer may specify the content of the
'0 0 0 0 0
memory and the method of enabling the outputs.
0 0 0 1 1
Information on the general options of the MCM68A332
0 0 1 0 2
should be submitted on an Organizational Data form such as that 0 0 1 1 3
shown in Figure 3. (A "No·Connect" or "Don't Care" must always 0 1 0 0 4
be the highest order Chip Select(s).) 0 1 0 1 5

II
Information for custom memory content may be sent to 0 1 1 0 6
Motorola in one of four forms (shown in order of preference): 0 1 1 1 7
1. IBM Punch Cards: 1 0 0 0 8
A. Hexadecimal Format 1 0 0 1 9
1 0 1 0 A
B. Intel Format
1 0 1 1 B
C. Binary Negative-Postive Format
1 1 0 0 C
2. EPROMs-two 16K (MCM2716 or TMS2716) or four 1 1 0 1 D
8K (MCM2708) 1 1 1 0 E
3. Paper tape output of the Motorola M6800 software 1 1 1 1 F
4. Hand punched paper tape

PAPER TAPE PRE-PROGRAMMED MCM68A332P2, MCM68A332C2

Included in the software packages developed for the M6800
Microcomputer Family is the ability to produce a paper tape The -2 standard ROM pattern contains sine-lookup and arctan-
output for computerized mask generation. The assembler direc- lookup tables.
tives are used to control allocation of memory, to assign values. for Locations 0000 through 2001 contain the sine values. The
stored data, and for controlling the assembly process. The paper sine's first quadrant is divided into 1000 parts with sine values
tape must specify the full 4096 bytes. corresponding to these angles stored in the ROM. Sin 1r/2 is
included and is rounded to 0.9999.
IBM PUNCH CARDS, HEXADECIMAL FORMAT The arctan values contain angles in radians corresponding to
The hexadecimal equivalent (from Figure 2) may be placed on the arc tangents of 0 through 1 in steps of 0.001 and are contained
80 column IBM punch cards as follows: in locations 2048 through 4049.
Locations 2002 through 2047 and 4050 through 4095 are
Step Column zero filled.
1 12 Byte "0" Hexadecimal equivalent for outputs All values are represented in absolute decimal format with four
07 through 04 (07 = M.S.B.) digit precision. They are stored in BCD format with the two most
2 13 Byte "0" Hexadecimal equivalent for outputs significant digits in the lower byte and the two least significant
03 through 00 (03 = M.S.B.) digits in the upper byte. The decimal point is assumed to be to
3 14-75 Alternate steps 1 and 2 for consecutive bytes. the left of the most significant digit.
4 77-79 Card number (starting 001).
5 Total number of cards must equal 128. 1
Example: Sin ('10 00 ~) = 0.0016 decimal
Address Contents
0002 0000 0000
0003 0001 0110

FIGURE 3 - FORMAT FOR PROGRAMMING GENERAL OPTIONS

ORGANIZATIONAL DATA
MCM68A332 MOS READ ONLY MEMORY

Customer:
Motorola Use Only
Company ___________________________________
Quote
Part No. ____________________________________
Part No.
Originator _________________________________
Specif. No.
PhoneNo. ______ ~ ______________________

Chip Select Options: Active High Active Low No-Connect

S1 0 0 0
S2 0 0 0

2-153
 ® MOTOROLA
MCM68A364
MCM68B364
Advance Infor:rnation
MOS
8192 X 8-BIT READ ONLY MEMORY IN-CHANNEL, SILICON-GATE)

I The MCM68A364/MCM68B364 is, a mask-programmable byte-

organized memory designed for use in bus-organized systems. It is
fabricated with N-channel silicon-gate technology. For ease of use,
the device operates from a single power supply, has compatibility
8192 X 8-BIT
READ ONLY MEMORY

with TTL and DTL, and needs no clocks or refreshing because of

static operation.
The memory is compatible with the M6800 Microcomputer CSUFFIX
Family, providing read only storage in byte increments. The active FRIT-SEAL
level of the Chip Enable input and the memory content is defined PACKAGE

by the user. The Chip Enable input deselects the output and puts
the chip in a power-down mode.
• Fully Static Operation
• Automatic Power Down
• Low Power Dissipation - 150 mW active (typical)
P SUFFIX
30 mW standby(typical)
PLASTIC PACKAGE
• Single ± 10% 5-Volt Power Supply CASE 709
• High Output Drive Capability (2 TTL Loads)
• Three-State Data Output for OR-Ties
• Mask Programmable Chip Enable
PIN ASSIGNMENT
• TTL Compatible
• Maximum Access Time - 250 ns - MCM68B364
350 ns - MCM68A364
• Pin Compatible with 8K - MCM68A308, 16K - MCM68A316E, 24
and 321< - MCM68A332 Mask-Programmable ROMs 23
3 22
4 21
MOTOROLA'S PIN COMPATIBLE ROM FAMILY 20
(Industry Standard Pinouts)
19
18
8 17
2
16
3
10 15
4
11 14
5
24 12 13
6
23
22

9 20
10
19
11
PIN NAMES
18
12 AO-A12 . Address
17
E . Chip Enable
16
00-07 . Data Output
15 V CC . + 5 V Power Supply
14 VSS .. Ground
13

MC1V\68A308

This is advance information and specifications are subject to. change without notice_

2-154
MCM68A364/MCM68B364

AD 9 DO
Al 01
10
A2 11 02
A3 13 03
BLOCK A4 4 Address
Decode 14 04

II
DIAGRAM A5 15 05
A6 16 06
A7 17 07
A8 23
A9 22
Al0 19 -
All 18
A12 21

*"E 20 Vee = Pin 24

* Active level defined by the user. VSS = Pin 12

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operatin9 voltage and temperature range unless otherwise noted.)

RECOMMENDED DC OPERATING CONDITIONS

Parameter Symbol Min Nom Max Unit
Supply Voltage VCC 4.5 5.0 5.5 Vdc
(V CC must be appl ied at least 100 J.l.S before proper device
operation is achieved)
Input High Voltage VIH 2.0 - 5.5 Vdc
I nput Low Voltage VIL -0.3 - 0.8 Vdc

DC CHARACTERISTICS
Characteristic Symbol Min Typ Max Unit
Input Current lin - - 2.5 J.l.Adc
(Vin = 0 to 5.5 V)
Output High Voltage VOH 2.4 - - Vdc
(IOH = -205 J.l.A)
Output Low Voltage VOL - - 0.4 Vdc
(IOL = 3.2 mAl
Output Leakage Current (Three-State) ILO - - 10 J.l.Adc
(E = 2.0 V, V out = 0.4V to 2.4 V)
Supply Current - Active ICC - 30 60 mAdc
(VCC = 5.5 V, TA = OoC)
Supply Current - Standby ISB - 6.0 15 mAdc
(VCC = 5.5 V, TA = OoC, E = VIH)

CAPACIT ANCE
(f = 1.0 MHz, TA = 25 0 C, periodically sampled rather than 100% tested.)

Characteristic
Input Capacitance
Output Capacitance
This device contains circuitry to protect the inputs
ABSOLUTE MAXIMUM RATINGS (See Note 1) against damage due to high static voltages or electric
Rating Symbol Value Unit fields; however, it is advised that normal precautions
be taken to avoid application of any voltage higher
Supply Voltage VCC -0.3 to +7.0 Vdc
than maximum rated voltages to this high impedance
Input Voltage Vin -0.3 to +7.0 Vdc
circuit.
Operating Temperature Range - TA o to +70 °c
Storage Temperature Range T stg -65 to +150 °c
NOTE 1. Permanent device damage may occur if ABSOLUTE MAXIMUM
RATINGS are exceeded. Functional operation should be restricted
to RECOMMENDED OPERATING CONDITIONS. 'Exposure to higher
than recommended voltages for extended periods of time could affect
device reliability.

2-155
 MCM68A364/MCM68B364

AC OPERATING CONDITIONS AND CHARACTERISTICS

Read Cycle

RECOMMENDED AC OPERATING CONDITIONS

(T A; 0 to 70 0 C, VCC ; 5.0 V ± 10%. All timing with tr; tf ; 20 ns, load of Figure 1.)
MCM68B364 MCM68A364.
Parameter Symbol Min Max Min Max Unit
Address Valid to Address Don't Care tAVAX 250 - 350 - ns

I
(CyCle Time when Chip Enable is held Active)
Chip Enable Low to Chip Enable High tELEH 250 - 350 - ns
Address Valid to Output Valid (Access) tAVOV - 250 - 350 ns
Chip Enable Low to Output Valid (Access) tELOV - 250 - 350 ns
Address Valid to Ou'tput Invalid tAVOX 10 - 10 - ns
Chip Enable Low to Output Invalid tELOX 10 - 10 _. ns
Chip Enable High to Output High Z tEHOZ 0 70 0 80 ns
Chip Selection to Power Up Time tpu 0 - 0 - ns
Chip Deselection to Power Down Time tpD - 100 - 120 ns
Address Valid to Chip Enable Low (Address Setup) tAVEL 0 - 0 - ns

TIMING PARAMETER ABBREVIATIONS TIMING LIMITS

I II
t X X X X The table of timing values shows either a minimum or
,Ig'" n,m, "om which Int"", I, d,fln,d -.l a maximum limit for each parameter. Input requirements
transition direction for first signal are specified from the external system point of view.
signal name to which interval is defined Thus, address setup time is shown as a minimum since the
transition direction for second signal system must supply at least that mu'ch time (even though
most devices do not require it). On the other hand,
The transition definitions used in this data sheet are: responses from the memory are specified from the device
H = transition to high point of view. Thus, the access time is shown as a maxi·
L = transition to low mum since the device never provides data later than
V = transition to valid that time.
X = transition to invalid or don't care
Z = transition to off (high impedance)

FIGURE 1 - AC TEST LOAD

WAVEFORMS
Waveform Input Output 5.0 V
Symbol

MUST BE WILL BE
VALlO VALID
Test ,..Olnt
CHANGE WILL. CHANGE .... ,~ or Equiv
~ FROM H TO L FROM H TO L

CHANGE WILL CHANGE 130 pF';:r: 11.7 k ,~ MMD7000

JZZlZ7 FROM L TO H FROM L TO H
~ ~ or Equiv
OON·T CARE

*
CHANGING

~ ANY CHANGE
PERMITTED
STATE
UNKNOWN ~
I 'I ncludes Jig Capacitance

==>- HIGH
IMPEDANCE

2-156
MCM68A364/MCM68B364

CUSTOM PROGRAMMING

By the programming of a single photomask for the FIGURE 2 - BINARY TO HEXADECIMAL CONVERSION

rlr-
MCM68A364/MCM68B364, the customer may specify Binary Hexadecimal
Data Character
the content of the memory and the method of enabl ing '-- r----------

•
the outputs. a a a
0 a 1

Information on the general options of the

a a 2
a a 3
MCM68A364/MCM68B364 should be submitted on an a 1 a a 4
Organizational Data form such as that shown in Figure 3. 0 1 a 1 5
Information for custom memory content may be sent a 1 1 a 6
to Motorola in one of two forms (shown in order of a 1 1 1 7

preference) : 1 a 0 0 8
1 a a 1 9
1 a 1 a A

1. IBM Punch Cards 1 a 1 1 B

1 1 a a c
A. Hexadecimal Format
1 1 a 1 D
B. I NTE L Hexadecimal Format 1 1 1 a E
C. Binary Negative'Positive Format 1 1 1 1 F
2. EPROMs - four 16K (MCM2716, or TMS2716,
or eight 8K (MCM2708). IBM PUNCH CARDS, HEXADECIMAL FORMAT
The hexadecimal equivalent (from Figure 2) may
PAPER TAPE be placed on 80 column IBM punch cards as follows:
Included in the software packages developed for the Step Column
M6800 Microcomputer Family is the ability to produce 1 12 Byte "a .. Hexadecimal equivalent for
a paper tape output for computerized mask generation. outputs Q7 through Q4 (Q7 = M.S.B.)
The assembler directives are used to control allocation
2 13 Byte "0" Hexadecimal equivalent for
of memory, to assign values for stored data, and for outputs Q3 through QO (Q3 = M.S.B.)
controlling the assembly process. The paper tape must
3 14-75 Alternate steps 1 and 2 for consecutive
specify the full 8,192 bytes.
bytes
4 77-79 Card number (starting 001)
5 Total number of cards must equal 256
FIGURE 3 - FORMAT FOR PROGRAMMING GENERAL OPTIONS

ORGANIZATIONAL DATA
MCM68A364/MCM68B364 MOS READ ONLY MEMORY

Customer:
Motorola Use Only:
Company
Quote: __________________________
Part No.
Part No.: _______________________
Orig i nator _____________________________________

Specif. No.:
Phone No. ____________________________

Enable Options:

Active High Active Low

Chip Enable D D

2-157
 MCM68A364/MCM68B364

READ CYCLE TIMING 1

IEHeld Low)
~ .
tAvAX---------
.. ~------VIH
__
ADDRESS
-----...... ~---- VIL

tAV~;~----~~
---------~---~~~~I,-----------------VOH

I
o (Data out) Previous Data Valid Data Valid
--~-------------~~~~I~--------------------VOL

READ CYCLE TIMING 2

X
.=j
Xl\.lIl
~ tAVEL

ADDRESS Address Valid

XXXX)U\~

tELEH
E

~:~~
tELOV -tEHOZi
I--tELox--l VOH
r
o (Data out) - - - - - - - - - - - HI Z

::O,C," :~~ _____ ~ _ :"- t=

~ Data Valid

~.II..I...L.I....L.:~-----------~-----tP-D.J
HI Z- VOL

Current

M6800 MICROCOMPUTER FAMILY

BLOCK DIAGRAM READ ONLY MEMORY
1 Microprocessor
MC6S00 ·1 BLOCK DIAGRAM
MCM68A364
MCM68B364
~ ;-----
Read Only
Memory
Memory

I Random
Matrix
(8192 X 8)
r---- Data
Buffer
~DataBus

I Access
I Memory
'-----
I
I
I
Interface
Adapter t
Salection
I and Control
Interface

• •
I
I
Adapter
Modem
I f
Address Data Mamory Address
Bus Bus and Control

2-158
MCM68A364/MCM68B364

PRE-PROGRAMMED MCM68A364P3/C3, MCM688364P3/C3

The -3 standard ROM pattern contains log (base 10) and antilog (base 10) lookup tables for the 64K ROM.

Locations 0000 through 3599 contain log base 10 values. The arguments for the log table range from 1.00 through
9.99 incrementing in steps of 1/100. Each log value is represented by an eight· digit decimal number with decimal point
II
assumed to be to the left of the most-significant digit.

Antilog (base 10) are stored ,in locations 4096 through 8095. The arguments range from .000 through .999 increment-
ing in steps of 1/1000. Each antilog value is represented by an eight· digit decimal number with decima! point assumed to
be to the right of the most·significant digit.

Locations 3600 through 4095 and 8096 through 8191 are zero filled.

All values are represented in absolute decimal format with eight digit precision. They are stored in BCD format with
the two most significant digits in the lower byte and the remaining six digits in the three consequitive locations.

Example: log10 (1.01) =.00432137 decimal

Address Contents
4 0000 0000
6 0100 0011
6 0010 0001
7 0011 0111

2-159
 \

2-160
 CMOS Memories
RAM, ROM
•

3-1
I

3-2
 ® MOTOROLA MCM14505

CMOS LSI
64-BIT STATIC RANDOM ACCESS MEMORY
(LOW-POWER COMPLEMENTARY MOS)

The MCM14505 64-bit random access memory is fully decoded

64-BIT (64 X 1) STATIC
on the_ chip and organized as 64 one-bit words (64 X 1). Medium
speed operation and micropower supply requirements make this RANDOM ACCESS MEMORY
device useful for scratch p,ad or buffer memory applications where
power must be conserved or where battery operation is required.
When used with a battery backup, the MCM 14505 can be util ized
as an alterable read-only memory, allowing the battery to retain in-
formation in the memory when the system is powered down, and
allowing the battery to charge wh~n power is applied. The micro-
power requirements of this memory allow qu iescent battery operation
for great lengths of time without significant discharging.

•
•
= 50 nA/package typical @ 5 Vdc
Quiescent Current
= 45% of VDD typical
Noise Immunity
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Single Read/Write Control Line
L SUFFIX
CERAMIC PACKAGE
CASE 632
P SUFFIX
PLASTIC PACKAGE
CASE 646
II
ORDERING INFORMATION
• Wired-OR Output Capability (3-State Output) for Memory
Expansion
MC14XXXB ~SUffIX Denotes
= 180 ns typical at VDD = 10 Vdc
• Access Time
T- pLCeramic Package
• Write Cycle Time = 275 ns typical at VDD = 10 Vdc L PlastiC Package
A Extended Operating
• Fully Buffered Low Capacitance Inputs Temperature Range
• Capable of Driving Two Low-power TTL Loads, One Low-power C Limited Operating
Temperature Range
Schottky TTL Load or Two HTL Loads Over the Rated Temper-
ature Range

MAXIMUM RATINGS (Voltages referenced to Vss)

BLOCK DIAGRAM
Rating Symbol Value Unit
DC Supply Voltage VDD -0,5 to +18 Vdc

l:~ ~
Input Voltage, All Inputs Yin -0.5 to VDD + 0.5 Vdc
DC Current Drain per Pin I 10 mAdc
Operating Temperature Range - AL Device -55 to +125 °c Address
TA Inputs A3 4 10 Data Out
CLlCP Device -40 to +85
A411
Storage Temperature Range T stg -65 to +150 °c A512'

a
Data In 13

This device contai"s circuitry to protect the inputs against damage due to high Strobe 5
static voltages or electric fields; however, it is advised that normal precautions be CE16
Control
taken to avoid application of any voltage higher than maximum rated voltages to CE28
this high impedance circuit. For proper operation it is recommended that Yin and R/W 9
V out be constrained to the range VSS';; (Vin or V out )';; VDD.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., VDD ~ Pin 14
either VSS or VDD)· VSS = Pin 7

3-3
 MCM14505

ELECTRICAL CHARACTERISTICS
voo Tlow * 25°C Thigh *
Characteristic Symbol Vdc Min Max Min Typ Max Min Max Unit
Output Voltage "0" Level VOL 5.0 0.05 0 0.05 0.05 Vdc
Vin VDO or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
"1" Level VOH 5.0 4.95 4.95, 5.0 4.95 Vdc
Vin o or VDD 10 9.95 9.95 10 9.95
15 14.95 . 14.95 15 14.95
NOise Immunity t± VNL Vdc
(.'V out "" 0.8 Vdc) 5.0 1.5 1.5 2.25 1.4
(.,v out';; 1.0 Vdc) 10 3.0 3.0 4.50 2.9
(AV out .;; 1.5 Vdc) 15 4.5 4.5 6.75 4.4
(,\V out ';; 0.8 Vdc) VNH 5.0 1.4 1.5 2.25 1.5 Vdc
(. V out .;; 1.0 Vdc) 10 2.9 3.0 4.50 3.0
(,W out ,:; 1.5 Vdc) 15 4.4 4.5 6.75 4.5
Output Drive Current (AL Device) IOH mAdc
(VOH ~ 2.5 Vdc) Source 5.0 -1.2 -1.0 -1.7 -0.7
(VOH ~ 4.6 Vdc) 50 -0.25 -0.2 -0.36 -0.14
(VOH = 9.5 Vdc) 10 -0.62 -Gl.5 -0.9 -0.35
(VOH = 13.5 Vdc) 15 -1.8 -1.5 -3.5 -1.1

•
(VOL = 0.4 Vdc) Sink IOL 5.0 0.3 0.25 0.35 '0.18 mAdc
(VOL = 0.5 Vdc) 10 0.9 0.75 1.2 0.50
(VOL = 1.5 Vdc) 15 2.2 1.7 4.5 1.2
Output Drive Current (CLlCP Device) IOH mAdc
(VOH ~ 2.5 Vdc) Source 5.0 -1.0 ·0.8 -1.7 -0.6
(VOH = 4.6 Vdc) 5.0 -0.2 -0.16 -0.36 -0.12
(VOH = 9.5 Vdc) 10 -0.5 -0.4 -0.9 -0.3
(VOH = 13.5 Vdc) 15 -1.4 -1.2 -3.5 -1.0
(VOL = 0.4 Vdc) Sink IOL 5.0 0.2 0.15 0.35 0.1 mAdc
(VOL = 0.5 Vdc) 10 0.6 0.5 1.2 0.4
(VOL = 1.5 Vdc) 15 3.9 0.75 4.5 0.6
Input Current (AL Device) I in 15 ± 0.1 to 00001 ± 0.1 ± 1.0 !lAdc
Input Current (CLlCP Device) I in 15 ± 1.0 ±0.00001 ± 1.0 ± 14 !lAdc
Input Capacitance Cin 5.0 7.5 pF
(Vin 0)
Quiescent Current (AL Device) 100 5.0 5.0 0.050 5.0 150 !lAdc
(Per Package) 10 10 0.100 10 300
. 15 20 0.150 20 600
Quiescent Current (CLlCP DeVice) 100 5.0 50 0.050 50 375 !lAdc
(Per Package) 10 100 0.100 100 750
15 200 0.150 200 - 1500
Total Supply Current' ."t IT 5.0 IT -(1.28 /JA/kHz) f + 100 !lAdc
(Dynamic plus Quiescent, 10 IT = (2.56 !lA/kHz) f + 100
Per Package) 15 IT = (3.85 !lA/kHz) f + 100
(CL - 50 pF on all outputs, all
buffers switching)
Three·State Leakage Current ITL 15 ± 0.1 -0.00001 ± 0.1 ±3.0 ilAdc
(AL Device)
Three·State Leakage Current ITL 15 ±1.0 -0.00001 ± 1.0 ± 7.5 !lAdc
Ir IrD n,

"Tlow = -55 0 C for AL Device, -40 oC for CLlCP Device.

Thigh = +125 0 C for AL Device, +85 0 C for CL/CP Device.
#Noise immunity sPl'lcified for worst-case input combination.
fTo calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + 1 x 10-3 (CL -50) VDDf
where: IT is in!lA (per package), CL in pF, VDD in Vdc, and f in kHz is input frequency.
""The formulas given are for the typical characteristics only at 25°C.

3-4
MCM14505

SWITCHING CHARACTERISTlCS* (CL = 50 pF T A = 25 0 C)

---------
Characteristic Symbol VOO Min Typ Max Unit
Output Rise Time tTLH ns
tTLH = (2.43 ns/pF) CL + 58.5 ns 5.0 - 180 360
tTLH = (1.08 ns/pF) CL + 36 ns 10 - 90 180
tTLH = (0.72 ns/pF) CL + 39 ns 15 - 75 150
Output Fall Time tTHL ns
tTHL = (2.16 ns/pF) CL + 52 ns 5.0 - 160 320
tTHL = (0.96 ns/pF) CL + 32 ns 10 - 80 160
tTHL = (0.69 ns/pF) CL + 33 ns 15 - 65 130
Propagation Delay Time tacc(R) ns
Read Access Time
tacc(R) = (1.4 ns/pF) CL +385 ns 5.0 - 455 750
tacc(R) = (10.7 ns/pF) CL + 175 ns 10 - 210 400
tacc(R) = (0.5 ns/pF) CL + 105 ns 15 - 130 300
Strobe Down Time tWL ns
5.0 500 100 -
10 125 50 -
15 95 75 -
Address Setup Time tsu ns
5.0 300 -100 -
10 120 -40 -
15 90 -25 -
Data Setup Time tsu(D) ns

II
5.0 200 70 -
10 75 25 -
15 55 20 -
Read Setup Time tsu(R) ns
5.0 270 90 -
10 60 20 -
15 45 15 -
Write Setup Time tsu(W) ns
5.0 400 80 -
10 100 25 -
15 75 11 -
Address Release Time trel(R) ns
5.0 75 15 -
10 25 10 -
15 20 5.0 -
Data Hold Time th(D) ns
5.0 50 0 -
10 15 0 -
,.
15 10 0 -
Read Release Time trel(R) ns
5.0 0 -90 -
10 0 -25 -
15 0 -10 -
Write Release Time trel(W) ns
5.0 0 5.0 -
10 0 10 -
15 0 30 -
Read Cycle-Time tcyc(R) ns
5.0 - 500 750
10 - 200 400
15 - 150 300
Write Cycle Time tcyc(W) n$
5.0 - 440 700
10 - 275 550
15 - 200 415
Output Disable Delay tdis ns
(10% Output Change into 1.0 kfl Load) 5.0 - 200 600
10 - 80 200
15 - 60 150
The formula IS for the typical charactenstlcs only.

3-5
 MCM14505

FIGURE 1 - READ CYCLE TIMING DIAGRAM

Address

Strobe

tWHmin ; tcyc(R) max tWLmin

tsu(R)

Note: The read/write input can be maintained at a logical "1"

(high voltage) during a read cycle.

; . - - - - k - - - - - - - - - VOH
Data Output -O-u-t-p-ut-.....
Disabled ~-~-+---~-------~--VOL

FIGURE 2 - WRITE CYCLE TIMING DIAGRAM

• Address

Strobe

Read/Write -------...
tWHmin = tcyc(W) max -tWL min

Note: The read/write input can be maintained at a logic "0"

(low voltage) during a write cycle. If the read/write
input is maintained at a logic "0" while the strobe is
a logic "1", then the output data will be disabled (high
impedance) during the write cycle.

Dataln __________ t_sU_(~DI f---i--l.' '_h_(D_)____________

50%~

FIGURE 3 - MAXIMUM STROBE PULSE WIDTH FIGURE 4 - TYPICAL READ ACCESS TIME
versus TEMPERATURE versus LOAD CAPACITANCE
100 800
TA =25°C

- -
~
::t:
t; 10 .........
Voo - 5.0 Vdc ! 600
::E
f-- :...--

--
~ i=
w
......
~ f-- ~ - Voo =5.0 Vdc
CI)
.........
...J
:::J
c.. .n
..,.., 10 Vdc ~ I
w
'"a: ~

-
0
~.
t;; 10 Vdc
x ""t-- 15 Vdc
r-...
« eo. 200
::E 0.1 r--
% ~ 15 Vdc
~
0.01 0
-60 -20 20 60 100 140 20 40 60 80 100

TA,AMBIENT TEMPERATURE (OC) CL, LOAD CAPACITANCE (pF)

3-6
MCM14505

FIGURE 5 - TYPICAL OUTPUT SOURCE FIGURE 6 - TYPICAL OUTPUT SINK

CAPABILITY versus TEMPERATURE CAPABILITY versus TEMPERATURE

voo-
Vlnput
0-- lClS --
. '. ,

--l ~300 ns
1.0 kHz

Notes' Voo
1. Cycle R/W to ground and then to VOO
prior to measurement to insure turn-
on of the device under test.
VOS = VOL
2. For the P·channel characteristics,

•
AO VOS = VO H - VOO'
AO
Al 3. For the N·channel characteristics, Al
A2
DO ut t-<J---+--+---{) VOS is measured directly. D out
A2
A3
100
4. For the drain current, 10 = ~ Amp A3
100
A4 100 A4
1''0 1%
A5 A5
' - - f - - o - - j 0 in Din
.--+---0-- C E 1 R/W CEl
L--I-o-- C E2 R/W
CE2
Vin o-----+--C~ Strobe Strobe

External External
Power VSS Power
Supply Supply

10
L !.
~ a
la) TA = -55 0 C
Ib) TA = +25 0 C
I :~e
lL VDD - 15 Vde .-!..

~~ W
~ "....- lk"
Ie) TA = +125 0 C VOOI = 5.0 Vde .: r- ~
.5 .kr--......... a

.L L L V ....
0
i!-20
V.." V'~'/
./
I-
Z

G -4.0

=>
~ -6.0 10
l-
=> Vde
b-
e~
- ---..---v. ./
_V

~ ~VdV
./
~~ LL
?' / /
V' /
/
c:
=>

'"z
Ui

~
6.0

40
I // ./
II h / /' /
IL /L
I V~ ....- -
b

e
I
10
Vde

;....----'" .........-; ~ / 1/1'/ ,./ la) TA =-55°C

-
l-
=>
~ -8.0 ~ 2.0 Ib)T A =+25 0 C-
l..-'~t:: I---
~ bjV V //~ V .at
b 5.0 Vde
le)TA =+125 0 C

-10 .... V Va o~ e I
-10 -8.0 -6.0 -4.0 -2.0 o 2.0 4.0 6.0 8.0 10

VOS,DRAIN VOLTAGE IVdc) VOS, DRAIN VOLTAGE IVdc)

3-7
 MCM14505

FIGURE 7 - FUNCTIONAL CI RCUIT DIAGRAM

iD-~)O-------..-y-t-----.--1y-+----I_y--+------'y

Data In 0-+--+-----1 Write Selection Drivers J

1a 1b 2a 2b 3a 3b 4a 4b
r-- 1 r --1--- -- r----- -- -- ""1 ---

AO (}-+--+-----1 f--<: '"

u ~A4
~
a

•
A 1 0---+--+-----1 >-f---c
A 2 0---+--+-----1
~
~-
f--< u
0

ll)

<t
A 30---+--+-----1 -:- --4)A5
<t

-~-

----
Basic Memory Celi

~ i
_ _ _ _YT....J K:,~
:I ...J~~_~
....J-~
Data Out
(3 State)

I ~
L
.J I~

-=- VSS

3-8
MCM14505

OPERATING CHARACTERISTICS

In considering the operation of the MCM14505 CMOS memory, row is in the low state, and the unselected 15 rows retain their
refer to the functional circuit diagram of Figure 7 and timing logic "1" level due to the row capacitance that exists when the row
diagrams shown in Figures 1 and 2. The basic memory cell is a decoder inhibit gates are disabled. This capacitive storage mecha-
cross·coupled flip-flop consisting of two inverter gates and two nism requires a maximum strobe width (see Figure 3) equal to the
P-channel devices for read/write control. The push-pull cell provides junction reverse bias RC time constant. When the strobe is returned
high speed as well as low power. to a logic "0" the rows are forced to VDO by the row decoder
Ouring a read cycle, when the strobe line is high the write inhibit gates (pullup devices). Similarly the column read/write
selection drivers are disabled and the data from the selected row is inhibit gates (pulldown devices) force the column lines to a logic
available on columns lb, 2b, 3b, and 4b. The A4 and A5 address "0" state.
bits are decoded to select output data from one of the four columns. Two column lines are associated with each memory cell in order
The output data is available on the data output pin only when the to write into the cell. The write selection drivers are enabled when
strobe and read/write lines are high simultaneously and after the the R/W line is a logic "0" and the strobe line is a logic "1 ". The
read access time, tacc( R), has occurred (see Figure 1). Note that input data is written into the column selected by the column
the output is initially disabled and always goes to the logic "0" state decoder. For instance, if a "1" is to be written in the memory cell
(low voltage) before data is valid. The output is in the high- associated with row 1 and column 1, then row 1 would be enabled
impedance state (disabled) when the strobe line or the R /W line is (logic "0") while column lb is forced high and column la is forced
in the low state. The memory is strobed for reading or writing only low by the write selection drivers. If a logic "0" is to be written
when the strobe, CE 1, and CE2 are high simultaneously. The R/W into the cell, then column la is forced high and lb is forced low.
line can be a dc voltage during a read or write cycle and need not The data that is retained in the memory cell is the data that was
be pulsed, as shown in the timing diagrams. For this case the R/W present on the data input pin at the moment the strobe goes low
line should be a logic "1" (high) for reading and a logic "0" for when R/W is low, or when R/W goes high when the strobe is high.
writing.

•
When the strobe line is high, the column read/write inhibit
gates and the row decoder inhibit gates are disabled, the selected

APPLICATIONS INFORMATION

Figure8showsa 256-word by n-bit static RAM memory system Figures 11, 12, and 13 show methods of interfacing the
The outputs of four MCM14505 devices are tied together to form memory output to TTL logic at various memory voltages. If a
256 words by 1 bit. Additional bits are attained by paralleling the VOO of 5.0 volts is used for slow-speed, low-power applications,
inputs in groups of four. Memories of larger words can be attained one transistor and one resistor must be used (Figure 11). The
by decoding the most significant bits of the address and ANDing MCM14505AL will drive one low-power TTL gate directly.
them with the strobe input. If a VOO of 10 volts is used, the output of the memory device
Fan-in and fan-Qut of the memory is limited only by speed can fan out to two low-power TTL gates (F igure 12a) or to a
requirements. The extremely low input and output leakage current discrete transistor (Figure 12b). The discrete transistor circuit
(100 nA maximum) keep the output voltage levels from changing provides higher speed and/or high fan-Qut. A pulldown resistor
significantly as more outputs are tied together. With the output at the base of the transistor is not needed for fast turn-Qff because
levels independent of fan-Qut, most of the power supply range is of the push-pull output of the memory. Turn-Qn time of the
available as logic swing, regardless of the number of units wired transistor is much faster in Figure 12b since the voltage rise is only
together. As a result, high noise immunity is maintained under 0.75 volt. The low output capacitance of the MCM14505 means
all conditions. that several outputs can be wire-ORed without significantly de-
Power dissipation is 0.1 Il-W per bit at a 1.0-kHz rate for a grading performance. The read access time is increased by only
5.0-volt power supply, while the static power dissipation is 2.0 nW 20 ns typically for 16 outputs tied together when Figure 12b
per bit. This low power allows non-volatile information storage is used.
when the memory is powered by a small standby battery. Five low-power TT L gates can be driven from the memory
Figure 9 shows an optional standby power supply circuit for output if a VOO of 15 volts is used (Figure 13a). Figure 13b
making a CMOS memory "non-volatile". When the usual power shows the interface if a discrete transistor is used. The 1.0 kilohm
fails, a battery is used to sustain operation or maintain stored resistor in the base is required to insure that not more than 10 mA
information. While normal power supply voltage is present, the flows through the output as listed in the maximum ratings. If a
battery is trickle-charged through a resistor which sets the charging 2.0 kilohm collector resistor is used (fan-Qut : 3), the turn-Qn
rate. VB is the sustaining voltage, and V+ is the ordinary voltage time of the transistor is only slightly faster than in the circuit
from a power supply. VOO connects to the power pin on the shown in Figure 12b due to the lower output impedance when
memory. Low-leakage diodes are recommended to conserve VOO : 15 volts. The voltage at the memory data output has to
battery power. rise to only 1.3 volts to insure driving a fan-Qut of three TTLdevices.
The memory system shown in Figure 8 can be interfaced If a 510-Qhm collector resistor is used, 20 TTL loads may be
directly with the other devices in the McMOS family. No external driven. The read access time is increased about 20 ns when four
components are required. memory outputs are tied together since the output voltage must
At the inputs to the CMOS memory, TTL devices can interface rise to 3.7 volts before the transistor can sink the full 10 L for a
directly if an open-collector logic gate such as the MC7407 is used fan-Qut of 20 TTL devices. Almost any NPN transistor with a
as shown in Figure 10. Oriver circuits are not required since the minimum beta of 15 can be used for the interface shown in
input capacitance is low (4.0 to 6.0 pF). The address, data, and Figures 11, 12and 13.
read/write inputs do not need to be fast since they can be changed The high source current from the push-pull output stage of the
for the duration when the strobe pulse is low, tSTL (see Figures 1 MCM14505 makes for a simpler interface circuit since a low source
and 2). For high-speed operation, a push-pull driver should be used current memory requires a differential comparator to achieve high-
if more than five strobe inputs must be driven at one time. One speed operation.
circuit of the type shown in Figure 10 can be used for every ten
strobe inputs.

3-9
 MCM14505

FIGURE 8 - CMOS 256-WORD BY n-BIT STATIC

READ/WRITE MEMORY

A 1
B 2
C 3
Address DO 4
Lines E 11 MCM14505
F 12 64-Bit 10f--
G 6 Ram
H 8
,---5
,-9
r - 13
1

lrL>
'--- G
2
3

V H 4
11 MCM14505

•
12 64-Bit 10 f--<
6 Ram
-~

-
8
5
t--- 9
Data In
-. 13
~BOOut
1
2
3
4
11 MCM14505
12 64·Bit 10f--
6 Ram
8
Dynamic
5
StrObJL.
~ r-- 9
~ 13

1
2
3
4
11 MCM14505
64-Bit
12 10 f--
Ram
6,
8
5
Read/Write 9
'--- 13

III I111111 I I
I I I II I II I I I I
1111111111 I I
I " I I I II I I I I
Expand Vertically For n·Bit.

Circuit diagrams utilizing Motorola products are included as a means IS believed to be entirely reliable However, no responsibility is
of illustrating typical semiconductor applications; consequently, assumed for inaccuracies. Furthermore, such information does not
cOMplete information suffic.ient for construction purposes is not convey to the purchaser of the semiconductor devices described any
necessarily given. The information has been carefully checked and license under the patent rights of Motorola Inc. or others.

3-10
MCM14505

FIGURE 9 - STAND BY FIGURE 11 - CMOS-TO-TTL INTERFACE

BATTERY CIRCUIT FIGURE 10 - TTL TO CMOS INTERFACE FOR VDD = 5_0 V

V+
(

V DD = 5.0 V VCC
."
-I-

~
70
2.0 k
.---~~------OVDD

R ::. TO TTL
o TO (F.O. = 1)
CMOS
2N3904
or Equiv
1/6 MC7407

1- Note: The MCM14505AL will drive one

low power TTL gate directly.

FIGURE 12 - CMOS-TO-TTlINTERFACE
FOR VDD= 10V

a. Using a low-Power TTL Gate b. Using Discrete Devices

VOD = 10 V
VDD = 10 V VCC

Germanium
Diode

TO TTL
(F.O.=20)
MCM14505 MCM14505
To TTL
D out
(F.O. = 1)

TTL
Input

FIGURE 13 - CMOS-TO-TTl INTERFACE

FOR Vee = 15V

a. Using low-Power TTL Gates b. Using Discrete Devices

VDD = 15 V VDD = 15 V
Germanium
Diode

- - - - - - . To TT L

D out Dout
2N3904
MCM14505 To TTL MCM14505
or Equiv
1.0 k

Low-Power TTL (Maximum = 5)

'2.0 kilohms for F.O. = 3
'510 ohms for F.O. = 20

3-11
 ® MOTOROI.A MCM14537

256·BIT STATIC RANDOM ACCESS MEMORY CMOS LSI

The· MCM 14537 is a static random access memory (R AM) organ- (LOW-POWER COMPLEMENTARY MOS) ,
ized in a 256 x 1-bit pattern and constructed with MOS P-channel
and N-channel enhancement mode devices in a single monolithic
structure. The circuit consists of eight address inputs (An!. one data 256-BIT (256 x 1) STATIC
input (Dlnl. one write enable input (WE), one strobe input (ST), two
RANDOM ACCESS MEMORY
chip enable inputs (CE n ). and one data output (Dout).
Using both chip enable inputs as extensions of the address inputs.
a 10-bit address scheme may be employed. Four MCM14537 devices
may be used to comprise a 1024-bit memory without additional

,,~
address decoding. The CE and ST inputs are dissimilary designed to
enable usage of the memory in a variety of applications. An output
latch is provided on the chip for storing the data read or written into
memory. making a data-out storage register unnecessary. The CE
inputs control the data output for third-state (high output imped-

•
arice) or active operation which makes the memory very useful in a
1
bus oriented system. When CE2 is high the chip is fully disabled.
When CE 1 is high the output is in the third state but da.ta can be CERAMIC PACKAGE
CASE 690
written into the output latch during a read cycle. This enables the
use of the memory for fast reading by using the CE 1 input to enable
ORDERING INFORMATION
the latch. The memory is also designed so that dc signals can operate
the memory with no maximum pulse width required on the CE and Suff,x Denotes
MCM14XXX

~
ST lines.
Medium speed operation and micropower operation make the L CeramIc Package
device useful in scratch pad and buffer applications where micro-
Extended Operatong
power or battery operation and high noise immunity are required. Temperature Range
• Quiescent Current = 0.5 ,uA/package typical @ 5 Vdc : LImIted Operating
Temperature Range
• ~oise Immunity = 45% of VDD typical
• 3-state Output Capability for Memory Expansion
• Output Data Latch Eliminates Need for Storage Buffer PIN ASSIGNMENT

• Access Time = 700 ns typical @ VDD = 10 Vdc

• Fully Decoded and Buffered Al 16
VD D
• Supply Voltage Range = 3.0 Vdc to 18 Vdc A2 AO 15

• Capable of Driving Two Low-power TTL Loads, One Low-power Din A7 14

Schottky TTL Load or Two HTL Loads Over the Rated Temper· 4 WE CEl 13
ature Range A3 CE2 12
6 A4 ST 11
7~ A5 D out r----' 10
8 c=: VSS A6 p9
~ ~
,..
n .. '''U~ .~~
.,,"
Rating Symbol Value Unit This device contains circuitry to protect
the inputs against damage due to high static
DC Supply Voltage VDD -0,5 to +18 Vdc voltages or electric fields; however, it. is
Input Voltage, AII,lnputs Vin -0,5 to VDD + 0,5 Vdc advised that normal precautions be taken
DC Current Drain per Pin 10 mAdc to avoid application of any voltage higher
than maximum rated voltages to this h.igh
Operating Temperature Range - AL Device TA -55 to +125 °c impedance circuit. For proper operation it
CL/CP Device -40 to +85 is recommended that Yin and V out be
Storage Temperature Range T stg -65 to +150 °c constrained to the range VSS .;; (Vin or
V out ) .;; VDD'
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either
VSS or VDD)'

3-12
MCM14537

ELECTRICAL CHARACTERISTICS
vee Tlow
. 2SoC Thigh·
Characteristic Symbol Vdc Min Max Min Typ Max Min Max Unit
Ou tpu t Vol tage "0" level Val 5.0 0.05 0 0.05 0.05 Vdc
Vin VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0 0.05 0.05
"1" level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Vin o or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
Noise Immunity *" VNl Vdc
(.·V out '. 0.8 Vdc) 5.0 1.5 1.5 2.25 1.4
(:,V out ,,; 1.0 Vdc) 10 3.0 3.0 4.50 2.9
(\V out " 1.5 Vdc) 15 4.5 4.5 6.75 4.4
(W out '" 0.8 Vdc) VNH 5.0 1.4 1.5 2.25 1.5 Vdc
( V out "; 1.0Vdc) 10 2.9 3.0 4.50 3.0
( W out " 1.5 Vdc) 15 4.4 4.5 6.75 4.5
Output Drive Current (Al Device) IOH mAde
(VOH = 2.5 Vdc) Source 5.0 -1.2 .. 1.0 -1.7 -0.7
(VOH = 4.6 Vdc) 5.0 -0.25 -0.2 -0.36 -0.14
(VOH = 9.5 Vdc) 10 -0.62 -0.5 -0.9 -0.35
(VOH = 13.5 Vdc) 15 -1.8 -1.5 -3.5 -1.1
(Val = 0.4 Vdc) Sink IOl 5.0 0.64 0.51 0.88 0.36 mAdc
(Val = 0.5 Vdc) 10 1.6 1.3 2.25 0.9

•
(Val = 1.5 Vdc) 15 4.2 3.4 8.8 2.4
Output Drive Current (CLlCP Device) IOH mAdc
(VOH = 2.5 Vdc) Source 5.0 -1.0 -0.8 -1.7 -0.6
(VOH ~ 4.6 Vdc) 5.0 -0.2 -0.16 -0.36 -0.12
(VOH = 9.5 Vdc) 10 -0.5 -0.4 -0.9 -0.3
(VOH = 13.5 Vdc) 15 -1.4 -1.2 -3.5 -1.0
(Val = 0.4 Vdc) Sink IOl 5.0 0.52 0.44 0.88 0.36 mAdc
(Val = 0.5 Vdc) 10 1.3 1.1 2.25 0.9
(Val = 1.5 Vdc) 15 3.6 3.0 8.8 2.4
Input Current (Al Device) lin 15 ± 0.1 ±0.00001 ± 0.1 ± 1.0 !-IAdc
Input Current (CLlCP Device) lin 15 ±1.0 ±0.00001 ±1.0 ±14 !-IAdc
Input Capacitance Cin 5.0 7.5 pF
(Vin = 0)
Quiescent Current (Al Device) 100 5.0 100 0.5 100 1800 !-IAdc
(Per Package) 10 200 1.0 200 3600
15 400 1.5 400 7200
QUiescent Current (CLlCP DeVice) 100 5.0 100 0.5 100 1800 !-IAdc
(Per Package) 10 200 1.0 200 3600
15 400 1.5 400 7200
Total Supply Current' ' l IT 5.0 IT = (1.46!-1A/~Hz)' + 100 !-IAdc
(Dynamic plus Quiescent. 10 IT = (2.91 !-lA/kHz) ,+ I DO
Per Package) 15 IT = (4.37 !-lA/kHz) ,+ 100
(Cl - 50 pF on all outputs, all
buffers switching)
Three·State leakage Current ITl 15 ± 0.1 '0.00001 ± 0.1 ±3.0 !-IAdc
(Al Device)
Three·State leakage Current ITl 15 ±1.0 '0.00001 ± 1.0 ± 7.5 !-IAdc
(CLlCP Device)

'Tlow = -55°C for Al Device, -40°C for cL/CP Device.

Thigh = +125 0 C for Al Device, +85 0 C for CLlCP Device .
... Noise immunity spet:ified for worst·case input combination.
Noise Margin for both "1" and "0" level = 1.0 Vdc min @ VDO = 5.0 Vdc
2.0 Vdc min @ VOO = 10 Vdc
2.5 Vdc min @ VOO = 15 Vdc
tTo calculate total supply current at loads other than 50 pF:
IT(Cl) = IT(50 pF) + 1 x 10- 3 (CL -50) VDe'
where: IT is in !-I A (per package), CL in pF, Voe in Vdc, and' in kHz is input frequency .
• 'The formulas given are for the typical characteristics only at 25°C.

3-13
 MCM14537

SWITCHING CHARACTERISTICS· (CL = 50 pF T A = 25 0 C)

Characteristic Figure Symbol VOO Min Typ Max Unit
Output Rise Time 3 tTLH ns
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 - 180 360
tTLH = (1.5 ns/pF) CL + 15 ns 1.0' - 90 180
tyLH = (1.1 ns/pF) CL + 10 ns 15 - 65 130
Output Fall Time 3 tTHL ns
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 - 100 200
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 - 50 100
tTHL = (0.55 ns/pF) CL + 9.5 ns 15 - 40 80
Read Access Time from ST or CE2 4,5 tacc(R) ns
tacc = (1.4 ns/pF) CL + 2480 ns 5.0 400 2500 6000
tacc = (0.7 ns/pF) CL + 690 ns 10 150 700 2000
ta.oc = (0.5 ns/pF) CL + 393 ns 15 115 400 1500
Output Enable Delay from CEl or CE2 5,6 tacc(CE n ) 5,.0 70 300 900 ns
lQ 25 100 300
15 20 70 225
Setup Time from An to ST or CE2 4,5,6,7 tsu(A) 5.0 1800 600 - ns
10 600 200 -
15 450 140 -
Hold Time from An to ST or CE2 4,5,6,7 th(A) 5.0 600 200 - ns
10 240 80 -
15 180 55 -
--

•
Data Hold Time 7 th(D) 5.0 1400 480 - ns
10 500 160 -
15 375 110 -
Data Setup Time 7 tsu(D) 5.0 3600 1200 - ns
10 1800 600 -
15 1350 420 -
Write Enable Hold Time 7 th(WE) 5.0 150 50 ns
10 60 20 -
15 45 15 -
Write Enable Setup Time 7 ' tsu(WE) 5.0 720 240 - ns
10 240 80 -
--~,
15 180 55 -
Write Enable to D out Disable** 4 tVifE 5.0 720 240 - ns
I
10 240 80 -
15 180 55 -
Strobe or CE2 Pulse Width When Reading 4,5,6 tWL(R) 5.0 1350 450 - ns
10 450 150 -
15 340 100 -
'-~
Strobe, CEl or CE2 Pulse Width When Writing 7 tWL(W) 5.0 2400 1200 - ns
10 1260 600 -
15 945 420 -
Write Recovery Time 4 tR(W) ns
tw = (1.4 ns/pF)CL + 219 ns 5.0 70 240 720
tw = (0.7 ns/pF) CL + 70 ns 10 25 80 240
tw = (0.5 ns/pF) CL + 47.5 ns 15 20 55 180
CEl or CE2 to Dout Disable Delay** 6 tCEn 5.0 70 300 900 ns
10 25 100 300
15 20 70 225
Read Setup Time 4,5 tsu(R) 5.0 0 -100 - ns
10 0 -40 -
15 0 30
Read Hold Time 4,5 th(R) 5.0 540 180 - ns
10 240 60 -
15 180 45 -
Read Cycle Time \ 4,5 tcyc(R) 5.0 - 2500 6000 ns
10 - 700 2100
15 - 500 1575
Write Cycle Time 7 tcyc(W) 5.0 - 1400 4800 ns
10 -' 700 2100
15 - 500 1575
** The formula giveni~ for the typical characteristics only.
10% output change Into a, 1.0 k.rl. load.

3-14
MCM14537

FIGURE 1 - TYPICAL OUTPUT SOURCE AND SINK CURRENT CHARACTERISTICS TEST CIRCUIT

<fVoo
T
~
AO

~ Al
A2
A3
f"'o.
A4

$
Output Source Output Sink

I '"'-
~
A5 Input Characteristics Characteristics
Generator
(Single Pulse)
A6
A7
°out
~ ~VO". WE Pulse Once Pulse Once
Din SWl in Position 1 SWl in Position 2
ST 10
VGS -VOO VOO
WE
VOS Vout-VOO V out
f"'o.
CEl External
VOO 01
Power

I I
CE2
SWl Supply
~ Din

VSS 02
~ VSS

FIGURE 2 - POWER DISSIPATION TEST CIRCUIT AND WAVEFORMS

fl
500J,LF

AD
Al
A2
A3
A4
Pulse
Generator
1

Pulse
(AO)

(ST)
Generator _ _
2
I
/
':::..:...J

r-\.
L-.J
r-\.
\"--'- -
"--
•
A5
A6 °out
1-_<>-~~-o0utPut (Oout) - - - - - -.....\"--_ _ _ _ _ _ _ _ 1
A7
f2
ST
WE
CEl
CE2
°in

VSS

FIGURE 3 - AC TEST CIRCUIT

9 Voo
AO
Al
~
A2
Pulse A3
Generator
1 A4

--
~
A5
A6 °out
A7
~
P.G.2
P.G.3
P.G.4
ST
WE
CEl
ICc
P.G.5 CE2
P.G.6
- °in

f VSS

3-15
 MCM14537

FIGURE 4 - READ CYCLE WAVEFORMS UTILIZING STROBE-TO-ACCESS MEMORY

~ ,---------vDD

~ ,-------t-su--~--t-sU-(-A-)---------~-o/:-h-(A-)------
Address
Inputs
(An)
---J vSS

, , - - - - - - - - - - , - - - - - - - V DD

'-----Vss
1 4 - - - - - t WL( R) -----t~

, - - - - - - - - VDD
Write Enable
(WE) 50%

--------.----- vss

~-----VOH
Data Output
(D out )
''-----VOL

II NOTES: 1

2
3
High impedance output state occurs when
"0" (low level).
WE is maintained as a logical

The output momentarily displays data from the previous state.

For read operation, WE may be maintained at a logical "1" (high level)
during the complete cycle.
4 GEl and CE2 are maintained at a logical "0" state (low level).
5 All input rise and fall ti mes are 20 ns.

FIGURE 5 - READ CYCLE WAVEFORMS UTILIZING CE2 FOR ACCESS MEMORY

,---------- VDD

f
Address
Inputs - 500/.
(An)
__. _ . _ th(A) _ _ _ 0_ _ _ _ _ _ _ _ VSS

ChipEnable--2
(t'EZ) '-----VSS

----1

G
·th(R)' .
. . . . - ' - - - - - - - VDD

@ 50%

---- VSS

Data Output

[<----VOL

NOTES: 1 High I mpedance output state occurs when CE 1 or CE2 is mamtained

in the logical "1" state (high level).
The output momentarily displays data from the previous state.
For read operation, WE may be maintained at a logical "1" (high level)
during the complete cycle.
4 All input rise and fall times are 20 ns.
5 tWL( R1) ~ tacc (R) max

~-1n
MCM14537

FIGURE 6 - READ CYCLE WAVEFORMS UTILIZING CEl AND CE2 TO ACCESS MEMORY

~ _~O%
VOO
Address
Inputs
(Ani
VSS
th(AI
--~~
VOO
CE2
®
VSS

tdelay( CE21

r --VOO

NOTES: 1 High impedance output state occurs when CE 1 or C E2 is maintained

•
in the logical" 1" state (high level I.
2 WE is maintained at the logical "1" state for this example.
3 All input rise and fall times are 20 ns
4 tdelay(CE21 minimum assuares that only data presently addressed
will appear at the output.

tdelay(CE21 min. ~ taccR max. - tacc(cEi I min.

5 tWL(R2) )!tdelay (CE2~) min + tacc (CE n ) max

FIGURE 7 - WRITE CYCLE WAVEFORMS

~
Address
Inputs
_
_________________________________________ ~r,O-%---------------- VOO
(An)

-----------tCyC(WI----------_~o_ll
'""1
..
/ I,,------------------ V ss

tsu(A) -----tWL(W).r--- -th(A)-_1 I

~
/v
Strobe or
VOO
CE10rCE2 CD
~ _ _ _ _ _ _ _ _ _ _ _ _ _ _- J
(ST, CE 1, CE2)

{ _.
' - - - - - VSS

Write Enable
(WE)
@' -. ',",W" _
r% ~th(WE)

Data Input
(Din) ®
""'0')( ;-~~ -------------------------- V

®
~-------------------------VOL
aH

NOTES: 1 The Strobe, CE1 and CE2 may be utilized to control a write cycle,
however, during changes of address either Strobe or CE2 must
be in the logical "1" state (high level).
2 Data input logic level is don't care during the indicated intervals.
3 Data input logic level must remain fixed.
4 Write Enable may be maintained as a logical "0" during the write cycle.
5 All input rise and fall times are 20 ns.

3-17
MCM14537

LOGIC/BLOCK DIAGRAM

Din
r-------
0 - - - - : - - - - - - - - - - - -___----.
I
---------,
CIT O-----I~--a
3-State Enable

(High Resistance State)

WE 0---+-+-_-1

ST O---t----,--OI

A7o-~-------~

A6o--.--------__~

A5o--+----------~

A40--+----------~
Set
16 x 16 x 1
Memory Output
A3o--.----------~
Array Latch
Q r---L, ---<l D out

,
A2o--+----------~
1 of 16
Reset ,
A 1 O--+----------~ Decoder
I
AOo--,----------~
,
I ,I
L ______ _ - __ J

FUNCTION CEl CE2 ST WE Djn Dout COMMENTS

~ will be acti~e_if CE1 and

X X X X RIA
Address changing CE2 ~ "0" and WE ~ "1".
valid CE2 ~ "1", fully disables internal
X X X X R
logic and output.
Address changing Changing address in this mode
X X X RIA
not valid may result in altered data.
CE 1 ~ "1" disables write cycle
00ut disabled in X X X X R
and D out '
high resistance state
X X X X R The chip is fully disabled.
WE ::= "0" enables writing into
X X X X R memory if CE1, CE2, and
ST ~ "0".
If ST ~ "1", the output stores
Dout enabled in
0 X X A and reads the previous data
active state
from or written into memory.
The output reads the present
0 0 X A
contents that are addressed.
Read addressed
The addressed location is read
In{'~tinn
into output latch with output in
into output latch. " the" R" state.
Oisable reading X X X X R Address changing can take
from memory X X X X RIA place in this condition.
Din is written into memory
Write into memory 0 0 0 0 A R
and into the oc.tput latch
Write disabled X X X X R WE ~ "1" is a read enable.
X 1 X X X R WE ~ "0" is a write enable.
X X 1 X X RIA
X X X 1 X RIA

R ~ High resistance state at 00ut

A ~ An active level of either VSS or VOD
RI A ~ An R or A condition depending on the don't care condition
X ~ Don't care condition (must be in thu "1" or "0" state)
1 ~ A high level at VOO
o~ A low level at VSS
MCM14537

TYPICAL APPLICATION FOR SERIAL WORDS UTILIZING BUS TECHNIQUES

Address
Register
1 1
- - ---- - -----~

------------
-
-
-
-
I I I IT -

I-"'c:,o"" I I~CM~~537
CE1 D CE1
@
D
I
<D 1 -

6b - ---0
II 1--1
1 of n
Decoder
I Tword = tace( ST) + (n-') taee( CE 1 )

II
T word(ty P ).- 3.8115 for a 32·bit serial word at V DD = 10 V

V
10·Bit
Address

1111 II I I TII I 1111

I' An

D
~II~~I I~~
A: CE
I~~I
1
Typical 1024 x 1 RAM Utilizing Four MCM14537's .

.!=- IE.-- I I
10-Bit
Addres

Till I III III

An
CE2 D
An
CE2

I
D II' CE2

I
An

D II~~I
1 of 4
-p-J
k
I T
D out

Decoder
1 r
Typical Low Power 1024 x 1 RAM Utilizing Four MCM14537's.

3-19
 ® MOTOROLA MCM14552

CMOS LSI
256-BIT STATIC RANDOM ACCESS MEMORY (LOW-POWER COMPLEMENTARY MOS)

. The MCM14552 is a static random access memory (RAM) organ-

ized in a 64 x 4 bit pattern. The three chip 'enable inputs can be used 256-BIT (64 X 4) STATIC
as extensions of the six address inputs, creating 9-bit address scheme.
Eight MCM 14552 devices may be used to comprise a 2048-blt mem-
RANDOM ACCESS MEMORY
ory (512 x 4) without additional address decoding.
The mode control (M) is used to change the control logic charac-
teristic of the circuit. For example, with M high, the 3-state input
(T) fully controls the 3·state characteristic of the output. With M
low, the output 3·state characteristic is controlled by chip enable
inputs (CEI. write enable input (WE) and T.
The memory Isdesigned so that dc signals may operate the memo
ory, with no maximum pulse width restrictions.

•
Medium speed, micropower operation, and control flexibility
make the device useful in scratch pad or buffer applications where
battery operation or high noise immunity are required.
L SUFFIX
• Quiescent Curtent = 50 JlA/package typical @ 5 Vdc CERAMIC PACKAGE
CASE 623
• Noise Immunity = 45% of VDD typical
• 3-state Output Capability for Memory Expansion
• Output Data Latch Eliminates Need for Storage Buffer
• Access Time = 700 ns typical @ VDD = 10 Vdc
• Fully Decoded and Buffered
• Supply Voltage Range = 3:0 Vdc to 18 Vdc P SUFFIX
• Capable of Driving Two Low·power TTL Loads, One Low-power PLASTIC PACKAGE
CASE 709
Schottky TTL Load or Two HTL Loads Over the Rated Temper-
ature Range

NOTE: Pin 20(LE)) must be connected to VSS

MeM'4XXX 1
ORDERING INFORMATION

tSUfflX
L
P
Denote5
Ceramic Package
Plastic Package
A Extended Operating
Temperature Range
C limited Operating
MAXIMUM RATINGS (Voltages referenced to Vssl Temperature Range
Rating Symbol Value Unit
DC Supply Voltage VDD -0.5 to +18 Vdc
PIN ASSIGNMENT
Input Voltage, All Inputs Vin -0.5 to VDD + 0.5 Vdc

1C~P24
DC Current Drain per Pin I 10 mAdc
Operating Temperature Range - AL DeVice TA -55 to +125 °c
I...L/I...t uevlce - co': 2 J= ST CE 1 P 23
3C D out a CE 2 P 2 2
Storage Temperature Range T stg -65 to +150 °c
. 4 C Din a CE3 P21
5C D out 1 LE P20
6C Din 1 T::::::J 19
7C D out 2 A5 p 1 8
This device contains circuitry tei protect the inputs against damage due to high
static voltages or electric fields; however, it is advised that normal precautions be 8 e Din 2 A4 p17
taken to avoid application of any voltage higher than maximum rated voltages 9C D out 3 A3 ~16
to this high impedance circuit. For proper operation it is recommended that
A2 p 1 5
Vin and V out be constrained to the range VSS « (Vin or V out ) «
VDD'
10C Din 3
11C WE A1 p 1 4
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either
12C VSS AO p 1 3
VSS or VDD·

.~.,,?O
MCM14552

ELECTRICAL CHARACTERISTICS
voo Tlow
. 25°C Thigh'
Characteristic Symbol Vdc Min Max Min Typ Max Min Max Unit
au tpu t Vol Wge "0" Level VOL 5.0 0.05 0 0.05 0.05 Vdc
Vin VDD or 0 10 0.05 0 0.05 0.05
15 0.05 0.05 0.05
"1" Level VOH 5.0 4.95 4.95 5.0 4.95 Vdc
Yin o or VDD 10 9.95 9.95 10 9.95
15 14.95 14.95 15 14.95
Input Voltage ll "0" Level VIL Vdc
(Va 4.5 or 0.5 Vdcl 5.0 1.5 2.25 1.5 1.5
(Va 9.0 Or 1.0 Vdcl 10 3.0 4.50 3.0 3.0
(Va 13.5 or 1.5 Vdcl 15 4.0 6.75 4.0 4.0
"1" Level VIH
(Va 0.5 or 4.5 Vdcl 5.0 3.5 3.5 2.75 3.5 Vdc
(Va 1.0 or 9.0 Vdcl 10 7.0 7.0 5.50 7.0
(Va' 1.5 or 13.5 Vdcl 15 11.0 11.0 8.25 11.0
Output Dflve Current (Al Devicel IOH mAdc
(VOH 2.5 Vdcl Source 5.0 -1.2 -1.0 -1.7 -0.7
(VOH 4.6 Vdcl 5.0 -0.25 -0.2 -0.36 -0.14
(VOH ,. 9.5 Vdcl 10 -0.62 -0.5 -0.9 -0.35
(VOH 13.5 Vdcl 15 -1.8 -1.5 -3.5 -1.1
(VOL '·0.4 Vdcl Sink IOL 5.0 0.64 0.51 0.88 0.36 mAdc

•
(Val ~ 0.5 Vdcl 10 1.6 1.3 2.25 0.9
(VOL ~1.5 Vdcl 15 4.2 3.4 8.8 2.4
Output Drive Current (CLlCP Devicel IOH mAdc
(VOH 2.5 Vdcl. Source 5.0 -1.0 -0.8 -1.7 -0.6
(VOH ~ 4.6 Vdcl 5.0 -0.2 -0.16 -0.36 -0.12·
(VOH ~ 9.5 Vdcl 10 -0.5 -0.4 -0.9 -0.3
'(VOH ~ 13.5 Vdcl 15 -1.4 -1.2 -3.5 -1.0
(VOL = 0.4 Vdcl Sink IOL 5.0 0.52 0.44 0.88 0.36 mAdc
(VOL ~ 0.5 Vdcl 10 1.3 1.1 2.25 0.9
(VOL = 1.5 Vdcl 15 3.6 3.0 8.8 2.4
Input Current (Al Devicel lin 15 ± 0.1 ±OOOOOl ± 0.1 ± 1.0 ).LAdc
Input Current (CLlCP Devicel lin 15 ±1.0 ±0.00001 i 1.0 ±14.0 ",Adc
Input Capacitance Cin 5.0 7.5 pF
(Vin ~ 0)
Quiescent CUI rent (AL Devicel IDD 5.0 5.0 0.050 5.0 150 ",Adc
(Per Packagel 10 10 0.100 10 300
15 20 0150 20 600
QUiescent Current (CLlCP Devicel IDD 5.0 50 0.050 50 375 ",Adc
(Per Packagel 10 100 0.100 100 750
15 200 0.150 200 1500
Total Supply Current' '·t IT 5.0 IT ~ (1.98 ).LA/kHzl f + IDD ",Adc
(Dynamic plus Quiescent, 10 IT "(3.96 ",A/kHzl I + IDD
Per Packagel 15 IT ~ (5.86 ",A/kHzl I + IDD
(Cl - 50 pF on all outputs, all
bulfers switchingl
Three·State Leakage Current ITL 15 ± 0.1 '000001 ± 0.1 ±3.0 ).LAdc
(AL Devicel
Three·State Leakage Current ITL 15 ± 1.0 '0.00001 ± 1.0 ± 7.5 ).LAdc
(CLlCP Devicel

'Tlow • -55°C for AL Device, -40°C for CLlCP Device.

Thigh ~ +125 0 C for AL Device, +85 0 C for CLlCP Device .
.:.Noise immunity specified for worst·case input combination.
Noise Margin lor both" 1" and "0" level ~ 1.0 Vdc min @ VDD = 5.0 Vdc
2.0 Vdc min @ VDD " 10 Vdc
2.5 Vdc min @ VDD ~ 15 Vdc
tTo calculate total supply current at loads other than 50 pF:
IT(CLI ~ IT(50 pFI +4 x 10- 3 (CL -501 VDDf
where: IT is in ",A (per packagel, CL in pF, VDD in Vdc, and f in kHz is input frequency.
"The formulas given are for the tYpical characteristics only at 25 0 C.

~-?1
 MCM14552

SWITCHING CHARACTERISTICS* (CL = 50 pF, T A = 250 C)

Characteristic Figure Symbol VOO Min Typ Max Unit
Output Rise Time 1 tTLH ns
tTLH = (3.0 ns/pF) CL + 30 ns 5.0 - 180 360
tTLH = (1.5 ns/pF) CL + 25 ns 10 - 90 180
tTLH = (1.1 ns/pF) CL + 10 ns 15 - 65 130
Output Fall Time 1 tTHL ns
tTHL = (1.5 ns/pF) CL + 25 ns 5.0 - 100 200
tTHL = (0.75 ns/pF) CL + 12.5 ns 10 - 50 100
tTtlL = (0.55 ns/pF) CL + 9.5 ns 15 - 40 80
Read Cycle Time 1,2 tcyc(R) 5.0 - 2000 6000 ns
10 - 750 2200
15 - 500 1650
Write Cycle Time 3,4 tcyc(W) 5.0 - 1200 3600 ns
-

•
10 750 2200
15 - 500 1650
Address to strobe Setup Time 1,3 tsu(A-ST) 5.0 1500 500 - ns
10 450 150 -
15 350 120 -
Strobe to Address Hold Time 1,3 th(ST-A) 5,0 150 50 - ns
10 100 0 -
15 75 0 -
Address to Chip Enable Serup Time 2,4 tsu(A-CE) 5.0 1800 600 - ns
10 600 200 -
15 450 150 -
Chip Enable to Address Hold Time 2,4 th(CE-A) 5.0 450 150 - ns
10 300 100 -
15 225 75 -
Strobe or Chip En.abl':~l.!lse Width When Reading 1,2 twL(R) 5.0 1800 450 - ns
10 450 150 -
15 350 100 -
Strobe or Chip Enable Pulse Width When Writing 3,4 tWL(W) 5.0 3600 1200 - ns
10 1800 600 -
15 1350 400 -
Read Setup Time ' 1 tsu(R) 5.0 0 -100 - ns
10 0 -40 -
15 0 -30 -
---
Read Hold Time' 1 th(R) 5.0 540 180 - ns
10 240 60 -
15 180 45 -
Data Setup Time 3,4 tsu(D) 5.0 1800 600 - ns
10 600 200 -
15 450 150 -
--
Data Hold Time 3,4 th(D) 5.0 600 200 - ns
IU ,~" V"

15 120 30 -
*The formula given is for the typical characteristics only. (continued)

3.. 22
MCM14552

SWITCHING CHARACTERISTICS* (Cl = 50 pF, T A = 25 0 C) (continued)

Characteristic Figure Symbol VDD Min Typ Max Unit
Write Enable Setup Time 3,4 tsu(WE) 5.0 720 240 ns
10 240 80 -
15 180 55 -
Write Enable Hold Time 3,4 th(WE) 5.0 150 50 ns
10 60 20 - ./
15 45 15 -
Read Access Time from Strobe 1,3 tacc(R-ST) 5.0 - 2000 6000 ns
10 - 700 2100
15 - 350 1600
Read Access Time from Chip Enable 2 tacc(R-CE) 5.0 - 2100 6300 ns
10 - 750 2250
15 - 400 1700
Output Enable/Disable Delay from Chip Enable or 2,4 tR(CE), 5.0 - 400 1200 ns
Write Enable tR(WE) 10 - 200 600
15 - 150 450
Three-State Enable/Disable Output Delay 2 tef) 5.0 - 400 1200 ns
10 - 160 480
15 - 120 360
latch to Output Propagation Delay 1 tlE 5.0 - 500 1500 ns
10 - 200 600
15 - 150 450
*The formula given is for the typical characteristics only.

Din Din Din Din

o 1 2 3 T
LOGIC DIAGRAM 4 6 8 10 19
9 9 20

WE 11

ST 2 o--------.~+-~--------------------r__r--r__r----------__,

CEl 23
CE222
CE321

A5 18o-----------------~
3 to 8
DO 00 3 Dout 0
A4 17o-----------------~
Decoder 64 x 4
A3 16o-----------------~ 01 01 5 D out 1
Memory Latches

02 02 7 D out 2
A2 15O-----------------~ Array
3 t08

Al 14o-----------------~ 03 03 9 D out 3
Oe\,oder

AO 13o-----------------~
VDO = Pin 24
VSS = Pin 12

3-23
 MCM14552

FIGURE 1 - READ CYCLE WAVEFORMS UTILIZING STROBE TO ACCESS MEMORY

Address
~_·_t_su __________ tc_y_C_(R_)_-_-_-_-~_-----'--h(-'A-~--T~=================~:sD
__

(A·Sf)
, . - - - - - - " " " \ - - - - - - - - - VDD
50%
~---------- VSS

Write Enable r--------------

50%
VDD

-----Vss

Latch Enable

II Data Out

Notes· 1 - eE1. CE2. CE3 and T are low. M is high

2·· WE may be held high during the complete read cycle

FIGURE 2 - READ CYCLE WAVEFORMS UTILIZING CHIP ENABLE TO ACCESS MEMORY

Address _ _ _ _ _ _ ~=---- tCyC(R)-------*'-~_o_% ________ ~::

- --tWL(R)---
tsu(A GE)
, . - - - - - - - - - ' " " - - - - - - - - - - VDD

' - - - - - - - - - - - VSS

OL
Notes: 1 - Unused IT. ST. M and T are low and WE is high.
2 - High impedance output state occurs when any CE is high
and M is low. or when T is high.
3 - The output displays data from the previous state.
4 - tWL(R) :;, tacc(R·CE)max·

3-24
MCM14552

FIGURE 3 - WRITE CYCLE WAVEFORMS UTILIZING STROBE

1 0 4 - - - - - - - tcyc(W)
- - - - - - - - - - VDD
Address
~------- VSS

r------,------- VDD

1'------ VSS

r----+------ VDD
Write Enable
'------t---' 1-----+------ VSS

r----+------ VDD
Data In

Data Out 4

•
Notes: 1 - CE 1, CE2, CE3 and T are maintained at the logical "0" level.
2 - M is maintained at the logical "1" level.
3 - The output displays the contents of the previous state.
4 - The output displays the contents of the presently addressed location as in a
read mOdify write cycle.
5 - The output displays the data that was written into addressed location.

FIGURE 4 - WRITE CYCLE WAVEFORM UTILIZING CHIP ENABLE

~
t------tCYC(W)----~'
VDD
Address --*50%
Vss
th (A-CE)~(A_CE)
r------~----------VDD

~----------VSS

r------VD D
Write Enable 50%
- - - - - - VSS

r---------+-------VDD
Data In
~--------+-------VSS

~---VOH
Data Out
'-----VOL
Notes: 1 - High impedance output state occurs when cr is high or when WE
is low, for M and T maintained in the low state.
2 - Unused cr's,ST, M and T are maintained at the logical "0" level.

3-25
 MCM14552

TRUTH TABLE
Function CE 1 CE 2 CE 3 LE M ST WE Din Dout Comments
Address X R/A D out will be active if all
Changing R/A CE = 0, T =0 and WE = 1
Valtd R/A or if M = 1 and T "" 0
R/A
Address Changing R/A Dout will be active if T '"' 0
Not Valid and WE '" 1 or if M .:: 1
andT=O
00ut Disabled
(in high resistance state) Disables write circuitry

T - 1 always disables Dout

M '" 0 and write operation
disables D out
D out Enabled Read operation, 00UI active
(in active state) Read or write. oOU1 active
Read Addressed R/A If WE '" 0, Din'" D out
Memory Location
I nto OUtput Latch
Disable Reading R/A
From Memory R/A
R/A
R/A
R/A
Write Into Memory R/A
Write Disabled R/A
R/A
R/A
R/A
RIA

•
Output Latch Enabled R/A
Output Latch Disabled R/A
R/A
R/A

i R "" High resistance state at 00U1 -' Don't care condition (must be
R/A
R/A

10 the "'" or "0" state)

A -. An active level of either VOD or VSS ~ A hIgh level at VOO
R/A '-- An R or A conrlitlon depending on the don't care condition A low level at VSS

FIGURE 5 - 512 WORD X 16 BIT MEMORY BOARD Data Inputs

DO 01 02 03 04 05 06 07 08 09010011 012013014015

'[ '[ '[ r '[ '[ '[ '[ '[ '[ '[ '[ '[ '[ '[ '[
AS CE3
A7 CE2
A6 CE1
A5 A5
A4 A4
A3 A3
A2 A2
A1 A1
AO AO
--< Sf
..---< T

All M and IT I t I I I
I MCM14552
inputs are
I 32 places I I I
grounded I I I
I I I I
A8 CE3
A7 CE2
A6 CE1
---< A5
- --< A4
A3
A2
A1
AO
f------< ST
Board Strobe T

t t t + ~ ~ ~ ~ ~ t t + + + + +
DO 01 02 03 04 05 O~ 07 0809010011 012013014015

Data Outputs

3-26
 ® MOTOROLA MCM145101

256 X 4 BIT STATIC RAM

CMOS LSI
The MCM145101 family of CMOS RAMs offers ultra low power (LOW-POWER COMPLEMENTARY MOS)
and fully static operation with a single 5 volt supply. The CMOS
1024-bit devices are organized in 256 words by 4 bits. Separate data
inputs and data outputs permit maximum flexibility in bus-oriented 1024-BIT STATIC
systems. Data retention at a power supply as low as 2.0 volts over RANDOM ACCESS MEMORY
temperature readily allows design into applications using battery
backup for nonvolatility. The MCM145101 is fully static and does
not require clocking in standby mode.

4} 1IIfIJ
The MCM145101 is fabricated using the Motorola advanced ion-
implanted, silicon-gate technology for high performance and
high reliability.
• Low Standby Power
• Fast Access Time
• Single + 5.0 Volt Supply L SUFFIX

11
• Fully TTL Compatible-All Inputs and Outputs CERAMIC PACKAGE P SUFFIX
• Three·State Output CASE 736 PLASTIC PACKAGE
• Fully Static Operation CASE 708

• Data Retention to 2.0 Volts

ORDERING INFORMATION
• Direct Replacement for:
Denotes
~~~'"
Intel 5101 Series
AMI S5101 Series MCM"XXXX

Hitachi MH435101 Series

• Pin Replacement for Harris HM6501 Series
-3 Selections for
-8 speed and
power (see
(Not table)
Typical Current Typical Current Max Access Used)
Type Number @2Vdc (/LA) @5Vdc (/LA) (ns)
MCM145101 L, MCM145101P 0.14 0.2 650
MCM145101-1 L, MCM145101·1P 0.14 0.2 450
PIN ASSIGNMENT
MCM145101-3L, MCM145101·3P 0.70 1.0 650
MCM145101-8L, MCM145101-8P - 10 800
22
21
BLOCK DIAGRAM
4 20
AO
Cell Array 4 19
A1 Address Row
32 Rows VCC = Pin 22 18
Buffers Decoders
A2 32 Columns Gnd = Pin 8 6 17
(Enable)
16
8 15
001 14
9
CE2
19 10 13
CE1
DQ2 11 12
(Enable)
20
R/W 003
9 Input
011 TRUTH TABLE
11 Data
012
13 Control 004 CE1 CE2 00 R!W Din Output Mode
013
15 H X X X X High Z Not Selected
014
X L 'X X X High Z Not Selected
X X H H X High Z Output Disabled
L H H L X High Z Write
18 H L X Write
00 L L Din
L H L H X DOut Read

3-27
 MCM145101

MAXIMUM RATINGS (Voltages referenced to VSS Pin 8)

Rating Symbol Value Unit This device contains circuitry to protect the
DC Supply Voltage VCC -0.5 to +7.0 Vdc inputs against damage due to high static voltages
Voltage on Any Pin or electric fields; however, it is advised that
Vin -0.3 to VCC +0.3 Vdc
normal precautions be taken to avoid applica-
Operating Temperature Range TA -40 to +85 °c tion of any voltage higher than maximum rated
Storage Temperature Range T stg -65 to +150 °e voltages to this high-impedance circuit.

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted)

DC CHARACTERISTICS (T A = 0 to 70 o e, Vce = 5 V ± 5%)

MCM145101,-1 MCM145101-3 MCM145101-8
Characteristic Symbol Min Typ Max Min Typ Max Min Typ Max Unit
Input Current lin(2) - 5.0 - - 5.0 - - 5.0 - nAdc
Input High Voltage VIH 2.2 - Vec 2.2 - Vec 2.2 - Vec Vdc

•
Input Low Voltage VIL -0.3 - 0.65 -0.3 - 0.65 -0.3. - 0.65 Vdc
Ou'tput High Voltage VOH 2.4 - - 2.4 - - 2.4 - - Vdc
(lOH = -1.0 mAl
Output Low Voltage VOL - - 0.4 - - 0.4 - - 0.4 Vdc
(lOL = 2.0 mAl
Output Leakage Current ILO(2) - - ± 1.0 - - ± 1,0 - - ±2.0 !LAdc
(eEl = 2.2 V, VOL = 0 V to Vee) \

Operating Current ICCl - 9.0 22 - 9.0 22 - 11 25 mAdc

(V in = VCC, except CEl .;; 0.65 V, outputs open)
Operating Current ICC2 - 13 27 - 13 27 - 15 30 mAdc
(Vin = 2.2 V, except CEl .;; 0.65 V, outputs open)
Standby Current ICCL (2) ,(4) - - 10 - - 200 - - 500 !LAdc
(CE2';; 0.2 V)

CAPACIT ANCE '.

Characteristic Symbol Typ Max Unit
Input Capacitance (Vin =0 V) Cin 4.0 8.0 pF
Output Capacitance (V out = 0 V) Cout 8.0 12.0 pF

LOW VCC DATA RETENTION CHARACTERISTICS (Excluding MCM145101-8) TA = OOC to 70 0 C

Parameter Test Conditions Symbol Min Typ. (1) Max Units
VCC for Data Retention VDR 2.0 - - Vdc
MCM145101 or MCM145101-1 Data VDR = 2.0 V, ICCDRl - 0.14 10 !LAdc
Retention Current
CE2.;; 0.2 V
MCM 145101- 3 Data Retention Current VDR = 2.0 V, ICCDR2 - 0.70 200 !LAdc
- .. -
Chip Deselect to Data Retention Time tCDR 0 - - ns
Operation Recovery Time tR tRC I31 - - ns

NOTES: 1. Typical values are T A = 25 0 C and nominal supply voltage.

2. Current through all inputs and outputs included in ICCL measurement.
3. tRC = Read Cycle Time.
4. Low current state is for CE2 = 0 only.

3-28
MCM145101

LOW VCC DATA RETENTION WAVEFORM TYPICAL ICCDR versus TEMPERATURE

Supply
I
Vce = 2.0 V
l
Voltage
1.0 - -
CE2 = 0.2 V LV
(VCC) Vin = 2.0 V -
VV
Chip Enable
CD
VIH
t S1
0.2 V ....._ _ _ _ _ _ _ _- '
~
a:
Cl
u
u 0.1
/V
)/
(CE2) OV - - - - - - -
V
0.01 0 10 20 ·30 40 50 60 70
TEMPE RATU RE (DC)

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature unless otherwise noted)

AC TEST CONDITIONS
Condition I Value
Input Pulse Levels I +0.65 V to 2.2 V
Input Rise and Fall Times
I 20 ns
Output Load - 1 TTL Gate and CL = 100 pF
Timing Measurement Reference Level
I 1.5 Volt

READ CYCLE
MCM145101-1 MCM145101,-3 MCM145101-8
Parameter Symbol Min Max Min Max Min Max
Read Cycle tRC 450 - 650 - 800 -
Access Time tA - 450 - 650 - 800
Chip Enable (eEl) to Output tCOl - 400 - 600 - 800
Chip Enable (CE2) to Output tC02 - 500 - 700 - 850
Output Disable to Output too - 250 - 350 - 450
Data Output to High Z State tDF 0 130 0 150 0 200
Previous Read Data Valid with Respect to Address Change tOHl a - 0 - 0 a
Previous Read Data Valid with Respect to Ch ip Enable tOH2 0 - 0 - 0 0

WRITE CYCLE
Write Cycle twc 450 - 650 - 800 -
Write Delay tAW 130 - 150 - 200 -
Chip Enable (CE1) to Write tCWl 350 - 550 - 650 -
Chip Enable (CE2) to Write tCW2 350 - 550 - 650 -
Data Setup tow 250 - 400 - 450 -
Data Hold tDH 50 - 100 - 100 -
Write Pulse twP 250 - 400 - 450 -
Write Recovery tWR 50 - 50 - 100 -
Output Disable Setup tDS 130 - 150 ~
200 -

3-29
 MCM145101

READ CYCLE TIMING WRITE CYCLE TIMING

J 4 - - - - - - t R C ---,---t~ ~--------twc-------~~

Address Address

CE1

CE2 CE2

~----tCW2----~
00-.....,1---,1 OD--I,~-----------+_--~---
(Common 1/0)[2J
-(Common 1/0)[1J

Data ---'-.....,----,IJ--..,.------ Data ---+-_Ir---------+-"\.I,~--t_-

Out ______________- J ~ _____________
In _-+0_..1 '-_________ -+-' ""_-+-_

• NOTES: 1. 00 may be tied low for separate 1/0 operation.

2. During the write cycle, 00 is "high" for common I/O and "don't care" for separate I/O operation.

3-30
 ® MOTOROLA MCM146504

Product Previe"","

CMOS LSI
4096X1-BIT STATIC RANDOM ACCESS MEMORIES (LOW-POWER COMPLEMENTARY MOS)

The MCM146504 is a 4096Xl-bit static random access memory,

fabricated with high density, high reliability CMOS silicon-gate 4096X1-BIT STATIC
technology. The device has TTL compatible inputs and outputs. It is
RANDOM ACCESS MEMORIES
designed to retain data at low supply voltages, to further reduce
supply current requirements.
The MCM 146504 is useful in memory applications where
low-power and non-volatility is required. It is assembled in 18 pin
dual in-line package with the industry standard pin-outs.

• Single Low Voltage Power Supply

II
• Static Operation
• I ndustry Standard 18-Pin Confi!:Juration
PIN ASSIGNMENT
• Fully TTL Compatible
• Common Data Input and Output Capability
• Three-State Outputs
• Low Power Dissipation - Standby 10 mW (Typical) 18

• Ideal for Battery Backup Operation 17

16
• Access Time - 450 ns (Maximum)
4 15
• Pinout and Functional Replacement for 14
Harris - HM6504 6 13
Intersil - IM6504
12
8 11
10

BLOCK DIAGRAM

AO------~~-1
---VSS PIN NAMES
A1
A2 ------''''.,..-......, Memory Array - - - V CC AO All Address Input
Row
A8 _____-''''0:---, Select
64 Row o Data Input
64 Columns
A7 Q Data Output

A6 -------' "''------' Ch ip Select

VCC Power Supply (; 5 V)

Data Input Ground

0--------1 Input W Write Enable
Data
W------I Control
and TRUTH TABLE
5-------t Clock
S W D Q Mode
H X X HI-Z Not Selected
A3 A4 A5 A11 A10 A9 HIZ Write "0"
H HI-Z Write "1"
H X Output data Read

This is advance information and specifications are subject to change without notice.

3-31
 ® MOTOROLA
MCM146508
MCM146518
Advance InforIDation
CMOS LSI
1024 X 1 BIT STATIC RANDOM ADDRESS MEMORY (LOW-POWER COMPLEMENTARY MOS)
The MCM146508 and MCM146518 are fully static 1024 X 1
RAMS fabricated using high performance silicon gate CMOS tech-
1024 X 1 BIT STATIC
nology. They offer low-power operation from a single 5.0 V supply
RANDOM ACCESS MEMORY,
with data retention to 2.0 V. The MCM 146508 has the two select
lines and the enable line brought out as a single enable line.
• Low Standby and Operating Power
• Single 5.0 V Supply
• Data Retention to 2.0 V
• Fast AcceSli Time
16
• Address Latches
• Three-State Outputs
L SUFFIX P SUFFIX

I •
•
•
Fully TTL Compatible Inputs/Outputs
Fully Static Operation
Direct Replacement for
Harris HM6508/HM6518
CASE 620 CASE 648

Intersi11M650S/IM6518

L SUFFIX P SUFFIX
TABLE 1
CASE 680 CASE 707
Maximum Operating
Package Typical Current Access Temperature
MCM14XXXX Suffix Denote,
Type Number
MCM146508/MCM146518
MCM 146508-1/MCM 146518-1
Suffixes
LIP
LIP
2 Vdc
0.11lA
0.0111A
5Vdc
5.01lA
1.011A
Time
460 ns
300 ns
Range
-40 to +85 0 C
-40 to +85 0 C
1TL-,
P
C."m," '"''''
Plastic Package
See Table 1
MCM146508-2/MCM146518-2 0.0111A 1.01lA 300 ns -55 to + 125°C

BLOCK DIAGRAM PIN ASSIGNMENT

A5
A6
16
A7
A8 15
A9
3 14
MCM146508
4 13
12
Q
6 11

10

18
17

w 16
15
MCM146518
14

13
12
, 1
AO' A 11A21A31A4
11

• For MCM146508 Sl, S2 are connected to the E input.

This is advance information and specifications are subject to change without notice.

3-32
MCM146508, MCM146518

MAXIMUM RATINGS (Voltages Referenced to Vss)

Rating Symbol Value Unit
DC Supply Voltage VOO -0.5 to +7.0 Vdc
Input Voltage, All Inputs Vin -0.3 to VOO + 0.3 Vdc
Operating Temperature Range TA °c
MCM146508/MCM146518 -40 to +85
MCM146508-1/MCM146518-1 -40 to +85
MCM146508-2/MCM146518-2 -55 to + 125
Storage Temperature Range T stg -65 to + 150 °c

DC CHARACTERISTICS (Voo = 5.0 V ± 10%, TA = 25°C)

MCM146508-1 MCM146508 MCM146508-2
MCM146518-1 MCM146518 MCM146518-2
Characteristic Symbol Min Typ Max Min Typ Max Min Typ Max Unit
Input Current lin - 5.0 - - 5.0 - - 5.0 - nAdc
Input High Voltage VIH VOO - 2.0 - VOO VOO - 2.0 - VOO - - VOO Vdc
Input Low Voltage VIL -0.3 - 0.8 -0.3 - 0.8 -0.3 - O.B Vdc
Output High Voltage VOH 2.4 - - 2.4 - - 2.4 - - Vdc
UOH = -1.0 mAl

II
Output Low'Voltage VOL - - 0.4 - - 0.4 - - 0.4 Vdc
(IOL = 2.0 mAl
Output Leakage Current IOL - - ± 1.0 - - ± 1.0 - - ±1.0 )lAde
(VOL = 0 V to VOO)
Standby Current IOOSS - 0.1 10 - 1.0 100 - 1.0 100 nAdc
(VIH = E=S1 =52 = VOO)
Data Retention Current IOOOR - 0.1 1.0 - 0.1 10 - 0.1 10 )lAde
(VOO=2.2V=VIH=
E =51=52)
. Operating Current IOOOp - - - - - - - - - mAde
(tELEH = 1.0 its)

CAPACITANCE
Characteristic
Input Capacitance (V in = 0 V)
Output Capacitance (V out - 0 V)

AC OPERATING CONDITIONS
Condition Value
Input Pulse Levels +0.8 V to VOO - 2.0 V
Input Rise and Fall Times 20 ns
Output Load 1 TTL Gate and CL = 50 pF
Timing Measurement Reference Level 1.5V
Supply Voltage 5.0 V ±10%
Temperature Range
MCM14650B/MCM146518 -40°C to +85 0 C
MCM146508-1/MCM146518-1 -40°C to +85 0 C
MCM146508-2/MCM146518-2 -55°C to + 125°C

This device contains circuitry to protect the

inputs against damage due to high static volt-
ages or electric fields; however, it is advised that
normal precautions be taken to avoid applica-
tion of any voltage higher than maximum rated
voltages to this high impedance circuit.

3-33
 MCM146508, MCM146518

AC CHARACTERISTICS
MCM14650S-1 MCM14650S-2 MCM14650S
MCM14651S-1 MCM14651S-2 MCM14651S
Parameter Symbol Min Max Min. Max Min Max Unit
Read or Write Cycle Time tELEL 500 - 500 - 760 - ns
Enable Pulse Width, Low tELEH 300 - 300 - 460 - ns
Enable Pulse Width, High tEHEL 200 - 200 - 300 - ns
Enable Access Time tELOV - 300 - 300 - 460 ns
Address Setup tAVEL 7.0 - 7.0 - 15 - ns
Address Hold tELAX 90 - 90 - 150 - ns
Data Setup tDVWH 200 - 200 - 300 - ns
Data Hold tWHDX 0 - 0 - 0 - ns
Write Pulse Width tWLWH 200 - 200 - 300 - ns
Write Enable to Output Disable tWLOZ - 180 - 180 - 285 ns
Output Disable (MC146508 Only) tEHOZ - 180 - 180 - 285 ns
Output Disable (MC146518 Only) tSHOZ - 180 - 180 - 285 ns
Write Disable to Output Enable tWHOX - 180 - 180 - 285 ns
Output Enable (MC146508 Only) tELOX - 180 - 180 - 285 ns
Output Enable (MC146518 Only) tSLOX - 180 - 180 - 285 ns

II Select to Write Pulse Setup

Select to Write Pulse Hold
Enable to Write Pulse Setup
Enable to Write Pulse Hold
tWLSH
tSLWH
tWLEH
tELWH
200
200
200
200
-
-
-
-
200
200
200
200
-
-
-

-
300
300
300
300
-
-
-
-
ns
ns
ns
ns

TIMING PARAMETER ABBREVIATIONS TIMING LIMITS

t X XXX The table of timing values shows 'either a minimum or

Slgn.al name from.WhiCh Interval i.5. def.ine.d:J

transition direction for first Signal
II a maximum limit for each parameter. Input requirements
are specified from the external system point of view.
signal name to which interval IS defined Thus, address setup time is shown as a minimum since the
transition direction for second Signal system must supply at least that much time (even though
most devices do not require it). On the other hand,
The transition definitions used in this data sheet are: responses from the memory are specified from the device
H = transition to high point of view. Thus, the access time is shown as a maxi·
L = transition to low mum since the device never provides data later than
V = transition to valid that time.
X = transition to invalid or don't care
Z = transition to off (high impedance)

Circuit diagrams utilizing Motorola products are included as a means is believed to be entirely reliable. However. no responsibility is
of illustrating typical semiconductor applications; consequently, assumed for inaccuracies. Furthermore, such information does not
complete information sufficient for construction purposes is not convey to the purchaser of the semiconductor devices described any
necessarily given. The information has been carefully checked and license under the patent rights of Motorola Inc. or others.

3-34
MCM146508, MCM146518

READ CYCLE TIMING

A

; -__________~I~----------tELEH------------~II~--~~~--~

__ tWLOZ_

W
------ tWHOX---l

D------------------+~----~t~E-L-O-V--------------------~---t-E-H-O-Z----~---­
-tELOX--
o Previous High Z
Valid Output
_Data

~ ~}_S_H_O_Z__________-_;Lts LOX

Time Reference -----------t-----+-----------4-------+------..,-----------lt--+-f--

4 5

TRUTH TABLE

•
Time Inputs Output
Reference E S W A D Q Function
-1 H H X X X Z Disabled

0 """\.. X H V X Z Address Latched

1 L L H X X X Output Enabled

2 L L H X X V Output Valid

3 J L H X X V Output Latched

4 H H X X X Z Disabled (Same as - 1)

5 \.. X H V X Z Next Cycle (Same as 0)

ItAVEL_1 CLA-)k- tAVEL~ ~

.
WRITE CYCLE TIMING
A )I( Valid Nex
~
tELEL
_ tEHEL_ • tEHEL _
tELEH

" 2
. Y
.. I
"~
tELWH tWLEH ..
'tI tWLWH-~

__ tWHDX
'-1_tDVWH-
D Valid Data

High Z
Q
..
s , - - - - - - - - - - - - - - - - _ ! - tWLSH
~tSLWH
1
S2---------------------~~------------------~---~----------------------
Time Reference -----------+-----+-------------i---------+-------t----------t~+t--
o 4 5

TRUTH TABLE
Time Inputs Output
Reference E S W A D Q. Function
-1 H X X X X Z Disabled
0 """\.. X X V X Z Address Latched
1 L L L X V Z Write Mode
2 L J L X V Z Data Written
3 J X X X X Z Write Completed
4 H X X X X Z Disabled (Same as -1)

NOTES:
5
'- X X V X Z Next Cycle (Same as 0)

1. MCM146518 selected only if both 51 and 52 are low and deselected if

either 51 or 52 is high. 51 and 52 are connected to E on the MCM146508.
2. The address within the memory will change only on falling E.

3-35
 ® MOTOROL.A MCM14524

CMOS LSI
1024-81T READ ONLY MEMORY
ILOW·POWER COMPLEMENTARY MOS)
The MCM 14524 is a complementary MOS mask programmable
Read Only Memory (ROM). This device is ordered as a factory spe-
cial with its unique pattern specified by the user.
1024-BIT
This ROM is organized in a 256 x 4·bit pattern. The contents of
(256 X 4)
a specified address « AD, A 1, A2, A3, A4, A5, A6, A 7 » will
READ ONLY MEMORY
appear at the four data outputs (80, 81, 82, 83) following the
negative going edge of the clock. When the clock goes high, the data
present at the output will be latched. The memory Enable may be
taken low asynchronously, forcing the data outputs low and reset-
ting the output latches. This device finds application wherever low
power or high noise immunity is a design consideration.
• Diode Protection on All Inputs
• Noise Immunity = 45% of VDD typical
• Quiescent Current - 10 nA/package typical @ 5 Vdc L SUFFIX P SUFFIX

I •
•
Single Supply Operation - Either Positive or Negative
Memory Enable Allows Expansion
• .Output Latches Provide a Usefu I Storage Register
•
•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low-power TTL Loads, One Low·power
CERAMIC PACKAGE

Me'4XXX
CASE 620

ORDERING INFORMATION

ltsuttlX
PLASTIC PACKAGE
CASE 648

Denotes

Schottky TTL Load to Two HTL Loads Over the Rated Temper- L Ceramic Package
P PlastIC Package
ature Range
A Extended Operating
Temperature Range
C L,m,ted OperatIng
Temperat~re Range

BLOCK DIAGRAM
2
Enable

1
Clock

15
AO

14
A1 VDD = Pin 16
VSS ~ Pin 8
7
A2

II
'-- Memory
1-: Address ~ Output 3

.A3~ W Matrix
(32 x 8) ~
Decoder
(1 of 8)
~
r--
Latch and
Buffer
p-<> BO

10
Address
A4 r---;-- ~
~
Output 4
Decoder
(32 x 8) I r-- Latch and ~B1
11
1 of 32 -L- (1 of 8) r-- Buffer
Address'
A5
Decoder
Address >-- Output
~ 5

AS
12 (32 x 8) I
-L-
Decoder
(1 of 8)
---.,- Latch and
Buffer
~B2

13 Address Output
A7
---c>- (32 x 8)
~

~
I Decoder
(1 of 8)
- ~
~
L--
Latch and
Buffer
~B3
6

3-36
MCM14524

MAXIMUM RATINGS IVolta'!es ref"renced to VSS I This device contams circuitry to protect the
Rating Symbol Value Unit inputs agarnst damage due to high static voltages
~~-I-y-V-O-I-!i-,g-"------------------+--V-D-D~--~O~5-t(-)-'~18--1---Vd-C~ or electric lields; however, it is advised that
normal precautions be taken to avoid applica·
Input VulldgP, All Inputs V 1n V,-dC_'-i
-0 S to VOO ",_O_5-+__ tions 01 any voltage higher than max imum rated
DC Current DnHn per Pin 10 mAde voltages to thIS high rmpedance circuit.
()C Unused inputs must always be tied to an
OperdtlrHJ Temperdture Rdnqe AL QpVICf' 55 to '125
appropriate logic voltage level le.g., either VSS
r_----------------~C~LC~·P~De~v~rc~"----r_----- 40 to '8~
or VDD)
St(Jr(l~W TernperJture Range 5t_- L _ _ _ _ _ _ _ _ _ _T (1 6" to '1 ~O "C
~ __ . _________. ________________- L _ _ _ ~ ____ ~

ELECTRICAL CHARACTERISTICS
-- - - - - - , - - -
Tlow 25 0 C Thigh'
VOO

Output Voltaqe
Characteristic
"0" Level
Symbol
-t-----
Vdc
----
5.0
_._- r-'--
Min Max
001
Min Typ Max
._----- r-------- - - - " -
0 0.01
----
Min Max
0.05
Unit
Vdc
VOL
10 001 0 0.01 0.05
15 0.01 0.01 0.05

--------_._----------
"1" Level

--
VOH 5.0
10
1~
4.99
999
14.99
- - - - f--------
___ ;__
-[ _~~99~
." 1 ~)
5.0

-------
10
4.95
9.95
14.95
Velc

---
NOise Immunity;' VNL Vdc
I V Clut II 8 VdcJ :, 0 1.5 - 1.5 l.75 1.4
V out 10 Vdcl 10 3.0 i 3.0 4.:'0 2.9
V out 1.5 Velci 15 3.75 3.75 6.75 3.75
0.8 Vdc) 1.4 1.5 Vdc

11
I V out VNH 50 15 '225
V out 1.0 Vdcl 10 2.9 3.0 4.50 3.0
V out 1.5 Vdcl IS 3.65 3.75 6.15 3.75
-- --.-~--~
1-------1------ ------ - .. ._-
Output Drtve Current (Al DeVIce) IOH mAdc
IVOH 2.5 Vdcl Source 5.0 -12 -10 -1.1 -0.7
IVOH 4.6 Velcl s.u -0.25 ·02 -0.36 -014
IVOH 95 Vdc) 10 0.62 -0.5 0.9 -035
IVOH 13.5 Vdcl 15 -18 -1 " 3.5 -1.1
IVOL 0.4 VcfcJ Sink IOl 5.0 064 051 0.88 0.36 mAde
{VOL 0.5 Vdc) 10 16 13 225 0.9
1.5 VdcJ 15 4.2 3.4 8.8 2.4
J--_ 1VOL - -1 - - - -1----- --
Output Drrve Current IClICP Devicel IOH mAdc
1VOH - 2.5 Vdc) Source 5.0 -1.0 -0.8 -17 -0.6
1VOH 0·4.6 Vdc) 5.0 -02 -0.16 -0.36 -0.12
IVOH - 9.5 Vdc) 10 -05 ·0.4 -0.9 -0.3
IVOH c 13.5 Vdcl 15 -1 4 -12 -3.5 -1.0
1VOL 00.4 Velc) S,nk IOl 5.0 0.52 044 0.88 0.36 mAde
IVOL = 0.5 VdcJ 10 13 1.1 2.25 0.9
IVOL = 1.5 Vdc) 15 3.6 3.0 8.8 2.4
Input Current IAL Device) lin 15 '0.1 ' 0.00001 '0.1 '1.0 /lAdc
Input Current ICl/CP Device) lin 15 ±1.0 ' 0.00001 ±1.0 ' 1.0 /lAdc
Input Capacitance Cin 5.0 pF
IVin 0)
Quiescent Current IAL Device) 100 5.0 5.0 0.010 5.0 150 /lAdc
(Per Package) 10 10 0.020 10 300
15 20 0.030 20 600
Quiescent Current ICL/CP Device) )00 5.0 50 0.010 50 375 /JAdc
(Per Package) 10 100 0.020 100 750
15 200 0,030 200 1500
Total Supply Current"t IT 5.0 IT = 11.6/JA/kHz) I + IDO /lAdc
(Dynamic pl·us Quiescent, 10 IT = (3.2 /JA/kHz) I + 100
Per Package) 15 IT = 14.8 /JA/kHz) I + 100
ICL - 50 pF on all outputs, all
buffers switching)

"Tlow" -55 0 C lor AL Device, -400C for CL/CP Device

Thigh = +125 0 C lor AL Device, +85 0 C lor Cl/CP Oevice.
p:Noise Immunity specified for worst-case input combination
tTo calculate total supply.current at loads other than 50 pF
ITICL) = ITI50 pF) + 1 x 10- 3 ICL -50) VODI
where: IT is in /JA Iper package), CL in pF, VOD in Vdc, and I in kHz is input frequency .
• "The lormulas given are lor the typical characteristics only at 25°C.

3-37
MCM14524

SWITCHING CHARACTERISTICS* (CL = 50 pF T A = 25 0 C)

Characteristic Symbol VDD Min Typ Max Unit
Output Rise Time tTLH ns
tTLH, tTHL = (3.0 ns/pF) CL + 30 ns 5.0 - 180 360
tTLH, tTHL = (1.5 ns/pF) CL + 15 ns 10 - 90 180
tTLH, tTHL = (1.1 ns/pF) CL+ 10 ns 15 - 65 130
Output Fall Time tTHL ns
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns 5.0 - 100 200
tTLH, tTHL = 10.75ns/pF) CL + 12.5 ns 10 - 50 100
tTLH, tTHL = 10.55'ns/pF) CL + 9.5 ns 15 - 40 80
Clock Read Access Delay Time taccC ns
taccc = 11.7 ns/pF) CL + 1265 ns 5.0 - 1350 4000
taccC = 10.66 ns/pF) CL + 517 ns 10 - 550 1600
taccC = 10.5 ns/pF) CL + 325 ns 15 - 350 .1200
Enable Access Delay Time taccEn ns
taecEn = 11.7 ns/pF) CL + 160 ns 5.0 - 245 615
taccEn = 10.66 ns/pF) CL + 77 ns 10 - 110 265
~n =~~/!,F)_~~O ns ___________ --------- 1---.,-----
15 - 75 190
Clock Pulse Width* tWH 5.0 450 150 - ns
10 165 55 -
15 125 35 -
tWL 5.0 3600 1200 - ns
10 1425 475 -
15 1070 300 -
- - - t---
Maximum Low Clock Pulse Width # tWL 5.0 2.0 10 - ms
~
10 0.9 3.0 -
15 0.1 0.3 -
Address Setup·Time tsulA) 5.0 0 0 - ns
10 0 0 -
15 0 0 -
-----
Address Hold Tir')1e thlA) 5.0 0 0 - ns
10 0 0 -
15 0 0 -
Clock to Enable Setup Time tsulcl) 5.0 4275 1425 - ns
10 1725 575 -
15 1295 400 -
Clock to Enable Hold Time th-(el) 5.0 150 0 - 'ns
10 75 0 -
-
-
*The clock can remain high indefinitely with the data remaining latched.
• 15 55 .0

#If clo~k stays low too long, the dynamically stored data will leak off and will have to tie recalled.

FIGURE 1 - OUTPUT DRIVE CURRENT FIGURE 2 - SWITCHING TIME TEST CIRCUIT

TEST CIRCUIT (Refer to timing diagram)

,. Source current. address ROM to obtain a"'"

Address ROM to obtain level change when
on all four outputs (80 thru 83),
clocking anv one address line.
2. Sink current. address ROM to obtain a "0"
on all four outputs (80 thru 83).

3-38
MCM14524

MEMORY READ CYCLE TIMING DIAGRAMS

a) Using Clock to
Read Memory
Address Address Valid
Input

Enable
Input in this diagram to read memory

Data
Output if clock ishigh
~------~~------~------L-------------VOL

• Data outputs always go to the logic "1" state before the data is valid
between accessing successive "O's"
b) Using the Enable •• Outputs forced to "0" by Enable.
to Read Memory

Clock
Input

Enable
__- - - - - tWH
tWL - ,...-_______________

•
Input

Data
Outputs Access "0"

t In this mode of operation, the negative going edge of Enable tThe data outputs are valid without the logic "1" pulSE' occurring
should occur on or before the clock negative edge. during the access cycle as shown in a) above.

CUSTOM PROGRAMMING

By the programming of a single photomask for the MCM14524,

the customer may specify the content of the memory.

Address Inputs:
Words are numbered 0 through 255 and are addressed using
sequential addressing of Address leads AO through A 7 with AO
as the least significant digit.
Logic "0" is defined as a "low" Address input (VI L).
Logic "'" is defined as a "high" Address input (VI H).

~
WORD
Word 0
A7
0
A6
0
A5
0
A4
0
A3
0
A2
0
Al
0
AO
0
Word 1 0 0 0 0 0 0 0 1
Word 2 0 0 0 0 0 0 1 0
Word 3 0 0 0 0 0 0 1 1

Word 255 1 1 1 1 1 1 1 1

3-39
 MCM14524

TRUTH TABLE
CLOCK ENABLE BO I B1 I B2 I B3

VDD~ VSS 1
1
<Add·ress) I I
(Ad:ress) (Ad:ress)
OUTPUT DATA
I <Add:ess)
VDD BINARY TO HEXA-
VSS .-./'" LATCHES DECIMAL CON-
X 0 0 I 0 0I 1 0
VERSION TABLE
x = Don't Care BINARY
., nd icates contents of specified Address will appear at outputs as stated above.
WORD CARD
DESIRED CHARACTER
o 0 0 0 0
o 0 0 1 1
Two methods may be used to transmit the custom memory o 0 1 0 2
pattern to Motorola. o 0 1 1 3
o 1 o 0 4
METHOD A: PUNCHED COMPUTER CARDS o 1 o 1 5
o 1 1 0 6
o 1 1 1 7
A binary coded decimal equivalent of each desired output may 1 0 o 0 8
be punched in standard computer cards (four cards are required 1 0 o 1 9
for all 256 words) in numerical (word number) order. 64 words 1 0 1 0 A

per card are punched in columns 12 thru 75 using the Binary to 1 0 1 1 B

Hexadecimal conversion table. Columns 77 and 78 are used 1 1 o 0 C

1 1 o 1 D
to number the cards, which must be in numerical order. Please 1 1 1 0 E
use characters as shown in the table when punching computer cards. 1 1 1 1 F

II
ROM SAMPLE WORD PROGRAMMING FOR PUNCHED CARD
SAMPLE WORD
ADDRESS INPUTS OUTPUTS
WORD CARD
NUMBER A7 A6 A5 A4 A3 A2 Al AO B3 B2 B1 BO CHARACTER
0 0 0 0 0 il 0 0 .0 0 0 0 0 0
Shown in columns
1 0 0 0 0 0 0 0 1 0 0 1 1 3
12 ~15 on card
2 0 0 0 0 0 0 1 0 0 0 1 1 3 } below
3 0 0 0 0 0 0 1 1 0 0 0 0 0

255 1 1 1 1 1 1 1 1 1 0 1 0 A

WORD NUMBER NO.,

Card

00000000000100111111111111111111111111111111111111111111111111111111111111101000
I 1 1 4 5 I 1 I , II 11 U I] 14 15 11 IJ \I l' 2111 22712.15 H 11 11 n 1111 12 n U 35 n 11 lilt 41 4' 041 .. 45 "4' •• '" ~ ~1 ~l ~l ~ ~5 ~ ~J ~. ~t SO $I 52 Sl ,. '5 is &1" " IG 11 11 13 I. I~ IS 11 11 11 U
11111111111111111111111111111111111111111111111111111111111111111111111111111111
2 22 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2. 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
3 3 3 3 3 3 3 3 33 3 3113 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 33 3 3 3 3 3 3 3 3 3 3 3 3 3 3

444444444444444444444444444444~444444444

5555555555555555555555555555555555555555555555555555 5 5 5 5 5 5 5 5 5 5 55 5 555555555555555
6 6 6& 55 56 55 & 6 6 66 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6
11111 711 711111111111111 71111111 711 71111111111 711111111 7 71 7 7 7 71 7 7 77 7 71 7 7 7 7 7 7 7 7 7 7 7
1181811118188888881aal88888888888888l8888888888888888888888888888888888888888888
9999999999999999999999 9999 99999999999 999 9 9 9 9 9 9 9 9 9 9.9 9 9999999 999 9 999 9 9 9 9 99 99999 999
1 l 1 • ~ , 1 , , "11 U U U U 15 11 I' " 21 H 12 23 2. IS " iT at a 11 31 12 II 14 3$ 3. J1 II 3~.' ., '2'~" .~ U H 4i'9 )0 51 5253 $4 % 56 51 H 59 'J 'I iZ n tt"'~ _5 ~1 fa E9 lD 11 12 13 a 1~ !i II 18 " "
GLOBE NO.1 STANDARD FORM 5081

3-40
MCM14524

METHOD B: TRUTH TABLE

For customers who do not have access to punch cards, Motorola

will accept Truth Tables. When filling out the table, use the 0 to F
hexidecimal character in column "C".

CUSTOM PROGRAM for the MCM14524 Read Only Memory

WORD C WORD C WORD C WORD C WORD C

0 51 102 153 204
1 52 103 154 205
2 53 104 155 206
3 54 105 156 207
4 55 106 157 208
5 56 107 158 209
6 57 108 159 210
7 58 109 160 211
8 59 110 161 212
9 60 111 162 213
10 61 112 163 214
11 62 113 164 215

II
12 63 114 165 216
13 64 115 166 217
14 65 116 1.67 218
15 66 117 168 219
16 67 118 169 220
17 68 119 170 221
18 69 120 171 222
19 70 121 172 223
20 71 122 173 224
21 72 123 174 225
22 73 124 175 226
23 74 125 176 227
24 75 126 177 228
25 76 127 ,178 229
26 77 128 179 230 ,
27 78 129 180 231
28 79 130 181 232
29 80 131 182 233
30 81 132 183 234
3.1 82 133 184 235
32 83 134 185 236
33 84 135 186 237
34 85 136 187 238
35 86 137 188 239
36 87 138 189 240
37 88 139 190 241
38 89 140 191 242
39 90 141 192 ' 243
40 91 142 193 244
41 92 143 194 245
42 93 144 195 246
43 94 145 196 247
44 95 146 197 248
45 96 147 198 249
46 97 148 199 250
47 98 149 200 251
48 99 150 201 252
49 100 151 202 253
50 101 152 203 254
255

3-41
•

3-42
 Bipolar Memories . •
TTL, MECL-RAM, PROM

4-1
•

4-2
 ® MOTOROLA MCM93415

1024·BIT RANDOM ACCESS MEMORY

TTL
The MCM93415 is a 1024·bit Read/Write RAM organized 1024 1024 X 1 BIT
words by 1 bit. RANDOM ACCESS MEMORY
The MCM93415 is designed for buffer control storage and high
perform ance mai n memory appl icati ons, and has a typical access
time of 35 ns.
The MCM93415 has full decoding on·ch ip, separate data
input and data output lines, and an active low chip select. The
F SUFFIX
device is fully compatible with standard DTL and TTL logic
families and features an uncommitted collector output for ease CASE 650

of memory expansion.

• Uncommitted Collector Output

• TTL Inputs and Output
• Non·1 nverti ng Data Output
• High Speed -
Access Time - 35 ns Typical
Chip Select - 15 ns Typical
• Power Dissipation Decreases with Increasing Temperature
D SUFFIX
• Power Dissipation 0.5 mW/Bit Typical CERAMIC PACKAGE

• Organized ~ 024 Words X 1 Bit CASE 620

Sense Amp
and
Write DrIvers
BLOCK DIAGRAM

}-----<> D au t
PIN ASSIGNMENT
P SUFFIX
PLASTIC PACKAGE
CASE 648

•
16

15
Word 32 X 32
Drivers Array 14 3 14

4 13

12

CS 11

10
15 8
Din
1 of 32 1 of 32
Decoder Decoder Pin Designation
cs Chip Select

AO-A9 Address Inputs

WE Write Enable
13 VCC = Pin 16
Gnd = Pin 8 Din Data Input
AO Al A2 A3 A4 A5 A6 A 7 A8 A9
D out Data Output

4-3
 MCM93415

FUNCTIONAL DESCRIPTION

The MCM93415 is a fully decoded 1024-bit Random Access VCC(Min) .;; RL';; VCC(Min)-VOH
Memory organized 1024 words by one bit. Bit selection is
IOL - FO( 1.6) n(lCEX) + FO(O.04)
achieved by means of a 10-bit address, AO to A9.
The Chip Select input provides for memory array expansion. RLisinkn
For large memories, the fast chip select access time permits the n = number of wired-OR outputs tied together
decoding of Chip Select (CS) from the address without affecting FO = number of TTL Unit Loads (UL) driven
system performance. ICEX = Memory Output Leakage Current
The read and write operations are controlled by the state of VOH = Required Output High Level at Output Node
the active low Write Enable (WE, Pin 14). With WE held low and IOL = Output Low Current
the chip selected, the data at Din is written into the addressed
location. To read, WE is held high and the chip selected. Data in The minimum R L value is limited by output current sinking
the specified location is presented at D out and is non-inverted. ability. The maximum R L villue is determined by the output and
Uncommitted collector outputs are provided to allow wired- input leakage current which must be supplied to hold the output
OR applications. In any application an external pull-up resistor o.f at VOH. One Unit Load = 40}JA High/1.6 mA Low. .
RL value must be used to provide a high at the output when it is
off. Any R L value within the range specifi~d be.low may be used.

ABSOLUTE MAXIMUM R.ATINGS (Note 1) TRUTH TABLE

Storage Temperature Inputs Output

Ceramic Package (0 and F Suffix) -55°C to +165 0 C Open
Plastic Package (P Suffix) -55°C to +125 0 C -
CS WE Din Collector Mode
. Operating Junction Temperature, T J H X X H Not Selected
Ceram ic Package (0 and F Suffix) < 165°C L L L H Write "0"
Plastic Package (P Suffix) < 125°C
L L H H Write "1"
. V CC Pin Potential to Ground Pin -0.5 V to +7.0 V
L H X D out Read
Input Voltage (del -0.5 V to +5.5 V
Voltage Appl ied to Outputs (Output High) -0.5 V to +5.5 V H = High Voltage Level
L = Low Voltage Level
Output Curfent (del (Output Low) +20 mA
X = Don't Care (High or Low)
Input Current (de) _-12 mA to +5.0 mA
~

NOTE1: Device damage may oeeur if ABSOLUTE MAXIMUM RATINGS are exceeded .

•
GUARANTEED OPERATING RANGES (Note 2)
Supply Voltage (Vec)
Part Number Min I Nom I Max Ambient Temperature (T A)
MCM93415DC, PC 4.75 V 1 5.0 V I 5.25 V OoC to +75 0 C
MCM93415FM, OM 4.50 V 1 5.0 V I 5.50 V -55°C to +125 0 C

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted)

Limits
Symbol Characteristic Min Max Unit Conditions
VOL Output Low Voltage 0.45 Vde VCC = Min, IOL = 16 mA
VIH Input High Voltage 2.1 Vdc Guaranteed Input High Voltage for All Inputs
VIL Input Low Voltage 0.8 Vde Guaranteealnpu LOW Vol\oll" 'u, '~Ul>

IlL Input Low Current -400 }JAdc VCC = Max, Vin = 0.4 V
IIH Input High Current 40 }JAde Vec - Max, Vin = 4.5 V
1.0 mAde Vce = Max, Vin = 5.25 V
ICEX Output Leakage Current 100 }JAde VCC = Max, V out = 4.5 V
VCO Input Oiod~ Clamp Voltage -1.5 Vde Vce = Max, lin = -10 mA
ICC Power Supply Current 130 mAde TA - Max I
Vcc = Max,
155 mAde TA = ooc 1 All Inputs Grounded
170 mAde TA = Min 1

4-4
MCM93415

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature unless otherwise noted)

AC TEST LOAD AND WAVEFORM

Loading Condition Input Pulses

VCC

--'---.---.--------.-\.- --
All Input Pulses

~
$It
90%
3.5Vp·~1 t--------~\;--10%
Gnd "" --,
II,--10 ns __
: I
1---10 ns
I '~ _ _ _ _ _ __

MCM93415 30 pF 3.~ ~ - - - - - - - -~ ~ - -10%

Capacitance J._p~.;.,--------1~--90%
( Including ~:I
Gnd-= --i 1.-,0 ns
I'
-.j \--10 ns
Scope and Jig)

MCM93415DC,PC MCM93415DM,FM
Symbol Characteristic (Notes 2, 3) Min Max Min Max Unit Conditions
READ MODE DELAY TIMES
tACS Chip Select Time 35 45 See Test Circuit
tRCS Ch ip Select Recovery Time 35 50 and Waveforms

tAA Address Access Time 45 60

WRITE MODE DELAY TIMES
tws Write Disable Time 35 45 See Test Circuit
tWR Write Recovery Time 40 50 and Waveforms
INPUT TIMING REQUIREMENTS

•
tw Write Pulse Width (to guarantee write) 30 40 See Test Circuit
tWSD Data Setup Time Prior to Write and Waveforms
tWHD Data Hold Time After Write
tWSA Address Setup Time (at tw ~ Min) 10 15
tWHA Address Hold Time 10 10
tWSCS Ch ip Sel ect Setup Time
tWHCS Ch ip Select Hold Time

READ OPERATION TIMING DIAGRAM

Propagation Delay from Chip Select Propagation Delay from Address Inputs

Chip Select ~ j AO-Ag--y

,'-----..... ,
}., I Addre~I....._ _ _ _ _ _ _ __

D out
I

Data Output - - - - " " - - - - . \

I
I
I
:

i\,---:-----,
r I
D out
I
I

:
Data O_u_tP_u_t_---::_ _ _ _ _ _" ' - -
V--
I I I I I I
tACS ---t-----I I" I I tRCS t--- tAA ----t
(All Time Measurements Referenced to 1.5 V)

4-5
 MCM93415

WRITE CYCLE TIMING

cs
Chip Select '\I
J
I

~~;r:'~1 _n_p_ut_s_ _ _....

: __ ..J~ ~",,---;i----
~~~a Input
_ _ _ _-+-_ _--+___..J
~ ~!
I i :i
WE 1------- t W - - - I J ; 1 I I
Write Enable ,\ tWHDI I
I I I l..-tWHA--l I
ItWSD-i-----J ~tWHCS_____i
D out
Data Output
I . i--tWSA--l
~twscs----t
111 I \1
_____________ ~I---J II I ~ ___________
I I I
I I I
tws ---f----.i f------I-tw R

(All Time Measurements Referenced to 1.5 V)

• NOTE 2: DC and AC specifications limits guaranteed with 500 linear feet per minute blown air. Contact your Motorola Sales Representative
if extended temperature or modified-operating c0nditions are desired.

Package
o Suffix
F Suffix
eJA (Junction to
Blown
50 0 C/W
55 0 C/W
Ambient)
Still
85 0 C/W
90 0 C/W
eJC (Junction to Case)
15 0 C!W
150 C/W
P Suffix 65 0 C/W 100 0 C/W 25 0 C/W

NOTE 3: The AG limits are lluaranteed to be the worst case bit in the memory.

4-6
 ® MOTOROLA MCM93425

1024-BIT RANDOM ACCESS MEMORY

The MCM93425 is a 1024-bit Read/Write RAM, organized 1024 TTL

words by 1 bit. 1024 X 1 BIT
The MCM93425 is designed for high performance main memory
I.
RANDOM ACCESS MEMORY
and control storage applications and has a typical address time of
35 ns.
The MCM93425 has full decoding on-chip, separate data input
and data output lines, and an active low-chip select and write enable.
The device is fully compatible with standard DTL and TTL logic
fam il ies. A three-state output is provided to drive bus-organized F SUFFIX
CERAMIC PACKAGE
systems and/or highly capacitive loads. CASE 650

• . Three-State Output
• TTL Inputs and Output
• Non-Inverting Data Output

• High Speed -
Access Time - 35 ns Typical
Chip Select - 15 ns Typical
• Power Dissipation - 0.5 mW/Bit Typical
D SUFFIX
• Power Dissipation Decreases With Increasing Temperature
CERAMIC PACKAGE
CASE 620

•
BLOCK DIAGRAM

P SUFFIX
PLASTIC PACKAGE
Sense Amp
CASE 648
and Dout
Write Drivers

PIN ASSIGNMENT

Word 32 X 32 16
Drivers Array 14
WE 15
3 14
4 13
cs 12
6 11
15
Din 10
1 of 32 1 of 32 9
8
Decoder Decoder

Pin Description

VCC = Pin 16
Cs Chip Select
13
Gnd = Pin 8 AO-AS Address Inputs
AO Al A2A3A4A5A6A7A8 A9
WE Write Enable

Din Data Input

NOTE: Logic driving sense amp/write drivers depicts
Dout Data Output
negative-only write used on C4m.

4-7
 MCM93425

FUNCTIONAL DESCRIPTION

The MCM93425 is a fully decoded 1024-bit Random Access low, the data at Din is written into the addressed location. To
Memory organized 1024 words by one bit. Word selection is read, WE is held high and Cs held low. Data in the specified
achieved by means of a 10-bit address, AO-A9. location is presented at D out and is non-inverted.
The Chip Select (Cs) input provides for memory array expan- The three-state output provides drive capability for higher
sion. Fa"r large memories, the fast chip select time permits the speeds with· capacitive load systems. The third. state (high
decoding of chip select from the address without increasing impedance) allows bus organized systems where multiple outputs
address access time. are connected to a common bus.
The read and write operations are controlled by the state of During writing, the output is held in the high-impedance state.
the active low Write Enable (WE, Pin 14). With WE and Cs held

ABSOLUTE MAXIMUM RATINGS (Note 1) TRUTH TABLE

Storage Temperature Inputs Output
Ceramic Package (D and F Suffix) -55 0 C to +165 0 C CS WE Din Dout Mode
Plastic Package (P Suffix) -55 0 C to +125 0 C X High Z
H X Not Selected
Operating Junction Temperature, T J
L L L High Z Write "0"
Ceramic Package (D and F Suffix) < 1650 C
L L H High Z Write "1"
Plastic Package (P Suf~ix) < 1250 C
L H X D out Read
V CC Pin Potential to Ground Pin -0.5 V to +7.0 V
Input Voltage (dc) -0.5 V to +5.5 V
Voltage Applied to Outputs (Output High) -0.5 V to +5.5 V H = H j gh Voltage Level
L = Low Voltage Level
Output Current (dc) (Output Low) +20 mA
X = Don't Care (High or Low)
Input Current (de) -12 mA to +5.0 mA

NOTE1: Device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.

GUARANTEED OPERATING RANGES (Notes 2 and 3)

Supply Voltage (VCC)
Part Number Min I Nom 1 Max Ambient Temperature (T A)
I I 5.25 V oOe to +75 0 C

•
MCM93425De, PC 4.75 V 5.0 V
MCM93425FM, DM 4.50 V I 5.0V 1 5.50 V -55°C to +125 0 C

DC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature range unless otherwise noted)

Limits
Symbol Characteristic Min Max Units Conditions
VOL Output Low Voltage 0.45 Vdc Vec = Min, IOL = 16 mA
VIH Input High Voltage 2.1 Vdc Guaranteed Input High Voltage for all Inputs
VIL Input Low Voltage 0.8 Vdc Guaranteed Input Low Voltage for all Inputs
IlL Input Low Current -400 /-lAdc VCC = Max, Vin = 0.4 V
IIH Input High Current 40 /-lAdc Vec = Max, Vin = 4.5 V
1.0 mAdc Vee = Max, Vin = 5.25 V
loff Output Current (High Z) 50 /-lAdc VCC - Max, V out - 2.4 V
-50 VCC = Max, V out = 0.5 V
lOS Output Current Short Circuit to Ground -100 mAdc Vec = Max
VOH Output High Voltage I MCM93425DC, PC 2.4 Vdc IOH = -10.3 mA, VCC = 5.0 V ±5%
I MCM93425FM, DM 2.4 Vdc IOH = -5.2 mA
VCD Input Diode Clamp Voltage -1.5 Vdc Vce - Max, lin - -10 mA
IC_C Power Supply Current 130 mAdc TA = Max I VCC =_Max,
155 mAdc TA = OOC I
170 mAdc TA = Min I All Inputs Grounded

4-8
MCM93425

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature unless otherwise notedf

AC TEST LOAD AND WAVEFORMS

Loading Conditions Input Pulses

All Input Pulses

~
VCC --------- -~--90%
3.5 V p _p
I I
,- i - - - - - - -,- \,..-_1_0_%_ __
I I I I
-=~ 1--10 ns ---1 1--10 ns
30 pF

~-------A-'"'
- f- - - - - - - - - -
-r- -
I I
I I
, :
90%

Load A Load B
- ---1 r--' 0 ns ---i 1--'0 ns

MCM93425DC, PC MCM93425DM, FM
Symbol Characteristic (Notes 2,"4) Min Max Min Max Units Conditions
READ MODE DELAY TIMES
tACS Chip Select Time 35 45 See Test Circuit
tZRCS Chip Select to High Z 35 50 and Waveforms
tAA Address Access Time 45 60
WRITE MODE DELAY TIMES
tzws Write Disable to High Z 35 45 See Test Circuit

I
tWR Write Recovery Time <10 5U and Waveforms
INPUT TIMING REQUIREMENTS
tw Write Pulse Width (to guarantee write) 30 40 See Test Circuit
tWSD Data Setup Time Prior to Write 5 and Waveforms
tWHD Data Hold Time After Write 5
tWSA Address Setup Time (at tw = Min) 10 15
tWHA Address Hold Time 10 10
tWSCS Chip Select Setup Time 5 5
tWHCS Chip Select Hold Time 5 5

READ OPERATION TIMING DIAGRAM

Propagation Delay from Chip Select Propagation Delay from Address Inut

AO-A9 ~
cs Address Inputs ---.1':\----------
Chip Select I
I

~
D out
D out
Load A
D out
Data Output
:
----~I~--------- I
Load B
~tAA--i

(All time measurements referenced to 1.5 V)

4-9
 MCM93425

WRITE CYCLE TIMING

Cs
Chip Select

AO-A9
Address

Din
Data Input

WE
Write Enable

D out
Data Output

(All above measurements reference to 1.5 V)

WRITE ENABLE TO HIGH Z DELAY

5V
WE
Write Enable

D
~15V
TZWS-..j~_ _ _ _
r-
out
Data Output "0" Level _ 0.5 V High Z

"1" Level

•
Oout'
Data Output

Load C

Propagation Delay from Chip Select to High Z

Cs
Chip Select 11.5 V

~tZRCS
D out ,----
Data Outp_u_t_"_O_"_L_e_ve_I_-J_ 0.5 V High Z

D out -------t-
"1" Level
0.5 V
' - _ _ _ _ High Z
Data Output

--------------~--n(A'>TI,-1t.-:Z;;:x-;-;X:;cx~p~a;;-;;ra'"m;oe...
te>i'r<s"'ar"'e7m"'e..a""suTIr""eo_at a delta of 6.5 • Ii 0", tl e logic Ie el 8 e usi"!llea8 C)

NOTE 2: DC and AC specifications limits guaranteed with 500 liriear feet per minute blown air. Contact your Motorola Sales Representative
if extended temperature or modified operating conditions are desired.

eJA (Junction to·Ambient)

Package Blown Still eJC (Junction to Case)
D Suffix 50 o C/W 85 0 C/W 15 0 C/W
F Suffix 55 0 C/W 90 o C/W 150 C/W
P Suffix 65 0 C/W 100o C/W 25 0 C/W

NOTE 3: Output short circuit conditions must not exceed 1 second duration.
NOTE 4: The maximum address access time is guaranteed to be the worst case bit in the memory.

4-10
 ® MOTOROLA
MCM5303
MCIS003
MCM5304
MCMS004
512-BIT PROGRAMMABLE READ ONLY MEMORY

The MCM5303/5003 and MCM5304/5004 are monolithic bipolar

512-bit Programmable Read Only Memories (PROMs) organized as
MTIL
64 eight-bit words. These memories are field programmable, i.e., 512-BIT PROGRAMMABLE
the user can custom program these memories himself. Metal inter-
READ ONLy MEMORY
connections establish each bit initially in the logic "a" state. By
"blowing" appropriate nichrome resistors and thus breaking metali-
zation links these bits can be changed to the logic "1" state to meet
specific program requirements. Detailed programming instructions
are contained in this data sheet.
The MCM5303/5003 and MCM5304/5004 have six address inputs
to select the proper word and two chip enable inputs, as well as
outputs for each o'f the eight bits.
The MCM5303 and MCM5304 are specified over an operating
temperature range of -550 C to +1250 C. The MCM5003 and
MCM5004 are specified over an operating temperature range of
OOC to +70 0 C.
The MCM5303 and MCM5003 have positive enables with open AL SUFFIX
collector outputs. The MCM5304 and MCM5004 have positive en- CASE 684
ables with 2.0 kilohm pullup resistors on the collector outputs. CERAMIC PACKAGE

MAXIMUM RATINGS
Rating Symbol Value Unit
Supply Voltage VCC -0.5 to +7.0 Vdc

•
Input Voltage Vin -1.0to+5.5 Vdc
Output Voltage (Open collectors) VOH -0.5 to +7.0 Vdc
Thermal Resistance °JA 100 °C/W
Operating Temperature Range TA oC L SUFFIX
MCM5303, MCM5304 -55 to +125 CERAMIC PACKAGE
MCM5003, MCM5004 o to +70 CASE 623

Storage Temperature Range Tst.g -55 to +165 oC

PIN ASSIGNMENT

FEATURES:
24
• Positive Logic for Both I nputs and Outputs
Logic "a" = Output Device ON (VoLl N.C. G2 23
Logic "1" = Output Device OFF (VOH) AO BO 22
• Logic Levels Compatible with MDTL and All MTTL Families Al Bl 21
• Ninth Bit Available f.or Circuit Test A2 B2 20
• Access Time < 75 ns CEl B3 19
• Outputs Sink 12 mA Open Collector, 10 mA with Pull up
CE2 84 18
Resistors
A3 85 17
• Field Programmable by Blowing Nichrome Links
A4 B6 16
• Hermetic Package
A5 B7 15
APPLICATIONS: • Code Conversion
11 Gl 14
• Look Up Tables • Number Conversion
N.C. G2 13
• Micro Programs • Handom Logic
• Decode Functions • Character Generation

4-11
 MCM5303/MCM5003, MCM5304/MCM5004

DC ELECTRICAL CHARACTERISTICS (T A = -55°C to +1250 C for MCM5303·and MCM5304,

OoC to +700 C for MCM5003 and MCM5004 unless otherwise noted)
\
Ch.lICteristic Symbol Min Max Unit
Input Fonvard Current
(VI L = 0.4 Vdc, VCC = 5.25 Vdcl IlL - 1.6 mAdc
Input Leakage Currerit
(VIH = VCC = 5.26 Vdcl IIH - 100 /JAdc
Logic "0" Output Voltage· VOL Vde
(TA = OoC to +1250 C for MCM5303 and MCM5304,
OOc to +700C for MCM5003 and MCM5004)
(lOL = 12 mAde, VCC = 4.75 Vdcl Open Collectors - 0.45
(lOL = 10 mAde, VCC = 4.75 Vdcl Pullup Resistors - 0.45
(T A = -55°C for MCM5303 and MCM5304)
(lOL = 12 mAde, VCC = 4.75 Vdcl Open Collectors - 0.50
(lOL'= 10 mAde, VCC = 4.75 Vdc) Pull up Resistors - 0.50

Logic "1" Output Voltage VOH 2.5 - Vdc

(lOH = -0.5 mAdc, VCC = 4.75 Vdcl Pullup Resistors
Output Leakage Current
(VCC = VCEX = 5.25 Vdcl Open Collectors ICEX - 200 /JAdc
Power Supply Drain Current ICC mAdc
(Enable and all other inputs Open Collectors - 95
grounded, VCC ,; 5.0 Vdcl Pullup Resistors - 120

AC ELECTRICAL CHARACTERISTICS (VCC ~ 5.0 Vdc, T A·- 25 0 C)

Access Times * (3QpF Load)
Address to Output
Enable to Output

·Pin 13 is schematically connected to G2. For optimum propagation delay and VOL characteristics, externally tie Pin 13 to.Pin 23 (G2).

SWITCHING TIME TEST CIRCUIT

TPout VCC = 5.0 Vdc

•
CE1 BO

:H:':.
CE2 B1
Enable Input Test:
AO B2 Connect data inputs to VIHX.
A1 B3 Address Input Test:
A2 B4 Inputs not under testleit open.
A3 B5 High impedance probes m'ust be used
A4 B6 when making these measurements.
A5 B7
-= VIHX = 3.0 Vdc

Bl:.OCK DIAGRAM

AO
A1
Memory Matrix
A2 (64 X9)
NOTE: Under normal operating A3 With
Nichrome Resistors
nected to ground. Both eEl and A5 10
eE2 must be high to enable the
memory.

CEl
eE2

Vee = Pin 24
Gl = Pin""
G2 = Pin 13, Pin 23
14 15 16 17 18 19 20 21 22
Test B7 B6 85 B4 83 B2 Bl BO
B8

4-12
MCM5303/MCM5003, MCM5304/MCM5004

PROGRAMMING THE MCM5303/5003 AND MCM5304/5004

The table and diagram below give instructions for field programming the MCM5303/5003 and MCM5304/5004.
All data given is for ambient temperatures of 250 C. If necessary, further programming aid can be obtained from Motorola
engineering and product marketing personnel by contacting your nearest Motorola sales office.

Programming Voltage Limits

Symbol Value Unit
Address and Chip Enable Voltages VIH -4.0 to +5.0 Vdc
VIL -6.0 to -5.2
Power Supply Voltage VCC +5.0±5% Vdc
Gl Voltage VGl -6.0±.5% Vdc
G2 Voltage VG2 0.0 Vdc
Program Voltage at Desired Bit Output VBP -6.0 ±.5% Vdc

Programming Procedure

-5.0 Vdc
1. Select the address code desired. Connect low (logic "0")
inputs to -6.0 Vdc nominal. Leave high (logic "1") inputs Vee To each
To ,II 8 n ::: logic "1"
unconnected. An' IOlJic "0"

2. With the output voltage of a 120-mA current generator DeVice

clamped to -6.0 Vdc, apply a negativelloing current pulse
of 800 ms duration to any output to be programmed as
a logic "1".
3. Repeat step 2 for each output to be programmed as a GI
logic "1", one bit at a time. -60Vdc

•
4. Select next address code desired and repeat steps 2 and 3.

Link Programming Diagram

Selected Word Line

r---------------------, I r------------------,
I
I : Program Circuil I
I I I
I :
I I
II II
0----------------- J I

'I:
~---- ----------------1 I
II
I
II
I . Sense

6_______~r~a~
Memory I
I
I
R2 Amplifier L_________:____ ____J
I I

I ______ _ I
I
I
I
I
I
L
I
_________________________J I
I
I
II
I
Programming Voltages I
Inputs: I Bit Output
+5.0 Vdc ;;'Iogic "''';;' -4.0 Vdc II
-6.0 Vdc .;; logic "0"';; -5.2 Vdc IL. _________________ _
Outputs:
Program logic ",", -6.0 Volts
Program logic "0'" 0.0 Volts or Open Circuit

4-13
 MCM5303/MCM5003, MCM5304/MCM5004

TRUTH TABLE FORMAT

BIT 7 BIT 6 BIT & 'BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT & BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

~~:~~~~-If---i--+--+--+-~-;-~
WOROO
WORO 1

:~:~~:~-If--;--+--+--+-~-;-~
WORO 2
WOR03
WOR04
WORO & ~~:~~~ ~~f--+--+-~-~-~-~~
~~:~~:~-If--+--+--+--+-;--;-~
WORD 6
WORD 7
WORO 8 WORD 40
WORD 9 WOR041 ~~f--+--+-~-~-~-~~

~~:~ ~~ ~-If---i---i--+--+--+--+--l ~~~~:~~-If--+--+--+--+-;--+-~

:~:~ ~~ ~-If---i---i--+--+--+--+--l ~~:~::f--I--+--+--+--+-;--+-~
:~ ~~ :~ ~-If---i---i.,---+--+--+--+--l :~:~:;f--I~-+--+--+--+-;--+-~
WOAD 16
WORD17~~~~-~--+--+--+--+-~ :~:~:: ~~'---+--+-~-~-~-~~
~~:~::~-If---i---i--+--+--+--+--l ~g;g~~f--I~-+--+--+--+-4--+-~
~~:g~~~~f---i---i--+--+--+--+--l ~~:~ ~; f--I--t--+--+--+--t--+-~
:~:~;~~~f---i---i--+--+--+--+--l :~:~~:~-~-I--+--+--+-~-~--4
:~:g;:~~~~-~--+--+--+--+-~ ~~:~~; ~~~-+--+-~-~-~-~~
:g:g ;; ~~~~-~--+--+--+--+-~ ~g:g~~f--Ir--t--+--+--+--t--~--1
:~:~ ;! ~-If---i---i--+--+--+--+--l ~~:~;~ f--Ir--+--+--+--+--t--~~
~~:g;~~-If---i---i--+--+--+--+--l ~~:~~~~-If--+--+--+--+-4--+-~

WHY niE NINTH BIT?

The ninth bit was designed into the MCM5303/ without destroying any of the normal 64x8 bit array.
MCM5003 and the MCM5304/MCM5004 because Functional and ac performance are assured by
field-programmable ROMs present testing problems verifying that changes do occur at the outputs as the
not encountered with conventional mask-program- addresses change. This is important in that all of the
mabie ROMs. outputs are in a logic "0" state regardless of the
Three areas of testing are affected: Program address selected, and no way is available to determine
Element Testing, Functional Testing, and AC Testing. whether the functions are correctly operating without

•
The ninth bit helps to solve the problem of Program the ninth testing bit.
Element Testing by assuring that links can be blown

4-14
 ® MOTOROLA MCM7620
MCM7621

2048-BIT PROGRAMMABLE READ ONLY MEMORY MTTL

The MCM7620/MCM7621 have common dc electrical characteris-
tics and identical programming requirements. They are fully decoded,
2048-BIT PROGRAMMABLE
high-speed, field-programmable ROMs and are available with open- READ ONLY MEMORIES
collector or three-state outputs. All bits are manufactured storing
a logical "1" (outputs high), and can be selectively programmed for MCM7620 - 512 X 4 - Open-Collector
logical "0" (outputs low). MCM7621 - 512 X 4 - Three-State
The field-programmable PROM can be custom programmed to
any pattern using a simple programming procedure. Schottky bipolar
circuitry pr,ovides fast access time, and features temperature and
voltage compensation to minimize access time variations.
All pinouts are compatible to industry·standard PROMs and
ROMs.
In addition to the conventional storage array, extra test rows and
columns are included to assure high programmability, and guarantee
parametric and ac performance. Fuses in these test rows and columns
are blown prior to shipment.
• Common dc Electrical Characteristics and
Programming Procedure
• Simple, High-Speed Programming Procedure
(0.1 Second per 1024 Bits, Typical)
CERAMIC PACKAGE
• Expandable - Open-Collector or Three-State Outputs CASE 620

and Chip Enable Inputs

• Inputs and Outputs TTL-Compatible

•
Low Input Current - 250 jJ.A Logic "0", 40 jJ.A Logic "1"
Full Output Drive - 16 mA Sink, 2.0 mA Source
• Fast Access Time - Guaranteed for Worst-Case
N2 Sequencing, Over Commercial and Military
Temperature and Voltage Ranges
• Pin-Compatible with Industry-Standard PROMs and ROMs
PIN ASSIGNMENT

ABSOLUTE MAXIMUM RATINGS (See Note)

Rating Symbol Value Unit 16
Supply Voltage (operating) VCC +7.0 Vdc 15
Input Voltage Vin +5.5 Vdc 3 14
Output Voltage (operating) VOH +7.0 Vdc 4 13
Supply Current ICC 650 mAdc 12
Input Current lin -20 mAdc 6 11
Output Sink Current 10 100 mAdc 10
Operating Temperature Range TA °c B 9
MCM76xxDM -55 to +125
MCM76xxDC oto +70
Storage Temperature Range T stg -55 to +150 °c
Maximum Junction Temperature TJ +175 °c
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages
for extended periods of time could affect device reliability. (While programming,
follow the programming specifications.)

4-15
 MCM7620, MCM762,.

DC OPERATING CONDITIONS AND CHARACTERISTICS

RECOMMENDED DC OPERATING CONDITIONS

Parameter Symbol Min Nom Max Unit
Supply Voltage Vcc Vdc
MCM76xxDM 4.50 5.0 5.50
MCM76xxDC ~

4.75 5.0 5.25

Input High Voltage VIH 2.0 - - Vdc
Input Low Voltage VIL - - 0.8 Vdc

DC CHARACTERISTICS
Open-Collector Three·State
Output Output
Symbol Parameter Test Conditions Min Typ Max Min Typ Max Unit
IRA,IRE Addressl Enable "1" VIH = VCC Max - - 40 - - 40 JJAdc
IFA,IFf Input Current "0" VIL = 0.45 V - -0.1 -0.25 - -0.1 -0.25 mAdc
VOH Output Voltage "1" 10H = -2.0 rnA, VCC - VCC Min NIA - - 2.4 3.4 - Vdc
VOL "0" 10L = +16 rnA, VCC = VCC Min - 0.35 0.45 - 0.35 0.45 Vdc
lOHE Output Disabled "1" VOH, VCC - VCC Max - - 100 - - 100 JJAdc
10LE Current "0" VOL = +0.3 V, VCC = VCC Max - - NIA - - -100 JJAdc
10H Output Leakage "1" VOH' VCC = VCC Max - - 100 - - N/A JJAdc
VCl Input Clamp Voltage lin = -10 mA - - -1.5 - - -1.5 Vdc
lOS Output Short Circuit Current Vec = Vce Max, V out = 0.0 V NIA - NIA 15 - 70 mAdc
One Output Only for 1 s Max r-

ICC Power Supply Current Vec = VCC Max

MCM7620/MCM7621 All Inputs Grounded - 60 100 - 60 100 mAdc

CAPACITANCE (f = 1.0 MHz, TA = 25°C. periodically sampled rather than 100% tested.)
Characteristic

•
Input Capacitance
Output Capacitance

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature unless otherwise noted) o to +700 C -55 to +125 O C
Characteristic Symbol Typ Max Typ Max Unit
Address to Output Access Time tAA 45 70 45 85 ns
Chip Enable Access Time tEA ns
MCM7620/7621 15 25 15 30

TIMING DIAGRAM AC TEST lOAD

Vr.r.'

I
CS~,3.0V

tf-
I 3.0 V
Address~
tAA--i L--
0.0 V -----+
1.5 V

tEA~
I
r-- ---t
1.5 V
t - I - - - O. OV
r--tEA Test Point Ox

Output 1.5V~
I

I
"0" Output 1.5V\
I, I

F
I
30pF' 600

t r , tf < 5.0 ns
'Includes JIg Capacitance

4-16
MCM7620, MCM7621

PROGRAMMING his own programmer to satisfy the sepcifications described

The PROMs are manufactured with all bits/outputs in Table 1, or buy any of the commercially available pro-
Logical "1" (Output High). Any desired bit/output can grammers which meet these specifications. These PROMs
be programmed to a Logical "0" (Output Low) by follow- can be programmed automatically or by the manual pro-
ing the simple procedure shown below. One may build cedure shown below.

PROGRAMMING PROCEDURE output enable pulses to each output which is to be

1. Address the PROM with the binary address of the programmed. The output enable pulses must be
selected word to be programmed. Address inputs separated by a minimum interval of td'
are TTL-compatible. An open circuit should not be 7. Lower Vce to 4.5 Volts following a delay of td
used to address the PROM. from the last programming enable pulse applied to
2. Disable the chip by applying input highs (VIH) to an output.
the es input. The chip select is TTL-compatible. 8. Enable the PROM for verification by applying a
An open circuit should not be used to disable the logic "0" (V I U to the es input.
chip. 9. If any bit does not verify as programmed, repeat
3. Disable the programming circuitry by applying an Steps 2 through 8 until the bit has received a total
of 1.0 ms of programming time. Bits which do not
Output Voltage Disable of less than VOPD to the
output of the PROM. The output may be left open program within 1.0 ms may be considered pro-
to achieve the disable. gramming rejects. Multiple pulses of durations
shorter than 1.0 ms may be used to enhance pro-
4. Raise Vee to VpH with rise time equal to t r .
gramming speed.
5. After a delay equal to or greater than td' apply a
10. Repeat Steps 1 through 9 for all other bits to be
pulse with amplitude of VOPE and duration of tp to
programmed in the PROM.
the output selected for programming. Note that the
PROM is supplied with fuses intact generating an 11. Programming rejects returned to the factory must
output high. Programming a fuse will cause the be accompanied by data giving address with desired
output to go low in the verify mode. and actual output data of a location in which a
6. Other bits in the same word- may be programmed programming failure has occurred.
while the Vee input is raised to VpH by applying

Symbol
VIH Address Input
Parameter
TABLE 1
PROGRAMMING SPECIFICATIONS

Min
2.4
Typ
5.0
Max
5.0
Unit
V
•
VIL Voltage(1 ) 0.0 0.4 0.8 V
VPH Programming/Verify '11.75 12_0 12.25 V
VPL Voltage to Vce 4.5 4.5 5.5 V
leep Programming Voltage Current Limit 600 600 650 mA
Programming (VCC)
tr Voltage Rise and 1 1 10 1'5
tf Fall Time 1 1 10. 1'5
td Programming Delay 10 10 100 1'5
tp Programming Pulse Width 100 - 1000 1'5
DC Programming Duty Cycle - 50 90 %
Output Voltage
VOPE Enable 10.0 10.5 11.0 V
VOPD Disable(2) 4.5 5.0 5.5 V
lOPE Output Voltage Enable Current. 2 4 10 mA
TC Case Temperature - 25 75 °c
(1) Address and chip select should not be left OPl:n for V,H.
(2) Disable condition will be met with output open circuit.

4-17
 MCM7620, MCM7621

FIGURE 1 - TYPICAL PROGRAMMING WAVEFORMS

cs------'

VpH----

Vee

Data-1 - - - - - - - - - - - '

Data-2 - - - - -.......- - - - -.....

Data-N - - - - - - - - - - - - - - - -.....

4-18
 MCM7640
® MOTOROLA thru
MCM7643

4096-BIT PROGRAMMABLE READ ONLY MEMORY

MTTL
4096-BIT PROGRAMMABLE
The MCM7640 through 43 PROMs comprise a completely com-
READ ONLY MEMORIES
patible family having common dc electrical characteristics and
identical programming requirements. They are fully-decoded, high-
MCM7640 - 512 X 8 - Open-Collector
speed, field-programmable ROMs and are available in commonly
MCM7641 - 512 X 8 - Three-State
used organizations, with both open-collector and three-state outputs.
MCM7642 - 1024 X 4 - Open-Collector
All bits are manufactured storing a logical "1" (outputs high), and
MCM7643 -1024 x 4 - Three-State
can be selectively pro'grammed for logical "0" (outputs low).
The field-programmable PROM can be custom programmed to
any pattern using a simple programming procedure. Schottky bipolar

~
circuitry provides fast access time, and features temperature and
voltage compensation to minimize access time variations.

,.-
All pinouts are compatible to industry-standard PROMs and
ROMs. 2~~VVVV' MCM7642/43

In addition to the conventional storage array, extra test rows and 1

columns are included to assure high programmability, and guarantee
parametric and ac performance. Fuses in these test rows and o SUFFIX
CERAMIC PACKAGE 1
columns are blown prior to,shipment.
o SUFFIX
• Common dc Electrical Characteristics and Programming Procedure CERAMIC PACKAGE

• Simple, High-Speed Programming Procedure

(0.1 Second per 1024 Bits, Typical)
• Expandable - Open-Collector or Three-State Outputs and Chip PIN ASSIGNMENT
Enable Inputs

•
• Inputs and Outputs TTL-Compatible
Low Input Current - 250 I1A Logic "0': 40 I1A Logic "1 " A6 18 VCC
Full Output Drive - 16 mA Sink, 2.0 mA Source A5 2 17 A7
A4 3 16 A8
• Fast Access Time - Guaranteed for Worst-Case N2 Sequencing;
A3 4 15 A9
Over Commercial and Military Temperature and Voltage
AO 5 14 01
Ranges
A1 13 02
• Pin-Compatible with Industry-Standard PROMs and ROMs
A2 7 12 03
CST 8 11 04
Gnd 9 10 CS2
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Symbol Value Unit
Supply Voltage (operating) VCC +7.0 Vdc
Input Voltage Vin +5.5 Vdc
Output Voltage (operating) VOH +7.0 Vdc
A7 24 VCC
Supply Current ICC 650 mAdc
A6 2 23 A8
Input Current 'in -20 mAdc
A5 3 22 NC'
Output Sink Current 10 100 mAdc
A4 4 21 CS1
Operating Temperature Range TA °c A3 5 20 CS2
MCM76xxDM -55 to +125
19 CS3
MCM76xxDC o to +70 A2 6
A1 18 CS4
Storage Temperature Range T stg -55 to +150 °c
AO 8 17 08
Maximum Junction Temperature TJ +175 °c
01 9 16 07

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are 02 10 15 06
exceeded. Functional operation should be restricted to RECOMMENDED 03 11 14 05
OPERATING CONDITIONS. Exposure to higher than' recommended voltages Gnd 12 13 04
for extended periods of time could affect device reliabilitY. (While programming,
follow the programming specifications.) • No Connection

4-19
 MCM7640 thru MCM7643

DC OPERATING CONDITIONS AND CHARACTERISTICS

RECOMMENDED DC OPERATING CONDITIONS

Parameter Symbol Min Nom Max Unit
Supply Voltage Vcc Vdc
MCM76xxDM 4.50 5.0 5.50
MCM76xxDC 4.75 5.0 5.25
Input High Voltage VIH 2.0 - - Vdc
Input Low Voltage VIL - - 0.8 Vdc

DC CHARACTERISTICS
Open-Collector Three-State
Output Output
Symbol Parameter Test Conditions Min Typ Max Min Typ Max Unit
IRA, IRE Addressl Enable "1" VIH = VCC Max - - 40 - - 40 /JAdc
IFA,IFE Input Current "0" VIL = 0.45 V - -0.1 -0.25 - -0.1 -0.25 mAdc
VOH Output Voltage "1" 10H - -2.0 mA, VCC - VCC Min N/A - - 2.4 3.4 - Vdc
VOL "0" 10L = +16 mA, VCC = VCC Min - 0.35 0.45 - 0.35 0.45 Vdc
10HE Output Disabled "1" VOH, VCC = VCC Max - - 100 - -- 100 }.lAdc
IOLE Curr-ent "0" VOL = +0.3 V, VCC = VCC Max - - N/A - - -100 }.lAdc
10H Output Leakage "1" VOH, VCC = VCC Max - - 100 - - N/A /JAdc
VCL Input Clamp Voltage lin = -10 mA - - -1.5 - - ~1.5 Vdc
lOS Output Short Circuit Current VCC - VCC Max, V out - 0.0 V N/A - N/A 15 - 70 mAdc
One Output Only for 1 s Max
ICC Power Supply Current VCC = VCC Max
MCM7640/MCM7641 All Inputs Grounded - 100 140 - 100 140 mAdc
MCM1642/MCM7643 - 100 140 - 100 140 mAdc

CAPACITANCE (f = 1.0 MHz, T A = 25°C, periodically sampled rather than 100% tested.)
Characteristic

II Input Capacitance
Output Capacitance

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature unless otherwise noted) o to +70o C -55 to +125 O C
Characteristic Symbol Typ Max Typ Max Unit
Address to Output Access Time tAA 45 70 45 85 ns
Chip Enable Access Time tEA ns
MCM7640/7641 30 40 30 50
MCM7642/7643 15 25 15 30

I IMIN\.> ",,~un~'v' I\"'~!':T InAn

VCC

I
Cs ~3.0V

tt.
I 3.0 V - 1.5 V
Address~
tAA---! L.-
0.0 V -----+
tEA-I
1.5 V
I
r-- _ --l
t -1- - -0.0 V
r-- tEA Test Point _ Ox

F
I I I I
Output I 1.5V~ "0" Output 1.5V\
30 pF" 600
I

t r , tf < 5.0 ns
"Includes Jig Capacitance

4-20
MCM7640 thru MCM7643

PROGRAMMING his own programmer to satisfy the sepcifications described

The PROMs are manufactured with all bits/outputs in Table 1, or buy any of the commercially available pro-
Logical "1" (Output High). Any desired bit/output can grammers which meet these specifications. These PROMs
be programmed to a Logicai "0" (Output Low) by follow- can be programmed automatically or by the manual pro-
ing the simple procedure shown below. One may build cedure shown below.

PROGRAMMING PROCEDURE while the VCC input is raised to VpH by applying

1. Address the PROM with the binary address of the output enable pulses to each output which is to be
selected word to be programmed. Address inputs programmed. The output enable pulses must be
are TTL-compatible. An open circuit should not be separated by a minimum interval of td'
used to address the PROM. 7. Lower VCC to 4.5 Volts following a delay of td
2. Disable the chip by applying input highs (VIH) to the from the last programming enable pulse applied to
CS input(s). CS inputs (MCM7640/41 only)' must an output.
remain at VIH for program and verify. The chip 8. Enable the PROM for verification by applying a
select is TTL-compatible. An open circuit should not logic "a" (VIL) to the CS input(s).
be used to disable the chip. 9. If any bit does not verify as programmed, repeat
3. Disable the programming circuitry by applying an Steps 2 through 8 until the bit has received a total
Output Voltage Disable of less than VOPD to the of 1.0 ms of programming time. Bits which do not
output of the PROM. The output may be left open program within 1.0 ms may be considered pro-
to achieve the disable. gramming rejects. Multiple pulses of durations
4. Raise VCC to VpH with rise time equal to t r . shorter than 1.0 ms may be used to enhance pro-
5. After a delay equal to or greater than td. apply a gramming speed.
pulse with amplitude of VOPE and duration of tp to 10. Repeat Steps 1 through 9 for all other bits to be
the output selected for programming. Note that the programmed in the PROM.
PROM is supplied with fuses intact generating an 11. Programming rejects returned to the factory must
output high. Programming a fuse will cause the be accompanied by data giving address with desired
output to go low in the verify mode. and actual output data of a location in which a
6. Other bits in the same word may be programmed programming failure has occurred.

Symbol
VIH
VIL
Address Input
Voltage(1)
Parameter
TABLE 1
PROGRAMMING SPECIFICATIONS

Min
2.4
0.0
Typ
5.0
0.4
Max
5.0
0.8
Unit
V
V
•
VPH Programming/Verify 11.75 12.0 12.25 V
VPL Voltage to Vec 4.5 4.5 5.5 V
ICCp Programming Voltage Current Limit 600 600 650 mA
Programming (Vce)
tr Voltage Rise and 1 1 10 /-IS
tf Fall Time 1 1 10 /-IS

td Programming Delay 10 10 100 /-IS

tp Programming Pulse Width 100 - 1000 /-IS
DC Programming Duty Cycle - 50 90 %
Output Voltage
VOPE Enable 10.0 10.5 11.0 V
VOPD Disable(2) 4.5 5.0 5.5 V
lOPE Output Voltage Enable Current 2 4 10 mA
TC Case Temperature - 25 75 °c
(1) Address and chip select should not be left open for VIH.
(2) Disable condition will be met with output open circuit.

4-21
 MCM7640 thru MCM7643

FIGURE 1 - TYPICAL PROGRAMMING WAVEFORMS

es-----~

VpH----

Vee

Data-1 --------------~

II Data-N-------------------~

4-22
 ® MOTOROLA MCM76S0
MeM76S1

8192-BIT PROGRAMMABLE READ ONLY MEMORY

The MCM7680/8l together with the MCM7620/2', MCM7640/43
MTTL
comprise a complete, compatible family having common dc elec-
8192-BIT PROGRAMMABLE
trical characteristics and identical programming requirements_ They READ ONLY MEMORIES
are fully decoded, high-speed, field-programmable ROMs and are
available in commonly used organizations, with both open-collector MCM7680 - 1024 X 8 - Open-Collector
and three-state outputs. All bits are manufactured storing a logical MCM7681 - 1024 X 8 - Three-State
"'" (outputs high), and can be selectively programmed for logical "0"
(outputs low).
The field-programmable PROM can be custom-programmed to
any pattern using a simple programming procedure. Schottky bipolar
circuitry provides fast access time, and features temperature and
voltage compensation to minimize access time variations.
Pinouts are compatible to industry-standard PROMs and ROMs.
In addition, the MCM7680 and 8' are pin compatible replacement
for the 512 X 8 with pin 2 connected as A9 on the 1024 X 8.
In addition to the conventional storage array, extra test rows and
columns are included to assure high programmability, and guarantee CERAMIC PACKAGE
parametric and ac performance. Fuses in these test rows and columns CASE 623
are blown prior to shipment.
• Common dc Electrical Characteristics and
Programming Procedure
• Simple, High-Speed Programming Procedure
(0.1 second per 1024 Bits, Typical)
• Expandable - Open-Collector or Three-State
Outputs and Chip Enable Inputs

•
• Inputs and Outputs TTL-Compatible
Low Input Current - 250 JiA Logic "0",40 JiA Logic "'"
Full Output Drive - 16 mA Sink, 2.0 rnA Source PIN ASSIGNMENT
• Fast Access Time - Guaranteed for Worst-Case
N2 Sequencing, Over Commercial and Military
Temperature Ranges 24

• Pin-Compatible with Industry-Standard PROMs and ROMs 23

22

4 21
ABSOLUTE MAX/MUM RATINGS (See Note) 20
Rating Symbol Value Unit 19
Supply Voltage (operating) VCC +7.0 Vdc 18
Input Voltage Vin +5.5 Vdc 17
Output Voltage (operating) VOH +7.0 Vdc 9 16
Supply Current ICC 650 mAdc 10 15
I nput Current lin -20 mAdc 11 14
Output Sink Current 10 100 mAdc 12 13
Operating Temperature Range TA °c
MCM76xxDM -55 to +125
MCM76xxDC o to +70
Storage Temperature Range Tstg -55 to +150 °c
Maximum Junction Temperature TJ +175 °c
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages
for extended periods of time could affect device reliability. (While programming,
follow the programming specifications.)

4-23
 MCM7680, MCM7681

DC OPERATING CONDITIONS AND CHARACTERISTICS

RECOMMENDED DC OPERATING CONDITIONS

Parameter Symbol Min Nom Max Unit
Sup"ly Voltage Vec Vdc
MCM76xxDM 4.50 5.0 5.50
MCM76xxDC 4.75 5.0 5.25
Input High Voltage VIH 2.0 - - Vdc
Input low Voltage Vil - - 0.8 Vdc

DC CHARACTERISTICS
Open-Collector Three-State
Output Output
Symbol Parameter Test Conditions Min Typ Max Min Typ Max Unit
IRA, IRE Address/Enable "1" VIH = VCC Max - - 40 - - 40 /-lAdc
IFA,IFE Input Current· "0" Vil = 0.45 V - -0.1 -0.25 - -0.1 -0.25 mAdc
VOH Output Voltage "1" IOH - -2.0 mA, Vec - VCC Min N/A - - 2.4 3.4 - Vdc
VOL "0" IOl = +16 mA, VCC = VCC Min - 0.35 0.45 - 0.35 0.45 Vdc
10HE Output Disabled "1" VOH' VCC = VCC Max - - 100 - - 100 /-lAdc
10lE Current "0" VOL = +0.3 V, VCC = VCC Max - - N/A - - -100 /-lAdc
IOH Output leakage "1" VOH, VCC = VCC Max - - 100 - - N/A /-lAdc
VCl Input Clamp Voltage lin = -10 mA - - -1.5 - - -1.5 Vdc
lOS Output Short Circuit Current VCC = VCC Max, V out = 0.0 V N/A - N/A 15 - 70 mAdc
One Output Only for 1 s Max
ICC Power Supply Current VCC = VCC Max
MCM7680/MCM7681 DC All Inputs Grounded - 110 150 - 110 150 mAde
MCM1680/MCM7681DM - 110 170 - 110 170 mAde

CAPACITANCE it = 1.0 MHz, T A = 25°C, periodically sampled rather than 100% tested.)
Characteristic

II
Input Capacitance
Output. Capacitance

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature unless otherwise noted) o to +700 C -55 to +125 0 C
Characteristic Symbol Typ Max Typ Max Unit
Address to Output Access Time tAA 45 70 45 85 ns
Chip Enable Access Time tEA ns
MCM7680/81 30 40 30 50

TIMING DIAGRAM AC TEST lOAD

U=
~
I
3.0V
cs~
~
~3.0V
1.5V
~:OO
Address ~--:-------O.O V CS 1"-:-1- - - t 0.0 V
tAA --l :--,..-_____ tEA-I t-- ---l t--tEA Test pOint. Ox

Output 1.5 v~
1'-------
"0" Output 1.5 V \
I I
F
I
30 pF' 600

'Includes Jig Capacitance

4-24
MCM7680, MCM7681

PROGRAMMING his own programmer to satisfy the sepcifications described

The .PROMs are manufactured with all bits/outputs in Table 1, or buy any of thEl commercially available pro-
Logical "1" (Output High). Any desired bit/output can grammers which meet these specifications. These PROMs
be programmed to a Logical "0" (Output Low) by follow- can be programmed automatically or by the manual pro-
ing the simple procedure shown below. One may build cedure shown below.

PROGRAMMING PROCEDURE while the Vec input is raised to VPH by applying

1. Address the PROM with the binary address of the output enable pulses to each output which is to be
selected word to be programmed. Address inputs programmed. The output enable pulses must be
are TTL-compatible. An open circuit should not be separated by a minimum interval of td'
used to address the PROM. 7. Lower Vee to 4.5 Volts following a delay of td
2. Disable the chip by applying inputs highs (V,H) to from the last programming enable pulse applied to
the es inputs. es inputs must remain at V,H for an output.
program and verify. The chip select is TTL-compatible .. 8. Enable the PROM for verification by applying a
An open circuit should not be used to disable the logic "0" (V IU to the es inputs.
chip. 9. If any bit does not verify as programmed, repeat
3. Disable the programming circuitry by applying an Steps 2 through 8 until the bit has received a total
Output Voltage Disable of less than VOPD to the of 1.0 ms of programming time. Bits which do not
output of the PROM. The output may be left open program within 1.0 ms may be considered pro-
to achieve the disable. gramming rejects. Multiple pulses of durations
4. Raise Vee to VpH with rise time equal to t r · shorter than 1.0 ms may be used to enhance pro-
5. After a delay equal to or greater than td' apply a gramming speed.
pulse with amplitude of VOPE and duration of tp to 10. Repeat Steps 1 through 9 for all other bits to be
the output selected for programming. Note that the programmed in the PROM.
PROM is supplied with fuses intact generating an 11. Programming rejects returned to the factory must
output high. Programming a fuse will cause the be accompanied by data giving address with desired
output to go low in the verify mode. and actual output data of a location in which a
6. Other bits in the same word may be programmed programming failure has occurred.

Symbol
VIH
VIL
Address Input
Voltage(1 )
Parameter
TABLE 1
PROGRAMMING SPECIFICATIONS

Min
2.4
0.0
Typ
5.0
0.4
Max
5.0
0.8
Unit
V
V
•
VPH Programming/Verify 11.75 12.0 12.25 V
VPL Voltage to VCC 4.5 4.5 5.5 V
ICCp Programming Voltage Current Limit 600 600 650 mA
Programming (VCC)
tr Voltage Rise and 1 1 10 IlS
tf Fall Time 1 1 10 IlS

td Programming Delay 10 10 100 IlS

tp Programming Pulse Width 100 - 1000 IlS

DC Programming Duty Cycle - 50 90 %

Output Voltage
VOPE Enable 10.0 10.5 11.0 V
VOPD Disable(2) 4.5 5.0 5.5 V
lOPE Output Voltage Enable Current 2 4 10 mA
TC Case Temperature - 25 75 °c
(1) Address and chip select should not be left open for VIH.
(2) Disable condition will be met with output open circuit.

4-25
 MCM7680, MCM7681

FIGURE 1 - TYPICAL PROGRAMMING WAVEFORMS

es------'

VPH----

vee

Data-1

J
Data-2 _ _ _ _ _ _ _ _ _ _ _...J

Data-N - - - - - - - - - - - - - - - -....

4 ..26
 ® MOTOROLA MCM1684
MCM7685

8192-BIT PROGRAMMABLE READ ONLY MEMORY

MTTL
The MCM7684/85 together with the MCM7620/21 /40/41 /42/43/
8192-BIT PROGRAMMABLE
80/81 comprise a complete, compatible family having common dc
electrical characteristics and identical programming requirements.
READ ONLY MEMORIES
They are fully decoded, high·speed, field-programmable ROMs
and are available in commonly used organizations, with both open- MCM7684 - 2048 X 4 - Open-Collector
collector and three-state outputs. All bits are manufactured storing MCM7685 - 2048 X 4 - Three-State
a logical "1" (outputs high), and can be selectively programmed
for logical "0" (outputs low).
The field·programmable PROM can be custom·programmed
to any pattern using a simple programming procedure. Schottky
bipolar circuitry provides fast access time, and features temperature
and voltage compensation to minimize access time variations.
Pinouts are compatible to industry-standard PROMs and ROMs.
In addition, the MCM7684 and 85 are pin compatible replacement
for the 1024 X 4 with pin 8 connected as A lOon the 2048 X 4.
In addition to the conventional storage array, extra test rows and
o SUFFIX
columns are included to assure high programmability, and guarantee CERAMIC PACKAGE
parametric and ac performance. Fuses in these test rows and columns CASE 726
are blown prior to shipment.
• Common dc Electrical Characteristics and
Programming Procedure
• Simple, High-Speed Programming Procedure
(0.1 second per 1024 Bits, Typical)
• Expandable - Open·Coliector or Three·State
Outputs and Chip Enable Input
• Inputs and Outputs TTL·Compatible

•
Low Input Current - 250 pA Logic "0",40 pA Logic "1"
Full Output Drive - 16 mA Sink, 2.0 mA Source PIN ASSIGNMENT
• Fast Access Time - Guaranteed for Worst· Case
N2 Sequencing, Over Commercial and Military
Temperature Ranges VCC 18
• Pin·Compatible with IndustrY·Standard PROMs and ROMs A7 17
3 16
4 15
ABSOLUTE MAXIMUM RATINGS (See Note) 01 14
Rating Symbol Value Unit 13
Supply Voltage (operating) VCC +7.0 Vdc A2 12
Input Voltage Vin +5.5 Vd~ Al0 11
Output Voltage (operating) VOH +7.0 Vdc Gnd 10
Supply Current ICC 650 mAde
Input Current lin -20 mAde
Output Sink Current 10 100 mAde
Operating Temperature Range TA °c
MCM76xxDM -55 to +125
MCM76xxDC oto +70
Storage Temperature Range T stg -55to+150 °c
Maximum Junction Temperature TJ +175 °c
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED
OPERATING CONDITIONS. Exposure to higher than recommended voltages
for extended periods of time could affect device reliability. (While programming,
fOllow the programming specifications.)

This is advance information and specific.ations are subject to change without notice.

4-27
 MCM7684, MCM7685

DC O'PERATING CONDITIONS AND CHARACTERISTICS

RECOMMENDED DC OPERATING CONDITIONS

I Parameter Symbol Min Nom Max Unit
Supply Voltage Vec Vdc
MCM76xxDM 4.50 5.0 5.50
MCM76xxDC 4.75 5.0 5.25
Input High Voltage VIH 2.0 - - Vdc
Input Low Voltage VIL - - O.~ Vdc

DC CHARACTERISTICS
(Over Recommended Operating Temperature Range) Open-Collector Three-State
Output Output
Symbol Parameter Test Conditions Min Typ Max Min Typ Max Unit
IRA,IRE Address/Enable "1" VIH = VCC Max - - 40 - - 40 /lAde
IFA,IFE Input Current "0" VIL = U.45 V - -0.1 -0.25 - -0.1 -0.25 mAdc
VOH Output Voltage "1" 10H = -2.0 mA, VCC Min N/A - - 2:4 3.4 - Vdc
VOL "0" 10L = +16 mA, VCC Min - 0.35 0.45 - 0.35 0.45 Vdc
10HZ Output Disabled "1" VOH, VCC Max - - 100 - - 100 /lAde
10LZ Current "0" VOL = +0.3 V, VCC Max ~ - N/A - - -100 /lAdc
10H Output Leakage "1" VOH, VCC Max - - 100 - - N/A /lAde
VIC Input Clamp Voltage lin = -10 mA - - -1.5 - - -1.5 Vde
lOS Output Short Circuit Current VCC Max, Vout - 0.0 V N/A - N/A 15 - 70 mAdc
One Output Only for 1 s Max
ICC Power Supply Current VCC Max
MCM7684/MCM7685 DC All Inputs Grounded - 80 120 -
80 120 mAdc
MCM7684/MCM7685 DM - 80 140 - 80 140 mAdc

CAPACITANCE (I = 1.0 MHz, T A = 25 0 C, periodically sampled rather than 100% tested.)

Characteristic

•
Input Capacitance
Output Capacitance

AC OPERATING CONDITIONS AND CHARACTERISTICS

(Full operating voltage and temperature unless otherwise noted) o to +700 C -55 to +125 0 C
Characteristic Symbol Typ Max Typ Max Unit
Address to Output Access Time tAA 45 70 45, 85 ns
Chip Enable Access Time tEA 15 25 15 30 ns

TIMING DIAGRAM AC TEST LOAD

Vee

~
cs~ ~3.0V
~
~ It~
3.0V
Addr9ss~_ _,.....-_ _~_ _ 0.0 V
es tEA--'I....,...~-----i-t J-""tE~·O V To" '0;" 0,

Output
tAA-i , :--,..-_ _ _ __
1.5V)E
1'------- "0" Output 1.5 V \
I 1 v:-:-:-
r1.5 V 30.'"t-J,oo
Input t r • tf < 5.0 ns
·1 ncludes Jig Capacitance

4-28
MCM7684, MCM7685

PROGRAMMING his own programmer to satisfy the sepcifications described

The PROMs are manufactured with all bits/outputs in Table 1, or buy any of the commercially available pro·
Logical "1" (Output High). Any desired bit/output can grammers which meet these specifications. These PROMs
be programmed to a Logical "0" (Output Low) by follow- can be programmed automatically or by the manual pro-
ing the simple procedure shown below. On~ may build cedure shown below.

PROGRAMMING PROCEDURE while the Vee input is raised to VpH by applying

1. Address the PROM with the binary address of the output enable pulses to each output which is to be
selected word to be programmed. Address inputs programmed. The output enable pulses must be
are TTL-compatible. 'An open circuit should not be separated by a minimum interval of td.
used to address the PROM. 7. Lower Vee to 4.5 Volts following a delay of td
2. Disable the chip by applying an input high (VIH) to from the last programming enable pulse applied to
the es input. The chip select is TTL-compatible. an output.
An open circuit should not be used to disable the 8. Enable the PROM for verification by applying a
chip. logic "0" (V I U to the es inputs.
3. Disable the programming circuitry by applying an 9. If any bit does not verify as programmed, repeat
Steps 2 through 8 until the bit has received a total
Output Voltage Disable of less than VOPD to the
output of the PROM. The output may be left open of 1.0 ms of programming time. Bits which do not
to achieve the disable. program within 1.0 ms may be considered pro-
gramming rejects. Multiple pulses of durations
4. Raise Vee to V PH with rise time equal to t r .
shorter than 1.0 ms may be used to enhance pro-
5. After a delay equal to or greater than td' apply a gramming speed.
pulse with amplitude of VOPE and duration of tp to 10. Repeat Steps 1 through 9 for all other bits to be
the output selected for programming. Note that the programmed in the PROM.
PflOM is supplied with fuses intact generating an 11. Programming rejects returned to the factory must
output high. Programming a fuse will cause the be accompanied by data giving address with desired
output to go low in the verify mode. and actual output data of a location in which a
6. Other bits in the same word may be programmed programming failure has occurred.

Symbol
VIH
VIL
VPH
VPL
Address Input
Voltage(l )
Parameter

ProgramminglVerify
Voltage to VCC
TABLE 1
PROGRAMMING SPECIFICATIONS

Min
2.4
0.0
11.75
4.5
Typ
5.0
0.4
12.0
4.5
Max
5.0
0.8
12.25
5.5
Unit
V
V
V
V
•
ICCp Programming Voltage Current Limit 600 600 650 mA
Programming (VCC)
tr Voltage Rise and 1 1 10 1.15
tf Fa" Time 1 1 10 1.15
td Programming Delay 10 10 100 IlS

tp Programming Pulse Width 100 - 1000 1.15

DC Programming Duty Cycle - 50 90 %
Output Voltage
VOPE Enable 10.0 10.5 11.0 V
VOPD Disable(2) 4.5 5.0 5.5 V
lOPE Output Voltage Enable Current 2 4 10 mA
TC Case Temperature - 25 75 °c
(1) Address and chip select should not be left open for VIH.
(2) Disable condition will be met with output open circuit.

4-29
 MCM7684, MCM7685

FIGURE 1 - TYPICAL PROGRAMMING WAVEFORMS

es----.....J

VPH----

Vee

Data-1

J
Data-2 _ _ _ _ _ _ _ _ _ _ _...J

Data-N - - - - - - - - - - - - - - - - - '

4-30
 MECL MEMORIES
GENERAL INFORMATION

Complete information is available in the MECL Data Book. Contact your sales representative or authorized
distributor for information.

TABLE 1 - LIMITS BEYOND WHICH DEVICE LIFE MAY BE IMPAIRED

Characteristic Symbol Rating Unit
Supply Voltage VEE -8.0 to 0 V
Input Voltage (V CC = 0) Vin o to VEE V
Output Source Current - Continuous lout 50 mA
Surge 100
Junction Temperature - Ceramic PackageG) TJ 165 °c
Plastic Package 150
Storage Temperatu re T stg -55 to +150 °c
CD Maximum T J may be exceeded (.;:;; 250 o C) for short periods of time (.;:;; 240 hours) without significant
reduction in device life.

Output Drive -
TABLE 2 - LIMITS BEYOND WHICH PERFORMANCE MAY BE DEGRADED
Characteristic
Supply Voltage (VCC = O)@)
MCM1 01 00 Series
M CM 10500 Series
Operating Temperature Range@
Symbol
VEE
-

TA
Rating
-4.94 to -5.46
50 n to -2.0 V
100 n to -2.0 V
Unit
V

°c
•
M CM 1 0100 Series o to
75
M CM 10500 Series -55to+125
Functionality only. Data sheet limits are specified for -5.19 to -5.21 V.
With airflow;" 500 Ifpm.

4-31
 MECL MEMORI ES (continued)

TABLE 3 - DC TEST PARAMETERS

\
Each MECL 10,000 series device has been designed to meet the dc specifications shown in the test table, after
thermal equilibrium has been established. The circuit is in a test socket oro mounted on a printed circuit board
and transverse airflow greater than 500 linear feet per minute is maintained. VEE = - 5.2 V ± 0.01 0 V.

Forcing -SSoC OOC 2SoC 7SoC 12SoC

Function Parameter MCM10S00* MCM10100** MCM10100** MCM10S00* MCM10100** MCM10S00*
vlHmax = VOHma~o -0.880 -0.840 -0.810 -0.780 -0.720 -0.630
VOHmin -1.080 -1.000 -0.960 -0.930 -0.900 -0.825
VOHAmin -1.100 -1.020 -0.980 -0.950 -0.920 -0.845
VIHAmin -1.255 -1.145 -1.105 -1.105 -1.045 -1.000
VILAmin -1.510 -1.490 -1.475 -1.475 -1.450 -1.400
VOLAmin -1.635 -1.645 -1.630 -1.600 -1.605 -1.525
-1.650 -1.620 -1.625 -1.545

r VOLAmax -1.655 -1.665

VILmin -1.920 -1.870 -1.850 -1.850 -1.830 -1.820
VOLmin
VILmin IINLmin 0.5 0.5 0.5 0.5 0.3 0.3
. .
* Driving100 n to -2.0 V .
**Driving 50 n to -2.0 V.

Vee = Gnd

~
____ IlL __ • I
0
0 I

•
0- I
I
I
I
I I I I
I
INPUT lEVELS
ro
I CSl CS2 CS3
1\0
I I
Al
I I
~ A2 I
I
A3 I tr ~ If - 2.0 ns typo
I
~ A4 I
I
A5' I All timing measurements !eferenced to 50% of input levels.
I
A6 Dout AT = 50 n
I
I
A7 I el Cl .;; 5.0 pF (including jig and stray capacitance)
I
I
I
I
I
RT

~
J Delay should be derated 30 ps/pF for cap,\citive load up to 50 pF

I I -2.0 V
! I

:'.,
Din WE I
I I
I
I I

err
I
I

L-------

-6.2 Vdc
Vee

FIGURE 1 - SWITCHING TIME TEST CIRCUIT

04-32
MECL MEMORIES (continued)
FIGURE 2 - CHIP SELECT ACCESS TIME WAVEFORM

Chip Select
cs
°out

FIGURE 3 - ADDRESS ACCESS TIME WAVEFORM

Address - - - - t - ot-- -=1---.__________

AA

D
out
_________ ~_....J
....5_0_%_0 _ _ _ _ _ _ _ __

FIGURE 4 - SETUP AND HOLD WAVEFORMS (WRITE MODE)

•
Address

°out ~-----tWSA----~

tws

. .4:33
 ·® MOTOROLA
MCM10143
8 X 2 MULTIPORT REGISTER
FILE (RAM)

8 x 2 MULTIPORT REGISTER FILE

(RAM)

The MCM10143 is an 8 wordby 2 bit multiport register file

(RAM) capable of reading two locations and writing one loca-
tion simultaneously. Two sets of eight latches are used for data
storage In this LSI circuit.

WRITE
The word to be written is selected by addresses AO-A2. Each bit
of the word has a separate write enabl.e to allow more flexibility in
system design. A write occurs on the positive transition of the clock.
Data is enabled by having the write enables at a low level when the
clock makes the transition. To inhibit a bit from being written, the
L SUFFIX
CERAMIC PACKAGE
bit enable must be at a high level when the clock goes low and not
change until the clock goes high. Operation of the clock and the bit CASE 623
enables can be reversed. While the clock is Iowa positivetransition of
the bit enable will write that bit into the address selected by AO-A2.

READ
When the clock is high any two words may be read out simulta-
neously, as selected by addresses BO-82 and CO-C2, including the
word written during the preceding half clock cycle. When the dock

•
goes low the addressed data is stored in the slaves. Level changes on PIN ASSIGNMENT
the read address lines have no effect on the output until the clock
again goes high. Read oLit is accomplished at any time by enabling
output gates (80-81). (CO-Cl).
Vcco 24

2 OB1 VCC1 23
tpd:
3 OBO OC1 22
Clock to Data out'" 5 ns (typ)
(Read Selected) 4 REB OCo 21

Address to Data out'" 10 ns (typ) 5 B2 REc 20

(Clock High)
6 Bo Clock 19
Read Enable to Data out = 2.8 ns (typ)
(Clock high, Addresses present) B1 C2 18

PD'" 610 mW/pkg (typ no load) 8 WE1 Co 17

9 WEo C1 16

10 DO A1 15
TRUTH TABLE
11 D1 AO 14
'MODE INPUT OUTPUT
, ·Clock WEo WE, DO 0, REB REc aBo OB, OCo OC, 12 VEE A2 13
Write L -->H L L H H H- H L L L L
Read H Q Q Q Q L L H H H H
Read H~L Q Q <!> Q L L H H H H
Read L~H~ H H Q Q L L H H H H
Write L~H L L L H H H L L L L
Read H Q <I> Q Q L L L H L H

··Note: Clock occurs sequential IX through Truth Table

'Note: AO-A2. 80-82. and CO·C2 are all set to same address location
throughout Table.
1> " Don't Care

4-34
MCM10143

BLOCK DIAGRAM

,.... 4
REB ~

Multi- Output 2
f-----t- Slave ~
6
plexer B-bit 1
Gate \--0
'-- ~
-
~

'V
7
~
Read
Decoder r-----
~ B-bit 1 ~ B-bit 1

,.... 5 B

Multi- l+ Output 3
-... f-- I-- Slave
plexer
B-bit 0
Gate ~ aBO
~ B-bit 0 ~ ~ B-bit 0

~ Write
WEO
9
Amplifier
L....-
a x1
'"
~

10 Master Latches
DO Bit 0 r--
~
Bit 0
r+-
~~

---
,.... 14
Write
,.... 15 Decoder
,.... 13 A
~

"

•
L.- a x 1
~ Write
a ~

-,., 11
Amplifier
Bit 1 ~
Master Latches
Bit 1

Multi- Output
~ ~ Slave ~
r-t----.
plexer
C-bit 1 ;...-
I--
C-bit 1
~
Gate
C-bit 1
~ aC1

~
17
Read
,.... 16 Decoder
~ ~
,.... 18 C Multi- Output
~ ~
~ ~ I-- f-+
~ aco
Slave
plexer Gate
C-bit 0
~ C-bit 0 ~ ~ C-bit 0

~
20

4-35
 MCM10143 '

ELECTRICAL CHARACTERISTICS
oOC +25 0 C +75 0 C
Characteristics Symbol Min Max Min Typ Max Min Max Unit
Power Supply Drain Current IE - 150 - 118 150 - 150 mAdc
Input Current linH MAdc
Pins 10, 11, 19 - 245 - - 245 - 245
All other pins - 200 - - 200 - 200
Switching Times Q) ns
Read Mode
Address Input tB Laa ± 4.0 15.3 4.5 10 14.5 4.5 15.5
Read Enable tRE-OB+ 1.1 5.3 1.2 3.5 5.0 1.2 5.5
Data tClock+OB- 1.7 7.3 2.0 5.0 7.0 2.0 7.6
Setup
Address tsetup(B -Clock-) - - 8.5 5.5 - - -
Hold
Address thold(Clock-B+) - - -1.5 -4.5 - - -
Write Mode
I
Setup
Write Enable tsetup(WE -Clock +) - - 7.0 4.0 - - -
tsetup(WE +Clock-) - - 1.0 -2.0 - - -
Address tsetup (A -Clock +) - - 8.0 5.0 - - -

•
Data tsetuoID-Clock+) - - 5.0 2.0 - - -
Hold
Write Enable thold(Clock +WE +) - - 5.5 2.5 - - -
thold (Clock +WE-) - - 1.0 -2.0 - - -
Address thold(Ciock+A+) - - 1.0 -3.0 - - -
Data thold(Clock+D+) - - 1.0 -2.0 - - -
Write Pulse Width PWWE - - 8.0 5.0 - - -
Rise Time, Fall Time tr~ tf 1.1 4.2 1.1 2.5 4.0 1.1 4.5
(20% to 80%)
(DAC timing figures do not show all the necessary presetting conditions.

4-36
MCM10143

READ TIMING DIAGRAMS

Access (Clock High)

S------~\
t8-08- _~----,--:---------'
I
- - - 1 t 8 +08+
FIGURE 1

OS -I,------------I----"""'¥
T~-------
I

___________ i...-_n_--''*. .
I I

Enable
RE---t
- I'--_ _
1 ---J
FIGURE 2

tRE-08~1r--I
i -{
I tRE+OB-

0---- I

Data
(Address Selected)
o ___________________>~:---------------
FIGURE 3

Setup and Hold

Clock

8
------------'1
~,--------~+I,-t-C-IO-C-k-+O-8--------­

---------X----:----------l--------
FIGUR,E 4
II
, '

Clock -------t-C--t-se-t-u-p----=t=_-t_h_O_ld_-_=1-+'_ _ _ _ __

4-37
 MCM10143

WRITE TIMING DIAGRAM

Enabfe Setup

----'L-'"Pi~--
FIGURE 5
WE

1 -1
a-
Clock - - - - - - - - - - -

Enable Hold
WE
--~
FIGURE 6

Clock
f
t_ hol d
_ - - - - -

Disable WE
----
------r--------
r- ~
~
f------ tho Id - - - - - - l
FIGURE 7

I
t setu p

---{ _. r ---+--I-
,
Clock - . - -

Pulse Width I~I

•
FIGURE 8

Address
FIGURE 9

Clock
® MOTOROLA MCM10144/MCM10544
256 X 1-BIT RANDOM
ACCESS MEMORY

The MCM10144/10544 ~s a 256 word

X 1-bit RAM. Bit selection is achieved by
means of an 8-bit address AO through A 7.
The active-low ch ip select allows memory
expansion up to 2048 words. The fast chip
select access time allows memory expansion
without affecting system .performance.
The operating mode of the RAM (CS inputs
low) is controlled by the WE input. With WE
low the chip is in the write mode-the output
AO
.. is low and the data present at Din is stored
Al
2 'S~
ID"O
-g~
. 14
WE at the selected address. With WE high the chip
is in the read mode-the data state at the
A2
3 ; 0~ <tID
-0 ~E ,selected memory location is presented non-
"ON ';: ~
4 <t~ inverted at D out '
A3 ~:;; Din
"O~
0 13
9 0 • Typical Address Access Time = 17 ns
A4 ~
• Typ ical Ch ip Select Access T ime ~ 4.0 ns
• 50 kf2 Input Pulldown Resistors on Chip
Select
• Power Dissipation (470 mW typ @ 25 0 C)
A5 A6 A7 Decreases with Increasing Temperature

•
• Pin-for-Pin Replacement for F10410

TRUTH TABLE
MODE INPUT OUTPUT
CS· WE Din D out PIN ASSIGNMENT
Write "0"
Write "1" H
AO vee 16
Read H ¢ 0
Disabled H ¢ ¢ A1 D out 15

·CS = eS1 + eS2 + CS3 ¢ = Don't Care. A2 'WE 14

4 A3 Djn 13

CS1 A7 12

~
6 CS2 A6 1t

F SUFFIX CS3 A5 10

~WCiE:AMIC
CERAMIC PACKAGE
LSUFFIX vEE A4
CASE 650
PACKAGE
CASE 620

4-39
 MCM10144/MCM10544

E LECTR I CAL CHARACTE R 1ST ICS

-SSoC OOC +2SoC +7SoC +12SoC
Characteristic Symbol Min Max Min Max Min Max Min Max Min Max Unit
Power Supply Drain Current lEE - 140 - 135 - 130 - 125 - 125 mAdc
Input Current High linH - 375 - 220 - 220 - 220 - 220 }lAdc

-5S0C and +125 0 C test values apply to MC105xx devices only.

SWITCHING CHARACTERISTICS (Note 1)

MCM10144 MCM10544
TA = 0 to TA = -55 to
+75 0 C, +12SoC,
VEE = VEE =
-5.2 Vdc -5.2 Vdc
± 5% ± 5%
Characteristics Symbol Min Max Min Max Unit Conditions
Read Mode ns Measured from 50% of
Chip Select Access Time tACS 2.0 10 2.0 10 input to 50% of output.
Chip Select Recovery Time tRCS 2.0 10 2.0 10 See Note 2.
Address Access Time tAA 7.0 26 7.0 26
Write Mode ns tWSA = 8.0 ns
Write Pulse Width tw 25 - 25 - Measured at 50% of
Data Setup Time Prior to Write 2.0 - 2.0 - input to 50% of output.

•
tWSD
Data Hold Time After Write tWHD 2.0 - 2.0 - tw = 25 ns.
Address Setup Time Prior to Write tWSA 8.0 - 8.0 -
Address Hold Time After Write tWHA 0.0 - 0.0 -
Chip Select Setup Time Prior to twSCS 4. 0 - 2.0 -
Write
Chip Select Ho!d Time After Write tl/\lHCS 2.0 - 2.0 -
Write Disable Time tws 2.5 10 2.5 10
Write Recovery Time tWR 2.5 10 2.5 10
Rise and Fall Time t r , tf ns Measured between 20%
and 80% points.
Address to Output .1.5 7.0 1.5 7.0
CS or WE to Output 1.5 5.0 1.5 5.0
Capacitance pF Measured with a pulse
Input Capacitance Cin - 5.0 - 5.0 , technique;
Output Capacitance Cout - 8.0 - 8.0
NOTES: 1. Test circuit characteristics: RT = 50 n, MCM10144; 100 n, MCM10544. CL"';; 5.0 pF (including jig
and stray capacitance). Delay should be derated 30 ps/pF for capacitive load up to 50 pF.
2. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
3. For proper use of MECL Memories In a system environment, consult MECL System Design
Handbook.

4-40
® MOTOROLA
MCM10145/MCM10545
16 X 4-BIT REGISTER FILE
(RAM)

The MCM10145/10545 is a 16 word X 4-bit

RAM. Bit selection is achieved by means of
a 4-bit address AO through A3.
The active· low chip select allows memory
expansion up to 32 words. The fast ch ip
select access time allows memory expansion
without affecting system performance.
The operating mode of the RAM (CS input
low) is controlled by the WE input. With 'WE
low the chip is in the write mode-the output
is low and the data present at On is stored at
the selected address. With WE high the chip
is in the read mode-the data state at the
selected mem ory location is p resented non·
inverted at an.
• Typical Address Access Time = 10, ns
• Typical Chip Select Access Time = 4.5 ns
• 50 k,Q Pulldown Resistors on All Inputs
• Power Dissipation (470 mW typ @ 25°C)
Decreases with Increasing Temperature

PIN ASSIGNMENT
00 01 02 03

01 16

•
00 15
TRUTH TABLE
MODE INPUT OUTPUT
cs 14
D1 13
cs WE On an
DO 12
Write "0"
A3 11
Write "1" H
A2 10
Read H Q
9
Disabled H '" 8 VEE

L SUFFIX ¢ = Don't CarBo

'" '"
CERAMIC PACKAGE
CASE 620
FIGURE 1 - CHIP ENABLE STROBE MODE

A----"I

Din -----t-"

F SUFFIX
CERAMIC PACKAGE
cs - - - - - - - -... 1

CASE 650
 MCM 1 0145/MCM 10545
ELECTRICAL CHARACTERISTICS

,...55 0 C oOC +25 0 C +75 0 C + 125°C

Characteristic Symbol Min Max Min Max Min Max Min'Max Min Max Unit
Power Supply Drain Current lEE - 135 - 130 - 125 - 120 - 120 mAdc
Input Curren~ High linH - 375 - 220 220 - 220 - 220 ,uAdc
0
-55°C and +125 C test values apply to MC105xx devices only.

SWITCHING CHARACTERisTICS (Note 1)

MCM10145 MCM10545
TA = 0 to TA = -55 to
+75 0 C, +125 0 C,
VEE = VEE =
-5.2 Vdc -5.2 Vdc
± 5% ± 5%
Characteristics Symbol Min Max Min Max Unit Conditions
Read Mode ns Measured from 50% of
Chip Select Access Time tACS 2.0 8.0 2.0 10 input to 50% of output~
Chip Select Recovery Time tRCS 2.0 8.0 2.0 10 See Note 2.
Address Access Time tAA 4.0 15 4.0 18
Write Mode ns tWSA = 5 ns
Write Pulse Width tw 8.0 - 8.0 - Measured at 50% of
Data Setup Time Prior to Write tWSD 0 - 0 - input to 50% of output.
Data Hold Time After Write tWHD 3.0 - 4.0 - tw = 8 ns.
Address Setup Time Prior to Write tWSA 5.0 - 5.0 -
Address Hold Time After Write tWHA 1.0 - 3.0 -
. Chip Select Setup Time Prior to tWSCS '0 - 5.0 -
Write
Chip Select Hold Time After Write tWHCS 0 - 0 -

•
Write Disable Time tws 2.0 8.0 2.0 10
Write Recovery Time tWR 2.0 8.0 2.0 10
Ch ip Enable Strobe Mode ns Guaranteed but not
Data Setup Prior to Chip Select tCSD 0 - - - tested on standard
Write Enable Setup Prior to tcsw 0 - - - product. See Figure 1.
Chip Select
Address Setup Prior to Chip Select tCSA 0 - - -
Data Hold Time After Chip Select tCHD 2.0 - - -
Write Enable Hold Time After tCHW 0 - - -
Chip Select
~ddress Hold Time After Chip tCHA 4.0 - - -
Select
Chip Select Minimum Pulse Width tcs 18 - - -
Rise and Fall Time t r , tf ns Measured between 20%
Address to Output 1.5 7.0 1.5 7.0 and 80% points.
CS to Output 1.5 5.0, 1.5 5.0
Capacitance pF Measured with a pulse
Input Capacitance Cin - 6.0 - 6.0 technique.
Output Capacitance Cout - 8.0 - 8.Q
NOTES: 1. Test circuit characteristics: RT = 50.Q, MCM10145; 100.Q, MCM10545. CL';;;; 5.0 pF (including jig
and Stray Capacitance). Delay should be derated 30 ps/pF for capacitive loads up to 50 pF.
2. The maximum Address Access Time is guaranteed to be the worst-case bit in the memory.
3. For proper use of MECL Memories in a system environment, consult MECL System Design Handbook.

4-42
® MOTOROLA
MCM10146/MCM10546
1024 X 1-BIT RANDOM
ACCESS MEMORY

The MCM10146/10546 is a 1024 X 1·bit

RAM. B it selection is ach iaved by means of
a 1 O··bit address, AO to A9.
The active·low chip select is provided for
memory expansion up to 2048 words.
The operating mode of the RAM (CS input
low) is con'trolled by the WE input. With WE
low, the chip is in the write mode, the output,
Dout, is low and the data state present at
2 Din is stored at the selected address. With WE
AO

Al
3
:
ii
high, the chip is in the read mode and the data
stored at the selected memory location will be
"tl
<{ 13 presented non-inverted at D out . (See Truth
4
A2 "tl
0 Table.)
5 :!:.
A3 - N • ~in-for-Pin Compatible with the 10415
15
A4
6 S • Power Dissipation (520 mW typ @ 25 0 C)
Decreases with I ncreasing Temperature
• Typical Address Access of 24 ns
• Typical Chip Select Access of 4.0 ns
• 50 kn. Pulldown Resistor on Chip Select
A5 A6 A7 AS A9 Input

PIN ASSIGNMENT

•
TRUTH TABLE
... _._-....._----,.. ,,-_._.
,.

MODE INPUT OUTPUT 16

D out 15
CS WE Din
14
Write "0" 'L
4 13
Write "1" H
12
Read H Q

Disabled ~i
'" 11

'" '" 10
'" = Don't Care. 9

_LSUFFIX CERAMIC PACKAGE

CASE 620
F-SUFFIX
CERAMIC PACKAGE
CASE 650-03

A::43
 MCM 10146/MCM 10546

ELECTRICAL CHARACTERISTICS
-55°C OOC +25 0 C +75 0 C +125 0 C
Characteristic Symbol Min Max Min Max Min Max Min Max Min Max Unit
Power Supply Drain Current lEE - 155 - 150 - 145 - 125 - 125 mAdc
Input Current High J linH -. 375 - 220 - 220 - 220 - 220 /-IAdc
Logic "0" Output Voltage VOL -1.970 -1.655 -1.920 -1.665 -1.900 -1.650 -1.880 -1.625 -1.870 -1.545 Vdc
NOTE: -55 0 C and +125 0 C test values apply to MCM105XX only.

SWITCHING CHARACTERISTICS (Note 1)

MCM10146 MCM10546
TA=Oto TA = -55 to
+75 0 C, +125 0 C,
VEE = -5.2 Vdc VEE = -5.2 Vdc
± 5% ± 5%
Characteristics Symbol Min Max Min Max Unit Conditions
Read Mode ns Measured at 50% of input
Chip Select Access Time tACS 2.0 7.0 2.0 8.0 to 50% of output.
Chip Select Recovery Time, tRCS 2.0 7.0 2.0 8.0 See Note 2.
Address Access Time tAA 8.0 29 8.0 40
Write Mode ns tWSA = 8.0 ns.
Write Pulse Width tw 25 - 25 - Measured at 50% of input
(To guarantee writing) to 50% of output.
Data Setup Time Prior to Write tWSD 5.0 - 5.0 - tw = 25 ns
Data Hold Time After Write tWHD 5.0 - 5.0 -
Address Setup Time Prior to Write twsA 8.0 - 10 -
Address Hold Time After Write tWHA 2.0 - 8.0 -

•
Chip Select Setup Time Prior to tWSCS 5.0 - 5.0 -
Write
Chip Select Hold Time After Write tWHCS 5.0 - 5.0 -
Write Disable Time tws 2.8 7.0 2.8 12
Write Recovery Time tWR 2.8 7.0 2.8 .12
Rise and Fall Time t r , tf ns Measured between 20% and
CS or ~ to Output 1.5 4.0 1.5 4.0 80% points.

Address to Output 1.5 8.0 1.5 8.0

Capacitance pF Measured with a pulse

I npu t Ca pac ita nce Cin - 5.0 - 5.0 technique.
Output Capacitance Cout - 8.0 - 8.0
NOTES: 1. Test circuit characteristics: RT = 50 n, MCM10146; 100 n, MCM10546. CL';;; 5.0 pf including jig and stray capacitance.
For Capacitance Loading';;; 50 pF, delay should be derated by 30 ps/pF.
2'. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
3. For proper use of MECL Memories in a system environment, consult MECL System Design Hand,book.

4-44
® MOTOROLA
MCM1 0'147IMCM1 0547
128 X 1-BIT
RANDOM ACCESS MEMORY

The MCM1047/10547 is a fast 128-word

X 1-bit RAM. Bit selection is achieved by
means of a 7-bit address, AO through A6 ..
The active-low chip selects and fast chip
select access time allow easy memory expansion
up to 512 words without affecting system
performance.
The operating mode (CS inputs low) is
controlled by the WE input. With WE low the
chip isin the write mode-the output is low and
AO .,
the data present at Din is stored at the selected
A1 " .,
£II "C
.. 0
12 WE address. With WE high the chip is in the read
~ ,~
4
A2 mode-the data state at the selected memory
"C location is presented non-inverted at D out .
A3
<{
"C
~ 11
(5 • . Typical Address Access Time of 10 ns
~ •. Typical Chip Select Access Time of 4.0 ns
• 50 k.Q Input Pulldown Resistors
on All Inputs
0
• Power Dissipation (420 mW typ @ 25 C)

•
Decreases with Increasing Temperature
A4 A5 A6
• Similar to F 1 0405

PIN ASSIGNMENT
TRUTH TABLE
VCC1 VCC2 16

MODE INPUT OUTPUT

AD D out 15
CS· WE Din D out
A1 CS1 14
Write "0" L L L L
A2 CS2 13 Wrote "1·' L L H L
A3 WE 12 Read L H rJ> a
A4 Disabled H q, rJ> L
Din 11

A5 A6 q, = Don't Care.

VEE N.C. "~

~~~_u LSUFFIX
CERAMIC PACKAGE CERAMIC PACKAGE
CASE 620 CASE 650

4-45
 MCM10147/MCM10547

ELECTRICAL CHARACTERISTICS
-SSoC ooc +25 0 C + 75°C +125 0 C
Characteristic Symbol Min Max Min Max Min Max Min Max Min Max Unit
Power Supply Drain Cunent lEE - 115 - 105 - 100 - 95 - 95 mAdc
Input Current High linH - 375 - 220 - 220 - 220 - 220 .uAdc

·55 0 C and +125 0 C test values apply to MCl 05xx devices only.

SWITCHING CHARACTERISTICS (Note 1)

MCM10147 MCM10S47
T A = 0 to +7SoC. T A'" -55 to + 125°C,
VEE = -S.2 Vdc ±5% VEl: = -S.2 Vdc ±5%
Characteristics Symbol Min Max Min Max Unit Conditions
Read Mode ns Measured from 50% of
Chip Select Access Time tACS 2.0 8.0 * * input to 50% of output.
Chip Select Recovery Time
Address Access Time
tRCS
tAA
2.0
5.0
8.0
15 .
* *
*
See Note 2.

Write Mode ns tWSA = 4.0 ns

Write Pulse Width tw 8.0 - * - Measured at 50% of input
Data Setup Time Prior to Write tWSD 1.0 - * - to 50% of output.
Data Hold Time After Write tWHD .3.0 - * - tw = 8.0 ns.
Address·Setup Time Prior to Write tWSA 4.0 - * -
Address Hold Time After Write tWHA 3.0 - * -
Chip Select Setup Time Prior to Write tWSCS 1.0 - * -
Chip Select Hold Time After Write tWHCS 1.0 - * -

II Write Disable Time

Write Recovery Time
Rise and Fall Time

Capacitance
tws
tWR
t r , tf
2.0
2.0
1.5
8.0
8.0

5.0
*
*
*
*
*

* ns

pF
Measured between 20% and
80% points.
Measured with a pulse
Input Capacitance Cin - 5.0 - * technique.
Output Capacitance Cout - 8.0 - *
NOTES: 1. Test CirCUit characterrstlcs: RT = 50 n, MCMl 0147; 100 n, MCM10547.
CL .;; 5.0 pF (including jig and stray capacitance).
Delay should be derated 30 ps/pF for capacitive load up to 50 pF.
2. The maximum Address Access Time is guaranteed to be the Worst·Case Bit in the Memory.
3. For proper use of MECL Memories in a system environment, consult MECL System Design Handbook.
*To be determined; contact your Motorola representative for up·to-date ~nformation.

4-46
.® MOTOROLA
MCM1 0148/MCM1 0548
64 X 1-BIT
RANDOM ACCESS MEMORY

The MCM10148/10548 is a fast 64-word X

l-bit RAM. Bit selection is achieved by means
of a 6-bit address, AO through A5.
The active-low chip selects and fast chip
select access time allow easy memory expansion
up to 256 words without affecting system
performance.
The operating mode (CS inputs low) is

-.
controlled by the WE input. With WE low the
AO chip is in the write mode-the output is low
~ and the data present at Din is stored at the
Al :> -
aI"O
-g:;'" 12
WE
selected address. With WE high the chip is
6 ; ~ <{aI
A2
nO
"ON
.~ ~
in the read mode-the data state at the selected
<{~
~ 10
memory location is presented non-inverted
~:o °in
"O~ 13
0 at D out .
0
~
• Typical Address Access Time of 10 ns
• Typical Chip Select Access Time of 4.0,ns
• 50 kD Input Pulldown Resistors
on All Inputs

A3 A4 A5
• Power Dissipation (420 mW typ @ 25 0 C)
Decreases with I ncreasing Temperature
PIN ASSIGNMENT

16
TRUTH TABLE
VCCI VCC2

•
D out MODE INPUT OUTPUT·
AO 15
cs· WE Din D out

-
Al N.C. 14
Write "0" L
4 CSI Din 13 Write "I" H L

CS2 WE 12 Read H q, Q

A2 N.C.
Disabled H q, q, L
11

A3 AS
LSUFFIX ·cs '" CS1 + CS2 + CS3 q, = Don't Care.
10
CERAMIC PACKAGE
VEE A4 9 CASE 620

4-47
 MCM10148/MCM10548

ELECTRICAL CHARACTERISTICS

-55°C OOC +25 0 C +75 0 C +125 0 C

Characteristic Symbol MiniMax MiniMax MiniMax MiniMax MiniMax Unit
Power Supply Drain Current lEE -- 1 115 - 1 105 - 1 100 --' 1 95 - 1 95 mAdc
Input Current High linH - 1 375 - 1 220 - 1220 - 1220 - 1220 }JAdc

-55°C and +125 0 C test values apply to MC105xx devices only.

SWITCHING CHARACTERISTICS (Note 1)

r---------------------r--------,,--------.------.-------''.---,---- --------.----.-----
MCM10148 MCM10548
~~" 0 to +75 0 C, TA" -55 to +125 0 C,
VEE" -5.2 Vdc ±5% VEE = -·5.2 Vdc ±5%
Characteristics Symbol 1-- Min _+-~M.:.:a::..:x-_+-~M::..:i~n-_+-~M.:.:a~x--+--.:U--n.:.:it_+----C-o-n-d-it-.io__n_5_:---;
Read Mode ns Measured from 50% of
Chip Select Access Time 7.5 input to 50% of output.
Chip Select Recovery Time 7.5 See Note 2.
Address Access Time 15
Writ;M~~-----·---------t--~c--+------+----t-·-
ns tWSA -~ 5.0 ns
Write Pulse Width Measured at 50% of input
Data Setup Time Prior to Write to 50% of output.
Data' Hold Time After Write tw~' 8.0 ns.
Address Setup Time Prior to Write
Address Ho!;:' Time After Write
Chip Select Setup Time Prim to Write
Chip Select Hold Time After Write

•
Write Disable Time 7.5
Write Recovery Time 7.5
Rise and Fall~-----'- 5.0 ns Measured between 20%
and 80% points.
---~---+---
Capacitance pF Measured with a pulse
Input Capacitance' Cin 5.0 technique.
_.. Output Capacitan==---.____ Cout 8.0
NOTES: 1, Test circuit characteristics: RT = 50 n, MCM10148; 100 n,MCM10548.
CL ~ 5.0 pF {i!1c!vd!ng jig and stray capacitance)
Delay should be derated 30 ps/pF for capacitive load up to 50 pF.
2. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
3. For proper use of MECL Memories in a system environment, consult MECL System Design Handbook.
"To be determined; contact your Motorola representative for up-to-date information.

4-48
® MOTOROLA
MCM1 0152/MCM1 0552
256 X 1-BIT
RANDOM ACCESS MEMORY

TheMCM10152/10552isa256-word X 1-bit
RAM. Bit selection is achieved by means of
an 8-bit address AO through A 7.
The active-low chip select allows memory
expansion up to 2048 words. The fast chip
select access time allows memory expansion
without affecting system performance.
The operating mode of the RAM (CS inputs
low) is controlled by the WE input. With WE
low 'the chip is in the write mode-the output
AD
is low and the data present at Din is stored
"
~ Q)
Al CIl"O WE at the selected address. With WE high the chip
"tl 14

A2 ~ 0~ ~ is in the read mode·-the data state at the

-0 " selected memory location is presented non-
"ON
A3
4
~S ~ inverted at D out .·
13
(;
A4 ~
• Typical Address Access Time = 11 ns
• Typical Chip Select Access Time = 4.0 ns
• 50 kD Input Pulldown Resistors
on All Inputs
• Power Dissipation (570 mW typ @ 25 0 C)
A5 A6 A7 Decreases with Increasing Temperature
• Pin-for-Pin Compatible with F10410/10414

•
PIN ASSIGNMENT

TRUTH TABLE
AD vee 16
MODE INPUT OUTPUT
Al D out 15
CS· WE Din D out
A2 WE 14
Write "0"
A3 Din 13 Write "I" H

eSl A7 12 Read H <P Q

Disabled H <P <P

eS2 A6 11

CS3 A5 ·Cs = CSI + CS2 + CS3 <P = Don't Care.

A4 w~
, "WfV1~~_U
VEE

LSUFFIX
CERAMIC PACKAGE CERAMIC PACKAGE
CASE 620 CASE 650

4-49
 MCM 10152/MCM 10552

ELECTRICAL CHARACTERISTICS

-55°C OOC +25 0 C +75 0 C +125 0 C

Characteristic Symbol Min Max Min Max Min Max Min Max Min Max Unit
Power Supply Drain Current lEE - 140 - 135 - 130 - 125 - 125 mAdc
Input Current High linH - 375 - 220 - 220 - 220 - 220 MAdc

-55°C and +125 0 C test values apply to MC 1 05xx devices only.

SWITCHING CHARACTERISTICS (Note 1)

MCM10152 MCM10552
T A = 0 to + 75°C. TA = -55 to +125 0 C.
VEE = -5.2 Vdc ±5% VEE = -5.2 Vdc ' 5%
Characteristics Symbol Min Max Min Max Unit Conditions
Read Mode Measured from 50% of
Chip Select Access Time tACS 2.0 7.5 * input to 50% of output.
Chip Select Recovery Time tRCS 2.0 7.5 * See Note 2.
Address Access Time tAA 7.0 15 * *
Write Mode ns tWSA - 5.0 ns
Write Pulse Width
Data Setup Time Prior to' Write
Data Hold Time After Write
tw
tWSD
10
2.0
2.0
-
-
. -
-
-
Measured at 50% of input
to 50% of output
tw ~ 10 ns.
tWHD
Address Setup Time Prior to Write tWSA 5.0 - * -
Address Hold Time After Write tWHA 3.0 - * -
Chip Select Setup Time Prior to Write tWSCS 2.0 - * -
Chip Select Hold Time After Write tWHCS 2.0 - * -
Write Disable Time tWS' 2.5 7.5 *
Write Recovery Time tWR 2.5 7.5
Rise and Fall Time t r • !f 1.5 5.0 * ns Measured between 20% and

•
80% points .
Capacitance pF Measured with a pulse
Input Canacitance Cin - 5.0 - * technique.
Output Capacitance Cout - 8.0 - *
NOTES: 1. Test circuit characteristics: RT = 50 n.. MCM10152; 100 n. MCM10552.
CL";; 5.0 pF (including jig and stray capacitance).
Delay should be derated 30 ps/pF for capacitive load up to 50 pF.
2. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
3. For proper use of MECL Memories In a system environment. consult ivlECL System Design Handbook.
*To be determined; contact your Motorola representative for up-to-da.te information.

4-50
® MOTOROLA
MCM1 0139/MCM1 0539
32 x 8-BIT PROGRAMMABLE
READ-ONLY MEMORY

-
16
15

3 14

4 13
12
L SUFFlx F SUFFIX 11
6
CERAMIC PACKAGE CERAMIC PACKAGE
10
CASE 620 CASE 650
8 9

The MCM10139/10539 is a 256-bit field • Typical Address Access Time =- 15 ns

programmable read only memory (PROM). • Typical Chip Select Access Time = 10 ns
Prior to programming, all stored bits are at • 50 kn Input Pulldown Resistors on all inputs
logic 0 (low) levels. The logic state of each bit • Power Dissipation (520 mW typ @ 25°C)
can then be changed by on-chip programming Decreases with I ncreasing Temperature
circuitry. The memory has a single negative
logic chip enable. When the chip is disabled
(CS = high), all outputs are forced to a logic 0
(low).

BLOCK DIAGRAM

AO 10

A111

A2 12

A3 13
Input
Decoder
32 x 8
Array and
Assoc iated Drivers
•
A414

cs 15 ------------------------~~--~_+--~_+~~_+--_._+--_._+--~_+--~

4 3 1
D7 D6 D5 D4 D3 D2 Dl DO

4-51
 MCM1 0139/MCM 10539

ELECTRICAL CHARACTERISTICS
-55°C -OoC +25 0 C +75 0 C + 125°C
Characteristic Symbol Min Max Min Max Min Max Min Max Min Max Unit
Power Supply Drain Current lEE - 160 - 150 - 145 - 140 - 160 mAdc
Input Current High linH - 450 - 265 - 265 - 265 - 265 /JAdc
Logic "0" Output Voltage VOL Vdc
MCM10139 - - -2.010 -1.665 -1.990 -1.650 -1.970 -1.625 - -
MCM10539 -2.060 -1.655 - - -1.990 -1.620 - - -1.960 -1.545

SWITCHING CHARACTERISTICS (Note 1)

MCM10139 MCM10S39
(VEE = -S.2 Vdc ±S%; (VEE = -S.2 Vdc ± 5 %;
Characteristic Symbol T A = OOC to +7S0C) T A = -SSoC to + 12S0C) Conditions
Chip Select Access Time

•
tACS 15 ns Max *
Me~sured from 50% of input to 50% ,
Chip Select Recovery Time tRCS 15 ns Max *
of output. See Note 2
Address Access Time tAA 20 ns Max *
Rise and Fall Time t r , tf 3.0 ns Typ * Measured between 20% and 80% points.
Input Capacitance Cin 5.0 pF Max *
Measured with a pulse technique.
Output Capacitance Cout 8.0 pF Max *

NOTES: 1. Test circuit characteristics.:..- RT =.50 .11, MCM 1 0139; 100 .11, M~~ 1053_9. CL .;:;; 5.0 pF including jig and stray capacitance.
For Capacitance Loading """bO pr, delay snould Oe derated Oy..su ps/p ....
2. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
3. For proper use of MECL Memories in a system environment, consult MECL System Design Handbook.

'To be determined; contact your Motorola representative for up-tO-date information.

4-52
MCM10139/MCM10539

FIGURE 1 - MANUAL PROGRAMMING CIRCUIT

+6.8 V 0.0 V +15 V

3k
Verify
-O.B V
(Momentary)
--,
I
I
Address 16 -c).-.....- Q Test
"1" Point
"0" ...----0-
460 n
Outputs
VEE
-5.2 V

CE
Open 8
7.5 k
(All Outputs)

VEE VEE '-----v-----'"

-5.2 V -5.2 V
VEE
-5.2 V

Address ~
FIGURE 2 - AUTOMATIC PROGRAMMING CIRCUIT

u U
I
L •
I I I
--L
~I--~

1 4 - - - - - - - - - - - - - < 1 Second - - - - - - - - - - - - - . . - . 1

4-53
 MCM10139/MCM10539

RECOMMENDED PROGRAMMING PROCEDURE*

The MCM10139 is shipped with all bits at logical "0" (low). To write logical "ls", proceed as follows.

MANUAL (See Figure 1). AUTOMATIC (See Figure 2)

Step 1 Connect VEE (Pin 8) to -5.2 V and Vee (Pin 16) to Step 1 Connect VEE (Pin 8) to -5.2 volts and Vee (Pin 16)
0.0 V. Address the word to be programmed by applying to 0.0 volts. Apply the proper address data and raise Vee
-1.2 to -0.6 volts for & logic "1" and -5.2 to -4.2 volts for a logic (Pin 16) to +6.8 volts.
"0" t.o the appropriate address inputs.
Step 2 After a minimum delay of 100 }JS and a maximum delay
Step 2 Raise Vee (Pin 16) to +6.8 volts. of 1.0 ms, apply a 2.5 mA current pulse to the first bit to
be programmed (0.1 ,,; PW"; 1 ms).
Step 3 After Vee has stabilized at +6.8 volts (including any
ringing which may be present on the Vee line), apply Step 3 Repeat Step 2 for each bit of the selected word specified
a current pulse of 2.5 mA to the output pin corresponding to the as a logic "1". (Program only one bit at a time. The delay
bit to be programmed to a logic "1 :'. between output programming pulses should be equal to or less than
1.0ms.!
Step 4 Return Vee to 0.0 Volts.
Step 4 A her all the desired bits of the selected word have been
CAUTION
programmed, change address data and repeat
To prevent excessive chip temperature rise, Vee should not
Steps 2 and 3.
be allowed to remain at +6.8 volts for more than 1 second.
NOTE: If all the maximum times listed above are maintained, the
Step 5 Verify that the selected bit has programmed by con- entire memory will program in less than 1 second. Therefore, it
necting a 460 .n resistor to. -5.2 volts and measuring would be permissible for Vee to remain at +6.8 volts during the
the voltage at the output pin. If a logic "1" is not detected at the entire programming time.
output, the procedure should be repeated once .. During verificati9n
VIH should be -1.0 to -0.6 volts. Step 5 After stepping through all address words, return Vee to
0.0 volts and verify that each bit has programmed. If one
Step 6 If verification is positive, proceed to the next bit to or more bits have not programmed, repeat the entire procedure
be programmed. once. During veri fication V I H should be -1.0 to -0.6 volts.

•
-NOTE: For devices that pr~gram incorrectly-return serialized units with individual truth tables. Noncompliance voids warranty ..

PROGRAMMING SPECIFICATIONS
Limits
Characteristic Symbol Min Typ Max Units Conditions
Power Supply Voltage VEE -5.46 -5.2 -4.94 Vdc
To Program Veep '¥S.04 +6.8 +7.56 Vdc
To Verify Vcev 0 0 0 Vdc
Programming Supply Current lecp - 200 600 mA Vce = +6.8 Vdc
Address Voltage VIH Program -1.2 - -0.6 Vdc
Logical "1" VIH Verify -1.0 - -0.6 Vdc
Logical "0" VIL -5.2 - -4.2 Vdc
Maximum Time a~ Vee - Vccp - - - 1.0 sec
Output Programming Current lOp 2.0 2.5 3.0 mAdc
Output Program Pulse Width to 0.5 - 1.0 ms
Output Pulse Rise Time - - - 10 }JS

Programming Pulse Delay (1)

. Following VCC change td 0.1 - 1.0 ms
Between Output Pulses td 1 0.01 - 1.0 ms

NOTE 1. Maximum is specified to minimize the amount of time V CC is at +6.8 volts.

4-54
® MOTOROI.A
MCM1 0149/MCM1 0549
256 X 4-BIT PROGRAMMABLE
READ-ONLY MEMORY

The MCM1 0149/1 0549 is a 256-word X 4-bit

PIN ASSIGNMENT
field programmable read only memory (PROM).
~ Prior to programming, all stored bits are at logic
1 (high) levels. The logic state of each bit
can then be changed by on-chip programming
circuitry. The memory has a single negative.
logic chip enable. When the chip is disabled
(CS = high), all outputs are forced to a logic
o (low).
• Typical Address Access Time of 20 ns
• Typical Chip Select Access Time of 8.0 ns
• 50 k[2 Input Pulldown Resistors
on All Inputs
0
• Power Dissipation (540 mW typ @ 25 C)
Decreases with Increasing Temperature

•
Input 32 x 32
Decoder Array and
Associated Drivers

L SUFFIX
CERAMIC PACKAGE
CASE 620

A7 7

' T - - - - - - - - - - l Output
A3 9 ,,0.--------1 Decoder I--------+-.--...J

A410

CS13--------------------------~_}------._~----~·~----~

F SUFFIX
CERAMIC PACKAGE 11 12 14 15
CASE 650 03 02 D1 DO

4-55
 MCM10149/MCM10549

ELECTRICAL CHARACTERISTICS
-55°C OOC + 25°C +75 0C +125 0C ..
Characteristic Symbol Min Max Min Max Min Max Min Max Min Max Unit
Power Supply Drain Current lEE - 140 - 135 - 130 - 125 - 125 mAdc
Input Current High linH - 450 - 265 - 265 265 !265 /JAdc

-55°C and +1 25°C test values apply to Me 105xx devices only_

SWITCHING CHARACTERISTICS (Note 1)

MCM10149 MCM10549
TA=Oto+750C, TA = -55 to +125 0 C,
VEE = -5.2 Vdc ± 5% VEE = -5.2 Vdc ±5%
Characteristics Symbol Min Max Min Max Unit Conditions
Read Mode ns Measured from 50% of
Chip Select Access Time tACS 2.0 10 " " input to 50% of output.
Chip Select Recovery Time tRCS 2.0 10 " * See Note 1.
Address Access Time tAA 7.0 25 " "
Rise and Fall Time tr,tf 1.5 7.0 " " ns Measured between 20%
and 80% points.
Capacitance pF Measured with a pulse
Input Capacitance Cin - 5.0 - 5.0 technique.
Output Capacitance C out - 8.0 - 8.0
NOTES: 1. Test circuit characterIStics: RT = 50 n, MCM10149; 100 n, MCM10549.
CL « 5.0 pF (including jig and stray capacitance)
Delay should be derated 30 ps/pF for capacitive load up to 50 pF
2. The maximum Address Access Time is guaranteed to be the Worst-Case Bit in the Memory.
3. For proper u'se of MECL Memories in a system environment, consult MECL SYstem Design Handbook.
4. VCP = VCC = Gnd for normal operation.
"To be determined; contact your Motorola representative for up-to-date information.

PROGRAMMING THE MCM10149 t

During programming of the MCM10(149, input Coincident With, or at some delay after the
pins 7, 9, and 10 are addressed with standard V CP pulse has reached its 100% level, the desired
M ECl 10K logic .Ievels. However, during program- bit to be fused can be selected. This is done by

II ming input pins 2, 3, 4, 5, and 6 are. addressed

with 0 V .;:;; VIH .;:;; + 0.25 V and VEE';:;; Vil .;:;;
-3.0 V. It should be stressed that this deviation
from standard input levels is required only during
the programming mode. During normal operation,
taking the corresonding output pin to a voltage
of + 2.85 V ± 5%. It is to be noted that only one bit
is to be fused at a time". The other three unselected
outputs should remain terminated through their
50 ohm load resistor (100 ohm for MCM10549)
standard M EC l 10,000 input levels must be used. to -2.0 V. Current into the selected output is
\,AJith ,these raqu irsrnents nlet, ano with 'v' Cp = 5 mA maximum.
VCC = 0 V and VEE = - 5.2 V ± 5%, the address After the bit select pulse has been applied to
is 'set up. After a minimum of 100 ns delay, VCP the appropriate output, the fusing current is
(pin 1) is ramped up to + 12 V ± 0.5 V (total sourced out of the chip select pin 13. The 0% to
voltage VCP to VEE is now 17.2 V, +12 V - 100% rise time of this current pulse should be
[-5.2 vl)' The rise time of this VCP voltage 250 ns max. Its pulse width should be greater than
pulse should be in the 1 -lOlls range, while its 100 IlS. Pulse magnitude is 50 mA ± 5.0 mAo The
pulse width (t w l) should be greater than 100 Ils voltage clamp on this current source is to
but less than 1 ms. The V CP supply current at + 12 be -6.0 V.
V will be, approximately 525 mA while current After the fusing current source has returned
drain from V CC will be approximately 175 mAo A o mA, the bit select pulse is returned to it initial
current limit should therefore be set on both of level, i.e., the output is re~urned through its load
these supplies. The current' limit on the VCP to -2.0 V. Thereafter, VCP isreturned to 0 V.
supply should be set at 700 mA while the V CC sup- Strobing of the outputs to determine success in
ply should be limited to 250 mAo It should be programming should occur no sooner than
noted that the VEE supply must be capable of 100 ns after V CP has returned to 0 V. The re-
sinking the combined current of the VCC and maining bits are programmed in a similar fashion.
V CP supplies while maintaining a voltage of
-5.2 V ± 5%.

t NOTE: F or devices that program incorrectly, return serialized units with individual truth tables.
Non compliance voids warranty.

4-56
MCM10149/MCM10549

PROGRAMMING SPECIFICATIONS
The following timing diagrams and fusing
Definitions and values of timing symhols are
information represent programming specifications
as follows.
for the MCM1 0149.

v cc -- Pin 16 - 0 V
Symbol Definition Value
VEE Pin 8 - -5.2 V ±5% + 12 V

VCP - Pin 1 ~ T~~5V t r1 Rise Time,

Programming Volt-age
?o 1 ]..!S
1 I

",J ~-'w'.- tw1 Pulse Width,

Programming Voltage
?o 100]..!s <1 ms

t2.85 1/ Delay Time, ?oO

t01
I ± 5%
Programming Voltage
Selecterl Output Open
Pulse to Bit
Pin (11. 12. 14 0' 15)
I Select Pu Ise

tD1-~ tw2 Pulse Width, Bit Select >- 100 ps

50 mA tD2 Delay Time, Bit Select ?oO

+5mA Pulse to Programming
Chip Select Pin 13 0 mA---+...J Voltage Pu Ise

t03 Delay Time, Bit Select ?o 1 ]..!s

Pulse to Programming
Current Pulse

•
tr3 Rise Time, Programming 250 ns max
The timing diagram is shown for programming
Current Pulse
one bit. Note that only one bit is blown at a time.
All addressing must be done 100 ns prior to the tw3 Pulse Width, ?o 100]..!s
beginning of the VCP pulse, i.e., VCP = 0 V. Programming
Likewise, strobing of the outputs to determine Current Pulse
success in programming should occur no sooner t04 Oel-ay Time, ?o 1 ps
than 100 ns after V CP retu rns to 0 V. Programming Current
Note that the fusing current is defined as Pulse to Bit
a positive current out of the chip select, pin 13. Select Pu Ise
A programming duty cycle of ~ 15% is to be
observed.

4-57
 MCM10149/MCM10549
MANUAL PROGRAMMING CIRCUIT

+5 V +5 V

12 k 8.2 k
0.0051o'F

+5 V
...I2Ot-
10'5 ..--JL-_.....L.....
Q
1 Delay
Verify
1/6 MC7406 680~ 1/2
MC8602 Enable
1/2 Current
MC8602 Q Pulse
Cp
Q -.r--L
> 100 Io's
Program
Enable +5 V
+5 V
~
1 N914
-5.2 V
(-6 V Clamp)

510
510
lN914
100 or Equiv.
-5.2 V

+5 V -12 V

+12.5 V
.....-------il...--o+5 V

1/4 150
MC7438 1/4 MC7438 240
180 n. 1/2 W 180

•
51 n. 1/2 W lN914
+5 V o--""".,--......- -....o f - - -....- - -.......

510
"0"
VCP CS

I
"'" 7
A7

5 11
A6 D3r--<~--~~-----~
1.0 k
-5.2 V 6
A5
1.0 k
12
-5.2 V
'0 D2
A4 680
1.0 k
MCM10149/ -5.2 V
-5.2 V 9
10549
A3 14
1.0 k
Dl
-5.2 V 3 680
A2 -5.2 V
1.0 k
-5.2 V 2 15
Al DO r - - < > - - - -......- - - - o
'.0 k 680
-5.2 V 4 -5.2 V

1.0 k
-5.2 V

4-58
 Memory Boards •

5-1
•
5-2
 ® MOTOROLA MMSll02

Advance Information

ADD-ON MEMORY CARD FOR THE LSI-11 FAMILY

The MMS11 02 is a dual height (5.187" x 8.94") add-on memory card for the LSI-11 family of computers.
It is compatible with the LSI-11 /2 and LSI-11 processors as well as the PDP 11 V03 computer systems. It
incorporates byte parity storage as well as generation and detection logic.

Specification Highlights
INTERFACE LSI-11, "0" Bus-Plus.
CAPACITY 8K words x 1 6 bits, 16K words x 16 bits, 32K words x 16 bits.

•
PARITY Optional on-board storage, generation and detection logic for both upper and lower byte.
Parity option does not degrade access times.
SPEED The MMS11 02-3X has a read access time under 300 ns. Read access time is defined here
as the time from receipt of SYNC H to the transmission of RPLY H, assuming that the
SYNC H to DIN H time is no greater than 160 ns.
ADDRESSING Switch-selectable, to start on any 4K word boundary between 0 and 128K.
I/O PAGE USE Three switches allow anyone of the lowest three kilowords of the I/O page to be used
as Read/Write memory.
BATIERY BACKUP Jumper selectable; allows the MMS 11 02 to be operated from a separate uninterrupted
power source (+5 BBU and +12 aaU).
REFRESH Implemented internal to the MMS11 02 and totally transparent to the system.

This is advance information and specifications are subject to change without notice.

5-3
 MMS1102

MMS1102-XX ORDERING INFORMATION

... .--------~--:~~---,..,~...-.-.---.----

~.-'
Part Number Part Number
Storage Capacity
(With Parity and Controller) (No Parity)
- .
16 Kilobytes MMS1102·31PC MMS1102-31

~
32 Kilobytes MMS1102-32PC MMS1102·32
64 Kilobytes MMS1102-34PC MMS1102-34
--
MMS1102-3X - AC <?PERATING CHARACTERISTICS
--------,-- .-
Read Access (ns) Write Access (ns)
Typical Worst Case Typical Worst Case
--
.
.-
_ .Access Time * 250 300 125 175
....•-
Cycle Time** 470 500 350 400
Refresh Latency*** 175 400 175 400
---
* As measured from receipt of RSYNC H to transmission of TRPLY H.
**This is the reciprocal of the maximum continuous transfer rate, assuming no refresh interference.
'**Occurs approximately once every 16 microseconds.

MMS1102 POWER REQUIREMENTS

Current Requirements (mA)

Standby Active
Worst Worst
Nominal Voltage Input Pins
Min Max Typical Case Typical Case
725 800 775 850
"-
+5 VDC (Total) 4.75 5.25 AA2,BA2
925* 1000' 1000· 1100'
+12 VDC 11.40 12.60 100 150 250 400 A02, S02
+5 VOC (BBU) 4.75 5.25 400 500 450 550 AV1*"
+ 12 VDC (BBU) 11.40 12.60 100 150 250 I 400 AS1***
... _-
*Parity version only.
**In systems without battery backup this voltage is obtained from the regular +5 V rail via an on-board jumper.
'**The +12 V supply requirement can be met via an on·board jumper from the regular +12 V rail.

MMS1102 BACKPLANE CONNECTOR PIN ASSIGNMENT

_ _----- t - - - - - - - - - - - - " . - - - - - - - , - - - r----.

..
Row
Side 1
A
2 1
B
2
--
Pin
A - +5 V BOCOK H +5 V
B - - -
C BA016 L** GND - GNO
0 BA017 L +12 V\ - +12 V

•
E - BOOUT L - BOAL 2 L
F - BRPLY L - BOAL 3 L
H - BOIN L - BOAL 4 L
80AL 5 L

}.
J GNO BSYNC L GNO
K BWTBT L BOAL 6 L
L } * BOAL 7 L
M GNO ;AKI L } *** GNO 80AL 8 L
N - BIAKO L - BOAL 9 L
P - BBS7 L - BOAL 10 L
R BREF L BOMGI L } .** - 80AL 11 L
S +12 V BBU BOMGO L ' - BOAL 12 L
T GND - GNO BOAL 13 L
U - BOAL 0 L - BOAL 14 L
V +5 V BBU BOAL 1 L +5 V BDAL 15 L
*Must be hardwired on backplane or damage to MOS devices may result.
**Or PRTYER or PRTYCK.
***Hardwired on MMSll 02.

S-4
 ® MOTOROLA MMSIIIO

Advance In£orIDation

16K x 16
LSI-11 ADD-IN SEMICONDUCTOR MEMORY

The Motorola MMS1110 is a 16K-word x 16-bit board that contains timing, control and bus interface
plug-in main memory system designed for use with logic. Memory refreshing is controlled by the LSI-11.
DEC's LSI-11 microcomputer system. The MMS1110 Address select changes are possible with jumpers
mounts directly into a H9270 backplane slot and is to provide up to 28K of main memory. A parity
both hardware and software compatible with the option, which generates, stores, and checks parity on
LSI-11 system. the MMS1110, is available for custom LSI-11
The memory module employs the MCM6604 4K systems.
Dynamic RAM components, mounted on a single PC

MMS1110 FEATURES
•
•
•
High Density
Low Cost
Fast Access and Cycle Times
•
•
Modular Expandability (Address Select Jumpers)
Options Available
MMS1110-1
MMS1110-2
12K x 16
8K x 16
•
• High Reliability
MMS1110P 16K x 18 (parity)
• Byte Operation
MMS1110-3 4K x 16

This is advance information and specifications are subject to change without notice.

5-5
 MMS1110

SPECIFICATIONS

CAPACITY
16K words per board

WORD LENGTH
16 bits

PERFORMANCE
Access Time 450 ns max
Read Cycle Time 800 ns min
Write Cycle Time 800 ns min
Read-Modify-Write Cycie Time 1275 ns min

DC POWER REQUIREMENTS
Standard With Parity
Active* Standby Active* Standby
+5 V ± 5% 6.0W max 6.0W max 7.5W max 7.5W max
+12 V ± 5% 12.5 W max
---._-- 2.8W max 14.0W max 3.1 W max
Total 18,5 W max 8.8 W max 21.5W max 10.6W max

*Continuous operation such as DMA

MODES OF OPERATION
Read -" Word
Write -" Word/Byte
Read-Modify-Write Cycle- Word/Byte

INTERFACE CHARACTERISTICS
Compatible with DEC Q bus**

STANDARD I/O SIGNALS

Sync (BSYNC L)
Data In (BDIN L)
Data Out (BDOUT L)
Reply (BRPLY L)
Refresh (BREF L)
Write Byte (BWTBT L)
Date/Address (BDALO L -- BDAL 15 L)
PQwer Up (BDCOK H)

• PHYSICAL DIMENSIONS OF BOARD

10.45" x 8.9" x 0.44"

ENVI RONMENT
Operating
Non-Operating
Humidity
DoC to +55 0 C
-40°C to +125 0 C
To 90% without condensation

• 'Trademark of Digital Equipment Corporation

 ® MOTOROLA MMSll17

Advance InforIllation

PDP-11* UNIBUS* COMPATIBLE RANDOM ACCESS MEMORIES, UP TO 128 KILOBYTES OF

STORAGE CAPACITY PLUS OPTIONAL PARITY CONTROLLER ON A SINGLE CARD

\
The MMSll17 family of memory systems offers owners The MMSl117 can provide up to 128K 8-bit bytes
of POP-ll * computers an opportunity to easily add of main memory on a single module. Quick address select
storage capacity and parity features to their system_ Each changes are possible via onboard switches. In addition,
member of the family is contained on a single plug-in 1 or 2 kilowords of I/O page can selectively be made
circuit card that interfaces mechanically and electrically available for random access storage. Optional parity as
with the following models of UNIBUS* POP-ll* proces- well as full parity generation, detection, and exception
sors: 11/04,11/05,11/10,11/34,11/35,11/40,11/45, control circuits can be provided on the same card with the
11/50, 11/55, and 11/60_ It plugs into a single hex SPC memory. No additional bus loading is imposed on the
slot in any of the following backplanes: 0011-B, 0011-C, system by the addition of the fully compatible parity
0011-0 and 0011-P. controller option.

MMS1117 FEATURES
11
• High Density • Fully UNIBUS Compatible
• Low Cost • High Reliability
• Fast Access and Cycle Times • One UNIBUS Load
• Low Power

*Trademark of Digital Equipment Corporation

This is advance information and specifications are subject to change without notice.

5-7
 MMS1117

MMSll17 OPTION DESIGNATOR SUFFIX

Typical Read Total Storage Capacity (in Kilobytes)

Access Time Parity Options 32K 64K 96K 128K
290 ns Parity + Controller -32-PC -34-PC -36-PC -38-PC
Parity Data Only -32-P -34-P -36-P -38-P
No Parity -32 -34 -36 -38
360 ns Parity + Controller -42-PC -44-PC -46-PC -48-PC
Parity Data Only -42-P -44-P -46-P -48-P
No Parity -42 -44 -46 -48

390 ns Parity + Controller -52-PC -54-PC -56-PC -58-PC

Parity Data Only -52-P -54-P -56-P -58-P
No Parity -52 -54 -56 -58

ACCESS AND CYCLE TIMES

Option Designator Write Read Cycle

Suffix Typical Worst Case Typical Worst Case Typical Worst Case
-3X 105 125 290 315 375 390
-4X 115 135 360 390 480 500
-5X 115 135 390 420 560 585

MMS1117 POWER REQUIREMENTS

Current Requirements
Voltage Tolerance Standby-Typ/WC Active- Typ/WC
Nominal Voltage Min Max (Amps) (Amps) Input Pins
+5 Vdc 4.75 5.25 2.0/2.5 2.0/2.5 DA2, EA2,·FA2
+15 Vdc 15 20 0.15/0.20 0.35/0.70 AV1, AR1, CE1, CU1
-15 Vdc -7.0 ":20 0.015/0.030 0.015/0.030 FB2

MMSll17 BACK PLANE CONNECTOR PIN ASSIGNMENT

Row A B C 0 E F
Side 1 2 1 2 1 2 1 2, 1 2 1 2
Pin A rL ",. +5 V +5 V +5 V
Pin B -15V
Pin C Gnd Gnd PA Gnd Gnd A12 Grid Gnd
Pin 0 +5BB 015 A17 A15
Pin E 'SSyn 'PA OE "'VOO 014 MSyn A16
Pin F 013 A02 C1
Pin H 011 012 A01 AOO

rL ••..
Pin J 010 SSyn CO
Pin K 009 A14 A13
Pin l 008 Init A11
PinM 007 r ••
Pin N 'P1 OClO 004 L •• A08
Pin P 'PO 005 r •• A10 A07

II Pin R
Pin S
Pin T
Pin U
Pin V
"'VOO

Gnd

"'VOO
Gnd
PB
Gnd
"'VOO
001
000
003
002
006
Gnd
L"
r ••
L ••
A09

Gnd
A06
A05
A04
A03
Gnd

Options for use with External Panty Controller.

"Grant Continuity Jumpers
**'VOD is any voltage between + 15 Vdc and +20 Vdc on anyone of the four listed pins.

5-8
 ® MOTOROLA MMSll18

Advance InforDl.ation

16Kx 18 BIT
PDP-11 ADD-IN SEMICONDUCTOR
MEMORY

The Motorola MMS1118 is a 16K x 18 bit plug-in main mounted on a single PC board that contains timing, con-
memory system designed for DEC's PDP-11/04 and 34 trol and bus interface logic.
computer family; The MMS1118 mounts directly into With DEC's memory management unit, the MMS1118
DEC's Modified UNIBUS* and is both hardware and soft- can provide up to 127K words of main memory. Quick ad-
ware compatible in the PDP-11 systems with or without dress select changes are possible with on board jumpers.
parity. The low power and fast acCess time of the MMS1118 will
The system employs the low power MCM6605A-2 4K greatly enhance the cost performance of a PDP-11
Dynamic RAM component. These RAM components are computer.

MMS1118 FEATURES
• High Density
• LowCost
• Fast Access and Cycle Times
• LowPower
• Modular Expandability (Address Select Jumpers)
• Module Interchangeability
• Short Circuit Memory Protection
• Optional Systems Available
•
• Byte Operation MMS1118-1 12K x 18
MMS1118-2 8K x 18
• High Reliability
• Power Down/Card Select Option

*Trademark of DigitalEquipment Corporation • Compatible with 0011 L Backplane (Consult Factory)

This is advance information and specifications are subject to change without notice.
 MMS1118

SPECIFICATIONS
CAPACITY MODES OF OPERATION
8K, 12K and 16K words per board Read - Word
Write - WordlByte
WORD LENGTH
18 bits INTERFACE CHARACTERISTICS
Compatible with DEC's Modified UNIBUS'
PERFORMANCE
Access Time 550 ns max ST ANDARD 110 SIGNALS
Read Cycle Time 700 ns min Master Sync - MSYN Internal Slave Sync - INTSSYN
Write Cycle Time 700 ns min Byte Select - CO Panty Bits - PO, Pl
Cycle Time with Refresh Interrupt. 1400 ns min' ReadlWrite -Cl DC Low - DCLO
Slave Sync - SSYN Address - AO-A 17
Parity Detect - PARDET Data - DO-D15
DC CURRENT REQUIREMENTS
Active" Standby
+ 5V±5% 1.9 A max 1.9 A max PHYSICAL DIMENSIONS OF BOARD
+ 15V±5% 400 mA max 60mA max 15.7" x 8.94" x 0.44"
-15V±20% 15 mA max 10 mA max

,ENVIRONMENT
Operating O°C to 55°C
"Continuous operation such as DMA Non-operating - 40°C to 125°C
Humidity 90% without condensation

BACKPLANE OPTIONS ADDRESSING

~!~~PLANEI:R~5V Jumper table for starting addresses

DDII-C Jumper selection
DDII-D Starting Address Addresses below
(Octal) starting address A B C D E
DDII-P -15V
AS1 0,
00000o OK 1 1 'I 0
020000 4K 1 1 0 1 1
040000 8K 1 1 0 1 0
-fN -5V 060000 12K 1 1 0 0 1

~~~~PLANEI:V~OV REGULATOR ARRAY 100000 16K 1 1 0 0 0

120000 20K 1 0 1 1 1
140000 24K 1 0 1 1 0
DDII-F 160000 28K 1 0 1 0 1
200000 32K 1 0 1 0 0
220000 36K 1 0 0 1 1
-5V 240000 40K 1 0 0 1 0
BV2 260000 44K 1 0 0 0 1
300000 48K 1 0 0 0 0
320000 52K 0 1 1 1 1
SPC -15V 340000 56K 0 1 1 1 0
SLOT CB2 360000 60K 0 1 1 0 1
40000u 64K 0 1 .1 0 ,0
420000 68K 0 1 '0 1 1
440000 72K 0 1 0 1 0
~~V:JE7
--'-~----------~--"·A~~:Y 460000
500000
76K
80K
0 1 0
0 1 0
0
0
1
0
BA2 . 520000 84K 0 0 1 1 1
540000 BBK 0 0 1 1 0
560000 92K 0 0 1 0 1
~D~BB E6
600000
620000
96K
lOOK
0 0 1
0 0 0
0
1
0
1
640000 104K 0 0 0 1 0
660000 100K 0 0 0 0 1
700000 112K 0 0 0 0 0
720000 116K 1 1 1 1 1
740000 120K 1 1 1 1 0

•
Semiconductor memory Core backplane
'backplane DDII-C, D,P DDII-F Jumper table for board options

Without battery backup With -15 V on CB2: Memory capacity Jumper selection
Cut: E4, E6, E10, E13 Cut E4, E6, E8, E9 F H J

With battery backup 16K (normal use) 1 0 1

Without -15 V on CB2 12K only 1 1 f
Cut: Er, E7, E10
With -5 V on BV2 14K (Lower 2K of I/O
Cut: E5, E6, E8, E9,E13 page assigned to
memory)'" 1 1 0
15K (Lower 3K of I/O
page assigned to
memory)'" 0 1 0
Power options selectable by zero ohm resistors shown above.
"'Set switches A-E for starting address of 100000 (Octal)
1 =OPEN=HIGH O=CLOSED=LOW

5-10
 ® MOTOROLA MMS3418

Advance InforDl.ation

128K X 18
SEMICONDUCTOR MEMORY

The Motorola M MS3418 Memory Array Card large memory. Multiple memory array cards can
provides 128K words by 18 bits of memory. I t is be used to increase word length and/or number
designed for use with a memory control card such as of words stored.
Motorola's MMSCC-2 in systems requiring a very

Basically the MMS3418 is an array of 144 high-

density, 16-pin, 16K dynamic RAM devices arranged
in eight rows of eighteen. Buffer and driver circuits
on the card interface the array to system circuitry.
by external signals, function to connect the proper
combination of address, strobe, and enable signals
to the array to provide read, write, and distributed
refresh operations. Sequencing and timing. is a func-
•
Gate and multiplexer circuits, which are controlled tion of the associated system circuits.

This is advance information and specifications are subject to change without notice.

5-11
 MMS3418

SPECIFICATIONS·

CAPACITY
128K Words per Board (K = 1024)

WORD LENGTH
18 Bits per Board

CYCLE TIME
Read Cycle Time 700 ns max
Write Cycle Time 700 ns max
Determined by associated memory control card

ACCESS TIME .
475 ns max

MODES OF OPERATION
Read 18 Bits, Write 18 Bits, Distributed Refresh

DC POWER REQUIREMENTS
Voltage Active Standby

+5 V ± 5% 2A max 2 A max
+15 V ± 5% 1 Amax 0.6 A max
-9V±10% 0.1 A max 0.1 A max

ENVIRONMENT
Operating Temperature o to 70 0 C
Non-Operating Temperature -40 to 1250 C
Humidity to 90% without condensation

BOARD DIMENSIONS
See outline diagram

INPUT/OUTPUT SIGNALS
Name Description Connector Pin

DO to 017 Bidirectional data, 18 bits Pl-9 to Pl-26

Al toAll, Memory address, 14 bits P2-8to P2-18,
A12 to A14 P2-48 to P2-50
RAO to RA6 Refresh address, 7 bits P2-51 to P2-57

•
R/W Read or write control, 1 signal P2-21
BS Board select, 1 signal P2-30
DATA ENABLE Data output enable, 1 signal P2-32
RASO to RAS7 Row address strobe, 8 signals P2-72 to P2-65
REF Refresh control, 1 signal P2-24
CAS Column address strobe, 1 signal P2-26
CAE Column address enable, 1 signal P2-25

5-12
 3:
3:
MMS3418 MEMORY ARRAY CARD BLOCK DIAGRAM
~
~
-'
CO
ROW
ADDRESS
A1 TO A14 A1 TO A7
COLUMN
ADDRESS ,ADDRESS ROW/COLUMN
CAE BUFFER AS TO A14 MULTIPLEXER

ROW OR COLUMN ADDRESS MEMORY ADDRESS MEMORY ARRAY ROW

as CAE WHEN REF IS LOW (Bits 0-8)
U1 0
COLUMN ADDRESS 1
WHEN CAE HIGH 2
ADDRESS 3

RAO TO RA6 J NAND

GATE II REFRESH ADDRESS
DRIVER
MEMORY ADDRESS
4
5

~
WHEN REF IS HIGH (Bits 9-17) 6
as U144 7

ROW ADDRESS
BSJ CONTROL lSTROBE DRIVER
ENABLED WHEN
REF REF ] GATE
ISS IS LOW OR REF HIGH
ROW
ADDRESS
L STROBE
RASa DRIVER M"ii'ASii T0 M'RA'S"7
~ TO
fi"A'S7
CONTROL
BUFFER RASO TO RAS7
TO ROWS 0 THROUGH 7 RESPECTIVELY
ONE LINE LOW IN READ/WRITE
W ALL LINES LOW IN REFRESH
ROW ADDRESS STROBE.S LINES

BS
DATA ENABLE
DATA ENABLE
WRO AND WFi2 TO ROWS 0.1.2.3
WRITE/READ WR1 AND Wii3 TO ROWS 4.5.6.7
WRITE/READ DRIVER ALL LOW IN WRITE
CONTROL DRIVER ENABLED WHEN ALL HiGH IN READ AND REFRESH
R/W
GATE REF IS LOW.AND DATA
ENABLE IS HIGH CASO AND CAS2 TO ROWS 0.1.2.3
COLUMN ~ASl AND CAS3 TO ROWS 4.5.6.7

!
CAS ADDRESS LL LOW WHEN REF AND CAS BOTH LOW
STROBE
DATA TRANSCEIVER DRIVER DRIVER
TO BUS ENABLED WHEN
BS. DATA ENABLE. AND R/W ARE HIGH

DiD TO 0i17 DATA IN TO ALL DEVICES

DATA
DO TO 017 BI-DIRECTIONAL DATA BUS TRANSCEIVER

...
-- ---
DOD TO 0017 DATA OUT FROM ALL DEVICES

- _ . -
 MMS3418

MMS3418 MEMORY ARRAY CARD TIMING DIAGRAM (ALL TIMES IN NANOSECONDS)

~~
700 MAX

200
MIN "
ADDRESS -j//~ VALID ADDRESS ~

RAS
--. r-- 520MAxi
35 MIN/5sMAX

210MAxi'
f4-.1 00 MIN ~
120MAX

CAE

I+----- ==:j 550 MAX

CAS
145 MIN
ISS MAX
'I
~?5 500

WRITE DATA
MAX
,/_

VALID
MIN
'I /////////~

~~~X "-
600

READIWRITE
(WRITE-ACTIVE LOW)
""
MIN
'I
/

READ DATA
475
MAX

OAT A BUS ENABLE

'I
X VALID DATA
-1 r 30
MAX

READIWRITE
(READ-ACTIVE HIGHl
--
- LJ
35
MAX 1_
600
MIN

600
'I
DATA ENABLE &
-
_200
MAX
MIN

BOARD SELECT
(ACTIVE LOW)

BOARD OUTLINE AND DIMENSIONS

• 9.70
.382
1

5-14
 ® ItIIOTOROLA MMS68102

Advance InforIllation

16K x 8 NON-VOLATILE SEMICONDUCTOR MEMORY

The Motorola MMS681 02 is a 16K x 8-Bit Non-Volatile The MMS681 02, using an external battery backup cir-
Memory System designed for use with the M6800 EXOR- cuit, has the capability of refreshing itself while power is
ciser System.· removed from the EXORciser power supply. This refresh
The system employs the MCM6605 22 pin 4K dynamic capability enables the module to retain its stored data
RAM component. These RAM components are mounted during a power loss.
on a single PC board that contains timing, control, and The MMS68102 may be paralleled to provide 64K
bus interface logic. The refresh requirement is handled words of memory. Onboard jumpers provide easy address
by stealing cycles from the processor. CMOS logic is select changes.
used in the refresh and powerfail circuits to allow low
power battery backup operation.

MMS68102 FEATURES

• High Density
• Low Cost
• Module Interchangeability
• Low Power Battery Backup Operation
• Systems Available
•
• Fast Access and Cycle Times MMS68102-18Kx8
• High Reliability MMS68102A 16K x 9
• Modular Expandability (Address Select Switches) MMS68102A-18Kx9
• Trademark of Motorola, Inc.
This is advance information and specifications are subject to change without notice.
 MMS68102

SPECIFICATIONS

CAPACITY INTERFACE CHARACTERISTiCS

16K words per board M6800 EXORciser Compatible

WORD LENGTH STANDARD 1/0 SIGNALS

'8 bits Memory CJock (MEMCLK)
Valid Memory Address (VMA)
PERFORMANCE ReadlWrite (RIW)
Access Time" 280 ns max Address (AO-A15)
Read Cycle Time 1.0 US min Data (fm-57)
Write Cycle Time 1.0 uS min Valid User Address (VUA)
Refresh Cycle Time 1.0 US min Refresh Request (REFREQ)
"Measured from rising edge of MEMCLK Refresh Grant (REFGRANT)
Battery + 12 Volts (BAT+12)
DC POWER REQUIREMENTS 16K x 8(9)
ADDITIONAL 1/0 SIGNALS
Battery
Active*** Standby Backup Power Fail (12 Volt Signal) (SIDBY) PinV
+5 V ±5% 4.2 Wmax 4.2 Wmax Refresh Clock (12 Volt Signal) (REFCLK) Pin 27
+ 12 V ± 5% 3.4 Wmax 1.4 Wmax .3 Wmax Parity Data (D8) Pin 28

Total 7.6 Wmax 5.6 Wmax .3 Wmax PHYSICAL DIMENSIONS OF BOARD

MODES OF OPERATION 6" x 9.75" x .5"
Read Cycle
Write Cycle ENVIRONMENT
Operating O°C to 70°C
Non-Operating - 40°C to 125°C,
"*Continuous operation such as DMA
Humidity To 90% without condensation
. PREPROGRAMMING: Table"1
* CAUTlON: The MMS68102 comes prewired OPTIONS JUMPERS IN JUMPERS OUT
in the following manner: I

VUA E4 E5
(1) Master Refresh VMA E5 E4
(2) VUA Master Refresh E1 &E6
(3) Lower32K Address Boundary Slave Refresh E1 & E6
For Alterations of the fibove see Table 1. Lower32K E3 E2
Upper32K E2 E3

AD'DRESSING

A fully populated MMS681 02 can be programmed with An example of mapping block A into address space
jumpers to occupy a 16K Memory Address Space, but (12K-16K) is as follows:
must be mapped on a 32K boundary. Lower 32K is selected with E2 out & E3 in.
The independent 4K blocks of the MMS68102 are Block A enable Pin 9 or 10 of J1 , from Table 3, is con-
shown as blocks A, B, C, & D in Figure 1. These blocks nected to Pin 7 of J1, from Table 2, for the (12K-16K) ad-
need not be mapped into any contiguous address,space, dress space .

•
but should not be mapped into the same one.

Table 2 Table 3
I BLOCK A I : E6 LOWER 32K UPPER 32K J1 J1 BLOCK ENABLE
I ,,.sLOCK B I PIN PIN
I BLOCKC I 1 J1 16 OK-4K 32K-36K 1 9& 10 A
I BLOCK D
,0 oE4
I 0
o 00 oE2
4K-SK
SK-12K
36K-4OK
40K-44K
3
5
11 & 12
13& 14
B
C
o 0E5 E1 0 0E3
12K-16K 44K-48K 7 15& 16 D
16K-2OK 48K-52K 2
2OK-24K 52K-56K 4
Figure 1 24K-2SK 56K-6OK 6
2SK-32K 6OK-64K 8

5-16
 ® MOTOROLA MMS68103

Advance InforIllation

16K x 8 SEMICONDUCTOR MEMORY

FOR M6800 SYSTEMS

The Motorola MMS68103 is a 16K-word x 8-bit additional cycles or interface from the CPU. This
plug-in memory module designed for use with permits the use of valuable CPU time for purposes
M6800 based systems. other than refreshing.
The module employs high density, 16-pin, 4K The MMS681 03 can provide up to 64K words of
dynamic RAM components, mounted on a single PC memory. Address select changes are easily made
board that contains timing, control, and bus inter- with on-board address jumpers.
face logic. A hidden refresh scheme requires no

MMS681 03 FEATURES
• Hidden Refresh
• High Density
• Low Cost
• Fast Access and Cycle Times
• High Reliability
• Modular Expandability (Address Select
• MEK6800D2 Compatible
• MicroModule Compatible
• Options Available
MMS68103-1 8K x 8
MMS68103A 16-K x 9
MMS68103A-1 8K x 9
•
Jumpers)

This is advance information and specifications are subject to change without notice.

_ 5:J7
 MMS68103

SPECIFICATIONS

CAPACITY

16K words per board

WORD LENGTH

8 bits

PERFORMANCE

Access Time 475 ns max

Read Cycle Time 1.0 J,ls min. 2.5 uS max·
Write Cycle Time 1.0 J,ls min. 2.5 uS max·
·(256 B02 cycles required within 640 us)

DC POWER REQUIREMENTS

Active" Standby
+5 V ±5% 6.0 Wmax 6.0 Wmax
+12 V ±5% 4.0 Wmax 2.0 Wmax
-12 V± 10% 0.02 W max 0.02 W max
Total 10.02 W max 8.02 W max
·Continuous operation such as DMA

MODES OF OPERATION

Read Cycle
Write Cycle

INTERFACE CHARACTERISTICS

MC6800 Compatible

ST ANDARD I/O SIGNALS

Bus 02 (B02)
Valid User Address (VUA)

II
Read/Write (R/W)
Address (AO-A15)
Data (00-07)

PHYSICAL DIMENSIONS OF BOARD

6.00" x 9.75" x 0.44"

ENVIRONMENT

Operating O°C to 70°C

Non-Operating -40°C to 125°C
Humidity To 90% without condensation

5-18
® MOTOROLA MMS68104

16K x 8 SEMICONDUCTOR MEMORY

FOR M6800 SYSTEMS

The Motorola MMS681 04 is a 16K x 8-bit plug In mem- trol, and bus Interface logic. The system employs a
ory system designed for use with the MEK6800D2 Kit. handshake refresh that Interfaces with the CPU.
The system employs the high density 16 pin 4K The MMS681 04 can provide up to 64K words of memo-
dynamic RAM component. These RAM components are ry. Address select changes are easily made with on-
mounted on a single PC board that contains timing, con- board address Jumpers ..

MMS68104 FEATURES

• High Density
• Low Cost
• High Reliability
• Modular Expandability (Address Select Jumpers)
•
5-19
 MMS68104

SPECIFICATIONS
CAPACITY INTERFACE CHARACTERISTICS
16K words per board MC6800 Compatible

WORD LENGTH STANDARD I/O SIGNALS

8 bits Memory Clock (MEMCLK) Refresh Grant (REF GNT)
Valid Memory
PERFORMANCE Address (VMA) Refresh Request (REF REO)
ReadlWrlte (RIW)
Access Time 650ns max'
Address (AO-A15)
Read Cycle Time 1.5/LS min
Data (00-07)
Write Cycle Time 1..5/Ls min
'From leading edge of MEMCLK
PHYSICAL DIMENSIONS OF BOARD
DC CURRENT REQUIREMENTS 600" x 9.75" x 0.44"
Actlve** Standby
+5 V ±5'10 920 mA max 920 mA max ENVIRONMENT
+12V±5% 450 mA max 80 mA max Operating O°C to 50°C
-12V ±10% 10 mA max 10 mA max Non-Operating - 40°C to 125°C
Total 1.4Amax 1.1 Amax Humidity To 90% without condensation
"Continuous operation such as DMA

ADDRESSING
The MMS68104 can be programmed with jumpers to occupy 16K in a 64K memory address space in independent 8K
blocks. To map the first 8K block into an address space, connect either J1-1 0, 13, 14 or 16 to the indicated pin in the
following table. To map the second 8K block into an address space, connect either J1-9, 11, 12 or 15 to the indicated pin
in the following table.

HEXADECIMAL ADDRESS PIN NUMBER

ADDRESS SPACE ON Jl
0000-lFFF OK- 8K 1
2000 -3FFF 8K -16K 2
4000 -5FFF 16K -24K 4
6000 -7FFF 24K -32K 6
8000-9FFF 32K -40K 3
AOOO -BFFF 40K -48K 5
COOO -DFFF 48K ;-56K 7
Eooo -FFFF 56K -64K 8

MEMORY EXPANSION
Four MMS68104 memory boards may be connected to the same bus to provide up to 64K words. When two or more
MMS68104s are connected to the same bus, E1 should be removed from all but one of the memory boards. (E1 is a green
zero ohm jumper located near the connector edge on the MMS68104.) This enables the one MMS68104 to act as the
master when requesting refresh cycles which all of the memory boards utilize.

APPLICATION TO MEK6800D2 KIT

U15 MC6871B
The following is a description of the modifications and MPUCLOCK
additions that are needed for using the MMS68104 3 TTL 20
02 ~--------.
memory card in the MEK6800D2 kit.

•
2 fc
1. Unplug 6810 RAMS (U14, U16, U18, U19) on kit
24
board.
2. Cut foil path to U7, pin 4. Tie pin 4 to + 5V. +5V
3. Plus, the following additions: See Figure 1. +5V +5V
4. For further information on adding data terminal and
memory expansion refer to Application Note 771.

The "U" prefiX refers to

existing D2 kit IC
packages.

FROM U9, PIN 9 ---<---../

5-20
 ,-'0
I At

;!I
r:, III 11 III 1
.,," ""'
:::~il
..
'2
:! 1;1
13

.1
3
7
SEE TIMING DIAGRAM BELOW
11 R11
R12
R13
OA3
DA'
DA
12
11
10
MEMORIES
" , , " UIN. .ARRAY
.,".,,

ROW ADDRESS lAO TO A51 WHEN CLK IS LOW

COLUMN ADDRESS IA6 TO A 111 WHEN CI'K IS LOW

g I~ I ·1 :11
REFRESH ADDRESS DISABLED
DURING READ/WRITE

REF 113 ONE OUTPUT OF U12 GOES LOW

FOR EACH COMBINATION
OF nTI AND T<rP"
WHEN A"A"S GOES LOW RAS2
FROM
KIT B'A"i2 lIAs.
AI213_'
A13 N
A,. Q 'rnl'
A15 33 m RAS4
'o'MA F
R/W 6
=
ONE RAS LINE GOES LOW
WHEN i1 GOES HIGH
SEE TIMING DIAGRAM BELOW
7400
2

HIGH WHEN
SYSTEM SELECTED

LOW IN WRITE MODE WHEN 1'1 GOES HIGH

ME" ~

'R'.
eLK
(]1
I ~

~
Wl-EN T4 GOES HIGH

r
EKCEPT OlRING REFRESH
1:]

U9&U13
.J=
TRANSCEIVERS

RECEIVER
ENABLED
FOR WRITE
TRANSMITTER

;~~~~

15 DE RDI 14

1ft
, RE R02

~ ~ gg; :g: ~
"

9 '90 ~ns 5?O 9?0 13po 'spa

1\: ~ gg! g:; ~ NANO SECOKlS I 7?O! ! I 17[>0
rn p
013 7
2
MEMeLK --+--- --7 ~
I
~~%~c=============
U9 014 4
TO/FROM
ADDRESS

L~ I"
DATA BIT
POSITIONS

2 3 0 ,
~ ,\:0

II
m J ITR

n
fi

+5 +'2'0' +5'0'
324096-BIT
RAMOEVICES
REi s
en S
en
:e·'
R19j" e161 eI21,0.,

wi X y
I WRITE

rnn
en
00
....a.
SCHEMATIC REVISION 2 MMS681 04 Memory System ReadlWrite o,a:::.,
APPLIES TO MEMORY BOARD REV A Schematic Diagram

II
 II
;~ 1
~1
DAI 5
~~
..
R18~6
.2 READ/WRITE ADDRESS
~12
DEVICE
MEMORIES
ADDRESS
IN ARRAY
TO ALl.

'3
t;1 DISABLED BY RG IN REFRESH ~11
A5 ~10
~

iq~1
REF 113
I: 1 COUNTER IN U15 ADVANCED
ONE STEP EACH REFRESH CYCLE
RG
,pO ;~~~-tr~~ ';I~~~Y 03 'r MICROSECONDS
.
~ 12 REF""'REo
GNT U -\
RAS2

RASi
MEMORY ROW SELECT CIRCUITS
OISABLED IN REFRESH
R'AS4

=
1fJ:'§'1 -1!fA'54 LOW IN REFRESH R14
(SEE TIMING DIAGRAM)
WHEN I f GOES HIGH

01 Wi!i'iTl HIGH IN REFRESH 18

I
I\) R2
I\) 18

l!A§' HIGH IN REFRESH

J OS

END
"to

fi

WA
________~..~
t:= L--

'lZ7fl27 ?/27!22zW/* ~

~, ~
~NOTEALLTIIroESINNANOSECON:)S
s:
s:
en
MMS681 04 Memory System Refresh
0)
Schematic Diagram
00
-'
SCHEMATIC REVISION 2 o
APPLIES TO MEMORY BOARD REV A ~
 ® MOTOROI.A MMS80810

Advance In:forInation

32K x 8 SEMICONDUCTOR MEMORY

FOR 8080A SYSTEMS

The Motorola MMS80810 is a 32K~word x 8 bit plug in tained on the memory board. A refresh cycle is generated
memory system designed for use with 8080A based by on-board refresh logic and is asynchronous to the
systems and is pin compatible with SSC 80/10 single CPU.
board computer. A fully populated MMS8081 0 can be programmed with
The system employs the high density 16 pin 4K jumpers to occupy 32K words out of a possible 64K
dynamic RAM component. The RAM components are memory space in independent 8K segments. The 8K
mounted on a single PC board that contains timing, con- segments must begin at 8K boundaries. Address select
trol and bus interface logic. Refresh logic is also con- changes are easily made with on-board address jumpers.

II
MMS80810 FEATURES
• High density • Modular Interchangeability
• Lowcost • Optional Systems Available:
• Fast access and cycle times MMS8081 0-1 16K x8
• High Reliability
• Modular Expandability (Address Select Jumpers)

ThiS is advance infoRnation and specifications are subject to change without notice.

5-23
 MMS80810

SPECIFICATIONS

CAPACITY INTERFACE CHARACTERISTICS

32K words per board SBC 80/10 Compatible

WORD LENGTH STANDARD 1/0 SIGNALS

8 bits Read MRDCI
Write MWTCI
PERFORMANCE System Reset INITI
Access Time 400 ns max* Address ADROI-ADRFI
Read Cycle Time 760 ns min* Data DATOI-DATlI
Write Cycle Time 760 ns min* Transfer Acknowledge XACKI
• Refresh cycle can extend these times by 760 ns.
PHYSICAL DIMENSIONS OF BOARD
MODES OF OPERATION 12" x 6.75" x 0.5"
Read Cycle
Write Cycle ENVIRONMENT
Operating O°C to 70°C
Non-Ope(ating - 40°C to 125°C
Humidity To 90% without
condensation

DC POWER REQUIREMENTS
32Kx8 16Kx8
Active· Standby Active· Standby
+5V±5% 6.0 Wmax 6.0 Wmax 6.0 Wmax 6.0 Wmax
+12V ±5% 7.5 Wmax 3.0· Wmax· 6.5 Wmax 1.5 Wmax
-5V ±10% 0.1 Wmax 0.1 Wmax 0.1 Wmax 0.1 Wmax
Totql 13.6 Wmax 9.1 Wmax 12.6 W.max 7.6 Wmax
·Continuous operation such as DMA

I.C. SOCKET MEMORY ADDRESS PIN OUT 8K BLOCK ENABLES

HEXADECIMAL ADDRESS PIN# Block Pin#

ADDRESS SPACE ONJ1 ONJ1

0000-lFFF OK-SK 1 A 9,10

2000-3FFF SK-16K 3 B 11,12
4000-5FFF 16K-24K 5 C 13,14
6000-7FFF 24K-32K 7 D 15,16
8000-9FFF 32K-4OK 2
AOOO-BFFF 40K-48K 4

•
COOO-DFFF 48K-56K 6 Table 2 .
EOOO-FFFF 56K-64K 8

Table 1.

The independent 8K blocks of the MMS80810 are

, C
~},I} D
shown as blocks A, B, C & D in Figure 1. These blocks
need not be mapped into any contiguous address space,
but should not be mapped into the same one.
An example of mapping block A into address space
(8K-16K) is as follows:
Block A Enable Pin 9 or 10 of J1 , from Table 2 is con-
nected to Pin 3 of J1, from Table 1, for the (8K-16K) ad-
PIN1 Figure 1. dress space. For 16K, blocks A & B will be populated.

5-24
 Mechanical Data •
6-1
I 6-2
MECHANICAL DATA
The packaging availability for each device is indicated on the individual data sheets. Dimensions
for the packages are given in this section.

- - - - - - - - - - 14-PIN PACKAGES

CERAMIC PACKAGE
CASE 632

~
4 8~
1 7t:J DIM
MILLIMETERS
MIN MAX MIN
INCHES
MAX

-ll-o J F
A
B
19.05 19.94
6.10 7.49
0.750 0.785
0.240 0.295 NOTES:
1. ALL RULES AND NOTES ASSOCIATED
C - 5.08 - 0.200
D 0.38 0.58 0.015 0.023 WITH MO·OOI AA OUTLINE SHALL APPLY.
F 1.40 1.77 0.055 0.070 2. DIMENSION "L"TO CENTER OF LEADS
G 2.54 BSC 0.100 BSC WHEN FORMED PARALLEL.
H 1.91 2.29 0.075 I 0.090 3. DIMENSION "A" AND "B" (632·06) DO
J 0.20 I 0.38 0.008 I 0.015
NOT INCLUDE GLASS RUN·OUT.
K 3.18 I 5.08 0.125 I 0.200
L 7.62 BSC 0.300 BSC 4. LEADS WITHIN 0.25 mm (0.010) DIA
M - I 15° - 15° OF TRUE POSITION AT SEATING PLANE
N 0.51 I 1.02 0.020 0.040 AND MAXIMUM MATERIAL CONDITION.

CASE 632-06

PLASTIC PACKAGE
CASE 646

MILLIMETERS INCHES NOTES:

1. LEADSWITHINO.13mm
DIM MIN MAX MIN MAX
(0.005) RADIUS OF TRUE
A 18.16 19.56 0.715 0.770 POSITION AT SEATING
B 6.10 6.60 0.240 0.260 PLANE AT MAXIMUM
C 4.06 5.08 0.160 0.200 MATERIAL CONDITION.
D 0.38 0.53 0.015 0.021 2. DIMENSION "L" TO
F 1.02 1.78 0.040 0.070 CENTER OF LEADS
G 2.54 BSC 0.100BSC WHEN FORMED
H 1.32 I 2.41 0.052 I 0.095
PARALLEL.
J 0.20 I 0.38 0.008 0.015
3. DIMENSION "BuDOES NOT
K 2.92 I 3.43 0.115 0.135
INCLUDE MOLD FLASH.
L 7.62 BSC 0.300 BSC

•
100 4. ROUNDED CORNERS OPTIONAL.
M 0° I 100 0°
N 0.51 I 1.02 0.020 0.040

CASE 646-05

6-3
MECHANICAL DATA (Continued)

- - - - - - - - - - 1 6 - P I N PACKAGES

CERAMIC PACKAGE
CASE 620

r--- A
c

.~
I MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 19.05 19.94 0.750 0.785
B 6.10 7.49 0.240 0.295
C - 5.08 - 0.200
D 0.38 0.53 0.015 0.021
F 1.40 1.78 0.055 0.070
G 2.54 BSC 0.100 BSC
PLANE H 0.51 1.14 0.020 I 0.045
J 0.20 0.30 0.008 I 0.012
K 3.18 I 5.08 0.125 I 0.200
1. LEADS WITHIN 0.13 mm (0.005) RADIUS 4. DIM "A" AND "B" DO NOT INCLUDE L 7.62 BSC 0.300 BSC
OF TRUE POSITION AT SEATING PLANE GLASS RUN:OUT. M - I 15° - 15°
AT MAXIMUM MATERIAL CONDITION. 5. DIM "F" MAY NARROW TO 0.76 mm N 0.51 I 1.02 0.020 0.040
2. PACKAGE INDEX: NOTCH IN LEAD (0.030) WHERE THE LEAD ENTERS
NOTCH IN CERAMIC OR INK DOT. THE CERAMIC BODY. CASE 620-06
3. DIM "L"TO CENTER OF LEADS WHEN
FORMED PARALLEL.

CERAMIC PACKAGE
CASE 650

r.; ..,
I 9 8 I
t
_~
I I
I A

L 1 I

to
I
I
1

--lr--R
16 1
::.J
I
I

I 11
iN
1t-----._
l .1 DIM
MILLIMETERS
MIN MAX
INCHES
MIN MAX
A 9.40 10:16 0.370 0.400

U
B 6.22 7.24 0.245 0.285
C 1.52 2.03 0.060 0.080
D 0.41 0.48 0.016 0.019
F 0.08 0.15 0.003 0.006
G 1.27 BSC 0.050 BSC

tc
f H
K
L
0.64 0.89
6.35 ·9.40
18.92 -
0.025 0.035
0.250 0.370
0.745 -
-N - 0.51 - 0.020
NOTES:
1. LEAD NO. 1 IDENTIFIED BY TAB R - 0.38 - 0.015
ON LEAD OR DOT ON COVER.
2. LEADS WITHI N 0.13 mm (0.005) CASE 650-03
TOTAL OF TRUE POSITION AT
MAXIMUM MATERIAL CONDITION.

6-4
MECHANICAL DATA (Continued)

- - - - - - - - - 1 6 - P I N PACKAGES (Continued)

CERAMIC PACKAGE
CASE 690

NOTE; .
1. LEADS WITHIN 0.13 mm (0.005) RADIUS
OF TRUE POSITION AT SEATING PLANE
AT MAXIMUM MATERIAL CONDITION.

MILLIMETERS INCHES MILLIMETERS INCHES

DIM MIN MAX MIN MAX DIM MIN MAX MIN MAX
A 20.07 20.57 0.790 0.810 A 20.07 20.57 0.790 0.810
S 7.11 7.62 0.280 0.300 S 7.11 7.62 0.280 0.300
C 2.67 3.81 0.105 0.150 C 2.67 3.94 0.105 0.155
0 0.38 0.53 0.015 0.021 D 0.38 0.53 0.015 0.021
F 0.76 1.40 0.030 0.055 F 0.76 1.40 0.030 0.055
G 2.54 sse 0.100 sse G 2.54 sse 0.100 sse
H 0.76 I 1.78 0.030 I 0.070 H 0.76 1.78 0.030 I 0.070
J 0.20 I 0.30 0.008 I 0.012 J 0.20 0.30 0.008 0.012
K 3.56 I 4.06 0.140 I 0.160 K 3.18 5.08 0.125 0.200
L 7.62 sse 0.300 sse L 7.62 sse 11.300 sse
M - I 100 - I 100 M - 10 0 - I 100
N 0.38 I 1.40 0.015 I 0.055 N 0.38 1.40 0.015 I 0.055
CASE 690-11 CASE 690-12

PLASTIC PACKAGE
CASE 648

OPTIONAL LEAD
CONFIG. (1,8,9,& 16)
A - - - - - - 1\ NOTE 5

MILLIMETERS INCHES NOTES;

DIM MIN MAX MIN 1. LEADS WITHIN 0.13 mm
MAX
(0.005) RADIUS OF TRUE

r. =J
A 18.80 21.34 0.740 0.840
POSITION AT SEATING
S 6.10 6.60 0.240 0.260
.------_----,~
PLANE AT MAXIMUM
C 4.06 5.08 0.160 0.200 MATERIAL CONDITION.
L D 0.38 0.53 0.015 0.021

J~jjFj
2. DIMENSION "L" TO
F 1.02 1.78 0.040 0.070
CENTER OF LEADS
G 2.54 Bse 0.100 sse WHEN FORMED
H 0.38 2.41 0.Q15 0.095
J 0.20 0.38 0.008 0.015 PARALLEL.
3. DIMENSION "B" DOES NOT

H
~ --I G I-- JL D SEATING K
PLANE
-II-J M l-
.
K
L
M
2.92 3.43
7.62 Bse
00 100
0.115 0.135
0.300 Bse
00 100
INCLUDE MOLD FLASH.
4. "F" DIMENSION IS FOR FULL

•
N a.51 1.02 0.020 o.a40 LEADS. "HALF" LEADS ARE
OPTIONAL AT LEAD POSITIONS
1,8, 9"and 16).
CASE 648-05 5. ROUNDED CO RNERS OPTIONAL.

6-5
 MECHANICAL DATA (Continued)

- - - - - - - - - - - 1 8 - P I N PACKAGES - - - - - - - - - -

CERAMIC PACKAGE
CASE 680

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 22.48 23.24 0.B85 0.915
B 7.16 7.57 0.282 0.298
C 3.18 4.27 0.125 0.168
D 0.38 0.58 0.015 0.023
F 0.76 1.40 0.030 0.055
G 2.54 BSC 0.100 BSC
H 1.02 1.52 0.040 0.060
J 0.20 0.30 0.008 0.012
NOTES:
K 2.68 4.44 0.105 0.175
1. LEADS WITH I N 0.13 mm (0.005) RAD 0 F
L 7.37 7.87 0.290 0.310
TRUE POSITION AT SEATING PLANE AT
MAXIMUM MATERIAL CONDITION.
M - 100 - 100
N 0.38 1.40 0.015 0.055 '
2. DIMENSION "L" TO CENTER OF LEADS
WHEN FORMED PARALLEL.
CASE 680-06

PLASTIC PACKAGE
CASE 707

1 - - - - - - - - 'A

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 22.22 23.24 0.875 0.915
B 6.10 6.60 0.240 0.260
C 3.94 4.57 0.155 0.180
D 0.36 0.56 0.014 0.022
F 1.27 1.78 0.050 0.070
G 2.54 Bse 0.100 Bse
NOTES: H 1.021 1.52 0.040 0.060
1. POSITIONAL TOLERANCE OF LEADS (D), J 0.20 I 0.30 0.008 0.012
SHALL BE WITHIN 0.25mm(O.010) AT K 2.92 I 3.43 0.115 0.135
MAXIMUM MATERIAL CONDITION, IN L 7.62 BSC 0.300 Bse
RELATION TO SEATING PLANE AND M 00 I 150 ooL 150
EACH OTHER. N 0.511 1.02 0.020 I 0.040
2. DIMENSION L TO CENTER OF LEADS

II WHEN FORMED PARALLEL. CASE 707-02

3. DIMENSION BODES NOT INCLUDE
MOLD FLASH.

6-6
MECHANICAL DATA (Continued)

- - - - - - - - - 1 8 - P I N PACKAGES (Continued) - - - - - - - -

PLASTIC PACKAGE
CASE 701-01

MILLIMETERS INCHES
NOTES: DIM MIN MAX MIN MAX
1. LEADSWITHINO.13mm
A 23.11 23.88 0.910 0.940
(0.005) RADIUM OF TRUE
B 6.10 6.60 0.240 0.260
POSITION AT SEATING
C 4.06 4.57 0.160 0.180
PLANE AT MAXIMUM
D 0.38 0.51 0.015 0.020
MATERIAL CONDITION
(DIM "G"). F 1.02 1.52 0.040 0.060
G 2.54 BSC 0.100 BSC
2. DIMENSION "L" TO CENTER H 1.32 1.83 0.052 0.072
OF LEADSWHEN FORMED J 0.20 0.30 0.008 0.012
PARALLEL. K 2.92 3.43 0.115 0.135
L 7.37 7.87 0.290 0.310
M 00 10 0 00 10 0
N 0.51 1.02 0.020 0.040

CASE 701-01

- - - - - - - - - - - 22-PIN PACKAGES - - - - - - - - - -
CERAMIC PACKAGE
CASE 677

22 12
NOTES:
1. LEADS WITHIN
0.13 mm (0.005)
B RADIUS OF TRUE
POSITION AT
II, \ 11
MAXIMUM
MATERIAL

I. \NOTE 3 CONDITION.
2. DIMENSION "L" TO
CENTER OF LEADS
A WHEN FORMED MILLIMETERS INCHES
PARALLEL. DIM MIN MAX MIN MAX
3. EXPOSED CONTACT A 27.15 27.71 1.069 1.091
TO LEAD 1, B 9.65 10.06 0.380 0.396
OPTIONAl. C 2.79 3.56 0.110 0.140
0 0.38 0.53 0.015 0.021
F 0.76 1.40 0.030 0.055
G 2.54 BSC 0.100 BSC
H 0.51 1.52 0.020 0.060
J 0.20 0.30 0.008 0.012
K 3.18 4.45 0.125 0.175
L 9.91 10.41 0.390 0.410
M - 100 - 10 0

•
N 0.64 1.27 0.025 0.050

CASE 677-05

6-7
 MECHANICAL DATA (Continued)

- - - - - - - - - 22-PIN PACKAGES (Continued)

PLASTIC PACKAGE
CASE 708

G:::::::::J f

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 28.83 29.59 1.135 1.165
B 8.64 9.14 0..340. 0..360.
C 4.57 5.0.8 0..180 0.20.0.
NOTES: D 0..36 0..51 0..0.14 0..020.
F 1.0.2 1.52 0..0.40. 0..0.60.
1. POSITIONAL TOLERANCE OF LEADS (0), G 2.41 2.67 0..0.95 0..10.5
SHALL BE WITHIN 0.25mm(O.0ID) AT H 1.18 2.03 0.0.70. 0..080.
MAXIMUM MATERIAL CONDITION, IN J 0.20 0.30. 0.0.0.8 0..0.12
RELATION TO SEATING PLANE AND K 3.0.5 3.56 0.120. 0..140.
EACH OTHER. L 9.65 10.16 0.380. 0.40.0
2. DIMENSION L TO CENTER OF LEADS M DO 100 00 10.0
WHEN FORMED PARALLEL. N 0.51 1.02 0..0.20 0.0.40
3. DIMENSION B DOES NOT INCLUDE
MOLD FLASH. CASE 708-01

- - - - - - - - - - 24-PIN PACKAGES

CERAMIC PACKAGE
CASE 684

NOTES:
1. LEADS WITHI N 0..13 mm
(0.0.0.5) RADIUS OF TRUE
POSITION AT SEATING
PLANE WITH MAXIMUM
MATERIAL CONDITION.
2. LEAD NO.1 CUT FOR
IDENTIFICATION, OR
BUMP ON TOP.
3. DIM "L" TO INSIDE
OF LEAOS. (MEASURED MILLIMETERS INCHES
0.51 mm (0.0.20) BELOW DIM MIN MAX MIN MAX
PKG BASE) A 29.34 30.86 1.155 1.215
B 12.70 14.22 0.50.0 0..560.
C 3.05 3.94 0.120 0.155
c D 0..38 0..51 0.015 0.020
F 0.89 1.40. 0..035 0..0.55
G 2.54 BSC 0..100. BSC
H 0..89 1.40. 0..0.35 0..0.55
nI rIll N K J J 0.20. 0.30. 0..0.0.8 0..0.12
.:.J ~ ---.' K 2.92 3.68 0..115 0..145

~EATING PLANE !-1M

L 14.86 15.87 0..585 0..625
L
M - 15 0 - 15 0

•
N 0..51 1.14 0..0.20. 0..0.45

CASE 684-04

6-8
M'ECHAN ICAl DATA (Continued)

- - - - - - - - - 2 4 - P I N PACKAGES (Continued)
CERAMIC PACKAGE
CASE 623

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 31.24 32.26 1.230 1.270
B 12.70 13.72 0.500 0.540
C 4.06 5.59 0.160 0.220
D 0.41 0.51 0.016 0.020
F 1.27 1.52 0.050 0.060
G 2.54 BSC 0.100SSC
J 0.20 0.30 0.008 I 0.012
K 2.29 4.06 0.090 I 0.160
L 15.24 sse 0.600 sse
NOTES: M 0° 15° 00 I 15°
1. DIM "L" TO CENTER OF 2. LEADS WITHIN 0.13 mm N 0.51 1.27 0.020 0.050
LEADS WHEN FORMED (0.005) RADIUS OF TRUE
PARALLEl. POSITION AT SEATING CASE 623-03
PLANE AT MAXIMUM
MATERIAL CONDITION.
(WHEN FORMED PARALLEL)

CERAMIC PACKAGE
CASE 623A

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 31.24 32.26 1.230 1.270
B 12.70 13.72 0.500 0.540
C 4.06 5.84 0.160 0.230
D 0.41 0.51 0.016 0.020
F 1.27 1.52 0.050 0.060
G 2.54 sse 0.100 sse
J 0.20 0.30 0.008 0.012
K 2.29 4.06 0.090 0.160
L 15.24 sse 0.600 sse
NOTES: M 00 I 15° 0° 15°
1. DIM "L"TO CENTER DF 2. LEADS WITHIN 0.13 mm N 0.51 I 1.27 0.020 0.050
LEADS WHEN FORMED (0.005) RADIUS OF TRUE
PARALLEl. POSITl.ON AT SEATING PLANE CASE 623A-01
AT MAXIMUM MATERIAL
CONDITION. (WHEN FORMED

•
PARALLEL).

6-9
 MECHANICAL DATA (Continued)

- - - - - - - - 24-PIN PACKAGES (Continued) - - - - - - - -

CERAMIC PACKAGE
CASE 716

NOTE:
1. LEADS TRUE POSITIONED WITHIN MILLIMETERS INCHES
0.25mm (0.010) DIA (AT SEATING
DIM MIN MAX MIN MAX
PLANE) AT MAXIMUM MATERIAL
CONDITION. A 27.64 30.99 1.088 1.220
B 14.94 15.34 0.588 0.604
2. DIM "L" TO CENTER OF LEADS C 2.67 4.32 0.105 0.170
WHEN FORMED PARALLEl. D 0.38 0.53 0.015 0.021
F 0.76 1.40 0.030 0.055
G 2.54 BSC 0100 IiS,C
H 0.76 1.78 0.030 0.J!1ll.
J 0.20 0.30 0.008 Jl.JJ.1l.
K 2.54 4.19 0.100 0.165
L 14.99 15.49 0.590 0.610
M - 10 0 100
N 1.02 1.52 0.040 0.060

CASE 716-06

NOTE:
1. LEADS TRUE POSITIONED WITHIN
0.25mm (0.010) DIA (AT SEATING
PLANE) AT MAXIMUM MATERIAL
CONDITION. .
2. DIM "L"TO CENTER OF LEADS
WHEN FORMED PARALLEL MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 27.64 30.99 1.088 1.220
B 14.94 15.34 0.588 0.604
C 3.18 5.08 0.125 0.200
D 0.38 0.53 0.015 0.021
F 0.76 1.40 0.030 0.055
G 2.54 BSC\ 0.100 SSC
H 0.76 1.18 0.030 0.070
J 0.20 0.30 0.008 0.012
K 2.54 4.19 0.100 0.165
l 14.99 15.49 0.590 0.610
M - 100 100 -
N 1.02 1.52 0.040 0.060

CASE 716-07

I 6-10
MECHANICAL DAtA (Continued)

- - - - - - - - 2 4 - P I N PACKAGES (Continued) - - - - - - - - -

PLASTIC PACKAGE
CASE 709

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 31.37 32.13 1.235 1.265
PLANe"
B 13.72 14.22 0.540 0.560
C 3.94 5.08 0.155 0.200
D 0.36 0.56 0.014 0.022
NOTES: F 1.02 1.52 0.040 0.060
1. POSITIONAL TOLERANCE OF LEAOS (0), G 2.54 BSC 0.100 BSC
SHALL BE WITHIN 0.25 mm (0.010) AT H 1.65 2.03 0.065 I 0.080
MAXIMUM MATERIAL CONOITION, IN J 0.20 0.38 0.0081 0.01 5
RELATION TO SEATING PLANE ANO K 2.92 3.43 0.115 I 0.135
L 15.24 BSC 0.600 BSC
EACH OTHER. 00 00 I 150
M 15°
2. DIMENSION L TO CENTER OF LEADS N 0.51 1.02 0.020 I 0.040
WHEN FORMED PARALLEL.
3. DIMENSION B DOES NOT INCLUDE MOLD CASE 709-02
FLASH.

6-11 •
 NOTES

II 6-12
NOTES
NOTES
NOTES
NOTES
NOTES
 SELECTOR
II GUIDES
CROSS-REFERENCE·

NMOS Memories
II RAM, EPROM, ROM

CMOS Memories
II RAM, ROM

• Bipolar Memories
TTL, MECL-RAM, PROM

• Memory Boards .

• Mechanical Data
It"'~· · ~
.. jiJ; . . , ••
• •••••••••
~~il~\
.... ...' YI...a;;