Regulation – 2018 (CBCS Scheme) Computer Organization – 18CS34

MODULE 2: INPUT/OUTPUT ORGANIZATION

2.1 ACCESSING I/O DEVICES

• There are 2 ways to deal with I/O devices (Figure 4.1).

1) Memory mapped I/O
• Memory and I/O devices share a common address-space.
• Any data-transfer instruction (like Move, Load) can be used to exchange information.
• For example, Move DATAIN, R0; this instruction reads data from DATAIN(input-buffer associated
with keyboard) & stores them into processor-register R0.
2) In I/O mapped I/O, memory and I/O address-spaces are different.
• Special instructions named IN and OUT are used for data transfer.
• Advantage of separate I/O space: I/O devices deal with fewer address-lines.

2.2 I/O Interface for an Input Device

• Address decoder: decodes address sent on bus, so as to enable input-device (Figure 4.2).
• Data register: holds data being transferred to or from the processor.
• Status register: contains information relevant to operation of I/O device.
• Address decoder, data- and status-registers, and control-circuitry required to coordinate I/O
transfers constitute device's interface-circuit.

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2.2.1 MECHANISMS USED FOR INTERFACING I/O DEVICES

1) Program Controlled I/O
• Processor repeatedly checks a status-flag to achieve required synchronization between processor
& input/output device. (We say that the processor polls the device).

• Main drawback: The processor wastes its time in checking the status of the device before actual
data transfer takes place.

2) Interrupt I/O
• Synchronization is achieved by having I/O device send a special signal over bus whenever it is
ready for a data transfer operation.

3) Direct Memory Access (DMA)

•This involves having the device-interface transfer data directly to or from the memory without
continuous involvement by the processor

2.3 INTERRUPTS
• I/O device initiates the action instead of the processor. This is done by sending a special hardware
signal to the processor called as interrupt (INTR), on the interrupt-request line.
• The processor can be performing its own task without the need to continuously check the I/O
device.
• When device gets ready, it will "alert" the processor by sending an interrupt-signal (Figure 4.5).

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• The routine executed in response to an interrupt-request is called ISR(Interrupt Service Routine).

• Once the interrupt-request signal comes from the device, the processor has to inform the device
that its request has been recognized and will be serviced soon. This is indicated by a special control
signal on the bus called interrupt-acknowledge (INTA).

2.3.1 Difference between subroutine & ISR

• A subroutine performs a function required by the program from which it is called.
However, the ISR may not have anything in common with the program being executed at the time
the interrupt-request is received. Before starting execution of ISR, any information that may be
altered during the execution of that routine must be saved. This information must be restored
before the interrupted-program resumed.
• Another difference is that an interrupt is a mechanism for coordinating I/O transfers whereas a
subroutine is just a linkage of 2 or more function related to each other.

• The speed of operation of the processor and I/O devices differ greatly. Also, since I/O devices are
manually operated in many cases (like pressing a key on keyboard), there may not be
synchronization between the CPU operations and I/O operations with reference to CPU clock. To
cater to the different needs of I/O operations, 3 mechanisms have been developed for interfacing
I/O devices. 1) Program controlled I/O 2) Interrupt I/O 3) Direct memory access (DMA).

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• Saving registers increases the delay between the time an interrupt request is received and the
start of execution of the ISR. This delay is called interrupt latency.
• Since interrupts can arrive at any time, they may alter the sequence of events. Hence, facility must
be provided to enable and disable interrupts as desired.
• Consider the case of a single interrupt request from one device. The device keeps the interrupt
request signal activated until it is informed that the processor has accepted its request. This
activated signal, if not deactivated may lead to successive interruptions, causing the system to enter
into an infinite loop.

2.4 INTERRUPT HARDWARE

• An I/O device requests an interrupt by activating a bus-line called interrupt-request(IR).
• A single IR line can be used to serve „n‟ devices (Figure 4.6).
• All devices are connected to IR line via switches to ground.
• To request an interrupt, a device closes its associated switch. Thus, if all IR signals are inactive(i.e.
if all switches are open), the voltage on the IR line will be equal to Vdd.
• When a device requests an interrupt by closing its switch, the voltage on the line drops to 0,
causing the INTR received by the processor to go to 1.
• The value of INTR is the logical OR of the requests from individual devices
INTR=INTR1+ INTR2+ . . . . . +INTRn
• A special gate known as open-collector or open-drain are used to drive the INTR line.
• Resistor R is called a pull-up resistor because it pulls the line voltage up to the high-voltage state
when the switches are open.

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2.5 ENABLING & DISABLING INTERRUPTS

• To prevent the system from entering into an infinite-loop because of interrupt, there are 3
possibilities:
1) The first possibility is to have the processor-hardware ignore the interrupt-request line until the
execution of the first instruction of the ISR has been completed.
2) The second option is to have the processor automatically disable interrupts before starting the
execution of the ISR.
3) In the third option, the processor has a special interrupt-request line for which the interrupt-
handling circuit responds only to the leading edge of the signal. Such a line is said to be edge-
triggered.

• Sequence of events involved in handling an interrupt-request from a single device is as follows:

1) The device raises an interrupt-request.
2) The program currently being executed is interrupted.

3) All interrupts are disabled (by changing the control bits in the PS).
4) The device is informed that its request has been recognized, and in response, the device
deactivates the interrupt-request signal.
5) The action requested by the interrupt is performed by the ISR.
6) Interrupts are enabled again and execution of the interrupted program is resumed.

2.6 HANDLING MULTIPLE DEVICES

While handling multiple devices, the issues concerned are:

1. How can processor recognize the device
requesting an interrupt?
2. How can processor obtain the starting address of
the ISR?
3. How should 2 0r more simultaneous interrupt
requests be handled?

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2.6.1 Polling
• Information needed to determine whether a device is requesting an interrupt is available in its
status-register.
• When a device raises an interrupt-request, it sets IRQ bit to 1 in its status-register (Figure 4.3).
• KIRQ and DIRQ are the interrupt-request bits for keyboard & display.
• Simplest way to identify interrupting device is to have ISR poll all I/O devices connected to bus.
• The first device encountered with its IRQ bit set is the device that should be serviced. After
servicing this device, next requests may be serviced.
• Main advantage: Simple & easy to implement.
Main disadvantage: More time spent polling IRQ bits of all devices (that may not be requesting any
service).

2.6.2 Vectored Interrupts

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• A device requesting an interrupt identifies itself by sending a special-code to processor over bus.
(This enables processor to identify individual devices even if they share a single interrupt-request
line).
• The code represents starting-address of ISR for that device.
• ISR for a given device must always start at same location.
• The address stored at the location pointed to by interrupting-device is called the interrupt-vector.
• Processor
→ loads interrupt-vector into PC &
→ executes appropriate ISR
• Interrupting-device must wait to put data on bus only when processor is ready to receive it.
• When processor is ready to receive interrupt-vector code, it activates INTA line.
• I/O device responds by sending its interrupt-vector code & turning off the INTR signal.

2.6.3 CONTROLLING DEVICE REQUESTS

• There are 2 independent mechanisms for controlling interrupt requests.
• At device-end, an interrupt-enable bit in a control register determines whether device is allowed
to generate an interrupt request.
• At processor-end, either an interrupt-enable bit in the PS register or a priority structure
determines whether a given interrupt-request will be accepted.

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2.7 INTERRUPT NESTING

• A multiple-priority scheme is implemented by using separate INTR & INTA lines for each device
• Each of the INTR lines is assigned a different priority-level (Figure 4.7).
• Priority-level of processor is the priority of program that is currently being executed.
• During execution of an ISR, interrupt-requests will be accepted from some devices but not from
others depending upon device’s priority.
• Processor accepts interrupts only from devices that have priority higher than its own.
• At the time of execution of an ISR for some device is started, priority of processor is raised to that
of the device
• Processor's priority is encoded in a few bits of processor-status (PS) word. This can be changed by
program instructions that write into PS. These are called privileged instructions.
• Privileged-instructions can be executed only while processor is running in supervisor-mode.
• Processor is in supervisor-mode only when executing operating-system routines. (An attempt to
execute a privileged-instruction while in the user-mode leads to a special type of interrupt called a
privileged exception).

2.7.1 SIMULTANEOUS REQUESTS

• INTR line is common to all devices (Figure 4.8).
• INTA line is connected in a daisy-chain fashion such that INTA signal propagates serially through
devices.
• When several devices raise an interrupt-request and INTR line is activated, processor responds by
setting INTA line to 1. This signal is received by device 1.

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• Device 1 passes signal on to device 2 only if it does not require any service.
• If device 1 has a pending-request for interrupt, it blocks INTA signal and proceeds to put its
identifying code on data lines.
• Device that is electrically closest to processor has highest priority.
• Main advantage: This allows the processor to accept interrupt-requests from some devices but
not from others depending upon their priorities.

2.8 EXCEPTIONS
• An interrupt is an event that causes
→ Execution of one program to be suspended &
→ Execution of another program to begin.
• Exception refers to any event that causes an interruption. I/O interrupts are one example of an
exception.
2.8.1 Recovery from Errors
• Computers use a variety of techniques to ensure that all hardware-components are operating
properly. For e.g. many computers include an error-checking code in main-memory which allows
detection of errors in stored-data.
• If an error occurs, control-hardware detects it & informs processor by raising an interrupt.

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• When exception processing is initiated (as a result of errors), processor

→ suspends program being executed &
→ starts an ESR(Exception Service Routine). This routine takes appropriate action to recover from
the error to inform user about it.
2.8.2 Debugging
• Debugger
→ helps programmer find errors in a program and
→ uses exceptions to provide 2 important facilities: 1) Trace & 2) Breakpoints
• When a processor is operating in trace-mode, an exception occurs after execution of every
instruction (using debugging-program as ESR).
• Debugging-program enables user to examine contents of registers (AX, BX), memory-locations
and so on.
• On return from debugging-program,
next instruction in program being debugged is executed, then debugging-program is activated
again.
• Breakpoints provide a similar facility except that program being debugged is interrupted only at
specific points selected by user. An instruction called Trap(or Software interrupt) is usually
provided for this purpose.
2.8.3 Privilege Exception
• To protect OS of computer from being corrupted by user-programs, certain instructions can be
executed only while processor is in supervisor-mode. These are called privileged instructions.
• For e.g. when the processor is running in user-mode, it will not execute an instruction that
changes priority-level of processor.
• An attempt to execute such an instruction will produce a privilege-exception. As a result,
processor switches to supervisor-mode & begins to execute an appropriate routine in OS.

2.9 DIRECT MEMORY ACCESS (DMA)

• The transfer of a block of data directly between an external device & main memory without
continuous involvement by processor is called as DMA.
• DMA transfers are performed by a control-circuit that is part of I/O device interface. This circuit is
called as a DMA controller (Figure 4.19).

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• DMA controller performs the functions that would normally be carried out by processor
• In controller, 3 registers are accessed by processor to initiate transfer operations (Figure 4.18):
1) Two registers are used for storing starting-address & word-count
2) Third register contains status- & control-flags
• The R/W bit determines direction of transfer.
When R/W=1, controller performs a read operation(i.e. it transfers data from memory to I/O),
Otherwise it performs a write operation (i.e. it transfers data from I/O device to memory).
• When done=1, controller
→ completes transferring a block of data &
→ is ready to receive another command.
• When IE=1, controller raises an interrupt after it has completed transferring a block of data
(IE=Interrupt Enable).
• Finally, when IRQ=1, controller requests an interrupt. (Requests by DMA devices for using the bus
are always given higher priority than processor requests).
• There are 2 ways in which the DMA operation can be carried out:
1) In one method, processor originates most memory-access cycles. DMA controller is said to
"steal" memory cycles from processor. Hence, this technique is usually called cycle stealing.
2) In second method, DMA controller is given exclusive access to main-memory to transfer a block
of data without any interruption. This is known as block mode (or burst mode).

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2.10 BUS ARBITRATION

• The device that is allowed to initiate data transfers on bus at any given time is called bus-master.
• There can be only one bus master at any given time.
• Bus arbitration is the process by which next device to become the bus-master is selected and bus-
mastership is transferred to it.
• There are 2 approaches to bus arbitration:
1) In centralized arbitration, a single bus-arbiter performs the required arbitration.
2) In distributed arbitration, all device participate in selection of next bus-master.

2.10.1 CENTRALIZED ARBITRATION

• A single bus-arbiter performs the required arbitration (Figure: 4.20 & 4.21).
• Normally, processor is the bus. master unless it grants bus mastership to one of the DMA
controllers.
• A DMA controller indicates that it needs to become busmaster by activating Bus-Request line(BR).

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• The signal on the BR line is the logical OR of bus-requests from all devices connected to it.
• When BR is activated, processor activates Bus-Grant signal(BG1) indicating to DMA controllers
that they may use bus when it becomes free. (This signal is connected to all DMA controllers using a
daisy-chain arrangement).
• If DMA controller-1 is requesting the bus, it blocks propagation of grant-signal to other devices.
Otherwise, it passes the grant downstream by asserting BG2.
• Current bus-master indicates to all devices that it is using bus by activating Bus-Busy line (BBSY).
• Arbiter circuit ensures that only one request is granted at any given time according to a
predefined priority scheme

A conflict may arise if both the processor and a DMA controller try to use the bus at the same time
to access the main memory. To resolve these conflicts, a special circuit called the bus arbiter is
provided to coordinate the activities of all devices requesting memory transfers

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2.10.2 DISTRIBUTED ARBITRATION

• All device participate in the selection of next bus-master (Figure 4.22)
• Each device on bus is assigned a 4-bit identification number (ID).
• When 1 or more devices request bus, they
→ assert Start-Arbitration signal &
→ place their 4-bit ID numbers on four open-collector lines ARB 0 through ARB 3 .
• A winner is selected as a result of interaction among signals transmitted over these lines by all
contenders.
• Net outcome is that the code on 4 lines represents request that has the highest ID number.
• Main advantage: This approach offers higher reliability since operation of bus is not dependent on
any single device.

2.11 BUSES
• Bus
→ is used to inter-connect main-memory, processor & I/O devices
→ includes lines needed to support interrupts & arbitration
• Primary function: To provide a communication-path for transfer of data.
• Bus protocol is set of rules that govern the behaviour of various devices connected to the buses.

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• Bus-protocol specifies parameters such as:

→ asserting control-signals
→ Timing of placing information on bus
→ Rate of data-transfer
• A typical bus consists of 3 sets of lines: 1) Address, 2) Data and 3) Control lines.
• Control-signals specify whether a read or a write operation is to be performed.
• R/W line specifies
→ read operation when R/W=1
→ write operation when R/W=0
• In data-transfer operation, one device plays the role of a bus-master which initiates data transfers
by issuing Read or Write commands on bus ( Hence it may be called an initiator).
• Device addressed by master is referred to as a slave (or target).
• Timing of data transfers over a bus is classified into 2 types:
1) Synchronous and 2) Asynchronous
2.11.1 SYNCHRONOUS BUS
• All devices derive timing-information from a common clock-line.
• Equally spaced pulses on this line define equal time intervals.
• Each of these intervals constitutes a bus-cycle during which one data transfer can take place.
A sequence of events during a read operation:
• At time t0, the master (processor)
→ places the device-address on address-lines &
→ sends an appropriate command on control-lines (Figure 4.23).
• Information travels over bus at a speed determined by its physical & electrical characteristics.
• Clock pulse width (t1-t0) must be longer than the maximum propagation-delay between 2 devices
connected to bus.
• Information on bus is unreliable during the period t0 to t1 because signals are changing state.
• Slave places requested input-data on data-lines at time t1.
• At end of clock cycle (at time t2), master strobes(captures) data on data-lines into its input-buffer
• For data to be loaded correctly into any storage device (such as a register built with flip-flops),
data must be available at input of that device for a period greater than setup-time of device.

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2.11.2 ASYNCHRONOUS BUS

• This method uses handshake-signals between master and slave for coordinating data transfers.
• There are 2 control-lines:
1) Master-ready(MR) to indicate that master is ready for a transaction
2) Slave-ready(SR) to indicate that slave is ready to respond
The read operation proceeds as follows:
• At t0, master places address- & command-information on bus. All devices on bus begin to decode
this information.
• At t1, master sets MR-signal to 1 to inform all devices that the address- & command-information is
ready.
• At t2, selected slave performs required input-operation & sets SR signal to 1 (Figure 4.26).
• At t3, SR signal arrives at master indicating that the input-data are available on bus skew.
• At t4, master removes address- & command-information from bus.
• At t5, when the device-interface receives the 1-to-0 transition of MR signal, it removes data and SR
signal from the bus. This completes the input transfer

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2.12 INTERFACE CIRCUITS

● I/O interface consists of the circuitry required to connect an I/O device to a computer bus.
● Side of the interface which connects to the computer has bus signals for:
Address
Data
Control
● Side of the interface which connects to the I/O device has:
● Data path and associated controls to transfer data between the interface and the I/O device.
This side is called as a “port”.
● Ports can be classified into two:
Parallel port.
Serial port.
● Parallel port transfers data in the form of a number of bits, normally 8 or 16 to or from the
device.
● Serial port transfers and receives data one bit at a time.
● Processor communicates with the bus in the same way, whether it is a parallel port or a
serial port.
● Conversion from the parallel to serial and vice versa takes place inside the interface circuit.

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Keyboard is connected to a processor using a parallel port.

• Processor is 32-bits and uses memory-mapped I/O and the asynchronous bus protocol.
• On the processor side of the interface we have:
- Data lines.
- Address lines
- Control or R/W line.
- Master-ready signal and
- Slave-ready signal.
• On the keyboard side of the interface:
- Encoder circuit which generates a code for the key pressed.
- Debouncing circuit which eliminates the effect of a key bounce (a single key stroke may appear as
multiple events to a processor).
- Data lines contain the code for the key.
- Valid line changes from 0 to 1 when the key is pressed. This causes the code to
be loaded into DATAIN and SIN to be set to 1.

2.12.1 INPUT INTERFACE CIRCUIT

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Output lines of DATAIN are connected to the data lines of the bus by means of 3 state drivers
• Drivers are turned on when the processor issues a read signal and the address selects this
register.
• SIN signal is generated using a status flag circuit.
• It is connected to line D0 of the processor bus using a three-state driver.
• Address decoder selects the input interface based on bits A1 through A31.
• Bit A0 determines whether the status or data register is to be read, when Master-ready is
• active.
• In response, the processor activates the Slave-ready signal, when either the Read-status or Read-data
is equal to 1, which depends on line A0.

PRINTER TO PROCESSOR CONNECTION

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• Printer is connected to a processor using a parallel port.

• Processor is 32 bits, uses memory-mapped I/O and asynchronous bus protocol.
• On the processor side:
- Data lines.
- Address lines
- Control or R/W line.
- Master-ready signal and
- Slave-ready signal.
• On the printer side:
- Idle signal line which the printer asserts when it is ready to accept a character.
This causes the SOUT flag to be set to 1.
- Processor places a new character into a DATAOUT register.
- Valid signal, asserted by the interface circuit when it places a new character
on the data lines.

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2.12.2 OUTPUT INTERFACE CIRCUIT

• Data lines of the processor bus are connected to the DATAOUT register of the interface.
• The status flag SOUT is connected to the data line D1 using a three-state driver.
• The three-state driver is turned on, when the control Read-status line is 1.
• Address decoder selects the output interface using address lines A1 through A31.
• Address line A0 determines whether the data is to be loaded into the DATAOUT register or status
flag is to be read.
• If the Load-data line is 1, then the Valid line is set to 1.
• If the Idle line is 1, then the status flag SOUT is set to 1.

2.13 COMBINED I/O INTERFACE CIRCUITS

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• Address bits A2 through A31, that is 30 bits are used to select the overall interface.
• Address bits A1 through A0, that is, 2 bits select one of the three registers, namely, DATAIN,
DATAOUT, and the status register.
• Status register contains the flags SIN and SOUT in bits 0 and 1.
• Data lines PA0 through PA7 connect the input device to the DATAIN register.
• DATAOUT register connects the data lines on the processor bus to lines PB0 through PB7 which
connect to the output device.
• Separate input and output data lines for connection to an I/O device.

2.13.1 SERIAL PORT

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● Serial port is used to connect the processor to I/O devices that require transmission of data
one bit at a time.
● Serial port communicates in a bit-serial fashion on the device side and bit parallel fashion on
the bus side.
● Transformation between the parallel and serial formats is achieved with shift registers that
have parallel access capability.
● Input shift register accepts input one bit at a time from the I/O device. Refer fig no.4.37
● Once all the 8 bits are received, the contents of the input shift register are loaded in parallel
into DATAIN register.
● Output data in the DATAOUT register are loaded into the output shift register.
● Bits are shifted out of the output shift register and sent out to the I/O device one bit at a
time.

• As soon as data from the input shift registers are loaded into DATAIN, it can start accepting
another 8 bits of data.

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• Input shift register and DATAIN registers are both used at input so that the input shift register can
start receiving another set of 8 bits from the input device after loading the contents to DATAIN,
before the processor reads the contents of DATAIN. This is called as double-buffering.
• Serial interfaces require fewer wires, and hence serial transmission is convenient for connecting
devices that are physically distant from the computer.
• Speed of transmission of the data over a serial interface is known as the “bit rate”.
• Bit rate depends on the nature of the devices connected.
• In order to accommodate devices with a range of speeds, a serial interface must be able to use a
range of clock speeds.
• Several standard serial interfaces have been developed:
• Universal Asynchronous Receiver Transmitter (UART) for low-speed serial devices.
• RS-232-C for connection to communication links.
2.14 STANDARD I/O INTERFACES
● I/O device is connected to a computer using an interface circuit.
● Do we have to design a different interface for every combination of an I/O device and a
computer? A practical approach is to develop standard interfaces and protocols.
● A personal computer has:
● A motherboard which houses the processor chip, main memory and some I/O interfaces.
● A few connectors into which additional interfaces can be plugged.
● Processor bus is defined by the signals on the processor chip.
● Devices which require high-speed connection to the processor are connected directly to this
bus.
● Because of electrical reasons only a few devices can be connected directly to the processor
bus.
● Motherboard usually provides another bus that can support more devices.
● Processor bus and the other bus (called as expansion bus) are interconnected by a circuit
called “bridge”.
● Devices connected to the expansion bus experience a small delay in data transfers.
● Design of a processor bus is closely tied to the architecture of the processor.
● No uniform standard can be defined.
● Expansion bus however can have uniform standard defined.

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● A number of standards have been developed for the expansion bus.

● Some have evolved by default.
● For example, IBM’s Industry Standard Architecture.
● Three widely used bus standards:
● PCI (Peripheral Component Interconnect)
● SCSI (Small Computer System Interface)
● USB (Universal Serial Bus)

2.14.1 PCI BUS

● Peripheral Component Interconnect
● Introduced in 1992
● Low-cost bus
● Processor independent
● Plug-and-play capability
● In today’s computers, most memory transfers involve a burst of data rather than just one
word. The PCI is designed primarily to support this mode of operation.

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● The bus supports three independent address spaces: memory, I/O, and configuration.
● we assumed that the master maintains the address information on the bus until data
transfer is completed. But, the address is needed only long enough for the slave to be selected. Thus,
the address is needed on the bus for one clock cycle only, freeing the address lines to be used for
sending data in subsequent clock cycles. The result is a significant cost reduction.
● A master is called an initiator in PCI terminology. The addressed device that responds to
read and write commands is called a target.

2.14.2 Device configuration

● When an I/O device is connected to a computer, several actions are needed to configure both
the device and the software that communicates with it.
● PCI incorporates in each I/O device interface a small configuration ROM memory that stores
information about that device.
● The configuration ROMs of all devices are accessible in the configuration address space. The
PCI initialization software reads these ROMs and determines whether the device is a printer, a
keyboard, an Ethernet interface, or a disk controller. It can further learn bout various device
options and characteristics.
● Devices are assigned addresses during the initialization process.
● This means that during the bus configuration operation, devices cannot be accessed based
on their address, as they have not yet been assigned one.
● Hence, the configuration address space uses a different mechanism. Each device has an input
signal called Initialization Device Select, IDSEL#
● Electrical characteristics:
● PCI bus has been defined for operation with either a 5 or 3.3 V power supply

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2.14.3 SCSI BUS

● The acronym SCSI stands for Small Computer System Interface.
● It refers to a standard bus defined by the American National Standards Institute (ANSI)
under the designation X3.131.
● In the original specifications of the standard, devices such as disks are connected to a
computer via a 50-wire cable, which can be up to 25 meters in length and can transfer data at rates
up to 5 megabytes/s.
● The SCSI bus standard has undergone many revisions, and its data transfer capability has
increased very rapidly, almost doubling every two years.
● SCSI-2 and SCSI-3 have been defined, and each has several options.
● Because of various options SCSI connector may have 50, 68 or 80 pins.
● Devices connected to the SCSI bus are not part of the address space of the processor
● The SCSI bus is connected to the processor bus through a SCSI controller. This controller
uses DMA to transfer data packets from the main memory to the device, or vice versa.
● A packet may contain a block of data, commands from the processor to the device, or status
information about the device.
● A controller connected to a SCSI bus is one of two types – an initiator or a target.
● An initiator has the ability to select a particular target and to send commands specifying the
operations to be performed. The disk controller operates as a target. It carries out the commands it
receives from the initiator.
● The initiator establishes a logical connection with the intended target.
● Once this connection has been established, it can be suspended and restored as needed to
transfer commands and bursts of data.
● While a particular connection is suspended, other device can use the bus to transfer
information.
● This ability to overlap data transfer requests is one of the key features of the SCSI bus that
leads to its high performance.
● Data transfers on the SCSI bus are always controlled by the target controller.

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● To send a command to a target, an initiator requests control of the bus and, after winning
arbitration, selects the controller it wants to communicate with and hands control of the bus over
to it.
● Then the controller starts a data transfer operation to receive a command from the initiator.
● Assume that processor needs to read block of data from a disk drive and that data are stored
in disk sectors that are not contiguous.
● The processor sends a command to the SCSI controller, which causes the following sequence
of events to take place:
● The SCSI controller, acting as an initiator, contends for control of the bus.
● When the initiator wins the arbitration process, it selects the target controller and hands
over control of the bus to it.
● The target starts an output operation (from initiator to target); in response to this, the
initiator sends a command specifying the required read operation.
● The target, realizing that it first needs to perform a disk seek operation, sends a message to
the initiator indicating that it will temporarily suspend the connection between them. Then it
releases the bus.
● The target controller sends a command to the disk drive to move the read head to the first
sector involved in the requested read operation. Then, it reads the data stored in that sector and
stores them in a data buffer. When it is ready to begin transferring data to the initiator, the target
requests control of the bus. After it wins arbitration, it reselects the initiator controller, thus
restoring the suspended connection.
● The target transfers the contents of the data buffer to the initiator and then suspends the
connection again
● The target controller sends a command to the disk drive to perform another seek operation.
Then, it transfers the contents of the second disk sector to the initiator as before. At the end of this
transfers, the logical connection between the two controllers is terminated.
● As the initiator controller receives the data, it stores them into the main memory using the
DMA approach.
● The SCSI controller sends as interrupt to the processor to inform it that the requested
operation has been completed

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2.14.4 MAIN PHASES INVOLVED

● Arbitration
A controller requests the bus by asserting BSY and by asserting it’s associated data line
When BSY becomes active, all controllers that are requesting bus examine data lines Selection
Controller that won arbitration selects target by asserting SEL and data line of target. After that
initiator releases BSY line.
● Target responds by asserting BSY line
Target controller will have control on the bus from then
● Information Transfer
Handshaking signals are used between initiator and target
At the end target releases BSY line Reselection

2.14.5 USB
● Universal Serial Bus (USB) is an industry standard developed through a collaborative effort
of several computer and communication companies, including Compaq, Hewlett-Packard, Intel,
Lucent, Microsoft, Nortel Networks, and Philips.
● Speed
Low-speed (1.5 Mb/s)
Full-speed (12 Mb/s)
High-speed (480 Mb/s)
● Port Limitation
● Device Characteristics
● Plug-and-play

USB TREE STRUCTURE

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● To accommodate a large number of devices that can be added or removed at any time, the
USB has the tree structure as shown in the figure.
● Each node of the tree has a device called a hub, which acts as an intermediate control point
between the host and the I/O devices. At the root of the tree, a root hub connects the entire tree to
the host computer. The leaves of the tree are the I/O devices being served (for example, keyboard,
Internet connection, speaker, or digital TV)
● In normal operation, a hub copies a message that it receives from its upstream connection to
all its downstream ports. As a result, a message sent by the host computer is broadcast to all I/O
devices, but only the addressed device will respond to that message. However, a message from an
I/O device is sent only upstream towards the root of the tree and is not seen by other devices.
Hence, the USB enables the host to communicate with the I/O devices, but it does not enable these
devices to communicate with each other.
● When a USB is connected to a host computer, its root hub is attached to the processor bus,
where it appears as a single device. The host software communicates with individual devices
attached to the USB by sending packets of information, which the root hub forwards to the
appropriate device in the USB tree.
● Each device on the USB, whether it is a hub or an I/O device, is assigned a 7-bit address. This
address is local to the USB tree and is not related in any way to the addresses used on the processor
bus.
● A hub may have any number of devices or other hubs connected to it, and addresses are
assigned arbitrarily. When a device is first connected to a hub, or when it is powered on, it has the

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address 0. The hardware of the hub to which this device is connected is capable of detecting that
the device has been connected, and it records this fact as part of its own status information.
Periodically, the host polls each hub to collect status information and learn about new devices that
may have been added or disconnected.
● When the host is informed that a new device has been connected, it uses a sequence of
commands to send a reset signal on the corresponding hub port, read information from the device
about its capabilities, send configuration information to the device, and assign the device a unique
USB address. Once this sequence is completed the device begins normal operation and responds
only to the new address.

USB protocols
● All information transferred over the USB is organized in packets, where a packet consists of
one or more bytes of information. There are many types of packets that perform a variety of control
functions.
● The information transferred on the USB can be divided into two broad categories: control
and data.
● Control packets perform such tasks as addressing a device to initiate data transfer,
acknowledging that data have been received correctly, or indicating an error.
● Data packets carry information that is delivered to a device.

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● A packet consists of one or more fields containing different kinds of information. The first
field of any packet is called the packet identifier, PID, which identifies the type of that packet.
● They are transmitted twice. The first time they are sent with their true values, and the
second time with each bit complemented
● The four PID bits identify one of 16 different packet types. Some control packets, such as
ACK
● (Acknowledge), consist only of the PID byte.

ELECTRICAL CHARACTERISTICS
● The cables used for USB connections consist of four wires.
● Two are used to carry power, +5V and Ground.
● Thus, a hub or an I/O device may be powered directly from the bus, or it may have its own
external power connection.
● The other two wires are used to carry data.
● Different signaling schemes are used for different speeds of transmission.
● At low speed, 1s and 0s are transmitted by sending a high voltage state (5V) on one or the
other o the two signal wires. For high-speed links, differential transmission is used.

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