Types of Registers

Registers Function

Instructions Registers(IR) Hold instruction code of instruction currently executing

Address Registers(AR) All memory references are initiated by loading the memory address in AR

Temporary Registers(TR) Extra registers used to store data and address

Input Registers(IR) Hold the data from input devices

Output Registers(OR) Hold the data to send to output devices

Program Counter(PC) Holds the address of next instruction to be executed

Accumulator(AC) Store results produced by system

Data Registers(DR) Temporarily store data being transmitted to or from peripheral devices

Common Bus System 

Common Bus system is used to provides the path to transfer data from register to register or
in-between the registers and memory. 

Purpose Of Common Bus System

A pair of signal lines that facilitate the transfer of multi-bit data from one system to another is
known as a bus. The common bus is required in the computer for communication with
registers and memory to decrease the hardware complexity.

The basic computer has eight registers, a memory unit and control unit. The path is required
to transfer data, address and control signal. If there is a wire for every operation and every
address of memory location, then it will be excessive. So common bus system is
implemented through use of MUX and other circuit for proper implementation of wire.
Common Bus System Diagram
In common bus system diagram there are 7 components (six registers and a single memory)
are connected with a common bus. So, to represent these seven components of common
bus system in binary, we require three select lines S0, S1, and S2.

Basic Components of Common Bus System

• Common Bus System uses a multiplexer to implement Common BUS.

• Memory and all Registers are connected through a common bus system.

• We consider 3 select lines (S0, S1, and S2) because we are using 7 inputs

to multiplexer as shown in the following diagram. With the help of 3 select lines,

8 inputs to multiplexer can be given.

• Select lines are 2n. It means how many total inputs can be added.
 As 23=8x1(called 8 inputs and one output).

For example, When S2 S1 S0 = 010 then 2nd Input is activated.

 6 registers (AR, PC, DR, AC, IR and TR) and memory unit are connected to common bus. The
DR (Data Register) is also connected with the ADDER and Logic Unit to perform operations
on data through data Bus.

 INPTR (Input register) is not connected with the common bus. it receives data directly for
Input device and sends it to Adder and Logic unit (part of ALU) for operations (+, -,*, /) and
then pass it to Accumulator register. The adder and logic unit also contains a carry bit called
(E) in case of addition.

 OUTR (Output Register) does not send data to a common bus or any other register because
it sends directly to the output device but it receives data from the common bus.

Important

 Every register in the system is connected with Clock Signals.

 Clock Signal controls LD, INR (increment), CLR (Clear register) commands by the control unit.
 Memory read (R) and writes (W) operation also controlled by Control Unit.

Size of Registers In Common Bus System?

i. The Main memory is of 4096×16 = 2^12 x 16. To represent 4096 (2^12 ) memory we require 12
bits. So 12 bits are required to address 4096 Memory. X16 means 16 bits word, which will be access
or transfer at a time when we move data from memory to registers.
ii. We require a common bus of 16 bits because word size is 16 bits and it has to pass through a
common bus.

iii. AR and PC registers deal with the address of the memory so their sizes will be 12 bits. When the
address of these registers arrives at a common bus its 4 most significant bits becomes zero.

iv. DR, AC, IR, and TR register deal with data of memory so there size will be 16 bits because word
size is 16 bits.

v. Input register (INPR) and the output register (OUTR) send and receive data character by character,
So, 8 bits required for INPR and OUTR Registers and communicate with 8 least significant bits in the
common bus.

vi. Select lines bits value depends on how many components are connected with a common bus.
Select lines follow the rule of 2^n where n is select lines bit value. 2 bits can represent 4 components
(0-3). 3 bits require to represent 8(0-7) and so on.

How Common Bus System Works?

Step I: Any register can send its data to a common bus by activating its selected lines (S2, S1, S0).

Step II: If any register wants to receive data then its LD command will activate by setting the LD
command value to 1. And LD command of all others registers set to zero.

Note: Activation/Deactivation of LD, INR or CLR of any register is done through a circuit called
control unit.

Step III: Main process starts with the program counter.

Program counter fetches the address of memory which has to execute. And then pass this address to
common bus.

AR receive the address from common bus by activating its LD bits. Then AR sends the address to
memory directly because AR is directly connected with common bus.

Memory read the address and sends Data of that address to DR through common Bus.

Note: Other name of DR (data register) are MBR or MDR.

Step IV: Memory fetched data will be in DATA Register and then pass to Accumulator register by
Data BUS because DR is directly connected with AC by Data Bus. Copy of this data is transfer to IR
because when data pass to the accumulator register then Data Register will flush-out. So that the
next incoming data in the next cycle can store. If the Accumulator register wants to store, (received
data form DR) temporary in somewhere then it passes it to Temporary register (TR). If we want to
retrieve the data from TR then its data is first loaded in DR and then it passes to AC.

Common Bus System Example

Suppose one address instruction is

X= (A+B) * (C+D)

To execute the above single address instruction, the system executes the following seven micro-
instructions

LOAD A // AC <– M[A]

ADD B // AC <– AC + M[B]
STORE T // Store AC value in temporary register
LOAD C // AC <– M[C]
ADD D // AC <– AC + M[D]
MUL T // multiply temporary register value with AC
STORE X // Store value of X in memory

1. The first micro-instruction is LOAD A

It means to load the value A to Accumulator register.
 The program counter (PC) gets the address of this instruction. The program counter will
activate by select lines (010). And it transfers the address of an instruction to the common
bus through the address register.
 Through the control unit, the LD command of Address Register (AR) is activated in this way
AR get the address of PC through a common bus.
 The address register (AR) is directly attached to Main Memory.
 When the address of instruction arrives at the main memory then the READ command of
main memory will activate and data of the provided address is transferred to the common
bus through the data bus.
 Now LD command of data Register will activate and DR gets data from the common bus
through the data bus.
 The instruction in the MDR is then copied to the CIR. Data coming from memory (READ) or
going to memory (Write) is always in Memory Data Register MDR (DR or MBR). Fetch the
instruction is complete here, and now PC in Incremented by ONE. It means now Program
counter having the address of next memory location in the sequence
 Now data will transfer from MDR to Control unit (ALU section) where it will decode. In the
decode section, Operator/opcode (like ADD, LOAD) are separate from Operand (data like A).
 Now Data will transfer to Accumulator register by passing through ALU (for any operation
like +,-), through a data bus.
 Here the completion of the first micro-instruction.
Advantage Of Common Bus System

If we use wires to define the path of each register to everyone with other registers and memory (like
in Mesh topology), then It will be too complex and costly and difficult to implement.
So, the common bus system is an efficient way to transfer data from one register to other registers
and registers to main memory.
Computer Instructions

 The basic computer has three instruction code formats, as shown in Fig. below. Each
format has 16 bits.

 The operation code (opcode) part of the instruction contains three bits and the meaning
of the remaining 13 bits depends on the operation code encountered.

 A memory-reference instruction uses 12 bits to specify an address and one bit to

specify the addressing mode I. I is equal to 0 for direct address and to 1 for indirect
address.

 The register reference instructions are recognized by the operation code 111 with a 0
in the leftmost bit (bit 15) of the instruction.

 A register-reference instruction specifies an operation on or a test of the AC register. An

operand from memory is not needed; therefore, the other 12 bits are used to specify the
operation or test to be executed.

 Similarly, an input-output instruction does not need a reference to memory and is

recognized by the operation code Ill with a 1 in the leftmost bit of the instruction. The
remaining 12 bits are used to specify the type of input-output operation or test performed.

 The type of instruction is recognized by the computer control from the four bits in
positions 12 through 15 of the instruction. If the three opcode bits in positions 12 though
14 are not equal to 111, the instruction is a memory-reference type and the bit in position
15 is taken as the addressing mode I.

 If the 3-bit opcode is equal to 111, control then inspects the bit in position 15. If this bit
is 0, the


 instruction is a register-reference type. If the bit is 1, the instruction is an input-output

type. Note that the bit in position 15 of the instruction code is designated by the symbol I
but is not used as a mode bit when the operation code is equal to 111.

 Only three bits of the instruction are used for the operation code. It may seem that the
computer is restricted to a maximum of eight distinct operations.

 However, since register-reference and input-output instructions use the remaining 12 bits
as part of the operation code, the total number of instructions can exceed eight.

 In fact, the total number of instructions chosen for the basic computer is equal to 25.

 The instructions for the computer are listed in Table below. The symbol designation is a
three-letter word and represents an abbreviation intended for programmers and users.
The hexadecimal code is equal to the equivalent hexadecimal number of the binary code
used for the instruction.
 By using the hexadecimal equivalent we reduced the 16 bits of an instruction code to
four digits with each hexadecimal digit being equivalent to four bits.

 A memory-reference instruction has an address part of 12 bits. The address part is

denoted by three x's and stand for the three hexadecimal digits corresponding to the 12-
bit address.

 The last bit of the instruction is designated by the symbol I. When I = 0, the last four
bits of an instruction have a hexadecimal digit equivalent from 0 to 6 since the last bit is
0.

 When I = I, the hexadecimal digit equivalent of the last four bits of the instruction ranges
from 8 to E since the last bit is I. Register-reference instructions use 16 bits to specify an
operation. The leftmost four bits are always 0111, which is equivalent to hexadecimal 7.

 The other three hexadecimal digits give the binary equivalent of the remaining 12 bits.
The input-output instructions also use all 16 bits to specify an operation. The last four bits
are always 1111, equivalent to hexadecimal F.
 

Instruction Set Completeness

 A computer should have a set of instructions so that the user can construct machine
language programs to evaluate any function that is known to be computable.

 The set of instructions are said to be complete if the computer includes a sufficient

number of instructions in each of the following categories:
 1. Arithmetic, logical, and shift instructions

 2. Instructions for moving information to and from memory and processor

 registers

 3. Program control instructions together with instructions that check

 status conditions

 4. Input and output instructions

 Arithmetic, logical, and shift instructions provide computational capabilities for

processing the type of data that the user may wish to employ.

 The bulk of the binary information in a digital computer is stored in memory, but all
computations are done in processor registers.

 Therefore, the user must have the capability of moving information between these two
units. Decision making capabilities are an important aspect of digital computers.

 For example, two numbers can be compared, and if the first is greater than the second,
it may be necessary to proceed differently than if the second is greater than the first.

 Program control instructions such as branch instructions are used to change the

sequence in which the program is executed. Input and output instructions are needed for
communication between the computer and the user.

 Programs and data must be transferred into memory and results of computations must
be transferred back to the user. The instructions listed in Table above constitute a
minimum set that provides all the capabilities mentioned above.

 There is one arithmetic instruction, ADD, and two related instructions, complement
AC(CMA) and increment AC(INC).
 With these three instructions we can add and subtract binary numbers when negative
numbers are in signed-2's complement representation. The circulate instructions, CIR
and CIL, can be used for arithmetic shifts as well as any other type of shifts desired.

 Multiplication and division can be performed using addition, subtraction, and shifting.

There are three logic operations: AND, complement AC(CMA), and clear AC(CLA).

 The AND and complement provide a NAND operation. It can be shown that with the
NAND operation it is possible to implement all the other logic operations with two
variables.

 Moving information from memory to AC is accomplished with the load AC(LDA)

instruction. Storing information from AC into memory is done with the store AC(STA)
instruction.

 The branch instructions BUN, BSA, and ISZ, together with the four skip instructions,
provide capabilities for program control and checking of status conditions. The input (lNP)
and output (OUT) instructions cause information to be transferred between the computer
and external devices.

 Although the set of instructions for the basic computer is complete, it is not efficient
because frequently used operations are not performed rapidly. An efficient set of
instructions will include such instructions as subtract, multiply, OR, and exclusive-OR.
Timing and Control

 The timing for all registers in the basic computer is controlled by a master clock
generator.

 The clock pulses are applied to all flip-flops and registers in the system, including the
flip-flops and registers in the control unit.

 The clock pulses do not change the state of a register unless the register is enabled
by a control signal.

 The control signals are generated in the control unit and provide control inputs for the
multiplexers in the common bus, control inputs in processor registers, and
microoperations for the accumulator.

 There are two major types of control organization: hardwired control and
microprogrammed control. In the hardwired organization, the control logic is implemented
with gates, flip-flops, decoders, and other digital circuits.

 It has the advantage that it can be optimized to produce a fast mode of operation.

 In the microprogrammed organization, the control information is stored in a control

memory. The control memory is programmed to initiate the required sequence of
microoperations.

 A hardwired control, as the name implies, requires changes in the wiring among the
various components if the design has to be modified or changed. In the
microprogrammed control, any required changes or modifications can be done by
updating the microprogram in control memory.

 The block diagram of the control unit is shown in Fig. below. It consists of two
decoders, a sequence counter, and a number of control logic gates. An instruction read
from memory is placed in the instruction register (IR).

 The position of this register in the common bus system is indicated in Fig. previously
seen. The instruction register is shown again in Fig. below, where it is divided into three
parts: the I bit, the operation code, and bits 0 through 11.

 The operation code in bits 12 through 14 are decoded with a 3 x 8 decoder. The eight
outputs of the decoder are designated by the symbols D0 through D7
 The subscripted decimal number is equivalent to the binary value of the
corresponding operation code. Bit 15 of the instruction is transferred to a flip-flop
designated by the symbol I.

 Bits 0 through 11 are applied to the control logic gates. The 4-bit sequence counter can
count in binary from 0 through 15. The outputs of the counter are decoded into 16 timing
signals T0 through T15

 The sequence counter SC can be incremented or cleared synchronously

 . Most of the time, the counter is incremented to provide the sequence of timing signals
out of the 4 x 16 decoder. Once in awhile, the counter is cleared to 0, causing the next
active timing signal to be T0.

 As an example, consider the case where SC is incremented to provide timing signals

T0, T1, T2, T3, and T4 in sequence. At time T4, SC is cleared to 0 if decoder output D3 is
active.

 This is expressed symbolically by the statement D3T4: SC ← 0. The timing diagram of

Fig. below shows the time relationship of the control signals.

 The sequence counter SC responds to the positive transition of the clock. Initially, the
CLR input of SC is active. The first positive transition of the




 clock clears SC to 0, which in turn activates the timing signal T0 out of the decoder. T0
is active during one clock cycle.

 The positive clock transition labeled T0 in the diagram will trigger only those registers
whose control inputs are connected to timing signal T0.

 SC is incremented with every positive clock unless its CLR input is active.

 This produces the sequence of timing signals T0,T1,T2,T3,T4 and so on, as shown in

the diagram. (Note the relationship between the timing signal and its corresponding
positive clock transition.)

 If SC is not cleared, the timing signals will continue with T5, T6 up to T15 and back to T0.


 The last three waveforms in Fig. above show how SC is cleared when D3T4 = 1.
Output D3 from the operation decoder becomes active at the end of timing signal T2

 When timing signal T4 becomes active, the output of the AND gate that implements
the control function D3T4 becomes active.

 This signal is applied to the CLR input of SC. On the next positive clock transition (the
one marked T4 in the diagram) the counter is cleared to 0. This causes the timing signal
T0 to become active instead of T5 that would have been active if SC were incremented
instead of cleared.

 A memory read or write cycle will be initiated with the rising edge of a timing signal. It
will be assumed that a memory cycle time is less than the clock cycle time. According to
this assumption, a memory read or write cycle initiated by a timing signal will be
completed by the time the next clock goes through its positive transition.

 The clock transition will then be used to load the memory word into a register. This
timing relationship is not valid in many computers because the memory cycle time is
usually longer than the processor clock cycle.
 In such a case it is necessary to provide wait cycles in the processor until the memory
word is available. To facilitate the presentation, we will assume that a wait period is not
necessary in the basic computer.

 To fully comprehend the operation of the computer, it is crucial that one understands
the timing relationship between the clock transition and the timing signals. For example,
the register transfer statement T0: AR ← PC specifies a transfer of the content of PC into
AR if timing signal T0 is active.

 T0 is active during an entire clock cycle interval. During this time the content of PC is
placed onto the bus (with S2S1S0 = 010) and the LD (load) input of AR is enabled. The
actual transfer does not occur until the end of the clock cycle when the clock goes
through a positive transition.

 This same positive clock transition increments the sequence counter SC from 0000 to
0001 . The next clock cycle has T1 active and T0 inactive.