Name: Debjani Banerjee
Class Roll No.: CSE/19/013
Date of Experiment: 27/01/2021
Date of Submission: 29/01/2021
Experiment No.: 8(b)
Title: Cascade two RAM ICs for Horizontal Expansion
Circuit Diagram:
RAM Horizontal Expansion (using IC 7489)
Observation Table:
CE=Low, WE=Low
Address Input Data Input
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 1 1 1 1 1 1 1 1
0 0 1 0 1 1 1 0 1 1 1 0
0 0 1 1 1 0 1 0 1 0 1 0
CE=Low, WE=High
Address Input Data Output
A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 1 0 0 0 1
0 0 1 1 0 1 0 1 0 1 0 1