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    ME Summer 2017

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    Hema latha
    This document is an exam for a course on VLSI Signal Processing. It contains 5 questions assessing students' knowledge of key concepts in the subject. Question 1 defines terms related to iteration, pipelining, and graph theory. Question 2 discusses DSP algorithms and applications, and compares pipelining and parallel processing. Question 3 covers iteration bounds, number representations, and systolic design. Question 4 focuses on transforming graphs and using algorithms. Question 5 addresses power reduction techniques, DSP processor architectures, unfolding algorithms, and signal transition graphs.

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    ME Summer 2017

    Uploaded by

    Hema latha
    12 views2 pages
    This document is an exam for a course on VLSI Signal Processing. It contains 5 questions assessing students' knowledge of key concepts in the subject. Question 1 defines terms related to iteration, pipelining, and graph theory. Question 2 discusses DSP algorithms and applications, and compares pipelining and parallel processing. Question 3 covers iteration bounds, number representations, and systolic design. Question 4 focuses on transforming graphs and using algorithms. Question 5 addresses power reduction techniques, DSP processor architectures, unfolding algorithms, and signal transition graphs.

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    2724209-ME-Summer-2017 (1)

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    This document is an exam for a course on VLSI Signal Processing. It contains 5 questions assessing students' knowledge of key concepts in the subject. Question 1 defines terms related to iteration, pipelining, and graph theory. Question 2 discusses DSP algorithms and applications, and compares pipelining and parallel processing. Question 3 covers iteration bounds, number representations, and systolic design. Question 4 focuses on transforming graphs and using algorithms. Question 5 addresses power reduction techniques, DSP processor architectures, unfolding algorithms, and signal transition graphs.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    12 views2 pages

    ME Summer 2017

    Uploaded by

    Hema latha
    This document is an exam for a course on VLSI Signal Processing. It contains 5 questions assessing students' knowledge of key concepts in the subject. Question 1 defines terms related to iteration, pipelining, and graph theory. Question 2 discusses DSP algorithms and applications, and compares pipelining and parallel processing. Question 3 covers iteration bounds, number representations, and systolic design. Question 4 focuses on transforming graphs and using algorithms. Question 5 addresses power reduction techniques, DSP processor architectures, unfolding algorithms, and signal transition graphs.

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    Seat No.: ________ Enrolment No.

    ______________
    GUJARAT TECHNOLOGICAL UNIVERSITY
    M. E. - SEMESTER – II • EXAMINATION – SUMMER • 2017
    Subject code: 2724209 Date: 29-05-2017
    Subject Name: VLSI Signal Processing
    Time: 02:30 pm - 05:00 pm Total Marks: 70
    Instructions:
    1. Attempt all questions.
    2. Make suitable assumptions wherever necessary.
    3. Figures to the right indicate full marks.

    Q1 (a) Define Following Terms. 07


    1. Iteration 5. Critical Path
    2. Iteration Period 6. Acyclic Precedence Graph
    3. Loop Bound 7. Cutset
    4. Critical Loop
    (b) Explain Fine-Grain Pipelining using FIR Filter. 07

    Q2 (a) Write a brief note on DSP Algorithms & its applications. 07


    (b) Compare Pipelining & Parallel Processing for VLSI Signal Processing. 07

    OR
    (b) Write a note on look ahead computation in VLSI Signal Processing. 07

    Q3 (a) Compute the iteration bound for DFG given below. 07

    (b) Write a note on redundant number representation. 07

    OR
    Q3 (a) Define systolic design methodology. Compare it with other design methodologies.

    (b) Explain operation of Parallel Multipliers.

    Q4 (a) Transform below given MRDFG to SRDFG. 07


    (b) Draw a constraint graph for the below given system of inequalities. Decide whether the 07
    given system has a solution, and find the solution if exists using the Bellman-Ford
    algorithm.

    OR
    Q4 (a) Retimed DFG for Biquad Filter is given. Redesign the filter with folding factor equal to 4. 07
    Use 1-stage pipelined adder and 2-stage pipelined multiplier.

    (b) Briefly discuss scaling and round off noise. 07

    Q5 (a) What are the different Power Reduction Techniques available? Discuss in brief. 07
    (b) What are the essential architectural features of DSP Processors? 07
    OR
    Q5 (a) Briefly explain the unfolding algorithm. 07
    (b) Discuss Signal Transition Graphs. 07

    *************

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