ADC1283

Datasheet

8 multiplexed channels, 50 ksps to 200 ksps, 12-bit SAR ADC

ADC1283
Features
• 50 ksps to 200 ksps conversion rate
• 8-to-1-channel input MUX
• 2.7 V to 5.5 V digital I/Os supply voltage
• 2.7 V to 5.5 V analog supply voltage
TSSOP-16 • DNL (AVCC = DVCC = 5 V): +/- 0.9 LSB maximum
• INL (AVCC = DVCC = 5 V): +/- 1.2 LSB maximum
• Very low consumption: Pd = 3.2 mW typical @ 5 V supply
• Power-down mode
• Temperature range: -40 °C to 125 °C
• 4-wire SPI serial digital interface
Maturity status link • TSSOP-16 package
ADC1283
Applications
Related products • Industrial process control
ADC1281 • Shunt resistor monitoring
ADC1282 • Data acquisition and instrumentation
• Test and measurement equipment
• Strain gauge sensing
• Telemetry

Description
The ADC1283 is a low-power, eight-channel pure CMOS 12-bit analog-to-digital
converter specified for conversion from 50 ksps to 200 ksps, tested at 200 ksps
(3.2 MHz clock frequency). The architecture is based on a successive-approximation
register with an internal track-and-hold cell. The ADC1283 features 8 single-ended
multiplexed inputs. The output serial data is straight binary and is SPI™ compatible.
The analog power supply operates from 2.7 V to 5.5 V. The digital power supply
operates independently from analog supply from 2.7 V to 5.5 V. The power
consumption at 5 V nominal supply is as low as 3.2 mW. The ADC1283 comes
in a plastic TSSOP-16 package and can operate from -40 °C to +125 °C ambient
temperature.

DS13932 - Rev 1 - March 2022 www.st.com

For further information contact your local STMicroelectronics sales office.
 ADC1283
Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

Figure 2. Pin connection (top view)

Table 1. Pin description

Pin n. Pin name Description

1 CS Chip select. Active low. Conversion starts on a falling edge of CS

2 AVCC Analog power supply. Used as reference voltage for inputs
3 AGND Analog ground
4 - 11 IN0 – IN7 Single-ended analog inputs. Signals are referenced from 0 V to AVCC
12 DGND Digital ground
13 DVCC Digital power supply voltage
14 DIN Digital data input. Used to address the control register
15 DOUT Digital data output
16 SCLK Clock input. Applied clock signal varies from 0.8 MHz to 3.2 MHz

DS13932 - Rev 1 page 2/24

 ADC1283
Absolute maximum ratings and operating conditions

2 Absolute maximum ratings and operating conditions

Table 2. Absolute maximum ratings

Symbol Parameter Value Unit

AVCC Maximum analog supply voltage between AVCC and AGND -0.3 to 7 V
DVCC Maximum digital supply voltage between DVCC and DGND -0.3 to 7 V
Tstg Maximum storage temperature -65 to 150 °C
Tj Maximum Junction temperature +150 °C
Rthja Junction to ambient thermal resistance (for TSSOP-16) 95 °C/W
Rthjc Junction to case thermal resistance (for TSSOP-16) 35 °C/W
Vi Maximum applied voltage on any pin versus ground -0.3 V to AVCC +0.3 V V

Ii (1) Maximum input current applied on any pin ±10 mA

Human Body Model (HBM) 2000 V

ESD
Charged Device Model (CDM) 1000 V

1. When the input voltage at any pin exceeds the power supplies (that is VIN < AGND or VIN > AVCC or DVCC), the current at
that pin should be limited to 10 mA. A limit of 2 pins can sustain such a condition, limiting the current to 20 mA for the whole
device.

Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the devices.
These are stress ratings only, which do not imply functional operation of the device at these or any other
conditions beyond those indicated under Recommended Operating conditions. Exposure to the absolute
maximum rating for extended periods may affect device reliability.

Table 3. Operating conditions

Symbol Parameters Min. Unit

AVCC Analog supply voltage 2.7 to 5.5 V

DVCC Digital supply voltage 2.7 to 5.5 V
VINA Analog input voltage 0 to AVCC V
VIND Digital input voltage 0 to DVCC V
fSCLK Clock frequency 0.8 to 3.2 MHz

T Ambient temperature range -40 to +125 °C

Note: All voltages are related to GND = 0 V unless otherwise noted.

DS13932 - Rev 1 page 3/24

 ADC1283
Electrical characteristics

3 Electrical characteristics

Table 4. Electrical characteristics AGND = DGND = 0 V, fSCLK = 3.2 MHz, fSAMPLE = 200 ksps, CL = 50 pF, Ta = 25 °C, all
specifications Tmin to Tmax unless otherwise specified.

Symbol Parameters Test conditions Min. Typ. Max. Unit

Static characteristics
Resolution with no missing codes AVCC = DVCC = 2.7 V to 5.5 V 12 Bits

Integral non-linearity AVCC = DVCC = 3.3 V -1.2 ±0.4 +1.2

INL
(end point method) AVCC = DVCC = 5 V -1.2 ±0.4 +1.2
AVCC = DVCC = 3.3 V -0.9 ±0.4 +0.9
DNL Differential non-linearity
AVCC = DVCC = 5 V -0.9 ±0.4 +0.9
AVCC = DVCC = 3.3 V -2 ±0.3 +2
VOFF Offset error
AVCC = DVCC = 5 V -2 ±0.3 +2
LSB
AVCC = DVCC = 3.3 V -1.5 0 +1.5
OEM Offset error match
AVCC = DVCC = 5 V -1.5 0 +1.5
AVCC = DVCC = 3.3 V -2 ±0.4 +2
FSE Full scale error
AVCC = DVCC = 5 V -2 ±0.4 +2
AVCC = DVCC = 3.3 V -1.5 0 +1.5
FSEM Full scale error match
AVCC = DVCC = 5 V -1.5 0 +1.5
Dynamic characteristics
FIN = 1.03 kHz, −0.02 dBFS
69.2 73
Signal-to-noise plus distortion AVCC = DVCC = 3.3 V
SINAD
ratio (0 to Fs/2) FIN = 1.03 kHz, −0.02 dBFS
69.2 73
AVCC = DVCC = 5 V
FIN = 1.03 kHz, −0.02 dBFS
71 73
AVCC = DVCC = 3.3 V
SNR Signal-to-noise ratio (0 to Fs/2)
FIN = 1.03 kHz, −0.02 dBFS
71 73
AVCC = DVCC = 5 V
FIN = 1.03 kHz, −0.02 dBFS
-88 -74
AVCC = DVCC = 3.3 V
THD Total harmonic distortion dB
FIN = 1.03 kHz, −0.02 dBFS
-88 -74
AVCC = DVCC = 5 V
FIN = 1.03 kHz, −0.02 dBFS
75 88
Spurious-free dynamic range AVCC = DVCC = 3.3 V
SFDR
(0 to Fs/2) FIN = 1.03 kHz, −0.02 dBFS
75 89
AVCC = DVCC = 5 V
FIN = 1.03 kHz, −0.02 dBFS
11.2 11.8
AVCC = DVCC = 3.3 V
ENOB Effective number of bits
FIN = 1.03 kHz, −0.02 dBFS
11.2 11.8
AVCC = DVCC = 5 V
FIN = 1.03 kHz, −0.02 dBFS
90
AVCC = DVCC = 3.3 V
ISO Channel-to-channel isolation dB
FIN = 1.03 kHz, −0.02 dBFS
90
AVCC = DVCC = 5 V
FIN = 19.5 / 20.5 kHz, -0.02 dBFS
-99
AVCC = DVCC = 3.3 V
IM2 2nd order intermodulation dB
FIN = 19.5 / 20.5 kHz, -0.02 dBFS
-99
AVCC = DVCC = 5 V

DS13932 - Rev 1 page 4/24

 ADC1283
Electrical characteristics

Symbol Parameters Test conditions Min. Typ. Max. Unit

FIN = 19.5 / 20.5 kHz, -0.02 dBFS

-87
AVCC = DVCC = 3.3 V
IM3 3rd order intermodulation dB
FIN = 19.5 / 20.5 kHz, -0.02 dBFS
-88
AVCC =ˆDVCC = 5 V
Analog input characteristics (AVCC = 2.7 V to 5.5 V)
IDCL DC leakage current -1 0.01 +1 µA

Track mode 33 pF
CINA Input capacitance
Hold mode 4.5 pF
Digital input characteristics
VIH Input high voltage DVCC = 2.7 V to 5.5 V 0.7xDVCC
V
VIL Input low voltage DVCC = 2.7 V to 5.5 V 0.3xDVCC

DVCC = 3.3 V, Isource = -1 mA DVCC-0.5 V

VOH (1) Output high voltage
DVCC = 5 V, Isource = -1 mA DVCC-0.5 V
V
DVCC = 3.3 V, Isink = 1 mA 0.4
VOL (1)
Output low voltage
DVCC = 5 V, Isink = 1 mA 0.4

IIN Digital input current VIN = 0 V or DVCC -1 0.01 1 µA

CIND Digital input capacitance DVCC = 2.7 V to 5.5 V 3.5 pF

Hi-impedance output leakage

IOZH, IOZL -1 0.02 1 µA
current
COUT Hi-impedance output capacitance 3.5 pF

Power supply characteristic

Total supply current, normal AVCC = DVCC = 2.7 V to 5.5 V,

0.64 0.8 mA
mode (CS low) fS = 200 kSPS, FIN = 40 kHz

IAVCC + AVCC = DVCC = 2.7 V to 5.5 V,

0.02 2
IDVCC fS = 0, -40 °C < T < 85 °C
Total supply current, shutdown
µA
mode (CS high) AVCC = DVCC = 2.7 V to 5.5 V,
10
fS = 0, 85 °C < T < 125 °C

AC characteristics (AVCC = DVCC = 2.7 V to 5.5 V)

fS Sample rate 50 200 ksps

SCLK
tCONVERT Conversion (Hold) time 13
cycles
DC SCLK duty cycle 40 60 %
SCLK
tACQ Acquisition (Track) time cycles See Figure 4 3
cycles
SCLK
Throughput time Acquisition time + Conversion time 16
cycles
tAD Aperture delay 4 ns

Timing specifications (AVCC = 2.7 V to 5.5 V) (1)(2)

CS hold time after SCLK rising

tCSH 10 0 ns
edge
CS set-up time prior SCLK rising
tCSS 10 4.5 ns
edge
tEN CS falling edge to DOUT enabled 6 30 ns

DS13932 - Rev 1 page 5/24

 ADC1283
Electrical characteristics

Symbol Parameters Test conditions Min. Typ. Max. Unit

DOUT access time after SCLK

tDACC 20 35 ns
falling edge
DOUT hold time after SCLK
tDHLD 7 13 ns
falling edge
DIN set-up time prior to SCLK
tDS 10 ns
rising edge
DIN hold time after SCLK rising
tDH 10 ns
edge

CS rising edge to DOUT high- DOUT falling 12 20

tDIS ns
impedance DOUT rising 12 20
0.4 x
tCH Min. SCLK high time ns
tSCLK

0.4 x
tCL Min. SCLK low time ns
tSCLK

1. Datasheet minimum and maximum specification limits are specified by design, characterization or statistical analysis.
2. Timings are given with thresholds set to 50% of clock signals and 10% or 90% of data signals.

DS13932 - Rev 1 page 6/24

 ADC1283
Timing diagrams

4 Timing diagrams

Figure 3. Operational timing diagram

Figure 4. Serial timing diagram

Figure 5. SCLK and CS timing parameters

DS13932 - Rev 1 page 7/24

 ADC1283
Typical characteristics

5 Typical characteristics

TA = 25 °C, fSAMPLE = 200 ksps, fSCLK = 3.2 MHz, Fin = 10 KHz unless otherwise stated.

Figure 6. DNL vs. output codes (AVCC = DVCC = 3 V) Figure 7. DNL vs. output codes (AVCC = DVCC = 5 V)

1 1
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2

DNL(lsb)
DNL(lsb)

0 0
-0.2 -0.2
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1 -1
0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096

code code

Figure 8. INL vs. output codes (AVCC = DVCC = 3 V) Figure 9. INL vs. output codes (AVCC = DVCC = 5 V)

1 1
0.8 0.8
0.6 0.6
0.4 0.4
0.2 0.2
INL(lsb)
INL(lsb)

0 0
-0.2 -0.2
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1 -1
0 512 1024 1536 2048 2560 3072 3584 4096 0 512 1024 1536 2048 2560 3072 3584 4096

code code

Figure 10. +/- DNL vs. AVCC = DVCC Figure 11. +/- INL vs. AVCC = DVCC

1 1
0.8 0.8
0.6 0.6
DNL+ INL+
0.4 0.4
0.2 0.2
DNL(lsb)

INL(lsb)

0 0
-0.2 -0.2
-0.4 -0.4
DNL- INL-
-0.6 -0.6
-0.8 -0.8
-1 -1
2.5 3 3.5 4 4.5 5 5.5 2.5 3 3.5 4 4.5 5 5.5

AVCC, DVCC (V) AVCC, DVCC (V)

DS13932 - Rev 1 page 8/24

 ADC1283
Typical characteristics

Figure 12. SNR vs. AVCC = DVCC Figure 13. THD vs. AVCC = DVCC

80 -70

-75
75
-80
SNR (dB)

SNR (dB)

THD (dB)
THD (dB)
70 -85

-90
65
-95

60 -100
2.5 3 3.5 4 4.5 5 5.5 2.5 3 3.5 4 4.5 5 5.5

AVCC, DVCC (V) AVCC, DVCC (V)

Figure 14. ENOB vs. AVCC = DVCC Figure 15. +/- DNL vs. DVCC with AVCC = 5 V

12 1
0.8
0.6
DNL+
0.4
11.8
0.2
ENOB (bits)

DNL(lsb)

ENOB (bits)
0
-0.2
11.6
-0.4
DNL-
-0.6
-0.8
11.4 -1
2.5 3 3.5 4 4.5 5 5.5 2.5 3.0 3.5 4.0 4.5 5.0

AVCC, DVCC (V) DVCC (V)

Figure 16. +/- INL vs. DVCC with AVCC = 5 V Figure 17. +/- DNL vs. SCLK duty cycle

1 1
0.8 0.8
0.6 AVCC=DVCC=3V
0.6
0.4 INL+ 0.4
0.2 0.2
INL(lsb)

DNL(lsb)

DNL+
0 0
AVCC=DVCC=5V
-0.2 -0.2
-0.4 -0.4
INL-
-0.6 -0.6
-0.8 -0.8 DNL-
AVCC=DVCC=3V
-1 -1
2.5 3.0 3.5 4.0 4.5 5.0
30% 40% 50% 60% 70%
DVCC (V) Duty cycle (%)

DS13932 - Rev 1 page 9/24

 ADC1283
Typical characteristics

Figure 18. +/- INL vs. SCLK duty cycle Figure 19. SNR vs. SCLK duty cycle

1 80
0.8
AVCC=DVCC=5V
0.6 AVCC=DVCC=3V
75
0.4
0.2

SNR (dB)
INL(lsb)

INL+
0 70
AVCC=DVCC=5V
-0.2 AVCC=DVCC=3V
-0.4
65
-0.6
INL- AVCC=DVCC=3V
-0.8
-1 60
30% 40% 50% 60% 70% 30% 40% 50% 60% 70%
Duty cycle (%) Duty cycle (%)

Figure 20. THD vs. SCLK duty cycle Figure 21. ENOB vs. SCLK duty cycle

-70 12

AVCC=DVCC=5V
-75

-80 11.8
ENOB (bits)
THD (dB)

AVCC=DVCC=3V
-85
AVCC=DVCC=5V

-90 11.6
AVCC=DVCC=3V
-95

-100 11.4
30% 40% 50% 60% 70% 30% 40% 50% 60% 70%

Duty cycle (%) Duty cycle (%)

Figure 22. +/- DNL vs. SCLK Figure 23. +/- INL vs. SCLK

1 1
0.8 0.8
0.6 0.6
DNL+ AVCC=DVCC=3V INL+
0.4 0.4 AVCC=DVCC=3V
0.2 0.2
DNL(lsb)

INL(lsb)

0 AVCC=DVCC=5V 0
AVCC=DVCC=5V
-0.2 -0.2
-0.4 -0.4 INL-
DNL- AVCC=DVCC=3V
-0.6 -0.6 AVCC=DVCC=3V
-0.8 -0.8
-1 -1
0.8 1.6 2.4 3.2 0.8 1.6 2.4 3.2

SCLK (MHz) SCLK (MHz)

DS13932 - Rev 1 page 10/24

 ADC1283
Typical characteristics

Figure 24. SNR vs. SCLK Figure 25. THD vs. SCLK

80 -70

AVCC=DVCC=5V -75
75
-80

THD (dB)
SNR (dB)

70 AVCC=DVCC=3V -85 AVCC=DVCC=5V

-90
65
AVCC=DVCC=3V
-95

60 -100
0.8 1.6 2.4 3.2 0.8 1.6 2.4 3.2
SCLK (MHz) SCLK (MHz)

Figure 26. ENOB vs. SCLK Figure 27. +/- DNL vs. temperature

12 1
0.8
AVCC=DVCC=5V AVCC=DVCC=5V
0.6
DNL+
0.4
11.8
ENOB (bits)

0.2
DNL (lsb)

0 AVCC=DVCC=3V
AVCC=DVCC=3V -0.2
11.6 -0.4
-0.6 DNL -
AVCC=DVCC=5V
-0.8

11.4 -1
0.8 1.6 2.4 3.2 -40 -20 0 20 40 60 80 100 120
SCLK (MHz) Temperature (°C)

Figure 28. +/- INL vs. temperature Figure 29. SNR vs. temperature

1 80
0.8
AVCC=DVCC=5V AVCC=DVCC=5V
AVCC=DVCC=5V
0.6
INL+ 75
0.4
0.2
DNL (lsb)

SNR (dB)

0 70 AVCC=DVCC=3V
AVCC=DVCC=3V
AVCC=DVCC=3V
-0.2
-0.4
65
-0.6 INL-
AVCC=DVCC=5V
-0.8
-1 60
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120

Temperature (°C) Temperature ( °C)

DS13932 - Rev 1 page 11/24

 ADC1283
Typical characteristics

Figure 30. THD vs. temperature Figure 31. ENOB vs. temperature

-70 12
AVCC=DVCC=5V
-75

-80 11.8

ENOB (bits)
THD (dB)

AVCC=DVCC=3V
-85 AVCC=DVCC=5V

-90 11.6
AVCC=DVCC=3V
-95

-100 11.4
-40 -20 0 20 40 60 80 100 120 -40 -20 0 20 40 60 80 100 120

Temperature (°C) Temperature (°C)

Figure 32. SNR vs. Fin Figure 33. THD vs. Fin

80 -70

-75
AVCC=DVCC=5V
75
-80 AVCC=DVCC=3V
SNR (dB)

THD (dB)

AVCC=DVCC=3V
70 -85

-90
65 AVCC=DVCC=5V
-95

60 -100
10 20 30 40 50 60 10 20 30 40 50 60
Fin (kHz) Fin (kHz)

Figure 34. ENOB vs. Fin Figure 35. Power dissipation (mW) vs. SCLK

12 8

AVCC=DVCC=5V
Power dissipation (mW)

6
11.8
ENOB (bits)

AVCC=DVCC=3V 4
AVCC=DVCC=5V
11.6
2

AVCC=DVCC=3V
11.4 0
10 20 30 40 50 60 0.8 1.2 1.6 2 2.4 2.8 3.2

Fin (kHz) SCLK (MHz)

DS13932 - Rev 1 page 12/24

 ADC1283
Typical characteristics

Figure 36. Power dissipation (mW) vs. temperature

AVCC=DVCC=5.5V
4

Power dissipation (mW)

AVCC=DVCC=5V

2 AVCC=DVCC=3.3V

AVCC=DVCC=3V AVCC=DVCC=2.7V

0
-40 -20 0 20 40 60 80 100 120

Temperature (°C)

DS13932 - Rev 1 page 13/24

 ADC1283
Registers and input channel

6 Registers and input channel

Table 5. Control register bits

Bit # 7 (MSB) 6 5 4 3 2 1 0

Symbol DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC

Table 6. Control register bit description

Bit # Symbol Description

7, 6, 2, 1, 0 DONTC Don’t care

5 ADD2
4 ADD1 These bits determine which input channel is converted, as per Table 7.
3 ADD0

Table 7. Input channel description

ADD2 ADD1 ADD0 Address value (h) Input channel

0 0 0 00 IN0
0 0 1 08 IN1
0 1 0 10 IN2
0 1 1 18 IN3
1 0 0 20 IN4
1 0 1 28 IN5
1 1 0 30 IN6
1 1 1 38 IN7

DS13932 - Rev 1 page 14/24

 ADC1283
Application information

7 Application information

7.1 Functional description of the ADC1283

The ADC1283 implements a successive-approximation-register (SAR) structure to perform the conversion of
analog signals into 12-bit pure binary digital outputs. As shown in the block diagram in Figure 37, it is made
of capacitive Track and Hold, SAR ADC and control logic. The conversion circuit includes a fast settling time
comparator to convey instruction into the register to store digital 0 or 1, and a redistribution DAC with logic control
to have the ADC compare the track signal with a reference signal at each clock cycle.
The conversion is carried out in two phases. The sampling phase conveys the input signal through the
capacitance array for the first 3 clock-cycles and the evaluation phase performs the conversion into digital 12-bit
signal within 13 clock cycles. At each clock cycle of the evaluation phase, the hold signal is compared with a
new value distributed by the DAC and the result is stored in the 12-bit register, MSB first. 13 clock cycles are
necessary for this second step. So, a full conversion requires 16 clock cycles to generate a new 12-bit word on
the DOUT pin.

Figure 37. Functional block diagram

7.2 Analog inputs

The inputs are single-ended and referenced from AVCC to AGND, since AVCC behaves as internal reference
(refer to Table 1. Pin description). The dynamic range is AVCC and the LSB (Least Significant Bit) is:

LSB = AVCC (1)

212

The capacitance seen on the input varies depending on conversion step. During the sampling phase, a 33 pF is
seen from the input, thus care must be taken to the front-end driver to support this load.
The schematic below shows the equivalent input circuit.

Figure 38. Equivalent input circuit

To avoid aliasing of the input signals toward unwanted frequencies, it is recommended to insert a low-pass filter
whose value is fixed depending on inputs frequency and sampling rate.

DS13932 - Rev 1 page 15/24

 ADC1283
Interfacing the ADC1283

7.3 Interfacing the ADC1283

The conversion starts on a falling edge of CS and stops on a rising edge of CS. An internal 8-bit register contains
the address of the channel to be converted. 3 bits of this register are used to this purpose.
By default, if no value is written inside the register or if a wrong address is entered, channel 0 (IN0) is converted
and outputted on DOUT after the first conversion cycle. This address register is reset to its default value (IN0)
when (CS) goes high.
At the start of the conversion, the first data present on DOUT after 16 clock cycles is always channel 0 (IN0). To
get the information on another channel after starting conversion, 32 clock cycles are necessary (equivalent to two
12-bit words).
THE ADC1283 enters track mode under three different conditions. When (CS) goes low with SCLK high, the ADC
enters track mode on the first falling edge of SCLK. When (CS) goes low with SCLK low, the ADC automatically
enters track mode and the falling edge of (CS) is seen as the first falling edge of SCLK. Finally, when (CS) and
SCLK go low simultaneously, the ADC enters track mode. While there is no timing restriction with respect to the
rising edges of (CS) and SCLK, see Figure 5 for set-up and hold time requirements for the falling edge of (CS)
with respect to the rising edge of SCLK.
3 clock cycles are necessary to charge the capacitance to memorize the level of the signal. The signal is then
evaluated during 13 clock cycles. DOUT is always on the same format: four digital 0’s followed by 12-bit signal
(MSB first).
Conversion stops on (CS) turning high but if (CS) remains low, the ADC1283 continuously converts the analog
signal on the selected channel.
For further information, please look at the Application Note related to the ADC1283.

DS13932 - Rev 1 page 16/24

 ADC1283
Package information

8 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.

8.1 TSSOP-16 package information

Figure 39. TSSOP-16 package outline

DS13932 - Rev 1 page 17/24

 ADC1283
TSSOP-16 package information

Table 8. TSSOP-16 package mechanical data

mm
Dim.
Min. Typ. Max.

A 1.20
A1 0.05 0.15
A2 0.80 1.00 1.05
b 0.19 0.30
c 0.09 0.20
D 4.90 5.00 5.10
E 6.20 6.40 6.60
E1 4.30 4.40 4.50
e 0.65
k 0° 8°
L 0.45 0.60 0.75
L1 1.00
aaa 0.10

DS13932 - Rev 1 page 18/24

 ADC1283
Ordering information

9 Ordering information

Table 9. Order code

Order code Package Temperature range Marking

ADC1283IPT TSSOP-16 - 40 °C to 125 °C ADC1283

DS13932 - Rev 1 page 19/24

 ADC1283

Revision history
Table 10. Document revision history

Date Version Changes

15-Mar-2022 1 Initial release.

DS13932 - Rev 1 page 20/24

 ADC1283
Contents

Contents
1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 Absolute maximum ratings and operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
5 Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6 Registers and input channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
7 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
7.1 Functional description of the ADC1283 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.2 Analog inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.3 Interfacing the ADC1283 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
8 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
8.1 TSSOP-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
9 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

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 ADC1283
List of tables

List of tables
Table 1. Pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 3. Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 4. Electrical characteristics AGND = DGND = 0 V, fSCLK = 3.2 MHz, fSAMPLE = 200 ksps, CL = 50 pF, Ta = 25 °C, all
specifications Tmin to Tmax unless otherwise specified. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 5. Control register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 6. Control register bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 7. Input channel description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. TSSOP-16 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 9. Order code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 10. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

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 ADC1283
List of figures

List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 3. Operational timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Serial timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 5. SCLK and CS timing parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. DNL vs. output codes (AVCC = DVCC = 3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. DNL vs. output codes (AVCC = DVCC = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 8. INL vs. output codes (AVCC = DVCC = 3 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 9. INL vs. output codes (AVCC = DVCC = 5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 10. +/- DNL vs. AVCC = DVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 11. +/- INL vs. AVCC = DVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 12. SNR vs. AVCC = DVCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 13. THD vs. AVCC = DVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 14. ENOB vs. AVCC = DVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 15. +/- DNL vs. DVCC with AVCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 16. +/- INL vs. DVCC with AVCC = 5 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 17. +/- DNL vs. SCLK duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 18. +/- INL vs. SCLK duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 19. SNR vs. SCLK duty cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 20. THD vs. SCLK duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 21. ENOB vs. SCLK duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 22. +/- DNL vs. SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 23. +/- INL vs. SCLK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 24. SNR vs. SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 25. THD vs. SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 26. ENOB vs. SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 27. +/- DNL vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 28. +/- INL vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 29. SNR vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 30. THD vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 31. ENOB vs. temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 32. SNR vs. Fin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 33. THD vs. Fin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 34. ENOB vs. Fin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 35. Power dissipation (mW) vs. SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 36. Power dissipation (mW) vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 37. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 38. Equivalent input circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 39. TSSOP-16 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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 ADC1283

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