CD54HC107, CD74HC107,

CD74HCT107
Data sheet acquired from Harris Semiconductor
SCHS139D
Dual J-K Flip-Flop with Reset
March 1998 - Revised October 2003 Negative-Edge Trigger

Features Description
• Hysteresis on Clock Inputs for Improved Noise Immu- The ’HC107 and CD74HCT107 utilize silicon gate CMOS
nity and Increased Input Rise and Fall Times technology to achieve operating speeds equivalent to LSTTL
[ /Title parts. They exhibit the low power consumption of standard
• Asynchronous Reset
(CD74 CMOS integrated circuits, together with the ability to drive 10
HC107 • Complementary Outputs LSTTL loads.
, • Buffered Inputs These flip-flops have independent J, K, Reset and Clock
CD74 inputs and Q and Q outputs. They change state on the
• Typical fMAX = 60MHz at VCC = 5V, CL = 15pF, negative-going transition of the clock pulse. Reset is
HCT10 TA = 25oC accomplished asynchronously by a low level input.
7) • Fanout (Over Temperature Range) This device is functionally identical to the HC/HCT73 but
/Sub- - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads differs in terminal assignment and in some parametric limits.
ject - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
The HCT logic family is functionally as well as pin compatible
(Dual • Wide Operating Temperature Range . . . -55oC to 125oC with the standard LS family.
J-K
• Balanced Propagation Delay and Transition Times Ordering Information
Flip-
Flop • Significant Power Reduction Compared to LSTTL
TEMP. RANGE
Logic ICs
with PART NUMBER (oC) PACKAGE
Reset • HC Types CD54HC107F3A -55 to 125 14 Ld CERDIP
Nega- - 2V to 6V Operation
CD74HC107E -55 to 125 14 Ld PDIP
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC
tive- at VCC = 5V CD74HC107M -55 to 125 14 Ld SOIC

• HCT Types CD74HC107MT -55 to 125 14 Ld SOIC

- 4.5V to 5.5V Operation CD74HC107M96 -55 to 125 14 Ld SOIC
- Direct LSTTL Input Logic Compatibility, CD74HCT107E -55 to 125 14 Ld PDIP
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.

Pinout
CD54HC107 (CERDIP)
CD74HC107 (PDIP, SOIC)
CD74HCT107 (PDIP)
TOP VIEW

1J 1 14 VCC

1Q 2 13 1R

1Q 3 12 1CP

1K 4 11 2K

2Q 5 10 2R

2Q 6 9 2CP

GND 7 8 2J

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
1
 CD54HC107, CD74HC107, CD74HCT107

Functional Diagram
1
1J 3
1Q
4
1K FF 1 2
1Q
12
1CP
13
1R

8
2J 5
2Q
11
2K FF 2
6
9 2Q
2CP

10 GND = 7
2R VCC = 14

TRUTH TABLE

INPUTS OUTPUTS

R CP J K Q Q

L X X X L H

H ↓ L L No Change

H ↓ H L H L

H ↓ L H L H

H ↓ H H Toggle

H H X X No Change

H= High Level (Steady State)

L= Low Level (Steady State)
X= Irrelevant
↓= High-to-Low Transition

Logic Diagram

1 (8)
J 3 (5)
J Q
4(11)
K K

12 (9) CL 2 (6)
CP nA CL R Q

13 (10)
R

2
 CD54HC107, CD74HC107, CD74HCT107

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 1) θJA (oC/W)
DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 80
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . 86
DC Drain Current, per Output, IO Maximum Junction Temperature (Hermetic Package or Die) . . . 175oC
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
DC Output Diode Current, IOK Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
DC Output Source or Sink Current per Output Pin, IO (SOIC - Lead Tips Only)
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Specifications
TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
PARAMETER SYMBOL VI (V) IO (mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V
Voltage
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V
Voltage
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output VOH VIH or -0.02 2 1.9 - - 1.9 - 1.9 - V
Voltage VIL
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
CMOS Loads
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output - - - - - - - - - V
Voltage
-4 4.5 3.98 - - 3.84 - 3.7 - V
TTL Loads
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output VOL VIH or 0.02 2 - - 0.1 - 0.1 - 0.1 V
Voltage VIL
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
CMOS Loads
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output - - - - - - - - - V
Voltage
4 4.5 - - 0.26 - 0.33 - 0.4 V
TTL Loads
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA
Current GND

3
 CD54HC107, CD74HC107, CD74HCT107

DC Electrical Specifications (Continued)

TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
PARAMETER SYMBOL VI (V) IO (mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Quiescent Device ICC VCC or 0 6 - - 4 - 40 - 80 µA
Current GND
HCT TYPES
High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V
Voltage 5.5
Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V
Voltage 5.5
High Level Output VOH VIH or -0.02 4.5 4.4 - - 4.4 - 4.4 - V
Voltage VIL
CMOS Load
High Level Output -4 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads
Low Level Output VOL VIH or 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Voltage CMOS Loads VIL
Low Level Output 4 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads
Input Leakage II VCC - 5.5 - ±0.1 - ±1 - ±1 µA
Current and
GND
Quiescent Device ICC VCC or 0 5.5 - - 4 - 40 - 80 µA
Current GND
Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA
Device Current Per (Note 2) - 2.1 5.5
Input Pin: 1 Unit Load
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

HCT Input Loading Table

INPUT UNIT LOADS
All 0.3
NOTE: Unit Load is ∆ICC limit specified in DC Electrical Specifica-
tions table, e.g., 360µA max at 25oC.

Prerequisite For Switching Specifications

25oC -40oC TO 85oC -55oC TO 125oC
TEST VCC
PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
CP Pulse Width tw - 2 80 - - 100 - 120 - ns
4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns
R Pulse Width tw - 2 80 - - 100 - 120 - ns
4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

4
 CD54HC107, CD74HC107, CD74HCT107

Prerequisite For Switching Specifications (Continued)

25oC -40oC TO 85oC -55oC TO 125oC

TEST VCC
PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Setup Time, J, K to CP tSU - 2 100 - - 125 - 150 - ns
4.5 20 - - 25 - 30 - ns
6 17 - - 21 - 26 - ns
Hold Time, J, K to CP tH - 2 3 - - 3 - 3 - ns
4.5 3 - - 3 - 3 - ns
6 3 - - 3 - 3 - ns
Removal Time tREM - 2 60 - - 75 - 90 - ns
4.5 12 - - 15 - 18 - ns
6 10 - - 13 - 15 - ns
CP Frequency fMAX - 2 6 - - 5 - 4 - MHz
4.5 30 - - 25 - 20 - MHz
6 35 - - 29 - 23 - MHz
HCT TYPES
CP Pulse Width tw - 4.5 18 - - 23 - 27 - ns
R Pulse Width tw - 4.5 24 - - 30 - 36 - ns
Setup Time, J, K to CP tSU - 4.5 20 - - 25 - 30 - ns
Hold Time, J, K to CP tH - 4.5 5 - - 5 - 5 - ns
Removal Time tREM - 4.5 12 - - 15 - 18 - ns
CP Frequency fMAX - 4.5 28 - - 22 - 19 - MHz

Switching Specifications Input tr, tf = 6ns

25oC -40oC TO 85oC -55oC TO 125oC
TEST VCC
PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
Propagation Delay, tPLH, tPHL CL = 50pF 2 - - 170 - 215 - 255 ns
CP to Q
4.5 - - 34 - 43 - 51 ns
CL = 15pF 5 - 14 - - - - - ns
CL = 50pF 6 - - 29 - 37 - 43 ns
Propagation Delay, tPLH, tPHL CL = 50pF 2 - - 170 - 215 - 255 ns
CP to Q
4.5 - - 34 - 43 - 51 ns
CL = 15pF 5 - 14 - - - - - ns
CL = 50pF 6 - - 29 - 37 - 43 ns
Propagation Delay, tPLH, tPHL CL = 50pF 2 - - 155 - 195 - 235 ns
R to Q, Q
4.5 - - 31 - 39 - 47 ns
CL = 15pF 5 - 13 - - - - - ns
CL = 50pF 6 - - 26 - 33 - 40 ns
Output Transition Time tTLH, tTHL CL = 50pF 2 - - 75 - 95 18 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Input Capacitance CI - - - - 10 - 10 - 10 pF
CP Frequency fMAX CL = 15pF 5 - 60 - - - - - MHz

5
 CD54HC107, CD74HC107, CD74HCT107

Switching Specifications Input tr, tf = 6ns (Continued)

25oC -40oC TO 85oC -55oC TO 125oC

TEST VCC
PARAMETER SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Power Dissipation Capacitance CPD - 5 - 31 - - - - - pF
(Notes 3, 4)
HCT TYPES
Propagation Delay, tPLH, tPHL CL = 50pF 4.5 - - 43 - 54 - 65 ns
CP to Q
CL = 15pF 5 - 18 - - - - - ns
Propagation Delay, tPLH, tPHL CL = 50pF 4.5 - - 40 - 50 - 60 ns
CP to Q
CL = 15pF 5 - 17 - - - - - ns
Propagation Delay, tPLH, tPHL CL = 50pF 4.5 - - 38 - 48 - 57 ns
R to Q, Q
CL = 15pF 5 - 16 - - - - - ns
Output Transition Time tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns
Input Capacitance CI - - - - 10 - 10 - 10 pF
CP Frequency fMAX CL = 15pF 5 - 56 - - - - - MHz
Power Dissipation Capacitance CPD - 5 - 30 - - - - - pF
(Notes 3, 4)
NOTES:
3. CPD is used to determine the dynamic power consumption, per flip-flop.
4. PD = CPD VCC2 fi + Σ CL VCC2 fo where fi = input frequency, fo = output frequency, CL = output load capacitance, VCC = supply voltage.

Test Circuits and Waveforms

I
I tWL + tWH =
tWL + tWH = trCL = 6ns fCL
trCL tfCL fCL tfCL = 6ns

VCC 3V
90% 2.7V
CLOCK 50% CLOCK 1.3V
50% 50% 1.3V 1.3V
10% 10% GND 0.3V 0.3V GND

tWL tWH tWL tWH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For fMAX, input duty cycle = 50%. accordance with device truth table. For fMAX, input duty cycle = 50%.
FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH PULSE WIDTH

tr = 6ns tf = 6ns tr = 6ns tf = 6ns

VCC 3V
90% 2.7V
INPUT 50% INPUT 1.3V
10% GND 0.3V GND

tTHL tTLH tTHL tTLH

90% 90%
50% 1.3V
INVERTING 10% INVERTING
10%
OUTPUT OUTPUT
tPHL tPLH tPHL tPLH

FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA- FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION
TION DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC

6
 CD54HC107, CD74HC107, CD74HCT107

Test Circuits and Waveforms (Continued)

trCL tfCL trCL tfCL

VCC 3V
90% CLOCK 2.7V
CLOCK 50% 1.3V
INPUT 10% INPUT 0.3V
GND GND

tH(H) tH(L) tH(H) tH(L)

VCC 3V
DATA
DATA 50% 1.3V 1.3V 1.3V
INPUT INPUT
GND GND
tSU(H) tSU(L) tSU(H) tSU(L)

tTLH tTHL tTLH tTHL

90% 90%
90% 90%
50% 1.3V
OUTPUT OUTPUT 1.3V
10% 10%
tPLH tPHL tPLH tPHL

tREM tREM
VCC 3V
SET, RESET 50% SET, RESET 1.3V
OR PRESET OR PRESET
GND GND

IC IC
CL CL
50pF 50pF

FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,
AND PROPAGATION DELAY TIMES FOR EDGE AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS TRIGGERED SEQUENTIAL LOGIC CIRCUITS

7
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2022

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

5962-8515401CA ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8515401CA Samples
& Green CD54HC107F3A
CD54HC107F3A ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 5962-8515401CA Samples
& Green CD54HC107F3A
CD74HC107E ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC107E Samples

CD74HC107EE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC107E Samples

CD74HC107M ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC107M Samples

CD74HC107M96 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC107M Samples

CD74HC107MG4 ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC107M Samples

CD74HC107MT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC107M Samples

CD74HCT107E ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HCT107E Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2022

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC107, CD74HC107 :

• Catalog : CD74HC107
• Military : CD54HC107

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC107M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD74HC107MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC107M96 SOIC D 14 2500 356.0 356.0 35.0
CD74HC107MT SOIC D 14 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 3-Jun-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HC107E N PDIP 14 25 506 13.97 11230 4.32
CD74HC107E N PDIP 14 25 506 13.97 11230 4.32
CD74HC107EE4 N PDIP 14 25 506 13.97 11230 4.32
CD74HC107EE4 N PDIP 14 25 506 13.97 11230 4.32
CD74HC107M D SOIC 14 50 506.6 8 3940 4.32
CD74HC107MG4 D SOIC 14 50 506.6 8 3940 4.32
CD74HCT107E N PDIP 14 25 506 13.97 11230 4.32
CD74HCT107E N PDIP 14 25 506 13.97 11230 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
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