CD54HC00, CD74HC00

www.ti.com CD54HC00,
SCHS116D – JANUARY 1998 CD74HC00
– REVISED JANUARY 2021
SCHS116D – JANUARY 1998 – REVISED JANUARY 2021

CDx4HC00 Quadruple 2-Input NAND Gates

1 Features 3 Description
• Buffered inputs This device contains four independent 2-input NAND
• Wide operating voltage range: 2 V to 6 V gates. Each gate performs the Boolean function
• Wide operating temperature range: Y = A ● B in positive logic.
–55°C to +125°C
• Supports fanout up to 10 LSTTL loads Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
• Significant power reduction compared to LSTTL
logic ICs CD74HC00D SOIC (14) 8.65 mm × 3.90 mm
CD74HC00N PDIP (14) 19.30 mm × 6.40 mm
2 Applications CD54HC00J CDIP (14) 19.94 mm × 7.62 mm
• Alarm / tamper detect circuit
(1) For all available packages, see the orderable addendum at
• S-R latch the end of the data sheet.

1 14
1A VCC
2 13
1B 4B
3 12
1Y 4A
4 11
2A 4Y
5 10
2B 3B
6 9
2Y 3A
7 8
GND 3Y

Device functional pinout

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Table of Contents
1 Features............................................................................1 8.4 Standard CMOS Inputs...............................................8
2 Applications..................................................................... 1 8.5 Clamp Diode Structure................................................8
3 Description.......................................................................1 8.6 Device Functional Modes............................................9
4 Revision History.............................................................. 2 9 Application and Implementation.................................. 10
5 Pin Configuration and Functions...................................3 9.1 Application Information............................................. 10
Pin Functions.................................................................... 3 9.2 Typical Application.................................................... 10
6 Specifications.................................................................. 4 10 Power Supply Recommendations..............................13
6.1 Absolute Maximum Ratings ....................................... 4 11 Layout........................................................................... 13
6.2 ESD Ratings .............................................................. 4 11.1 Layout Guidelines................................................... 13
6.3 Recommended Operating Conditions ........................4 11.2 Layout Example...................................................... 13
6.4 Thermal Information ...................................................5 12 Device and Documentation Support..........................14
6.5 Electrical Characteristics ............................................5 12.1 Documentation Support.......................................... 14
6.6 Switching Characteristics ...........................................6 12.2 Receiving Notification of Documentation Updates..14
6.7 Operating Characteristics .......................................... 6 12.3 Support Resources................................................. 14
6.8 Typical Characteristics................................................ 6 12.4 Trademarks............................................................. 14
7 Parameter Measurement Information............................ 7 12.5 Electrostatic Discharge Caution..............................14
8 Detailed Description........................................................8 12.6 Glossary..................................................................14
8.1 Overview..................................................................... 8 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram........................................... 8 Information.................................................................... 15
8.3 Balanced CMOS Push-Pull Outputs........................... 8

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision C (September 2003) to Revision D (January 2021) Page

• Updated to new data sheet format......................................................................................................................1
• HCT device moved to new data sheet (SCHS398)............................................................................................ 1
• RθJA increased for the D package from 86 to 133.6 ℃/W and decreased for the N package from 80 to 69.5
℃/W....................................................................................................................................................................5

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5 Pin Configuration and Functions

1A 1 14 VCC
1B 2 13 4B
1Y 3 12 4A
2A 4 11 4Y
2B 5 10 3B
2Y 6 9 3A
GND 7 8 3Y

Figure 5-1. D, N, or J Package

14-Pin SOIC, PDIP, or CDIP
Top View

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
1A 1 Input Channel 1, Input A
1B 2 Input Channel 1, Input B
1Y 3 Output Channel 1, Output Y
2A 4 Input Channel 2, Input A
2B 5 Input Channel 2, Input B
2Y 6 Output Channel 2, Output Y
GND 7 — Ground
3Y 8 Output Channel 3, Output Y
3A 9 Input Channel 3, Input A
3B 10 Input Channel 3, Input B
4Y 11 Output Channel 4, Output Y
4A 12 Input Channel 4, Input A
4B 13 Input Channel 4, Input B
VCC 14 — Positive Supply

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 7 V
VI < –0.5 V or VI > VCC +
IIK Input clamp current(2) ±20 mA
0.5 V
VO < –0.5 V or VO > VCC +
IOK Output clamp current(2) ±20 mA
0.5 V
VO > –0.5 V or VO < VCC +
IO Continuous output current ±25 mA
0.5 V
Continuous current through VCC or GND ±50 mA
Plastic package 150
TJ Junction temperature(3) °C
Hermetic package or die 175
Lead temperature (soldering 10s) SOIC - lead tips only 300 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) Guaranteed by design.

6.2 ESD Ratings

VALUE UNIT
CD74HC00 IN D (SOIC) PACKAGE
Human-body model (HBM), per ANSI/ESDA/
±2000
JEDEC JS-001(1)
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC
±1000
specification JESD22-C101(2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Supply voltage 2 6 V
VCC = 2 V 1.5
VIH High-level input voltage VCC = 4.5 V 3.15
VCC = 6 V 4.2
VCC = 2 V 0.5
VIL Low-level input voltage VCC = 4.5 V 1.35
VCC = 6 V 1.8
VI Input voltage 0 VCC V
VO Output voltage 0 VCC V
VCC = 2 V 1000
tt Input transition time VCC = 4.5 V 500 ns
VCC = 6 V 400

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over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT
TA Operating free-air temperature –55 125 °C

6.4 Thermal Information

CD74HC00
THERMAL METRIC(1) N (PDIP) D (SOIC) UNIT
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 69.5 133.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 57.6 89.0 °C/W
RθJB Junction-to-board thermal resistance 49.3 89.5 °C/W
ΨJT Junction-to-top characterization parameter 37.6 45.5 °C/W
ΨJB Junction-to-board characterization parameter 49.1 89.1 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

6.5 Electrical Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
PARAMETER TEST CONDITIONS VCC 25°C –40°C to 85°C –55°C to 125°C UNIT
MIN TYP MAX MIN TYP MAX MIN TYP MAX
2V 1.9 1.9 1.9
IOH = –20
4.5 V 4.4 4.4 4.4
µA
6V 5.9 5.9 5.9
High-level VI = VIH or
VOH V
output voltage VIL IOH = –4
4.5 V 3.98 3.84 3.7
mA
IOH = –5.2
6V 5.48 5.34 5.2
mA
2V 0.1 0.1 0.1
IOL = 20
4.5 V 0.1 0.1 0.1
µA
Low-level output VI = VIH or 6V 0.1 0.1 0.1
VOL V
voltage VIL
IOL = 4 mA 4.5 V 0.26 0.33 0.4
IOL = 5.2
6V 0.26 0.33 0.4
mA
Input leakage
II VI = VCC or GND 6V ±0.1 ±1 ±1 µA
current
VI = VCC or
ICC Supply current IO = 0 6V 2 20 40 µA
GND
Input
Ci 5V 10 10 10 pF
capacitance

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6.6 Switching Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
Operating free-air temperature (TA)
TEST
PARAMETER FROM TO CONDITIO VCC 25°C –40°C to 85°C –55°C to 125°C UNIT
NS
MIN TYP MAX MIN TYP MAX MIN TYP MAX
2V 90 115 135
A or B Y CL = 50 pF 4.5 V 18 23 27
tpd Propagation delay ns
6V 15 20 23
A or B Y CL = 15 pF 5 V 7
2V 75 95 18 110
tt Transition-time Y CL = 50 pF 4.5 V 15 19 22 ns
6V 13 16 19

6.7 Operating Characteristics

over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
Power dissipation capacitance
Cpd No load 5V 25 pF
per gate

6.8 Typical Characteristics

TA = 25°C
7 0.3
2-V
6 4.5-V
0.25 6-V
VOH Output High Voltage (V)

VOL Output Low Voltage (V)

5
0.2
4
0.15
3
0.1
2

2-V 0.05
1 4.5-V
6-V
0 0
0 1 2 3 4 5 6 0 1 2 3 4 5 6
IOH Output High Current (mA) IOL Output Low Current (mA)
Figure 6-1. Typical output voltage in the high state (VOH) Figure 6-2. Typical output voltage in the low state (VOL)

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7 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.

Test VCC
Point
Input 50% 50%
0V
From Output
tPLH(1) tPHL(1)
Under Test
VOH
CL(1)
Output 50% 50%
VOL
(1) CL includes probe and test-fixture capacitance.
tPHL(1) tPLH(1)
Figure 7-1. Load Circuit for Push-Pull Outputs VOH
Output 50% 50%
VOL
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-2. Voltage Waveforms, Propagation
Delays
VCC
90% 90%
Input
10% 10%
0V
tr(1) tf(1)

VOH
90% 90%
Output
10% 10%
VOL
tr(1) tf(1)
(1) The greater between tr and tf is the same as tt.
Figure 7-3. Voltage Waveforms, Input and Output Transition Times

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8 Detailed Description
8.1 Overview
This device contains four independent 2-input NAND gates. Each gate performs the Boolean function Y = A ● B
in positive logic.
8.2 Functional Block Diagram

xA

xY

xB

Figure 8-1. Logic Diagram (Positive Logic) for the CD74HC00

8.3 Balanced CMOS Push-Pull Outputs

This device includes balanced CMOS push-pull outputs. The term "balanced" indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.4 Standard CMOS Inputs
This device includes standard CMOS inputs. Standard CMOS inputs are high impedance and are typically
modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case
resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the
maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I).
Standard CMOS inputs require that input signals transition between valid logic states quickly, as defined by the
input transition time or rate in the Recommended Operating Conditions table. Failing to meet this specification
will result in excessive power consumption and could cause oscillations. More details can be found in
Implications of Slow or Floating CMOS Inputs.
Do not leave standard CMOS inputs floating at any time during operation. Unused inputs must be terminated at
VCC or GND. If a system will not be actively driving an input at all times, a pull-up or pull-down resistor can be
added to provide a valid input voltage during these times. The resistor value will depend on multiple factors,
however a 10-kΩ resistor is recommended and will typically meet all requirements.
8.5 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Electrical
Placement of Clamping Diodes for Each Input and Output.

CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.

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VCC
Device

+IIK +IOK

Input Logic Output

-IIK -IOK

GND

Figure 8-2. Electrical Placement of Clamping Diodes for Each Input and Output

8.6 Device Functional Modes

Table 8-1. Function Table
INPUTS OUTPUT
A B Y
H H L
L X H
X L H

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9 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

9.1 Application Information

In this application, the CD74HC00 is used to create an SR latch. The two additional gates can be used for a
second active-low SR latch, individually used for their logic function, or the inputs can be grounded and both
channels left unused. This device is used to drive the tamper indicator LED and provide one bit of data to the
system controller. When the tamper switch outputs LOW, the output Q becomes HIGH. This output remains
HIGH until the system controller addresses the event and sends a LOW signal to the R input which returns the Q
output back to LOW.

9.2 Typical Application

R1 System
R Controller

Tamper Q
Switch S
R2

Tamper
Indicato r

Figure 9-1. Typical application diagram

9.2.1 Design Requirements

9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the CD74HC00 plus the maximum static supply current, ICC, listed in Electrical Characteristics and
any transient current required for switching. The logic device can only source as much current as is provided by
the positive supply source. Be sure not to exceed the maximum total current through VCC listed in the Absolute
Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
CD74HC00 plus the maximum supply current, ICC, listed in Electrical Characteristics, and any transient current
required for switching. The logic device can only sink as much current as can be sunk into its ground connection.
Be sure not to exceed the maximum total current through GND listed in the Absolute Maximum Ratings.
The CD74HC00 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of the
datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed 50
pF.
The CD74HC00 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and
current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the high state, the
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output voltage in the equation is defined as the difference between the measured output voltage and the supply
voltage at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.

CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.

9.2.1.2 Input Considerations

Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
CD74HC00, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ resistor
value is often used due to these factors.
The CD74HC00 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined in the
Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power
consumption, and reduction in device reliability.
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Feature Description section for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the CD74HC00 to
the receiving device(s).
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.

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4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.3 Application Curve

Figure 9-2. Application timing diagram

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10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
given example layout image.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example

GND VCC

Recommend GND flood fill for

improved signal isolation, noise Bypass capacitor
reduction, and thermal dissipation placed close to
0.1 F the device

1A 1 14 VCC
Unused inputs
1B 2 13 4B tied to VCC
1Y 3 12 4A
Unused output
2A 4 11 4Y
left floating
2B 5 10 3B
2Y 6 9 3A
Avoid 90°
corners for GND 7 8 3Y
signal lines

Figure 11-1. Example layout for the CD74HC00.

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12 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

12.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

CD54HC00F ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 CD54HC00F Samples
& Green
CD54HC00F3A ACTIVE CDIP J 14 1 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8403701CA Samples
& Green CD54HC00F3A
CD74HC00E ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC00E Samples

CD74HC00EE4 ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74HC00E Samples

CD74HC00M ACTIVE SOIC D 14 50 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC00M Samples

CD74HC00M96 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 HC00M Samples

CD74HC00MT ACTIVE SOIC D 14 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 HC00M Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 14-Oct-2022

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC00, CD74HC00 :

• Catalog : CD74HC00
• Military : CD54HC00

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 15-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC00M96 SOIC D 14 2500 330.0 16.4 6.6 9.3 2.1 8.0 16.0 Q1
CD74HC00M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
CD74HC00MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 15-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC00M96 SOIC D 14 2500 366.0 364.0 50.0
CD74HC00M96 SOIC D 14 2500 367.0 367.0 38.0
CD74HC00MT SOIC D 14 250 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 15-Aug-2022

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD74HC00E N PDIP 14 25 506 13.97 11230 4.32
CD74HC00E N PDIP 14 25 506 13.97 11230 4.32
CD74HC00EE4 N PDIP 14 25 506 13.97 11230 4.32
CD74HC00EE4 N PDIP 14 25 506 13.97 11230 4.32
CD74HC00M D SOIC 14 50 506.6 8 3940 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
J0014A SCALE 0.900
CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

PIN 1 ID A 4X .005 MIN

(OPTIONAL) [0.13] .015-.060 TYP
[0.38-1.52]

1
14
12X .100
[2.54] 14X .014-.026
14X .045-.065 [0.36-0.66]
[1.15-1.65]
.010 [0.25] C A B

.754-.785
[19.15-19.94]

7 8

B .245-.283 .2 MAX TYP .13 MIN TYP

[6.22-7.19] [5.08] [3.3]

C SEATING PLANE

.308-.314
[7.83-7.97]
AT GAGE PLANE

.015 GAGE PLANE

[0.38]

0 -15 14X .008-.014

TYP [0.2-0.36]

4214771/A 05/2017

NOTES:

1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for
reference only. Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This package is hermitically sealed with a ceramic lid using glass frit.
4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only.
5. Falls within MIL-STD-1835 and GDIP1-T14.

www.ti.com
 EXAMPLE BOARD LAYOUT
J0014A CDIP - 5.08 mm max height
CERAMIC DUAL IN LINE PACKAGE

(.300 ) TYP
[7.62] SEE DETAIL B
SEE DETAIL A

1 14

12X (.100 )
[2.54]

SYMM

14X ( .039)
[1]

7 8

SYMM

LAND PATTERN EXAMPLE

NON-SOLDER MASK DEFINED
SCALE: 5X

.002 MAX (.063)

[0.05] [1.6]
ALL AROUND METAL
( .063)
SOLDER MASK [1.6]
OPENING

METAL

SOLDER MASK .002 MAX

(R.002 ) TYP [0.05]
OPENING
[0.05] ALL AROUND
DETAIL A DETAIL B
SCALE: 15X 13X, SCALE: 15X

4214771/A 05/2017

www.ti.com
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