Introduction to an FPGA Technology

Hassan S. O. Migdadi

School of Engineering, Design and Technology

University of Bradford
Agenda

– Hardware implementation

– FPGA

– FPGA architecture

– Computer-Aided-Design (CAD)
 Hardware Implementation

• Processors, Application Specific Integrated Circuits (ASIC), and

Field-Programmable-Gate-Array (FPGA) are the three main
methods used to implement digital domain communication
systems.
 Hardware implementation Cont.
• Using programmable FPGA to implement communication systems
combines the attributes of

• ASIC: density, power and speed

• Microprocessor or Microcontroller: general purpose

programmability.
 Hardware implementation Cont.
• In addition to that, the reconfigurability of FPGAs means that there
is no need for custom fabrication of the IC which provides the
engineer designer with a full control over the actual system design
implementation.

More Details
 Hardware implementation Cont.
• The historical advantages of ASIC over FPGA are being reduced
by several factors:
I. modern FPGAs contain large hard building blocks like
multiplier/accumulators and memory blocks which significantly
increase the energy efficiency, decrease the critical path delay and the
area. Thus the gap between FPGA and ASIC in term of logic density,
power consumption, circuit speed is reduced .
Hardware implementation Cont.

II. when the ASIC designed functions become part of the manufacture’s
Intellectual Property (IP) and can re-used, they are incorporated into
their FPGAs to reduce the overall cost of development, manufacturing,
and test of the FPGAs and hence the board space, power, and money
are saved which leads to a more reduction in the gap between FPGA
and ASIC

More Details
 FPGA :
• A field-programmable gate array (FPGA) is an integrated circuit designed to be
configured by a customer or a designer after manufacturing.

• The FPGA configuration is generally specified using a hardware description

language (HDL).

• FPGAs can be used to implement any logical function.

• The ability to update the functionality after shipping, partial re-configuration of

a portion of the design offer advantages for many applications

More Details
FPGA : Cont.

• FPGA applications now are include a wide range of markets

such as consumer electronics and communications due to the
interested design requirements in terms of power efficiency,
high operation performance, and cost effective.

in other words
FPGA architecture
• FPGA architecture

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 Computer-Aided-Design (CAD) programs
• It is essential to make use of Computer-Aided-Design (CAD)
programs and tools when implementing desired circuits in FPGAs.

• A general typical CAD flow for implementing the designed

circuits in FPGAs is shown in the Figure below .
 CAD flow

More Details
Commercially Available FPGAs
 Commercially Available FPGAs Cont.
• Both Xilinx and Altera work on the following two main approaches
to expand the market for FPGAs:
– a) Low-End-Market by lower the per-FPGA-unit-production-cost.
– can be achieved by many methods, such as by designing FPGAs with less processing power
and/or less memory.

– b) High-End-Market by higher the per-FPGA-unit-production-capacity.

– is needed for applications which require a high performance DSP, embedded processing and/or
high-speed I/O
 Commercially Available FPGAs Cont.
• Altera provides a variety of development and education boards
designed to meet educational and researchable needs that help
students to simplify the design process from simple tasks that
clarify essential concepts to complex designs needed to prove a
novel proposal

• For MPhil we have used DE2 board, while for PhD we will use
DE4 board.
Thank you for your attention
Questions, please?
 Hardware implementation Cont.

• Implementing OFDM system on ASIC hardware is the most power

efficiency, smallest, and fastest.

• However, it is inflexible and needs more time for marketing the

designed chip compared to FPGA.
 Hardware implementation Cont.

• Using universal purpose Microprocessor or Microcontroller to

implement desired ystem is needed more peripheral such as
memory, higher power, larger memory space.

• Also its operation speed is lower compared to ASIC and FPGA.

Back
Hardware implementation Cont.
• Historically, compared to FPGAs, ASICs offer many
advantages including reduced in silicon area, reduced in power
consumption, and increased in performance.

• However, these advantages come at the cost of an increase in

non-recurring engineering, an increase in time to market, and
inability to re-programme in the field for debugging when
designs are implemented on ASICs.
Back
 FPGA :

• Over the last decade, pre-fabricated and re-programmable silicon

devices that define the feature of FPGAs, have evolved to become
one of the key role of the present and the future generation of
digital circuit implementation since it avoids the significant
hardware implementation challenges that were associated with
previous design developments.
Back
FPGA : Cont.

• Over the last decades, FPGA are used on a wide range of

communication applications market which have different
requirements of power efficiency, performance, and cost

Back
 FPGA architecture: Cont.
• The basic structure of FPGAs is array-based.

• The most common FPGA architecture consists of:

– a two dimensional matrix of programmable-logic-blocks (called Configurable Logic
Block (CLB) by Xilinx, and Logic Element (LE) by Altera for example),

– a two dimensional matrix of programmable-routing-channels,

– and I/O blocks

• The programmable-logic-blocks can be interconnected via the

horizontal and vertical programmable-routing-channels.
FPGA architecture: Cont.
• Commonly, the programmable-logic-block consists of function
generators, storage elements, and dedicated arithmetic logic
circuits. Function generator can be configured as a Look-Up-
Table (LUT), while a storage element as edge-triggered Flip-Flop
(FF) or as level-triggered latches.
FPGA architecture: Cont.
• An n-by-m LUT is a (2n X m) bit wide memory array where the
n-address lines fed into the memory are the LUT input, and m-
data lines output from the memory are the LUT output. Thus, a
LUT with n inputs can encode and realize any Boolean function
of its n inputs by modelling the Boolean function as a truth table
and then programing that truth table directly into the memory.
 FPGA architecture: Cont.

• To connect logical blocks with each other, a two dimensional

matrix of programmable routing cannels is used where the
structure of this interconnect is considered a significant feature
in FPGA device.
 FPGA architecture: Cont.
• one of the user-programmable switch technologies is used to
connect the wire-segments (in routing channels) to the
inputs/outputs of the Logical-Blocks, or the wire-segments
together.
 FPGA architecture: Cont.
• The speed-performance of the configured circuit depends on how
the CAD tools allocate the wire-segments for each signal. This is
because when the signal travels from one CLB to another it needs
to pass through a number programmable-switches, where the
particulate setting of wire-segments used determine how many
switches crossed
FPGA architecture: Cont.

• Contemporary FPGAs contain of other resources in addition to

Programmable-Logic-Blocks and Programmable-Routing-
Channels such as:
FPGA architecture: Cont.

1. RAM blocks to implement in-chip data storage,

2. clock management blocks to synthesize numerous clock signals,

3. DSP modules to implement blocks used in digital signal

processing algorithms such as digital filters, high-speed serial
transceivers to support a high-speed I/O, and

4. a hardware-CPU or hardware-PowerPC cores

FPGA architecture: Cont.

Configuration memory:

•Upon configuration memory, FPGAs can be categorised into the

following: [page 34-35]
a) antifuse-based FPGAs .

b) SRAM-based FPGAs.

c) SRAM-based FPGAs with integrated Flash.

d) Flash-based FPGAs.
 FPGA architecture: Cont.

• FPGA are pre-fabricated silicone chip that can be electrically

programmed using build-in logical elements and programmable
connections to become any design of digital system,

• it can be re-configured when it is needed.

• The unneeded for physical fabrication make marketing design

using FPGA is easier than other hardware implementation
methods.
 FPGA architecture: Cont.
• In the last two decades, these devices have been changed and
improved dramatically and Altera and Xilinx offer many new
FPGA families with better performance, power efficiency and
cost.

Back
CAD flow Cont.

• Design Entry:
– using graphical CAD programme.
– Using hardware description languages like VHDL and
Verilog.
– DSP builder and MATLAB
• Synthesis:
– produce the intermediate representation of the hardware
design called netlist,
– the contents of netlist is independent on the specifics of the
FPGA
CAD flow Cont.
• Functional simulation:
– is performed, where the functional correctness of the
synthesised circuit as it is being designed is verified in this
stage.
– simulates the behaviour of the desired circuit without timing
information, it does not take into account the timing
properties of the logical blocks and inter-connection-wires
inside the FPGA chip, they are assumed ideal and therefore
the signal propagates through the circuit without
propagation delay.
– takes much less time than timing simulation
 CAD flow Cont.
• Fitting :
• consists of four phases:
1. Translation phase: the EDIF netlist is converted to a FPGA’s manufacturer
netlist format
2. Map phase: they are mapped into available resources in the actual selected
FPGA chip such as logical-blocks, flip-flops, RAMs, and LUTs
3. Placement phase: placement of the resources like logical-blocks defined in
the incoming netlists from mapping phase is determined into the resources in
the actual chosen FPGA chip.
4. Routing phase : the essential routing wires in the actual chip required to
establish a connection between these particular resources are selected.
 CAD flow Cont.

• Fitting Cont. :

• Placement and routing phases are considered the most important

and time consuming phases in fitting task.
• At the end of this task, a generation of a programming file is created
and stored in a bitstream format.
 CAD flow Cont.
• Timing analysis:
1. the timing properties of the logical blocks and inter-connection-
wires inside the FPGA chip are taken into account.
2. This task is considered as the closet emulation to actually
implementation of the desired circuit into the selected FPGA
device by providing the behaviour of the desired circuit when it is
actually downloaded onto the chosen chip.
3. Thus, it allows the designer to verify that behaves, functional
requirements, and timing requirements of the implemented
circuits meets the expected one and solve the problems when it
happened before the actually implementation.
CAD flow Cont.
• Programming and Configuration:
• The bitstream file is loaded into the chosen FPGA device.
• Thus, the configuration switches inside the chosen FPGA -which
is responsible for the configuration logical-blocks and
establishing the required inter-connect wiring connections- are
programed.
• Therefore, the desired circuit is implemented into a physical
chosen FPGA chip.
• Because of that, the execution and testing of a desired hardware
design is provided by the FPGA chip at the end of this task.
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