DLD Exp05

Digital Logic Design Lab (0630212)
Eng.Hassan S. Migdadi ,
Lab 05 : Week 20-April-2014
Do Step 1,2,3, and 4 only .
Experiment Sequential Circuits

6 PART B: COUNTERS
Objectives
-To design a ripple counter using JK flip flop.

-To connect a pre-settable counter and observe its operation.
-To create different counter module by decoding outputs and loading preset inputs.
Introduction
A counter is a circuit consisting of a number of Flip Flop and gates

working together to count the number of clock pulses applied to its input. Such
counters are used in digital clocks, frequency counters, digital voltmeters,
digital computers, and numerous other applications. There are numerous
types of counters, and we cannot look at theme in this experiment. The
basic binary counter is probably the simplest to construct and form the
basis for more advanced types of counters. In this experiment, we look at
some of the counter circuits found most often and give you an opportunity to
connect and observe them.
Ripple Counter(Asynchronous)
A ripple counter is a serial counter. The clock input is applied to only the first of
the series of the Flip Flop. Clock pulses for the other Flip Flop come from the
preceding Flip Flop.Thus, the clock pulse ―ripple‖ through the circuit in a series
fashion. Such circuit is also called asynchronous since the only pulse required
for the operation is the clock pulse.
The JK Flip Flop have the J and K inputs both tied high, which allows them
to toggle with each input pulse. Fig 7-1 shows a 4-bit ripple
counter.
8|Page
Fig. 7.1 : Logic diagram for a 4-bit (mod16) ripple counter.
Synchronous Counters
The synchronous counter has the limitation of the time lag in triggering all the
Flip Flop. To cure this problem, parallel counters can be used. The logic
diagram for a 3-bit parallel counter is shown in fig 7-2. Note that all CLK
inputs are tied directly to input clock. They are wired in parallel. Note that
also the use of the AND gate at the output of Flip Flop
2 which will either hold Flip Flop 3(AND=0), or toggle Flip Flop
3(AND=1).
Fig 7.2
9|Page
UP DOWN IC Counter : The 74193
The 74193 is a synchronous up-down 4-bit binary counter. It has a master
reset (CLR), and it can be reset to any desired count with the parallel load
inputs. Basically, it functions like any binary counter, except that is has two clock
inputs, one for UP counting , and the other for DOWN counting.
The logic symbol for the 74193 is shown in fig 7-3 (examine the data
sheet).LOAD is a control input to load data into pins A, B,C and D.
Figure 7.3
Pin CLR is the master reset, and it is normally held below (a high level on CLR
will reset all FF).
CO and BO are outputs to be used to drive the following 74193’s and we shall
simply leave them open.
The clock inputs are UP and DOWN. Placing the clock on UP will cause the counter
to count UP, and placing the clock on DOWN will cause the counter to count
DOWN. Note that the clock should be connected to either UP or DOWN, but not
both, and the unused inputs should be held
HIGH. The outputs of the counter are QA,QB,QC and QD .
Components needed:
1-74LS00 Quad NAND Gate TTL IC

2-74LS76 Dual JK Flip Flop
1-74LS93 4 bit binary counter
1-74LS193 4 bit UP-DOWN counter
1- Oscilloscope
10 | P a g e
Procedure
1) Construct the Ripple counter shown in fig 7.1. Clear all output FF by giving
a negative clock pulses to the clear inputs, and apply the clock of a one shot
actuated by the push button. Repeat that for 17 clock pulses. Record the output
QA,QB,QC and QD of the counter in table 1 below
(MSB = QD ; LSB = QA )
Draw the timing diagram of the above circuit.

CLK QC QD QB QA CLK QD QC QB QA
Pulse Pulse
1 10
2 11
3 12
4 13
5 14
6 15
7 16
8 17
9 18
74 193 Table 1
Step 42) Use the 74LS93 counter to implement a counter counts from m to n , where m and n as following :
a) A modulo 16 counter; m = 0 , n = 10 hint :
b) A decade counter m = 4 , n = 15 you need to use some gates such
as AND gate and OR gate.
c) m = 4 , n = 10
Step 13) Make these connections to the counter of fig 7.3
• Pin 15,1,10 and 9 (preset data inputs ) Open

• Pins 12 and 13 (CO and BO)Open
• Pins 3,2,6 and 7 (outputs ) to LED’s
• Pin 11 (LOAD) to +Vcc
• Pin 16 (+Vcc) to +Vcc
• Pin 14 (CLR) to ground
• Pin 8 (GND) to ground
11 | P a g e
Step 24) For the count-up mode, connect pin 4 (DOWN) to +Vcc, and apply the clock
to pin 5(UP). Record carefully the 4 output waveforms with respect to
the clock.
Step 35) For the count-down mode, connect pin 5(UP) to +Vcc , and apply the clock
to pin 4(DOWN). Record the resulting output waveforms.
12 | P a g e
74LS76 Dual JK Flip Flop
74LS193 4 bit UP-DOWN counter
17 | P a g e
74LS93 4 bit binary counter
74LS95 4 bit parallel access shift register
18 | P a g e

DLD Exp05

Uploaded by

Copyright:

Available Formats

DLD Exp05

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

DLD Exp05

Uploaded by

Copyright:

Available Formats

Digital Logic Design Lab (0630212)

Experiment Sequential Circuits

-To design a ripple counter using JK flip flop.

A counter is a circuit consisting of a number of Flip Flop and gates

1-74LS00 Quad NAND Gate TTL IC

Draw the timing diagram of the above circuit.

• Pin 15,1,10 and 9 (preset data inputs ) Open

74LS193 4 bit UP-DOWN counter

74LS95 4 bit parallel access shift register

You might also like