MOD-5 Counter and Truth Table

Then we can use combinational logic decoding circuits around a basic counter, either synchronous
or asynchronous to produce any type of MOD Counter we require as each of the counters unique
output states can be decoded to reset the counter at the desired count.

In our simple example above, we have used a 3-input AND gate to decode the 110 state, but the
first time that QB and QC are both at logic 1 is is when the count reaches six, so a 2-input AND
gate connected to QB and QC could be used without the complication of the third input and the
inverter.

However, one of the disadvantages of using asynchronous counters for producing a MOD counter
of a desired count is that undesired effects called “glitches” can occur when the counter reaches
its reset condition. During this brief time the outputs of the counter may take on an incorrect value,
so it is sometimes better to use synchronous counters as modulo-m counters as all the flip-flops
are clocked by the same clock signal so change state at the same time.

Modulus 10 Counter

A good example of a modulo-m counter circuit which uses external combinational circuits to
produce a counter with a modulus of 10 is the Decade Counter. Decade (divide-by-10) counters
such as the TTL 74LS90, have 10 states in its counting sequence making it suitable for human
interfacing where a digital display is required.

The decade counter has four outputs producing a 4-bit binary number and by using external AND
and OR gates we can detect the occurrence of the 9th counting state to reset the counter back to
zero. As with other mod counters, it receives an input clock pulse, one by one, and counts up from
0 to 9 repeatedly.

Once it reaches the count 9 (1001 in binary), the counter goes back to 0000 instead of continuing
on to 1010. The basic circuit of a decade counter can be made from JK flip-flops (TTL 74LS73)
that switch state on the negative trailing-edge of the clock signal as shown.

MOD-10 Decade Counter

MOD Counter Summary

MOD Counters that binary counters are sequential circuits that generate binary sequences of bits
as a result of a clock signal and the state of a binary counter is determined by the specific
combination formed by all the counters outputs together.
The number of different output states a counter can produce is called the modulo or modulus of
the counter. The Modulus (or MOD-number) of a counter is the total number of unique states it
passes through in one complete counting cycle with a mod-n counter being described also as a
divide-by-n counter.

The modulus of a counter is given as: 2n where n = number of flip-flops. So a 3 flip-flop counter
will have a maximum count of 23 = 8 counting states and would be called a MOD-8 counter. The
maximum binary number that can be counted by the counter is 2n–1 giving a maximum count of
(111)2 = 23–1 = 710. Then the counter counts from 0 to 7.

Common MOD counters include those with MOD numbers of 2, 4, 8 and 16 and with the use of
external combinational circuits can be configured to count to any predetermined value other than
one with a maximum 2n modulus. In general, any arrangement of a “m” number of flip-flops can
be used to construct any MOD counter.

A common modulus for counters with truncated sequences is ten (1010), called MOD-10. A
counter with ten states in its sequence is known as a decade counter. Decade counters are useful
for interfacing to digital displays. Other MOD counters include the MOD-6 or MOD-12 counter
which have applications in digital clocks to display the time of day.

SYNCHRONOUS COUNTERS:

The result of this is that the Asynchronous counter suffers from what is known as “Propagation
Delay” in which the timing signal is delayed a fraction through each flip-flop.

However, with the Synchronous Counter, the external clock signal is connected to the clock input
of EVERY individual flip-flop within the counter so that all of the flip-flops are clocked together
simultaneously (in parallel) at the same time giving a fixed time relationship. In other words,
changes in the output occur in “synchronisation” with the clock signal.

The result of this synchronisation is that all the individual output bits changing state at exactly the
same time in response to the common clock signal with no ripple effect and therefore, no
propagation delay.

Binary 4-bit Synchronous Up Counter

It can be seen above, that the external clock pulses (pulses to be counted) are fed directly to each
of the J-K flip-flops in the counter chain and that both the J and K inputs are all tied together in
toggle mode, but only in the first flip-flop, flip-flop FFA (LSB) are they connected HIGH, logic
“1” allowing the flip-flop to toggle on every clock pulse. Then the synchronous counter follows a
predetermined sequence of states in response to the common clock signal, advancing one state for
each pulse.

The J and K inputs of flip-flop FFB are connected directly to the output QA of flip-flop FFA, but
the J and K inputs of flip-flops FFC and FFD are driven from separate AND gates which are also
supplied with signals from the input and output of the previous stage. These additional AND gates
generate the required logic for the JK inputs of the next stage.

If we enable each JK flip-flop to toggle based on whether or not all preceding flip-flop outputs (Q)
are “HIGH” we can obtain the same counting sequence as with the asynchronous circuit but
without the ripple effect, since each flip-flop in this circuit will be clocked at exactly the same
time.

Then as there is no inherent propagation delay in synchronous counters, because all the counter
stages are triggered in parallel at the same time, the maximum operating frequency of this type of
frequency counter is much higher than that for a similar asynchronous counter circuit.

4-bit Synchronous Counter Waveform Timing Diagram

Because this 4-bit synchronous counter counts sequentially on every clock pulse the resulting
outputs count upwards from 0 ( 0000 ) to 15 ( 1111 ). Therefore, this type of counter is also known
as a 4-bit Synchronous Up Counter.

However, we can easily construct a 4-bit Synchronous Down Counter by connecting

the AND gates to the Q output of the flip-flops as shown to produce a waveform timing diagram
the reverse of the above. Here the counter starts with all of its outputs HIGH ( 1111 ) and it counts
down on the application of each clock pulse to zero, ( 0000 ) before repeating again.

COUNT QD QC QB QA

0 0 0 0 0

1 0 0 0 1

2 0 0 1 0
 3 0 0 1 0

4 0 1 0 0

5 0 1 0 1

Binary 4-bit Synchronous Down Counter

As synchronous counters are formed by connecting flip-flops together and any number of flip-
flops can be connected or “cascaded” together to form a “divide-by-n” binary counter, the
modulo’s or “MOD” number still applies as it does for asynchronous counters so a Decade counter
or BCD counter with counts from 0 to 2n-1 can be built along with truncated sequences. All we
need to increase the MOD count of an up or down synchronous counter is an additional flip-flop
and AND gate across it.

Decade 4-bit Synchronous Counter

A 4-bit decade synchronous counter can also be built using synchronous binary counters to
produce a count sequence from 0 to 9. A standard binary counter can be converted to a decade
(decimal 10) counter with the aid of some additional logic to implement the desired state sequence.
After reaching the count of “1001”, the counter recycles back to “0000”. We now have a decade
or Modulo-10 counter.
Decade 4-bit Synchronous Counter

The additional AND gates detect when the counting sequence reaches “1001”, (Binary 10) and
causes flip-flop FF3 to toggle on the next clock pulse. Flip-flop FF0 toggles on every clock pulse.
Thus, the count is reset and starts over again at “0000” producing a synchronous decade counter.

We could quite easily re-arrange the additional AND gates in the above counter circuit to produce
other count numbers such as a Mod-12 counter which counts 12 states from”0000″ to “1011” (0
to 11) and then repeats making them suitable for clocks, etc.

Triggering A Synchronous Counter

Synchronous Counters use edge-triggered flip-flops that change states on either the “positive-
edge” (rising edge) or the “negative-edge” (falling edge) of the clock pulse on the control input
resulting in one single count when the clock input changes state.

Generally, synchronous counters count on the rising-edge which is the low to high transition of
the clock signal and asynchronous ripple counters count on the falling-edge which is the high to
low transition of the clock signal.
It may seem unusual that ripple counters use the falling-edge of the clock cycle to change state,
but this makes it easier to link counters together because the most significant bit (MSB) of one
counter can drive the clock input of the next.

This works because the next bit must change state when the previous bit changes from high to low
– the point at which a carry must occur to the next bit. Synchronous counters usually have a carry-
out and a carry-in pin for linking counters together without introducing any propagation delays.

Johnson Ring Counter

The Johnson Ring Counter consists of a number of counters connected together with the output
fed back to the input

In the previous Shift Register tutorial we saw that if we apply a serial data signal to the input of
a Serial-in to Serial-out Shift Register, the same sequence of data will exit from the last flip flip in
the register chain.

This serial movement of data through the resister occurs after a preset number of clock cycles
thereby allowing the SISO register to act as a sort of time delay circuit to the original input data
signal.

But what if we were to connect the output of this shift register back to its input so that the output
from the last flip-flop, QD becomes the input of the first flip-flop, QA. We would then have a closed
loop circuit that “recirculates” the same bit of DATA around a continuous loop for every state of
its sequence, and this is the principal operation of a Ring Counter.
Then by looping the output back to the input, (feedback) we can convert a standard shift register
circuit into a ring counter. Consider the circuit below.

4-bit Ring Counter

The synchronous Ring Counter example above, is preset so that exactly one data bit in the register
is set to logic “1” with all the other bits reset to “0”. To achieve this, a “CLEAR” signal is firstly
applied to all the flip-flops together in order to “RESET” their outputs to a logic “0” level and then
a “PRESET” pulse is applied to the input of the first flip-flop ( FFA ) before the clock pulses are
applied. This then places a single logic “1” value into the circuit of the ring counter.

So on each successive clock pulse, the counter circulates the same data bit between the four flip-
flops over and over again around the “ring” every fourth clock cycle. But in order to cycle the data
correctly around the counter we must first “load” the counter with a suitable data pattern as all
logic “0’s” or all logic “1’s” outputted at each clock cycle would make the ring counter invalid.

This type of data movement is called “rotation”, and like the previous shift register, the effect of
the movement of the data bit from left to right through a ring counter can be presented graphically
as follows along with its timing diagram:

Rotational Movement of a Ring Counter

Since the ring counter example shown above has four distinct states, it is also known as a “modulo-
4” or “mod-4” counter with each flip-flop output having a frequency value equal to one-fourth or
a quarter (1/4) that of the main clock frequency.

The “MODULO” or “MODULUS” of a counter is the number of states the counter counts or
sequences through before repeating itself and a ring counter can be made to output any modulo
number. A “mod-n” ring counter will require “n” number of flip-flops connected together to
circulate a single data bit providing “n” different output states.
For example, a mod-8 ring counter requires eight flip-flops and a mod-16 ring counter would
require sixteen flip-flops. However, as in our example above, only four of the possible sixteen
states are used, making ring counters very inefficient in terms of their output state usage.