Syllabus

Unit 2: MOSFET amplifiers:


Current mirrors: Basic current mirror, Cascode current mirror

Single-ended amplifiers:

CS amplifier – with resistive load, diode connected load, current
source load, triode load, source degeneration

CG and CD amplifiers, Cascode amplifier
 Current Mirror
Basic Current Mirror:

How to bias MOSFET to act as stable current source?

Consider a simple resistive biasing in Fig. 5.2.

Assume M1 is in saturation. We can write,

Expression reveals PVT dependence of Iout.

Overdrive voltage is a function of VDD, Vth – 50 to 100 mV (vary from wafer to wafer)

μn and and Vth are temperature dependent.

Iout is poorly defined.

Vgs is precisely defined, drain current is not. Other methods of MOSFET biasing needed.
 Current Mirror
Basic Current Mirror:
Current source design based on copying current from a reference (precisely defined
current source).

A relatively complex circuit—sometimes requiring external adjustments—is used to

generate a stable reference current, IREF.

Reference current is cloned to create many current sources in the system.

Copying operation is studied here.

 Current Mirror
Basic Current Mirror:
In Fig. 5.4, how to guarantee Iout = Iref?

For MOSFET,

Two identical MOS devices that have equal gate-source voltages and operate in saturation
carry equal currents.
 Current Mirror
Basic Current Mirror:
The structure consisting of M1 and M2 is current mirror.

In general transistor need not be identical.

Neglecting channel-length modulation,

Topology allows precise copying of the current with no dependence on process and
temperature.

Translation from IREF to Iout merely involves the ratio of device dimensions. Can be
controlled with reasonable accuracy.
 Current Mirror
Basic Current Mirror:
The cause-and-effect relationships:

generate a VGS (effect) from IREF (cause).

A MOSFET can perform this function only if it is configured as a diode while carrying a
current of IREF

A transistor must sense and generate

(Vgs is cause, IREF is effect.)

Fig. 5.6 does not copy current. Vb is not caused by IREF.

Iout does not track IREF.
 Current Mirror
Basic Current Mirror:
Find the drain current of M4 if all of the transistors are in saturation.
 Current Mirror
Basic Current Mirror: Sizing issues
We wish to copy a reference current, IREF , and generate 2IREF

Begin with a width of WREF for the diode-connected reference transistor.

Choose 2WREF for the current source. But, direct scaling of the width faces difficulties.

The “corners” of the gate are poorly defined, if the drawn W is doubled.

The actual width does not exactly double.

Employ a “unit” transistor and

create copies by repeating such a device
(Fig. 5.9(c))
 Current Mirror
Basic Current Mirror: Sizing issues
Generate a current equal to IREF/2 from IREF.

The diode-connected device itself must consist of two units, each carrying IREF/2.

In Fig. 5.10(a), each unit has a width of W0 (and the same length).

This approach requires large number of transistors if many different currents must be
generated.

Figure 5.10 Current mirrors providing IREF /2

from IREF by (a) same-width device
 Current Mirror
Basic Current Mirror: Sizing issues
It is possible to reduce the complexity by scaling the lengths.

Double the equivalent length by placing two unit transistors in series.

Figure 5.10 Current mirrors providing IREF /2

from IREF by (a) series transistor
 Current Mirror
Current mirrors can process signals as well:

If IREF increases by ΔI, then Iout increases by

The circuit amplifies the small-signal current if

Calculate the small-signal voltage gain of the circuit:

 Current Mirror
Chennel length modulation:

The actual length of the channel gradually decreases as the potential difference between
the gate and the drain decreases.

L is the channel length. After pinch-off, the channel length is L’.

The drain current is

L’ is a function of VDS. L’ = L – ΔL.

Assuming a first-order relationship

between ΔL/L and VDS,
 Current Mirror
Chennel length modulation:

In saturation,

λ is the “channel-length modulation coefficient.”

This phenomenon results in a nonzero slope in the ID/VDS characteristic.

A nonideal current source between D and S in saturation.

The parameter λ represents the relative variation in length for a given increment in VDS.
Thus, for longer channels, λ is smaller.
 Current Mirror
Cascode current mirrors:

Basic current mirror discussion ignored channel length modulation.

This effect produces significant error in copying currents.

For the current mirror in (b), we can write

VDS1 = VGS1 = VGS2

VDS2 may not equal VGS2 because of the circuitry fed by M2.
 Current Mirror
Cascode current mirrors:

To suppress the effect of channel-length modulation:

(1) force VDS2 to be equal to VDS1.

(2) force VDS1 to be equal to VDS2.

First approach:

Ensure that VDS2 in Fig. 5.5(b) is both constant and equal to VDS1.
 Current Mirror
Cascode current mirrors: First approach

A cascode device can shield a current source, thereby reducing the voltage variations
across it.

The analog circuit may allow VP to vary substantially. VY remains relatively constant.

To ensure VDS2 = VDS1, generate Vb as

Vb can be established by two diode-connected devices in series

 Current Mirror
Cascode current mirrors: First approach

Vb can be established by two diode-connected devices in series

Attach the Vb generator of (b) to the cascode current source as shown in (c).
 Current Mirror
Cascode current mirrors: First approach

Sketch VX and VY as a function of IREF. If IREF requires 0.5 V to operate as a current source,
what is its maximum value?

M2 and M3 are properly ratioed with respect to M1 and M0.

Max value of IREF.

 Current Mirror
Cascode current mirrors: First approach

(c) operates as current source with high output impedance and accurate value.

But, it consumes large headroom.

Minimum allowable voltage at node P is

Which is two overdrive voltages plus one threshold voltage.

Compare the value with Vb in (a)

The minimum allowable voltage at P

is merely two overdrive voltages.

(c) “wastes” one threshold voltage in the headroom as

VDS2 could be as low as VGS2 − VTH while maintaining M2 in
saturation.
 Current Mirror
Cascode current mirrors: First approach

(a) Vb is chosen to allow the lowest possible value of VP

But, the output current does not accurately track IREF because M1 and M2 sustain unequal
drain-source voltages.

(b) A higher accuracy is achieved, but the minimum level at P is higher by one threshold
voltage.

Figure 5.14 (a) Cascode current source with minimum headroom voltage;
(b) headroom consumed by a cascode mirror.
 Current Mirror
Cascode current mirrors: Second approach

Force VDS1 to be equal to VDS2 in this approach. (to avoid the V TH penalty in the voltage
headroom)

In (a), VTH headroom consumption is eliminated only if Vb = VGS3 + (VGS2 − VTH2)

We have to ensure VDS1 = VDS2 (= VGS2 − VTH2)

M1 is a diode-connected device, VDS1 = VGS1. (appears impossible)

Sol:

Create a deliberate voltage difference between

the gate and drain of M1 by a means of a resistor.
 Current Mirror
Cascode current mirrors: Second approach

Choose R1 IREF ≈ VTH1 and Vb = VGS3 + (VGS1 − VTH1)

Now, VDS1 = VGS1 − R1 IREF ≈ VGS1 − VTH1 ≈ Vb − VGS3 = VDS2

Circuit in (a) entails two issues:

1. Difficult to guarantee that R1 IREF ≈ VTH1 in PVT

(R1 and VTH1 vary differently)

2. The generation of Vb = VGS3 + (VGS1 − VTH1)

is not straightforward.

Figure 5.16 (a) Use of IR drop to improve accuracy of current mirror,

(b) generation of Vb , and (c) alternative generation of V b.
 Current Mirror
Cascode current mirrors: Second approach

Sol to 2. The generation of Vb = VGS3 + (VGS1 − VTH1) is not straightforward.

Add one gate-source voltage to overdrive ==> begin with diode connected device.

For (b), Vb = VGS5 +R6 I6.

Choose I6 and dimensions of M5 so that VGS5 = VGS3

R6 I6 = VGS1 − VTH1 = VGS1 − R1 IREF ==> R6 I6 + R1 IREF = VGS1

This is difficult to meet. I R do not tract MOS gate-source voltage.

Value of R falls with temperature, VGS rise with temperature.

Figure 5.16 (a) Use of IR drop to improve accuracy of current mirror,
(b) generation of Vb , and (c) alternative generation of V b.
 Current Mirror
Cascode current mirrors: Second approach

Sol to 2. The generation of Vb = VGS3 + (VGS1 − VTH1) is not straightforward.

In (c), M5 establishes the VGS . M6 and R6 establish the overdrive.

Select I6 and the device parameters such that:

It is now possible to ensure that VGS6 and VGS1 track each other.

R1 IREF and R6 I6 track each other.

For this, choose:

I6 = IREF , R6 = R1, and (W/L)6 = (W/L)1.

Figure 5.16 (c) alternative generation of V b.
 Current Mirror
Cascode current mirrors: Second approach

Sol to 1. Difficult to guarantee that R1 IREF ≈ VTH1 in PVT (R1 and VTH1 vary differently)

Develop a topology to force VDS of the diode-connected device to be equal to the VDS of the
current source transistor.

The level shift between the gate and drain voltages need not be created by a resistor.

Tie the output node of a cascode topology to its input (a).

Vb can be chosen to place M1 at the edge of saturation.

Figure 5.18 Modification of cascode mirror for low-voltage

operation.
 Current Mirror
Cascode current mirrors: Second approach

Sol to 1. Difficult to guarantee that R1 IREF ≈ VTH1 in PVT (R1 and VTH1 vary differently)

Connect the branch in (a) to the main cascode current source in (b)

VDS1 is forced to be equal to VDS2 if VGS0 = VGS3

This is called “low-voltage cascode”.

Figure 5.18 Modification of cascode mirror for low-voltage

operation.
 Single ended amplifier
Common-Source Stage with Resistive Load

A MOSFET converts changes in its gate-source voltage to a small-signal drain current.

Drain current pass through a resistor to generate an output voltage (a).

The input impedance of the circuit is very high at low frequencies.

If the input voltage increases from zero, M1 is off and Vout = VDD

As Vin approaches VTH, M1 begins to turn on.

Current is drawn from RD, Vout lowered.

 Single ended amplifier
Common-Source Stage with Resistive Load

Transistor M1 turns on and we have

Further increase in Vin, Vout drops more, and the transistor continues to operate in
saturation.

Until Vin exceeds Vout by VTH, we have

Vin1 − VTH and Vout can be calculated.

For Vin > Vin1, M1 is in the triode region:

 Single ended amplifier
Common-Source Stage with Resistive Load

If Vin is high enough to drive M1 into the deep triode region,

From the equivalent circuit in (c),

The transconductance drops in the triode region, ensure

Ensure that the current operates to the left of point A in (b)

The small-signal gain is

 Single ended amplifier
Common-Source Stage with Resistive Load

M1 converts an input voltage change ΔVin to a drain current change gmΔVin

The output voltage change is

The small-signal model of (d) yields

The equation , predicts certain effects if the circuit senses a large signal
swing.

Since , the gain of the circuit changes substantially if the

signal is large.

The dependence of the gain upon the signal level leads

to nonlinearity, needs to be minimized.
 Single ended amplifier
Common-Source Stage with Resistive Load

Maximize the voltage gain of a common-source stage:

VRD denotes the voltage drop across RD

The magnitude of Av can be increased by increasing W/L or VRD or decreasing ID

Trade-offs from this:

1. A larger device size leads to greater device capacitances.

2. A higher VRD limits the maximum voltage swings.

If , M 1 is at the edge of the triode region, allowing only very small

swings at the output (and input).
 Single ended amplifier
Common-Source Stage with Resistive Load

If VRD remains constant and ID is reduced, then RD must increase.

This leads to a greater time constant at the output node.

For large values of RD, the effect of channel-length modulation in M1 becomes significant.

Recognize that
 Single ended amplifier
Common-Source Stage with Resistive Load

New small signal model is given in figure including the transistor output resistance.
 Single ended amplifier
Common-Source Stage with Resistive Load: Example

Assuming that M1 in Fig. 3.8 is biased in saturation, calculate the small-signal voltage gain of the
circuit.

Since I1 introduces an infinite impedance, the gain is limited by the output resistance of M 1

The “intrinsic gain” of a transistor

This quantity represents the maximum voltage gain that can be achieved using a single device.

We usually assume

KCL requires that ID1 = I1

How can Vin change the current of M1 if I1 is constant?
 Single ended amplifier
Common-Source Stage with Resistive Load: Example

How can Vin change the current of M1 if I1 is constant?

Vin appears in the square term and Vout in the linear term.

Vin increases, Vout must decrease such that the product remains constant.

Conclusion:

To maximize the voltage gain, we must maximize the (small-signal) load impedance.

Can we replace the load with an open circuit? No.

The circuit still needs a path from V DD to ground for the bias current of M1.
 Single ended amplifier
CS Stage with Diode-Connected Load:

It is difficult to fabricate resistors with tightly-controlled values or a reasonable physical

size.

It is desirable to replace RD with a MOS transistor.

A MOSFET can operate as a small-signal resistor if its gate and drain are shorted (a).
Called a “diode-connected” device.

This configuration exhibits small-signal behavior similar to that of two-terminal resistor.

The transistor is always in saturation

because the drain and the gate have
the same potential.
 Single ended amplifier
CS Stage with Diode-Connected Load:

The small-signal equivalent shown in (b) to obtain the impedance of the device.

The impedance of the diode is equal to

If body effect exists, we can use the circuit in 3.11 (a)-(b) to write

Figure 3.11 (a) Arrangement for measuring the equivalent resistance

of a diode-connected MOSFET; (b) small-signal equivalent circuit.
 Single ended amplifier
CS Stage with Diode-Connected Load:

If body effect exists, we can use the circuit in 3.11 (a)-(b) to write

We get

In general,

The impedance seen at the source of M1 is lower

if body effect is included.

Figure 3.11 (a) Arrangement for measuring the equivalent resistance

of a diode-connected MOSFET; (b) small-signal equivalent circuit.
 Single ended amplifier
CS Stage with Diode-Connected Load:

With negligible channel-length modulation, we get

Expressing gm1 and gm2 in terms of device dimensions and bias currents

Since

If the variation of η with the output voltage is neglected,

the gain is independent of the bias currents and voltages
(so long as M1 stays in saturation).

Figure 3.13 CS stage with

Input output relationship remains relatively linear. diode-connected load.
 Single ended amplifier
CS Stage with Diode-Connected Load: Large-signal analysis

Neglecting channel-length modulation for simplicity

If the variation of VTH2 with Vout is small, the circuit exhibits a linear input-output
characteristic.

The squaring function performed by M1 (from the input voltage to its drain current).

The square root function performed by M2 (from its drain current to its overdrive).

This act as
 Single ended amplifier
CS Stage with Diode-Connected Load:

The small-signal gain can also be computed by differentiating both sides with respect to
Vin:

Upon application of the chain rule

 Single ended amplifier
CS Stage with Diode-Connected Load:

As I1 decreases, so does the overdrive of M2.

For small I1, VGS2 ≈ VTH2 and Vout ≈ VDD − VTH2.

The subthreshold conduction in M2 eventually brings Vout to VDD if ID approaches zero.

The finite capacitance at the output node slows down the change from VDD − VTH2
to VDD.

In switching circuits:

Vout remains around VDD − VTH2 when I1 falls to small

values.
 Single ended amplifier
CS Stage with Diode-Connected Load:

The output voltage equals VDD − VTH2 if Vin < VTH1.

For Vin > VTH1, Vout follows an approximately straight line.

As Vin exceeds Vout + VTH1 (beyond point A), M 1 enters the triode region, and the
characteristic becomes nonlinear.

Diode connected load can be implemented in PMOS.

Small-signal voltage gain equal is

Figure 3.13 CS stage with

diode-connected load.
 Single ended amplifier
CS Stage with Diode-Connected Load:

The gain of a common-source stage with diode-connected load is a relatively weak

function of the device dimensions.

To achieve a gain of 5,

A high gain requires a “strong” input device and a “weak” load device.

==> disproportionately wide or long transistors (and hence a large input or load
capacitance)
 Single ended amplifier
CS Stage with Diode-Connected Load:

High gain also reduces voltage swing.

The overdrive voltage of M2 must be 5 times that of M1.

With VGS1 − VTH1 = 100 mV and |VTH2| = 0.3 V, we have |VGS2| = 0.8 V.

==>Severely limiting the output swing.

 Single ended amplifier
CS Stage with Diode-Connected Load:

If we write

The voltage gain of the circuit is

Av is inversely proportional to
 Single ended amplifier
CS Stage with Diode-Connected Load:

M1 is biased in saturation with a drain current equal to I1. The current source IS = 0.75I1
is added to the circuit. How is (3.37) modified for this case?

|ID2| = I1/4

For a gain of 5, the overdrive of M2 need be only 1.25 times that of M1.
For a given overdrive voltage, this circuit achieves a gain four times.
 Single ended amplifier
CS Stage with Current-Source Load:

A large voltage gain in a single stage suggests we increase RD.

With a resistor or diode-connected load, however, increasing the load resistance translates
to a large dc drop across the load.

Limiting the output voltage swing.

A more practical approach is to replace the load with a device that does not obey Ohm’s
law, a current source.

M1 and M2 both in saturation.

 Single ended amplifier
CS Stage with Current-Source Load:

The total impedance seen at the output node is equal to

The gain is given by

The output impedance and the minimum required |VDS| of M2 are less strongly coupled.
==> does not satisfy Ohm’s law.

The value and voltage drop of a resistor are stongly coupled. ==> satisfies Ohm’s law.

The voltage |VDS2,min| = |VGS2 − VTH2| can be reduced to less than a hundred millivolts by
simply increasing the width of M2.

Longer transistors yield a higher voltage gain.

 Single ended amplifier
CS Stage with Current-Source Load:

Consider M1 and M2 separately.

If L1 is scaled up by a factor of α (> 1), then W1 may need to be scaled proportionally as

well.

For a given drain current,

==> If W1 is not scaled, the overdrive voltage increases, limiting the output voltage swing.

Since scaling up only L 1 lowers gm1.

The intrinsic gain of M 1 can be written as

 Single ended amplifier
CS Stage with Current-Source Load:

Compare the maximum output voltage swings of CS stages with resistive and current-
source loads.

For the resistively-loaded stage [Fig. 3.19(a)], the maximum output voltage is near VDD
(when Vin falls to about VTH1). The minimum is the value that places M1 at the edge of the
triode region, Vin − VTH1.

Max output voltage in (b) is

Smaller swing.

But, can achieve a higher gain if

L1 and L2 are increased.
 Single ended amplifier
CS Stage with Active Load:

The PMOS device serves as a constant current source in figure.

M2 can operate as an amplifying device too. Apply the input signal to the gate of M2 as
well, converting it to an “active” load.

This topology is a CMOS inverter.

Suppose both transistors are in saturation and Vin rises by ΔV0.

Two changes now occur:

(a) ID1 increases, pulling Vout lower.

(b) M2 injects less current into the output node, allowing Vout to drop.
The two changes thus enhance each other, leading to a greater voltage gain.
 Single ended amplifier
CS Stage with Active Load:

As seen in Fig. 3.20(b), the two transistors operate in parallel and collapse into one as
illustrated in Fig. 3.20(c).

It follows that

This circuit exhibits the same output resistance, but a higher transconductance.
 Single ended amplifier
CS Stage with Active Load:

The amplifier of Fig. 3.20(a) must deal with two critical issues.

1. the bias current of the two transistors is a strong function of PVT.

Since VGS1 + |VGS2| = VDD, variations in VDD or the threshold voltages directly translate to
changes in the drain currents.

2. The circuit amplifies supply voltage variations (“supply noise”).

Consider the arrangement depicted in Fig. 3.21.

VB is a bias voltage to place M1 and M2 in saturation.

The small-signal gain from VDD to Vout is given by

About half of the Av found here.
 Single ended amplifier
CS Stage with Triode Load:

A MOS device operating in the deep triode region behaves as a resistor, can serve as the
load in a CS stage.

Such a circuit biases the gate of M2 at a sufficiently low level.

This ensures that the load is in the deep triode region for all output voltage swings.

The voltage gain can be calculated from

 Single ended amplifier
CS Stage with Triode Load:

Drawback of this circuit is the dependence of Ron2 upon

and vary with process and temperature.

Generating a precise value for Vb requires additional complexity.

==> This circuit is difficult to use.

Triode loads, however, consume less voltage headroom than do diode-connected devices.
 Single ended amplifier
CS Stage with Source Degeneration:

The nonlinear dependence of the drain current upon the overdrive voltage introduces
excessive nonlinearity.

Reduce the nonlinearity by softening the device.

Accomplished by placing a “degeneration” resistor in series with the source terminal.

This makes the input device more linear.

As Vin increases, so do ID and the voltage drop across RS.

A fraction of the change in Vin appears across the

resistor rather than as the gate-source overdrive.

This leads to a smoother variation of ID.

 Single ended amplifier
CS Stage with Source Degeneration:

Make the gain equation a weaker function of gm.

==> linear

The nonlinearity of the circuit arises from the nonlinear dependence of ID upon Vin.

Define the equivalent transconductance of the circuit as

Assume that , we get

 Single ended amplifier
CS Stage with Source Degeneration:

Since

The transconductance of M1 is

The small-signal voltage gain is thus equal to

Using KVL in (b), we get

 Single ended amplifier
CS Stage with Source Degeneration:

As RS increases, Gm becomes a weaker function of gm and so the drain current.

The drain current is a “linearized” function of the input voltage.

 Single ended amplifier
CS Stage with Source Degeneration:

Gm in the presence of body effect and channel length modulation.

The current through RS equals Iout.

KCL at node X
 Single ended amplifier
CS Stage with Source Degeneration:

For RS = 0, are given in (a).

For RS = 0, the turn-on behavior is similar to that in (a). At low current levels,

As the overdrive and therefore gm increase, the effect of degeneration, 1 + gm RS, becomes
more significant.

For large values of Vin:

ID is approximately
a linear function of Vin.

Gm approaches 1/RS.
Drain current and transconductance of a CS device (a) without and (b) with source degeneration.
 Single ended amplifier
Source Follower (“common-drain” stage):

To achieve a high voltage gain with limited supply voltage, the load impedance must be as
large as possible in CS amplifier.

If such a stage is to drive a low-impedance load, then a “buffer” must be placed after the
amplifier to drive the load with negligible reduction in gain.

The source follower can operate as a voltage buffer.

(a) Source follower, (b) example of its role as a buffer, and (c) its input-output characteristic.
 Single ended amplifier
Source Follower (“common-drain” stage):

In (a), the source follower senses the signal at the gate, gives a high input impedance, and
drives the load at the source.

The source potential “follow” the gate voltage.

For Vin < VTH, M1 is off and Vout = 0.

As Vin exceeds VTH, M1 turns on in saturation, ID1 flows through RS.

As Vin increases further, Vout follows the input with a

difference (level shift) equal to VGS.
 Single ended amplifier
Source Follower (“common-drain” stage):

The input-output characteristic is

The small-signal gain of the circuit

Since
 Single ended amplifier
Source Follower (“common-drain” stage):

From figure, we have

The voltage gain begins from zero for , monotonically increases.

As the drain current and gm increase, Av approaches

η itself slowly decreases with Vout. Av would eventually become equal to unity.
 Single ended amplifier
Source Follower (“common-drain” stage):

From figure, the drain current of M1 heavily depends on the input dc level.

If Vin changes from 0.7 V to 1 V, ID may increase by a factor of 2, VGS − VTH by sqrt(2).

Even if VTH is relatively constant, the increase in VGS means that Vout (= Vin − VGS) does not
follow Vin, incurring nonlinearity.

To alleviate this issue, the resistor can be replaced by a constant current source.
 Single ended amplifier
Source Follower (“common-drain” stage):

The small-signal output resistance of the circuit in (a). (b) is equivalent circuit.

VX = −Vbs .

Body effect decreases the output resistance of source followers.

VX decreases by _x005F_x0004_ΔV so that the drain current increases.

With no body effect, only the gate-source voltage of M1 would increase by

_x005F_x0004_ΔV.

With body effect, the threshold voltage of the device decreases as well.

- the first term increases and the second decreases.

 Single ended amplifier
Source Follower (“common-drain” stage):

Compare the gain of source followers and common-source stages.

The load can be driven by a source follower with an overall voltage gain of

Gain for CS stage is

If , the source follower exhibits a gain of at most 0.5.

The common-source stage provides a gain close to unity.

Source followers are not necessarily efficient drivers.

 Single ended amplifier
Common-Gate Stage:

A common-gate (CG) stage senses the input at the source and produces the output at the
drain.

The gate is connected to a dc voltage to establish proper operating conditions.

The bias current of M1 flows through the input signal source.

M1 can be biased by a constant current source,

with the signal capacitively coupled to the circuit.

(a) Common-gate stage with direct coupling at input;

(b) CG stage with capacitive coupling at input.
 Single ended amplifier
Common-Gate Stage:

Assume that Vin decreases from a large positive value.

For Vin ≥ Vb − VTH, M1 is off and Vout = VDD.

For lower values of Vin, M1 in saturation,

As Vin decreases, so does Vout , eventually driving M1 into the triode region if

In saturation, output voltage is

 Single ended amplifier
Common-Gate Stage:

In saturation, output voltage is

Small-signal gain is

Since,

The gain is positive.

 Single ended amplifier
Common-Gate Stage:

The impedance seen at the source of M1 is the same as that at

the source of M1 is bottom figure.
 Single ended amplifier
Common-Gate Stage: Voltage Gain with body effects, rO

The current flowing through RS is equal to −Vout /RD, we have

The current through rO is equal to

Substitution for V1, we get

 Single ended amplifier
Common-Gate Stage: Input impedances

Equivalent circuit of (a) in (b) is used to find the impdances.

The current through rO is equal to

Add up the voltages across rO and RD and equate to

The drain impedance is divided by when seen

at the source.
 Single ended amplifier
Common-Gate Stage: Output impedance

The current through RS is equal to IX.

The current flowing through rO

Adding the voltage drops across rO and RS

The output impedance is

 Single ended amplifier
Cascode Stage:

The input signal of a common-gate stage may be a current.

A transistor in a common-source arrangement converts a voltage signal to a current signal.

The cascade of a CS stage and a CG stage is called a “cascode” topology.

M1 generates a small-signal drain current proportional to the small-signal input voltage, Vin

M2 simply routes the current to RD.

M1 the input device and M2 the cascode device.

M1 and M2 carry equal bias and signal currents.

 Single ended amplifier
Cascode Stage:

What happens if the value of Vin or Vb changes by a small amount?

Assume that both transistors are in saturation.

If Vin rises by Δ_x005F_x0004_V , then ID1 increases by gm1 _x005F_x0004_ΔV .

Change in current flows through the impedance seen at X.

The impedance seen at the source of M2 is

VX falls by an amount given by

The change in ID1 also flows through RD producing a drop of

 Single ended amplifier
Cascode Stage:

Consider Vin is fixed and Vb increases by _x005F_x0004_ΔV.

VGS1 is constant, circuit is simplified.

M2 operates as a source follower, it senses an input, _x005F_x0004_ΔV and generates an

output at X.

The small-signal voltage gain of the follower is equal to unity.

VX rises by _x005F_x0004_ΔV.

Vout does not change because ID2 is equal to ID1 .

The voltage gain from Vb to Vout is zero.

 Single ended amplifier
Cascode Stage: The bias conditions of the cascode

For M1 to operate in saturation,

M1 and M2 are both in saturation, M2 operates as a source follower.

VX is determined primarily by Vb.

For M2 to be saturated,

The minimum output level for M1 and M2 in saturation:

The overdrive voltage of M1 plus that of M2.
Addition of M2 to the circuit reduces the output voltage swing
by at least the overdrive voltage of M2.
 Single ended amplifier
Cascode Stage: The large-signal behavior of the cascode stage

Consider Vin goes from zero to VDD.

For , M1 and M2 are off, Vout = VDD.

Vin exceeds VTH1, M1 begins to draw current, and Vout drops.

ID2 increases, VGS2 must increase as well, causing VX to fall.

As Vin assumes sufficiently large values, two effects can occur:

(1) VX drops below Vin by VTH1, forcing M1 into the triode region.
(2) Vout drops below Vb by VTH2, driving M2 into the triode region.
 Single ended amplifier
Cascode Stage: The small-signal characteristics

Assume that both transistors operate in saturation.

The voltage gain is equal to that of a common-source stage, the drain current produced by
the input device must flow through the cascode device.

The voltage gain of this stage is

 Single ended amplifier
Cascode Stage: The small-signal characteristics

The small-signal drain current of M1, gm1 Vin, is divided between RP.

The impedance seen looking into the source of M2 is

The current flowing through M2 is

 Single ended amplifier
Poor Man’s Cascode:

A “minimalist” cascode current source omits the bias voltage necessary for the cascode
device.

M2 in the triode region because:

If M1 and M2 have identical dimensions:

The structure is equivalent to a single transistor having twice the length.

 Single ended amplifier
Shielding Property:

If the output-node voltage is changed by _x005F_x0004_ΔV, the resulting change at

the source of the cascode device is much less.

The cascode transistor “shields” the input device from

voltage variations at the output.

The shielding property of cascodes diminishes if the cascode device enters

the triode region.
 Single ended amplifier
Shielding Property:

Assume that VX decreases from a large positive value.

As VX falls below Vb2 − VTH2, M2 enters the triode region.

M2 requires a greater gate-source overdrive so as to sustain the current drawn by M1.

As VX decreases, VP also drops, so that ID2 remains constant.

Variation of VX is less attenuated as it appears at P.

If VX falls sufficiently, VP goes below Vb1 − VTH1,

driving M1 into the triode region.
 Single ended amplifier
Folded Cascode:

The input device and the cascode device need not be of the same type.

A PMOS-NMOS combination performs the same function as a cascode.

To bias M1 and M2, a current source must be added as in (b).

Note that |ID1| + ID2 is equal to I1 and hence constant.

If Vin becomes more positive, |ID1| decreases.

This forces ID2 to increase and hence Vout to drop.

 Single ended amplifier
Folded Cascode: Large signal behavior

Vin decreases from VDD to zero.

For Vin > VDD − |VTH1|, M1 is off and M2 carries all of I1 giving Vout = VDD − I1 RD.

For Vin < VDD − |VTH1|, M1 turns on in saturation, giving

Vin drops, ID2 decreases further, falling to zero if ID1 = I1.

This occurs at Vin = Vin1 if

 Single ended amplifier
Folded Cascode: Large signal behavior

This occurs at Vin = Vin1 if

Solving for Vin1, we get,

If Vin falls below this level, ID1 tends to be greater than I1.

M1 enters the triode region so as to ensure ID1 = I1.