“Roll No. 42004006 Grou: 2CE4 (Sem-4) wlbjecst | Merb a¢@s§ or LIA Pro, what i Programmable Peripheral Tatevtace? _____ port device The bor!S may be piagrammecl in avariely oP ways — devices. Tntel 82558 iS_one of the widely used peripheral Tnt- =erfacing unit Que:to Explain Intel 285A Tin Configuration ,Taternal.struclate f onde bits, Modes, Bit Set/ReSe} Feature in Detail? — “he Tatel £255 18.0. programmable beri bheral Tnterface i.e PPT 8255 T+ is device Tt contains 3-T/o borts which can be prog- -rammed in different modes These _3-T/o ports can be viewed as three &242 TC's — (or 4418343) with much more additional facilities provided with it: “Fe_program ne function te all these 2=T/o pons, Th Contains o register called as Control Register Ban eee eats i z+o Select go55 10 = *) in dato Transfer from/to goa Otherwise §255 will be in deactive state hese lines are Internally used ae tresseS aS Follows: Ai | Ao | Selected Part: o | 0 Port A a peste. Fort B Hes. 50) Park C pigs es Control Reg.we DCH, \ to 8255 hen £255 iS veset, it clears. Control word Register _ and all borts ave Set ty Input Mode. _~_— Generally RESET (out) of gos iS Connected to RESET of 9055 t e i : =bi 4a send dato. 4o peripheral 4o read dato. fim — beribheral “The Contents are transferred to/from port A. loo \PBo-PBy (Port B bins a +o +): These are R-bit bidive- Some aS PAo-PAF { S.IPCo- PC (Pret C pins 0 to%)* These are g-hit bi-divect- i sional T/o bins ‘These lin: ivi into = Poy= PCF. — +I These 9. Sent jf -Mbber_port_t—(Cuther or Cull and Lower bork — ( Cromer or Ci).Group A Port A PAs PAE > (8 bits) | DsDF A = Control cot . Group A rte K-17) Porkc upper | Data Bus T ~~ (a bits) | Par SUffer | | ] Group B Ja ™ : I PortC Lower <-> Rat ay G i Cains) _| Peer | Ao SRE ee CaS] AT ibeic Dorie! | Group B t/o Reser a) Pe ype 7B 4, cS C8 bits) | 4 Dato. Bus Buffer 2 Read/urrite Contrl teqie 3.1 G: ‘ou A 1 4! Port A and Port B Sul Tork C (a) fae: The & bit baie 2 bi data, bus With Syston Bu: ———_—_ - is Taterna Connvecte. Et 6 }Ly L Ye Lipa, Pe ati Logi Accept tne it father fam | A Control till Contral Ga ports and GB Canitrol twill - 4 Control GB hors ‘Th: r + ii) Th i Ci) To Control the Operation of GA and GB. Operating Modes of 9955 PPL: Tntel $255 has the following three _m ion Mode = Simp\2 Input /outut |! Mode 4 — Strobed Tapub/ outs {Mode 2 — Bidirectional port im = The £265 has two g-bit portS,port A and port B, ond two, 4y bit ports bort CG pber PCy-PCs) & 0; e axe = Pc3). Tn Mo Simb\e Tobut or dutbet pork. Ec be_ either Input or Output port. 2a The Tabut /output Features in mode a ave as Follow: | Outputs ave Latched Tabuts are not latchedH oct Bl from port Gas fae - signals. The ines of pork can be used for 2 a ; imple iF Function lL PGo , P' r ort. 263, Poy, and Pos dan be used to Control bin: aS Ta put or output ort A [TP it Oberat te ne Ded sake as. td ahead Popul oro j J |emaining three Signals from Pa Con be vsed “usth: aaa ers eras Simble Zo or OS hand Shake B eteiieinged ith ah cae 0 i BSR_Control_Word, and it doe. recognized brevio transmitted Control word (Thus, te t/o Oberations of with bi vot olter any | {pas affected by o BSR Contra word. Bore not LBSR Contral_uorel ? | The Control! ord in_the giste, ets orresets one bit ot a time a by 4h following fea: a 1 2.1 Any of 4 i using oo. Sige Instruction bohen Fort 6 a stolus/ contro\ for et by the Bit 1 ata. output bot v hort Aor B ‘ine a ne oan be Seto or_vSBN i oa Mode Generally Set =0 — aan are oit-Bit3 [4oo- Bit4 4o4=BitS 4o- Bite 114 -Bi: H Dy D6 Ds Dy 93 Da Di Do t ToToJofo [a [a [4 Jo] The contrel word will be po00 1110 = oF H 5. Jn gene, |__To Set pit PG4 = 0000 4144 =aEH | _To reset PCy = 000 41102 OEM To Set bit PC3= 0000 0144 = OF \ To-veSet bit Pu3= 0000 o410 = 66HiS Suce -nt comb yomi Se i this fraction { I (tes Ihonere by is either 0 or 4. ADC 0808 /oR09.+ The ADC 008 oy 0809 is an 8-bit A/D Converter usith = channel multiplexer _____________} Tt isa monolithic CMoS device of mationol Semican=| -ductor make The Alp Converler uses sueessive_ofpanination 08 | ithe Conversion Te hnique We[© loo [BA] en Outpol Conrol—| cuk—| Veu—|44 RrePF__ 42. GND — 13 fl Dai 44 “7 Tae aane/ne08 nas efgh Taput_channels, S04 Select — desived Thput channel, it i necessary ty Send 3-brt — | Addyess on A,Band C inbuts 2. The Address af the desived channel is sent to. ynultiplexer a Address inputs through park bins alter ak least SOns iis address mug} be Lackched using. ALE Signal. After another 2-5.48, the Start of Conversion : (S0€) Signal. woust be high then low te start the conve~ — = Sion _p yocess. 4.) To = i = = enab! ing the outhut Sion after Eos is activatei wes. S ese Compensation 1 @nd—| 2 dso Wek. [ VeE—13 44 -—WreP 64) I to—|4¥ pac 43 LL es8 ar SS oRo8 a ai Az—|6 Digi al A3—|+ do = ae g | | i NG No Connection ey ‘ TO — Tnbut pistput pin Signal bin Achg-? Digit Input bitas parallel port to E 4 Vee ig eo at : aSk | 3 We be | Pho Ag 6k ADS lap: rad | Aa cea a = AWW +4 (aR RS Tae. eos —T & 0 Seoete [D 1s [Topo Sy BPR ela Me “<. geset | : © eS f | ovb—w Reset 5 I 8 l PE te t+ = Be 2 [acs ~ ale Slacwes 16 34 atil i From 808 T _ASRE Lt fea 3 X 7 | oe AS a oS 2 Me] ic phe aia y | Fig: “Interfacing of 0805 asith Mic _}[| F | _CS_| chip Select | — “A ey~ “Select the 253 TC tn 2 i i i 1 TBR Bad es an five lun Topst Sigal used to In hed es | is 7 5. ko=Ay (Address Lines): = t “These. are Tnbvt active high addveCounted Counter 4 Counter 2Bus Buffer = pend, stipe icWen write (OR) { Woted Tt receives data fom the System data bus. Read/uaile ingles “The_block_accetts Topuls from the Stem Control bus Maddress bus lused ove As ond Ad from the above S$ StenalS@5_u ibR_are connecied 43. RO and wR deci i i i; berPorm j-€ whether pias uniting dota._+n 3353 or part reading dataci) | Mode a “Tnterrubt on Terminal count —_tin._Mode 4 _Pmgrammable one shot Gi) tiv). Mode 2 Square wave Generator (vi) Mode 5 Hardware “Triggered Strobe39 F* Ag 38 |; As 3t Ay 36> TC SOAR a Ar 3 [<> AL 32\* Ao 3h Nec 30 Do 29K D1 28 KPa 2t D3 26 >Dy 25} > Dacka 24 |->DACKL _|Dack-Dag 23~oDs ts. “ a2ie>De +8Vac | + SVd.c Supply oe | GND | 0 volts [elo | +] |r] = oo] RJ Tele ee Bla fe |B IB IE IS ui cs co 29 $8 PE oFduring the DMA lune cycle Ta Enya mode the line 18 used by CPUtn read Conbel Register cf ~25¢ | Tot (to write): Tnfor mation te 8254. 4, MEMR (Memory Read LeGyho=Aa (Address Lines bidiventional: These ore bidirectional lines In the Master made these Lines e de-bi Ra eB UNeS Corry 4yiSBs o 46-bit. in S i . B Ht mecd, | Au-Az (Address bus ): “These Lines give dristate outputs which carry. by. the 825+. ala (clocks Tnput |: Tt isa. clock Input Signo) 9. Reset (RESET): This _Stgnal_is used tp Reset the DMA Cont- - roller. by diSabling the all_DMA channels ££ ____ i 4o,| READY (ready Signal 2 ue __Tt is an Ackve-hi Hive-high asynchronous Tnbyt_ ____ | signe, whi 28 DMA ready by “Inserking wait Stotes.re Fndicates the present DMA Cycle tn Tine present peripheral device, _______ E is apstB: - AHigh on this_line latches the 2M Rs of the. 2 i i = ae lane ; : Ee Lor Tntegral yaultiple_of ib from the begining z | Jz /DRQS-DROs [DMA Request): 7 - : Jonone of these lines. A high Status of this line _ ——llgenerates DMA Request M 7 St ius. : t f i i: ‘has been Selected for DMA dato Transfer: