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Instruction Cycle in Computer System Architecture - CSE

1. The document describes the fetch-execute cycle of a computer's instruction cycle. It has 4 phases - fetch, decode, execute, and halt. 2. It explains the steps involved in fetching and decoding an instruction from memory. This includes using the program counter and memory address register to retrieve the instruction from memory. 3. It provides a flowchart showing the different paths executed depending on if the instruction is a register reference, memory reference, or input/output instruction.

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Deepak kumar
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193 views4 pages

Instruction Cycle in Computer System Architecture - CSE

1. The document describes the fetch-execute cycle of a computer's instruction cycle. It has 4 phases - fetch, decode, execute, and halt. 2. It explains the steps involved in fetching and decoding an instruction from memory. This includes using the program counter and memory address register to retrieve the instruction from memory. 3. It provides a flowchart showing the different paths executed depending on if the instruction is a register reference, memory reference, or input/output instruction.

Uploaded by

Deepak kumar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Page No....

*****

Iuuo.Zero.Zero..One.zero.ero
Roll No. (In Figures).12.0010.0.6...(in Words).One..
..Six.B.Tech.CSE Einal.Examinatien-2021. Medium.English.
Name of the Student.Deebak.kuma.. ... Class/Semester. 29E1..B1eCh..cSE..5..
Name of Paper...GS.A.. .Code of Paper.110.64/NJ.. Total Number of pages written....1.

Date of Exam.23/02 202. * * * * * * * * *

Signature 120010o6
LDeebak kumar
AnSwer Sheet:

An$:1 AProgram re.siding in the_memory unit of the Combufer_


ConSists of a sequence ot InstrucHons.
The progrom is exe.cuted in the Combuter by aning
through 0. Gucle tor each Tnstruc.tion.
The þrocesSing inunlve.d in the execution ot a single Tnst
-Tucion is termed as Tnstruttion Cucle
Each Tnstrucion Cucle is in turn Subdivided into a seq-
-Uence ot Sub cycles or bhaSes.
In basit Combuter each ToStrucion Cucle consists ot he
tollowing bhases:
1.Fetch the Tnshru.cion from the mmemory
2 Decode he Instruction
. Reod he effec.hive address from the memory i the
Instruction_has an Indifect Addre.ss.
Execute the Tnstrucion
Fetch Cycle Execute Cucle

Start Fetch Fxecute Halt


Inskruction LTastruction

Dpon CombleHon of sBepiv),the Control goeS back th the


StebLi to Fetth,decode_and Execute the Nexk Tnstruotian
TheprocesS iS Coninous unless a Halt InsBruchion EntounBen
Roll No..1001006... Paper Code .061IN.. Page No . . *sA******

Fetch and Decode:


Stebs Tnvolued in Fetch and decode the Inshuction:

Step1:nitially,the þrogam Counter PG 1S loaded with tHhe address


of the First instrucion in the brogram.
Step2: The Sequence Counter SC iS cleared to 0,proyiding timmin
Signal To
Step3: Tne micro-oberation for fetch and decode bhases_Can_be
Specified by he Follouwing reqisBerTransfer StatementS

To: AR PC
T:IR< M[ARI,P¢-PCA1
I2 Do, D Decode IR(12-14) AR-TR(0-11),K-IR5
S2
To BUS

Memory Unit
AddresS
Read

AR 1

PC 2

IR

LD
clock
peppo
Dee1ature
Poge
Page No12001006 11064/N Rol No
3.

transer
Stepu:The above figure shows how the rst tw0 register
Statements are imblementedin fhe bus SyStem.
Steb 5:D þmvide the_dato. both for the transfer ot PG to AR
achieve the pllowing
e mUSt abbly immin9 Sianal D o
ConnecHpns:
LDI6laCe the aontent o PG onto the bus bs making tne bus-
Selechon inbuts S2Si and Sn egual to 010.
lranster the Content t the bus to AR by enahling the
LD inbut o ARR
STep6: n Order, to imblement the Second Stotement i+ 1S
þrouide the Falle-
necessary h use imming Sianal
oina Gonnecinns in the bus Sustem
iEnable the read inbut o memor
GnSlace the ontent o memory ontn bus by making SoSSo
=111
Li Transfer the_content of the bus to IR by enablimg the ID
inbut o Po.
Ltu Intre.ment P¢ by enabling the TNR input 0 PC
he_dfagram bec
Steb Moltible inbut OR 9ates are inclucded in inilinitiaf
-auSe there are other Conhralunchnnsthet
the similan dherations.

Determine the ube ot nstruction:

decoding is Ta
he Timminq Signal hot is ACtHive oer fhe o
ime 1a, th Conirnl nit _dekermine the Tue
During
memaru
the lnsHuttion that LuaS read om the
Address
f D4=0 and T1, Memory reterente luith_lndirëctAddress_
direct
f DE0 and T:0; Memory reterenc.e Luith
1f D 1 and 1=0 indicates Reqister-reference Instruchor
TnstrucHons
f D =1and T:1 indic.ate.s nbut-outhut
Deepak (umar
Signature
Roll No 120010D6 Paper Code 1061NI Page No_4 .

he Three Tnstrucion tuhes are Subdiided into tour Seharate


baths
The $elect Oberahion is_activated with_clock tran&iian that
iS OSSociated uith timing Signal I3.
his Can be Smbalized as hlo
Da IT3 AR-MIAR]
DiT I3: Nothing
DI13 2Execute a register-referenc.e Tnshrucion
LD:T3: Execute_an Inbut -Outb1ut LashiiCion

Flnu chart
Start
SC-0
To
AR-TC
Fekch
T
IR-MTARJ, PC<- PCt1
T2
Decode oberation Cade IR(2-14 Deco de
AR4-IR0-11), I4-IR 05)
Execute
CRegister orI/o) =1 0 (Memory-Reference)

6)1/ 0 (register) CTdirect) =i o Cdirec+)

T3 T3 T3 T3
Execute Exectie AR-M[AR Nothing
I/o Register-
InStfucion reterence Execute
SC-0 SC-O
Memory-reference Ins.
s c-0
Deebak kumar
Signature

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