See discussions, stats, and author profiles for this publication at: https://www.researchgate.

net/publication/349211497

2:1 Multiplexer Using Different Design Styles: Comparative Analysis

Conference Paper · September 2020

CITATION READS

1 13,180

2 authors:

Tripti Dua Anju Rajput

JECRC Foundation JECRC Foundation
8 PUBLICATIONS   8 CITATIONS    8 PUBLICATIONS   6 CITATIONS   

SEE PROFILE SEE PROFILE

Some of the authors of this publication are also working on these related projects:

2:1 Multiplexer Using Different Design Styles: Comparative Analysis View project

Half Adder Using Different Design Styles: A Review on Comparative Study View project

All content following this page was uploaded by Tripti Dua on 11 February 2021.

The user has requested enhancement of the downloaded file.

 Journal of Advancements in Robotics
ISSN: 2455-1872
Volume 7, Issue 3
www.stmjournals.com

2:1 Multiplexer Using Different Design Styles:

Comparative Analysis
Tripti Dua 1,*, Anju Rajput 2
1,2
Assistant Professor, Department of Electronics and Communication Engineering, Jaipur
Engineering College and Research Center, Jaipur, Rajasthan, India

Abstract
This paper presents a comparative analysis of 2:1 multiplexer using different logic styles
(transmission gate, pass transistor and CMOS logic), with three different technologies i.e.
45nm, 32nm and 16nm. Simulation is done using Synopsys HSPICE tool at 1V power supply.
As a result, it is found that the least power is consumed by 2:1 multiplexer implemented using
TGL. It consumes 99.7% less power than pass transistor logic and PTL consumes 99% more
power than CMOS. Since multiplexer implemented by PTL utilizes minimum number of
transistors, i.e., 2 ,therefore it is the area efficient logic circuit for 2:1 MUX but its
performance is low as its output is somewhat distorted.

Keywords: Power dissipation, CMOS, pass transistor, transmission gate, insert.

*Author for Correspondence E-mail: [email protected]

INTRODUCTION Multiplexer is a universal combinational

In recent years, Very-large-scale integration circuit which can be used to implement any
(VLSI) is the vital method used for designing logic gate. The multiplexer is a digital switch
integrated circuits (IC) by putting together which has 2n input lines, ‘n’ select lines and
millions of transistors or electrical components single output line. In conformity with the
onto a single chip. This leads to reduction in binary combination of the select lines, output
silicon area, delay and power consumption of is generated by connecting itself to the
any electronic device [1, 2]. selected data input line [3-5].

The multiplexer is basic building block in 2:1 MUX has 2 input data lines, single select
communications networking. A multiplexer is line and single output line as well. When the
a combinational circuit that converts serial binary value of select line is logic ‘0’then
data into parallel data. The main function of input D0 is passed to the output line. When
multiplexer is to connect many users (or the binary value of select line is logic ‘1’,
channels) on to a single data transmission path then data line D1 is connected to output line
to increase the efficiency of that channel. The and transmitted through it. The Boolean
2:1 MUX has one output, two inputs and one expression and block diagram of 2:1 MUX
select line. According to the binary value of are as follows: The Boolean expression and
the select line the particular input is selected block diagram of 2:1 MUX are as follows in
and passed to the output. In this paper design Figure 1:
of 2:1 MUX is constructed using transmission
gate logic, pass transistor logic and CMOS (1)
logic. Number of transistors used to design
these circuits as well as their corresponding Logic circuit of 2:1 MUX using basic logic
power dissipation is compared. These circuits gates i.e., AND, OR and NOT gates can be
are simulated using Synopsys HSPICE tool. formed as follows in Figure 2:

JoARB (2020) 5-13 © STM Journals 2020. All Rights Reserved Page 5
2:1 Multiplexer Using Different Design Styles: Comparative Analysis Rajput and Dua

Fig. 1: Basic 2:1 Multiplexer.

Fig. 2: Logic Circuit of 2:1 MUX.

Truth table as shown in Table 1 with all the NMOS transistor. It obstructs or transmits a
possible combinations of select line and data signal from the input to the output on the basis
inputs is shown below. It can be clearly of externally applied control signal. The
inferred from the table that whenever the control signal applied to the gates in such a
select line is low logic, then output is same as manner that they are complement to each other
data input ‘D0’ irrespective of the values of so that both transistors are either active or
other data input. Similarly, whatever may be deactivate simultaneously [6-8].
the value of data line D0, if the select line is at
high logic, then output obtained has same A 2:1 multiplexer designed using transmission
value as data input D1. gate logic is shown in Figure 3. The circuit is
comprised of 4 transistors. This logic circuit
Table 1: Truth Table of 2:1 MUX. selects either data line A or B in accordance
S D0 D1 Y with the logic applied at control input 'S'.
0 0 0 0
0 0 1 0
When ‘S ’is applied with logic value ‘0’, then
0 1 0 1
0 1 1 1 transistors N1 and P1 are switched on and
1 0 0 0 behave like short circuits whereas transistors
1 0 1 1 N2 and P2 are switched off and behave like
1 1 0 0 open circuits. Thus, data A is passed to the
1 1 1 1 output. When control signal ‘S’ is provided
with logic ‘1’, then transistors N1 and P1 are
TRANSMISSION GATE LOGIC switched off and behave like open circuit and
BASED 2:1 MUX transistors N2 and P2 are turned on and
A transmission gate is a bilateral switch which behave like short circuits. Hence, only
is composed of a PMOS transistor and an conducting path is available between data

JoARB (2020) 5-13 © STM Journals 2020. All Rights Reserved Page 6
Journal of Advancements in Robotics
Volume 7, Issue 3
ISSN: 2455-1872

input B and output. The circuit is simulated 2:1 MUX USING PASS TRANSISTOR
using HSPICE tool at 45nm, 32nm and 16 nm LOGIC
technologies with 1V power supply and As the name suggests, Pass transistor logic
desired output is obtained. Waveforms (PTL) uses NMOS transistors to pass or block
obtained after simulation are shown in Figure the electrical signal in conformity with the
4(a, b). logic applied externally as control signal at the
gate of the transistor. It is used to reduce the
transistor count by trading the performance of
the logic circuit by eliminating redundant
transistors. By using Pass Transistor logic, a
2:1 multiplexer can be implemented with the
aid of just two NMOS transistors. The circuit
designed is shown in Figure 5.

Two data inputs A and B are applied at the

source of two pass transistors N1 and N2
respectively. When control signal S is
provided with low logic then transistor N1 is
actuated and portrays like short circuit
whereas transistor N2 is switched off. Thus,
data input A is supplied to the output line.
However, when control signal S is applied
with high logic then transistor N1 is turned off
whereas transistor N2 reflects as short circuit.
Hence, only conducting path is available
Fig. 3: 2:1 MUX using transmission gate only. between data input B and output line and
therefore output follows input B. Input and
Power consumption by 2:1 MUX using TGL Output waveforms obtained after simulation
at 45nm, 32nm and 16 nm technologies are the circuit at 1V power supply is displayed in
shown below in form of bar graph. Figure 6(a, b).

Fig. 4: (a) Simulation waveform of 2:1 MUX using transmission gate only.

JoARB (2020) 5-13 © STM Journals 2020. All Rights Reserved Page 7
2:1 Multiplexer Using Different Design Styles: Comparative Analysis Rajput and Dua

2:1 MUX using Transmission Gate only

3.0000E-09
Power Consumption

2.5000E-09
2.0000E-09
1.5000E-09 2.6811E-09
2.4098E-09
1.0000E-09
5.0000E-10 7.7183E-10

0.0000E+00
45nm 32nm 16nm
Power 2.6811E-09 2.4098E-09 7.7183E-10
Technology Used
Fig. 4: (b) 2:1 MUX using Transmission Gate only.

Fig. 5: Circuit diagram of 2:1 MUX using pass transistor only.

Fig. 6: (a) Simulation waveform of 2:1 MUX using pass transistors only.

JoARB (2020) 5-13 © STM Journals 2020. All Rights Reserved Page 8
Journal of Advancements in Robotics
Volume 7, Issue 3
ISSN: 2455-1872

2:1 MUX using pass transistors only

2.5000E-06
Power Consumption

2.0000E-06

1.5000E-06
2.0207E-06
1.0000E-06
1.0064E-06 1.0068E-06
5.0000E-07

0.0000E+00
45nm 32nm 16nm
Power 1.0064E-06 1.0068E-06 2.0207E-06

Technology Used

Fig. 6: (b) 2:1 MUX using pass transistors only.

Fig. 7: 2:1 MUX using CMOS logic only.

The circuit is simulated at 45nm, 32nm and 16 2:1 MUX using CMOS modelled using 10
nm technologies and the comparison of power transistors as shown in Figure 7.
consumption by the circuit at different
technologies is represented by a bar graph. The circuit is simulated using HSPICE tool
and the waveforms obtained for inputs and
2:1 MUX USING CMOS LOGIC outputs are displayed in Figure 8(a-e).
Complementary Metal Oxide Semiconductor
(CMOS) logic deploys symmetric number of Simulation of the multiplexer using CMOS is
both types of MOSFETs, i.e., PMOS and carried out at 45nm, 32nm and 16 nm
NMOS. This leads to better performance of technologies. Power consumption by the
any logic circuit since NMOS is strong ‘0’ circuit at those technologies is compared in
device and PMOS is strong ‘1’device. Thus, following bar graph representation. Thus it can
CMOS provides complete ‘1’ and complete be inferred that as technology is decreased,
‘0’ logics at the output without any distortion. power consumption is also decreased.

JoARB (2020) 5-13 © STM Journals 2020. All Rights Reserved Page 9
2:1 Multiplexer Using Different Design Styles: Comparative Analysis Rajput and Dua

Fig. 8: (a) Simulation waveform of 2:1 MUX using CMOS logic.

2:1 MUX using CMOS

1.0000E-08

9.0000E-09
Power Consumption

8.0000E-09

7.0000E-09

6.0000E-09

5.0000E-09 9.0686E-09
4.0000E-09
5.8714E-09
3.0000E-09

2.0000E-09
2.3305E-09
1.0000E-09

0.0000E+00
45nm 32nm 16nm
Power 9.0686E-09 5.8714E-09 2.3305E-09

Technology Used

Fig. 8: (b) Simulation waveform of 2:1 MUX using CMOS logic.

JoARB (2020) 5-13 © STM Journals 2020. All Rights Reserved Page 10
Journal of Advancements in Robotics
Volume 7, Issue 3
ISSN: 2455-1872

Comparison in 45 nm
1.2000E-06
1.0064E-06
1.0000E-06
Power Consumption

8.0000E-07

6.0000E-07

4.0000E-07
2.6811E-09 9.0686E-09
2.0000E-07

0.0000E+00
Transmission
Pass Transistor CMOS
Gate
Power 2.6811E-09 1.0064E-06 9.0686E-09
DESIGN STYLE
Fig. 8: (c) Comparison in 45 nm.

Comparison in 32 nm
1.2000E-06
1.0068E-06
1.0000E-06

8.0000E-07
Power Consumption

6.0000E-07

4.0000E-07 5.8714E-09
2.4098E-09
2.0000E-07

0.0000E+00
Transmission
Pass Transistor CMOS
Gate
Power 2.4098E-09 1.0068E-06 5.8714E-09
DESIGN STYLE
Fig. 8: (d) Comparison in 32 nm.

Comparison in 16 nm
2.5000E-06
2.0207E-06
2.0000E-06
Power Consumption

1.5000E-06

1.0000E-06

5.0000E-07 2.3305E-09
7.7183E-10

0.0000E+00
Transmission
Pass Transistor CMOS
Gate
Power 7.7183E-10 2.0207E-06 2.3305E-09
DESIGN STYLE
Fig. 8: (e) Comparison in 16 nm.

JoARB (2020) 5-13 © STM Journals 2020. All Rights Reserved Page 11
2:1 Multiplexer Using Different Design Styles: Comparative Analysis Rajput and Dua

Table 2: Comparison Table of different 2:1 MUX.

Name of Circuit No. of Transistors Technology Supply Power Consumption (in
used Used Voltage watts)
(i) 2:1 MUX using 4 45nm 1v 2.6811E-09
Transmission Gate only 32nm 2.4098E-09
16nm 7.7183E-10
(ii) 2:1 MUX using pass 2 45nm 1v 1.0064E-06
transistors only 32nm 1.0105E-06
16nm 2.0207E-06
(iii) 2:1 MUX using CMOS 10 45nm 1v 9.0686E-09
only 32nm 5.8714E-09
16nm 2.3305E-09

COMPARATIVE ANALYSIS transistors and second goal is to have

2:1 MUX is implemented using Transmission minimum power consumption. The analysis is
gate logic (TGL), Pass Transistor Logic (PTL) done in three different technologies i.e. 45nm,
and CMOS logic. All the circuits are simulated 32nm and 16nm using Synopsys HSPICE at
using HSPICE tool at 45nm, 32nm and 16nm 1v power supply. As a result, it is found that
technologies with 1V power supply and power the least power is consumed by 2:1
consumption in each case is analysed. Power multiplexer implemented using TGL. It
consumption by multiplexer designed using consumes 99.7% less power than pass
Transmission gate as well as CMOS is transistor logic and PTL consumes 99% more
remarkably low as compared to that designed power than CMOS. Although power
by Pass Transistor Logic. consumed by the circuits formed using TGL
and CMOS is comparable but there is a huge
In comparing all the three circuits with difference in number of transistors used to
different design styles, the least power is design these circuits . Since multiplexer
consumed by 2:1 multiplexer implemented implemented by PTL utilizes minimum
using TGL. Although power consumed by the number of transistors, i.e., 2 ,therefore it is the
circuits formed using TGL and CMOS is area efficient logic circuit for 2:1 MUX but its
comparable but there is a huge difference in performance is low as its output is somewhat
number of transistors used to design these distorted.
circuits. CMOS uses 3 times the number of
transistors utilized by TGL approach to design REFERENCES
2:1 MUX. Since multiplexer implemented by 1. Neil H. E. Weste and David Money
PTL utilizes minimum number of transistors, Harris, "CMOS VLSI Design A Circuits
i.e., 2 therefore it is the area efficient logic and System Perspective", Pearson
circuit for 2:1 MUX but its performance is low Education (Asia) Pvt. Ltd., 2000.
as its output is somewhat distorted. CMOS 2. S. Abirami, M. Arul Kumar, E. Abinaya
uses large number of components but its and J. Sowmaya, "Design and analysis of
performance is high and its switching time is 2: 1 multiplexer circuit for high
minimum therefore its delay is the minimum performance", International Journal of
as compared to those of TGL and PTL circuits. Electrical and Electronics Engineers Vol.,
no. 7, Jan-June 2015.
Comparative analysis of power consumption 3. M. Padmaja and V. N. V. Satya Prakash,
and transistor count at different technologies is "Design of multiplexer in multiple logic
elaborated by the table and bar graphs given styles for low power VLSI", International
below in Table 2. Journal of Computer Trends and
Technology, vol. 3, no. 3, 2012
CONCLUSION 4. Nishant Kumar,Poornima Mittal,
The comparative analysis is done to identify “Performance Investigation of 2:1
the architecture of 2:1 MUX with two main Multiplexer using 90nm Technology Node
goals. The first one is to have lesser number of for Low Power Application,” International

JoARB (2020) 5-13 © STM Journals 2020. All Rights Reserved Page 12
 Journal of Advancements in Robotics
Volume 7, Issue 3
ISSN: 2455-1872

Conference on Electrical and Electronics logic families at 180 nm technology.”

Engineering (ICE3),2020. IEEE,2018.
5. A. Morgenshtein, A. Fish and I. A. 8. Purnima Kumari Sharma and Neeraj
Wagner, "Gate-Diffusion Input (GDI): A Kumar Singh, "Power comparison of
Power-Efficient Method for Digital single and dual rail 2: 1 MUX design at
Combinatorial Circuits", IEEE different levels of technology", IEEE
transactions on very large scale integration Conference, pp. 671-775, 2014.
(VLSI) systems, vol. 10, no. 5, October
2002..
6. K. Yano, Y. Sasaki, K. Rikino and K. Cite this Article
Seki, "Top-down pass transistor logic Anju Rajput, Tripti Dua. 2:1 Multiplexer
design", IEEE Journal of Solid-State Using Different Design Styles:
Comparative Analysis. Journal of
Circuits, vol. 31, no. 6, pp. 792-803, 1996.
Advancements in Robotics. 2020; 7(3):
7. Rose V Anugraha ; Devi S Durga ; R.
5–13p.
Avudaiammam, “Design and performance
analysis of 2:1 multiplexer using multiple

JoARB (2020) 5-13 © STM Journals 2020. All Rights Reserved Page 13

View publication stats