Scribd
Upload
684 views7 pages

Lab5 - Logic Gates Simulation Using LTSpice

The document provides instructions for students to model and simulate logic gates using LTSpice software. It describes drawing schematic diagrams of basic logic gates like NAND gates using spice directives. It also explains how to define custom MOSFET models and set parameters. Students are asked to draw and simulate several logic gate circuits like AND, OR, NOR, XOR and XNOR gates using combinations of NAND gates and NOT gates.

Uploaded by

Rodolfo Jr Doromal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
684 views7 pages

Lab5 - Logic Gates Simulation Using LTSpice

The document provides instructions for students to model and simulate logic gates using LTSpice software. It describes drawing schematic diagrams of basic logic gates like NAND gates using spice directives. It also explains how to define custom MOSFET models and set parameters. Students are asked to draw and simulate several logic gate circuits like AND, OR, NOR, XOR and XNOR gates using combinations of NAND gates and NOT gates.

Uploaded by

Rodolfo Jr Doromal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 7

CPEDRF – Computer Engineering Drafting and Design

Lab 5 – Logic Gates Modeling Simulations using LTSpice

Name Yr. & Sec. Date

I. Objectives

1. Learn how to draw/model a logic gates schematic diagram using LTspice.


2. Demonstrate how to simulate using LTSpice.

II. Materials
a. PC/Desktop
b. LTSpice Software

III. Concepts

LTSpice has a few “behavior logic gates” it is nice to have a collection of the basic gates with the
standard number of inputs and ports for power supply (some systems use 5V, some use 3V3, some use
other source references).

IV. Procedures

Draw the following Logic Gates with Spice Directives

Model of NAND Gate with Spice Directives

Custom MOSFET Models

Even though LTSpice has a large collection of components in the library, sometimes it is better to
define components using specific parameters. The MOSFETs used in my forum post above use specific
values to ensure proper behavior. The program has two models that allow custom parameters:

pmos4 and nmos4


You will want to make sure to rename “M4” to something unique so you don’t mix them up for the
“Model” name. The “model” by default is PMOS and NMOS. Renamed them to PMODA, PMODB,
NMODA, and NMODB.

MOSFET Parameters

The following parameters at minimum must be included: KP (transconductance), gamma (bulk


threshold parameter), phi (surface inversion potential), lambda (channel length modulation), L (length
of channel), W(width of channel), and VTO (zero-bias threshold voltage). To add custom values to
these parameters you need to add a spice directive for the NMOSFETs and PMOSFETs by pressing the
“S” key. The entry will be :

.model yourModelName nmos (KP=200u GAMMA=0.9 phi=0.6 lambda=0.02 VTO=0.7)

Change “yourModelName” to something else unique, I used NMOD1 and PMOD1 respectively. Place
the spice directive somewhere on your diagram. Press the “S” key again and add this for the
PMOSFET:

.model yourModelName pmos (KP=100u GAMMA=0.9 phi=0.6 lambda=0.02 VTO=-0.7)


Place this somewhere on your schematic.

To edit the length and width of each MOSFET channel, right-click the MOSFET in question. The P-
MOSFETs share the same values:

Again, change “yourModelName” to the one you typed in the spice commands. Mine would have
been PMOD1 for the P-MOSFETs and NMOD1 for the N-MOSFETs.

The N-MOSFETs have slightly different lengths and widths. The top one (NMODA in my diagram) has
these values:

The one below it (NMODB):

Make sure to use the same model name as both SPICE commands otherwise the program doesn’t
know what parameters to use.
Output SPICE Directive for Simulation

One other SPICE command is added: CL Out 0 1p. This is a shortcut to tell LTSpice that you want some
kind of capacitance and inductance on the output. Out refers to the output, 0 is the amount of
inductance present and 1p is the amount of capacitance present (backward from the letters). This is
done sometimes to help the program simulate a little quicker.

Derivative Gates: AND, OR, NOR, XOR, XNOR

You can make all the other gates using just NAND gates or a combination of NOT and NAND gates.

AND

OR

NOR
XOR

XNOR

V. Exercises

1. Draw the logic circuit below using LTSpice and simulate.


2. Draw the logic circuit below using LTSpice and simulate.
3. Draw the logic circuit below using LTSpice and simulate.

4. Draw the logic circuit below using LTSpice and simulate.

You might also like