Top Verilog Interview Questions for 2023

1. What are Verilog parallel case and full case statements?

Parallel Case
It is a statement where it matches only one case item. Otherwise, it becomes
overlapping case items.

Full Case
It is a statement where binary patterns case expressions match a case item or a default.

2. Differentiate between == and ===.

== ===

Output can be 1,0 or X Output can be 0 or 1

It can compare 1s and 0s but not Xs Can also compare Xs

3. Differentiate between Verilog and VHDL

Verilog VDHL

It is an HDL used for electronic design

It is an HDL used for digital systems
automation

It is based on the “C” language It is based on Ada and Pascal languages

It is case sensitive It is not case sensitive

It is simple and easy It is complex

It is compact It requires more code lines

4. What does wire refer to?
It is a physical connection between structural elements that enable Verilog to function.
A continuous assignment or gate output denotes its value. A wire cannot store value
when there is no connection between a and b. The Default value of a wire is Z.

5. What is reg in Verilog?

The reg represents the abstract data storage element. It is also called a register type
integer, real and real-time. Its value is assigned within an always or an initial statement.
The default value of reg is X.

6. What are Blocking and non-blocking in Verilog?

The blocking assignment completes the entire statement before the control goes to the
following statement. It behaves similarly to older programming languages. It is
symbolized as =.

A non-blocking assignment evaluates the right-hand side for the current time unit and
the left-hand side later at the end of the time unit. It is symbolized as <=.

7. Differentiate between Task and Function.

Task Function

Enable a function and additional It cannot enable a task but can enable
versions of a task. other functions.

Can contain any statements Can yield one value

Can use 0, input, or output statements Cannot use input or output statements

8. What is the Sensitivity list?

It specifies the list of the signals one wants to cause the code during the process to be
evaluated when it changes its state.
9. Explain $monitor, $display and $strobe.
 These commands have similar syntax and show text on the screen during
simulation.
 $display and $strobe appear once when executed.
 $monitor appears every time a parameter is changed.

10. What is transport delay?

This delay is caused by the wires connected with gates. The signal is due to the wire’s
resistance and inductance.

11. What is the inertial delay?

The delay caused by the output change happens in the gate.

12. What are the ways of writing FSM code?

 All input decoders, output decoders, and present states are combined in one
process.
 Where sequential and combinational circuits are separated in different
processes.
 Where input decoder and present state are combined, but output decoders are
separated.
 Where all three inputs are separated into three processes.

13. Explain deposit and force command

Deposit
This command is used to give an initial value to a signal. But it will hold it until it is
overwritten. For example, depositing 1 to a flip-flop will remain the same until simulation
changes it to a new value.

Force
It is used to drive signals at any time stamp of the simulation.

14. Explain freeze and drive

Freeze
It is used to put a value on a signal. Value remains the same throughout the simulation.

Drive
It puts value on a signal but changes to a new value when updated by a simulation.
15. What does timescale 1 Ns/1 Ps mean?
It means all delays are interpreted in nanoseconds, and fractions are rounded off to the
nearest picosecond.

16. Between variable and signal, which will be updated first?

The signal will be updated first.

17. What are the features of VHDL?

Very High-speed integrated circuit HDL describes and simulates the system before
making it into a digital one. Its features are

 Complexity management
 Design data portability
 Independent of technology
 Efficient and less time consuming
 Readability

18. What is PLI?

It is the Programming Language Interface used for enabling C programming in Verilog.
It performs multiple tasks

 Passing data
 Altering and returning object value in the design hierarchy
 Accessing simulator database
 Monitoring alterations in the design hierarchy

19. What is a continuous assignment?

When inputs of the right-hand side drive the left-hand side, it is a continuous
assignment. It also means that changing the right side will change the whole equation.
The target is wire driven by right-hand side inputs. It is used to synthesize combination
logic.

20. Explain the repeat loop.

It is similar to the loops of a common programming language. It repeats a code for the
number of times mentioned within the code. It reduces the redundancy in code lines.
Syntax
Repeat(<no. of times the loop should run>) <statement should be repeated >

21. What is Virtual and Pure virtual function in Verilog?

Virtual Pure virtual

It allows the overriding of a function in a It has only declaration and no

derived class implementation

The base class doesn’t need to Any derivative class must implement the
implement a virtual function function

22. What are Semaphores?

It controls access to shared resources. It is used for mutual exclusion, primary
synchronization, and accessing control of shared resources. It can be viewed as a
bucket with several keys during its creation. The Execution process requires one of the
keys.

23. What is the Factory and Factory pattern?

A factory creates different objects for a prototype. It is done By calling the
corresponding constructor when different classes are registered with the factory.

The Factory pattern directly creates an object without calling the constructor method. It
allows the use of polymorphism for object creation.

24. What is Callback?

A callback is when a function calls another function taking the first one as an argument.
It is used when an event happens. It includes calling back a function

 to inject errors on transactions

 To train depending on transactions
 In the event of a specific occurrence
Full Stack Ja25. What is DPI called?
The Direct programming interface is a bridge between system Verilog and any other
foreign programming language like Python. It ensures direct inter-language function
calls doing languages on both sides of the interface. It supports both functions and
tasks across the boundary.

26. What is Parameter and Typedef in Verilog?

A parameter is a constant value within the module structure used to define various
attributes for the module. It also characterizes the behavior and physical representation
of the module.

Typedef Enables users to craft unique names for type definitions for frequent use in
their codes. They are easily used while building technical array definitions.

27. Explain some uses of Clocking Blocks

Clocking Block is used for

 Specifying synchronization characteristics of a design

 Testbench driving the signals at the right time
 Cleaning the drive and sample design and race-free operations in specific
applications

28. What is the need for an Alias in Verilog?

An alias statement offers a bidirectional and short circuit connection. Usually, a Verilog
has a one-way assign statement which may have delay and strength changes for
unidirectional assignment.

FAQs
1. What are the data types in Verilog?
Data types are used to represent the data storage and transmission elements that are
found in digital hardware. These are of 2 types NETS and REGISTERS.

They can attain any value.

0 Logic zero / False

 1 Logic one / True

X Unknown logical value

Z The High impedance of the tristate gate

2. What is Verilog used for?

Uses of Verilog

 To model electronic systems

 Designing and verifying digital circuits
 Verification of analog circuits and mixed-signal circuits
 Designing genetic circuits

3. What software is used for Verilog?

Some of the Verilog Simulators are

Cascade GPL Cver Icarus Verilog

Isotel Mixed Signal &

LIFTING OSS CVC
Domain Simulation

Verilog Behavioral
TKGate Verilator
Simulator

VeriWell

4. What is RTL in Verilog?

RTL is the Register transfer level. It means Verilog code describes data transformation
as it passes register to register. This transformation is done by combination logic that
exists between registers.
Conclusion
Verilog is a vast subject with numerous questions. The questions given above will give a
wide knowledge of the concepts of Verilog that will help you in clearing your interview.
Prepare these questions with other useful Practical knowledge before going for the
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