Lecture-26

15. DCR r: It is a single byte instruction. The meaning of the

instruction is “Decrement the content of register (r) by 1 and store the
result back to the register (r)”. The macro RTL implemented is
(r) (r) + 1
The opcode of the instruction is

0 0 D D D 1 0 1 N

It has 7 variations in this all the flags are affected except carry flag.
The micro RTL flow implemented is given below:
Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =

T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)

T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. DCR r = 1.

Machine Cycle- 2 or (Machine Cycle-1 of next instruction):

OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
FEO [(Temp) (r)]
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
FEO [(r) (Temp) - 1]
It requires single machine cycle OFMC and 4 states. The addressing
mode is register addressing mode. All flags are affected except the
CY flag.
16. DCR M: It is a single byte instruction. The meaning of the
instruction is “Decrement the content of memory location by 1 whose
address is available in (H, L) pair and stores the result back in the
same location”. The macro RTL implemented is
M(H,L) M(H,L) + 1
The opcode of the instruction is

0 0 1 1 0 1 0 1 N

It has no variations. All the flags are affected except carry flag. The
micro RTL flow implemented is given below:
Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =

T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)

T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. DCR M = 1.
Machine Cycle- 2:
MRMC: Status signals IO/M=0, S1=1, S0=0
T1: A15-A8 (H), AD7-AD0 (L), ALE =
T2: RD = 0, AD7-AD0 M(AB)
T3: RD = 1, , (Temp) AD7-AD0
Machine Cycle- 3
MWRMC: Status signals IO/M=0, S1=0, S0=1
T1: A15-A8 (H), AD7-AD0 (L), ALE =
T2: WR = 0, AD7-AD0 (Temp) + 1
T3: WR = 1, , M(AB) AD7-AD0
It requires three machine cycles OFMC, MRMC & MWRMC, and 10
states. The addressing mode is register addressing mode. All flags
are affected except CY.

17. INX rp: It is a single byte instruction. The meaning of the

instruction is “Increment the content of register pair (rp) by 1 and
store it in same register pair. The macro RTL implemented is
(rp) (rp) + 1
or (rpH, rpL) (rpH, rpL) + 1
The opcode of the instruction is

0 0 R P 0 0 1 1 N

It has 4 variations for register pairs (B,C), (D,E), (H,L) and 16-bit
register (SP). No flag is affected in this instruction. It is register
addressing mode. The micro RTL flow implemented is given below:
Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =

T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)

T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. INX rp = 1.
T5: (Temp) (rpL), (Z) (F)
T6: (rpL) (Temp) + 1, CY Flag is affected.
Machine Cycle- 2 or (Machine Cycle-1 of next instruction):
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
 FEO [(Temp) (rpH)]
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
FEO [(rpH) (Temp) + (CY), (F) (Z) ]
Therefore, the instruction requires only one machine cycle OFMC and
of 6 states.

18. DCX rp: It is a single byte instruction. The meaning of the

instruction is “Decrement the content of register pair (rp) by 1 and
store it in same register pair. The macro RTL implemented is
(rp) (rp) - 1
or (rpH, rpL) (rpH, rpL) - 1
The opcode of the instruction is

0 0 R P 1 0 1 1 N

It has 4 variations for register pairs (B,C), (D,E), (H,L) and 16-bit
register (SP). No flag is affected in this instruction. It is register
addressing mode. The micro RTL flow implemented is given below:

Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =

T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)

T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. INX rp = 1.
T5: (Temp) (rpL), (Z) (F)
T6: (rpL) (Temp) - 1, CY Flag is affected.
Machine Cycle- 2 or (Machine Cycle-1 of next instruction):
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
FEO [(Temp) (rpH)]
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
FEO [(rpH) (Temp) - (CY), (F) (Z) ]
Therefore, the instruction requires only one machine cycle OFMC and
of 6 states.

19. DAD rp: It is a single byte instruction. The meaning of the

instruction is double precision addition, i.e., “Add the contents of (H,L)
register pair with the contents of register pair (rp) and store the result
back into (H,L) register pair”. The macro RTL implemented is
(H, L) (H, L) + (rp)
or (H, L) (H, L) + (rpH, rpL)

The opcode of the instruction is

0 0 R P 1 0 0 1 N

It has 4 variations for register pairs (B,C), (D,E), (H,L) and 16-bit
register (SP). Only CY flag is affected in this instruction. It is register
addressing mode. Since the instruction is a single byte instruction,
therefore, only one memory reference operation is required. To add
two 16-bit numbers, two 8-bit operations are required one by one
which need two machine cycles. These operations cannot be
completed during FEO (where only two extra states are available)
and, therefore, two Bus Idle Machine Cycles (BIMC) are required.
The micro RTL flow implemented is given below:

Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =

T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)

T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. DAD rp = 1.

Machine Cycle- 2:
BIMC: Status signals IO/M=0, S1=1, S0=0
T1: (W) (A), (Z) (F)
T2: (A) (rpL), (Temp) (L)
T3: (L) (L) + (Temp), CY flag is affected as per result

Machine Cycle- 3:
BIMC: Status signals IO/M=0, S1=1, S0=0
T1: (A) (rpH), (Temp) (H)
T2: (H) (A) + (Temp) + (CY)
T3: (A) (W), (F) (Z), All flags are restored except CY.

Therefore, the instruction requires three machine cycles OFMC & teo
BIMC and a total of 10 states.
DAD H is one important instruction. The macro RTL implemented is
(H, L) (H, L) + (H, L)
The meaning of this multiplying the 16-bit contents of (H,L) by 2. It
actually shifts all the 16 bits of (H, L) register pair to left by one bit
position.

20. DAA: It is a single byte instruction. The meaning of the instruction

is decimal adjust accumulator. It is specifically used for BCD addition
operation. It adjusts the content of accumulator to two digit BCD. It
performs the following operations on 8-bit data in the accumulator.
Accumulator

A7 A6 A5 A4 A3 A2 A1 A0

CY AC
Fig.5.16 CY Flag, AC Flag and Both Nibbles checked for DAA Instruction

This instruction is used just after the addition operation. Whenever

DAA is executed the following checks and corrections are made:
A. If the lower order 4-bits A3A2A1A0 is an illegal BCD code or if AC
is SET then 06H is added to accumulator.
B. Thereafter, if the higher order 4-bits A7A6A5A4 is an illegal BCD
code or if CY is SET then 60 H is added to accumulator else no
action.
The opcode of the instruction is

0 0 1 0 0 1 1 1 N

It has no variations. The micro RTL flow is

Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =

T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)

T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. DAA = 1.

Machine Cycle- 2 or (Machine Cycle-1 of next instruction):

OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
FEO [Checks the lower nibble of (A) and adjusts it to valid BCD]
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
FEO[Checks the upper nibble of (A) and adjusts it to valid BCD]

Therefore, the instruction requires only one machine cycle OFMC and
a total of 4 states.