Lecture 22

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Lecture-22:

9. LHLD ADDR: This is an ALP statement. LHLD is the mnemonic


for LOAD (H,L) REGISTER PAIR DIRECT. The meaning of the
instruction is “Load the content of the memory location whose
address is directly available as 2nd & 3rd byte of the instruction to
register L and the content of the memory location at next higher
address to the register H”. This is a 3-byte instruction. The instruction
format is

0 0 1 0 1 0 1 0 N

<B2> N+1

<B3> N+2

The macro RTL implemented is


(L) M(B3, B2)
(H) M((B3, B2) + 1)
This instruction has no variation. The addressing mode is direct
addressing mode. The micro RTL flow is:
Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. LHLD addr = 1.
Machine Cycle- 2:
MRMC: Status signals IO/M=0, S1=1, S0=0
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
T3: RD = 1, , (Z) AD7-AD0

Machine Cycle- 3:
MRMC: Status signals IO/M=0, S1=1, S0=0
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
T3: RD = 1, , (W) AD7-AD0

Machine Cycle- 4:
MRMC: Status signals IO/M=0, S1=1, S0=0
T1: A15-A8 (W), AD7-AD0 (Z), ALE =
T2: RD = 0, AD7-AD0 M(AB)
T3: RD = 1, , (L) AD7-AD0

Machine Cycle- 5:
MRMC: Status signals IO/M=0, S1=1, S0=0
T1: A15-A8 (W), AD7-AD0 (Z+1), ALE =
T2: RD = 0, AD7-AD0 M(AB)
T3: RD = 1, , (H) AD7-AD0
The instruction requires 5 machine cycles- OFMC & fours MRMC and
total number of 16 states. It needs 8.0µsec using 2 MHz internal
clock. The data flow during the execution of instruction is shown in
fig.5.9.

Memory
X 3 X2 X 1 X0 2A H N

Y1Y0 N+1 Y3 Y2 Y1 Y0 Z1 Z0
16 AB
Y3Y2 N+2 Z3 Z2

X3 X 2 X1 X 0
Y 3Y2 Y 1Y 0
PC
W Z Z3Z2 Z1Z0

8 H L

BDB

IR

Fig.5.9 Data Flow during the Execution of LHLD Addr Instruction

10. SHLD ADDR: This is an ALP statement. SHLD is the mnemonic


for STORE (H, L) REGISTER PAIR DIRECT. The meaning of the
instruction is the “Store the content of (L) register into the memory
location whose address is available as 2nd & 3rd byte of the instruction
itself and store the content of (H) register into the memory location
whose address is next higher address”. The instruction format is

0 0 1 0 0 0 1 0 N

<B2> N+1

<B3> N+2
The macro RTL implemented is
M(B3, B2) (L)
M((B3, B2) + 1) (H)
This instruction has no variation. The addressing mode is direct
addressing mode. The data flow during the execution of instruction is
shown in fig.5.10.

Memory
X 3 X2 X 1 X0 22 H N

Y1Y0 N+1 Y3 Y2 Y1 Y0 Z1 Z0
16 AB
Y3Y2 N+2 Z3 Z2

X3 X 2 X1 X 0
Y 3Y2 Y 1Y 0
PC
W Z Z3Z2 Z1Z0

8 H L

BDB

IR

Fig.5.10 Data Flow during the Execution of SHLD Addr Instruction


The micro RTL flow is:
Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. SHLD addr = 1.

Machine Cycle- 2:
MRMC: Status signals IO/M=0, S1=1, S0=0
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
T3: RD = 1, , (Z) AD7-AD0
Machine Cycle- 3:
MRMC: Status signals IO/M=0, S1=1, S0=0
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
T3: RD = 1, , (W) AD7-AD0

Machine Cycle- 4:
MWRMC: Status signals IO/M=0, S1=0, S0=1
T1: A15-A8 (W), AD7-AD0 (Z), ALE =
T2: WR = 0, AD7-AD0 (L)
T3: WR = 1, , M(AB) AD7-AD0

Machine Cycle- 5:
MWRMC: Status signals IO/M=0, S1=0, S0=0
T1: A15-A8 (W), AD7-AD0 (Z+1), ALE =
T2: WR = 0, AD7-AD0 (H)
T3: WR = 1, , M(AB) AD7-AD0
The instruction requires 5 machine cycles- OFMC, two MRMC & two
MWRMC and total number of 16 states. It needs 8.0µsec using 2
MHz internal clock.

11. LDAX rp: This is an ALP statement. LDAX is the mnemonic for
LOAD ACCUMULATOR INDIRECTLY. As discussed earlier, the
alphabet „X‟ in the mnemonic tells that a register pair is involved in
the instruction. „rp‟ stands for register pair. The meaning of the
instruction is “Load the accumulator from the memory location whose
address is available in a register pair specified in the instruction”.
Only one operand in involved in this instruction & the operand is
available in the memory location whose address is in a register pair.
The macro RTL implemented is
(A) M(rpH, rpL)
This is a single byte instruction. The instruction format is

0 0 R P 1 0 1 0 N

There are two variations of this instruction RP = 00 for (B, C) register


pair and RP= 01 for (D, E) register pair. Note that RP = 10 and 11 are
not allowed in this instruction. The micro RTL is
Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. LDAX rp = 1.
Machine Cycle- 2:
MRMC: Status signals IO/M=0, S1=1, S0=0
T1: A15-A8 (rpH), AD7-AD0 (rpL), ALE =
T2: RD = 0, AD7-AD0 M(AB)
T3: RD = 1, , (A) AD7-AD0
This instruction requires 2 machine cycles OFMC & MRMC and 7
states. It needs 3.5 µsec using 2MHz clock. The addressing mode is
register indirect addressing mode.
12. STAX rp: This is an ALP statement. STAX is the mnemonic for
store accumulator indirectly using register indirect addressing mode.
The meaning of the instruction is “Store the content of accumulator in
the memory location whose address is available in register pair
specified in the instruction”. The macro RTL implemented is
M(rpH, rpL) (A)
This is a single byte instruction. The instruction format is

0 0 R P 0 0 1 0 N

This instruction also has only two variations. RP = 00 and 01 are


allowed for register pair (B, C) and (D, E) respectively. The micro RTL
flow is
Machine Cycle- 1:
OFMC: Status signals IO/M=0, S1=1, S0=1
T1: A15-A8 (PCH), AD7-AD0 (PCL), ALE =
T2: RD = 0, (PC) (PC) +1, AD7-AD0 M(AB)
T3: RD = 1, , (IR) AD7-AD0
T4: 𝜇𝑝 decodes the opcode. LDAX rp = 1.

Machine Cycle- 2:
MWRMC: Status signals IO/M=0, S1=0, S0=1
T1: A15-A8 (rpH), AD7-AD0 (rpL), ALE =
T2: WR = 0, AD7-AD0 (A)
T3: WR = 1, , M(AB) AD7-AD0
This instruction requires 2 machine cycles OFMC & MWRMC and 7
states. It needs 3.5 µsec using 2MHz clock. The addressing mode is
register indirect addressing mode.

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