1-to-12, Differential HCSL Fanout Buffer 8V31012

DATA SHEET

General Description Features

The 8V31012 is a 1-to-12 Differential HCSL Fanout Buffer. The • Twelve differential HCSL outputs
8V31012 is designed to translate any differential signal levels to • Translates any differential input signal (LVPECL, LVHSTL, LVDS,
differential HCSL output levels. An external reference resistor is HCSL) to HCSL levels without external bias networks
used to set the value of the current supplied to an external • Maximum output frequency: 250MHz
load/termination resistor. The load resistor value is chosen to equal
the value of the characteristic line impedance of 50. The 8V31012 • Output skew: 265ps (typical)
is characterized at an operating supply voltage of 3.3V. • VOH: 850mV (maximum)
The differential HCSL outputs, accurate crossover voltage and duty • Full 3.3V supply voltage
cycle make the 8V31012 ideal for interfacing to PCI Express and • Available in lead-free (RoHS 6) package
FBDIMM applications. • -40°C to 85°C ambient operating temperature

Block Diagram Pin Assignment

nCLK
nQ11

nQ10

GND
CLK

CLK
Q11

Q10
VDD

VDD

VDD
nc

nc
nCLK
48 47 46 45 44 43 42 41 40 39 38 37
Q6 Q0
Q0 1 36 VDD
nQ6 nQ0
nQ0 2 35 nQ9
VDD 3 34 Q9
Q7 Q1
nQ7 nQ1 Q1 4 33 GND
nQ1 5 32 nQ8
Q8 Q2
GND 6 31 Q8
nQ8 nQ2
Q2 7 8V31012 30 VDD
Q9 Q3 nQ2 8 29 nQ7
nQ9 nQ3 VDD 9 28 Q7
Q3 10 27 VDD
Q10 Q4
nQ3 11 26 nQ6
nQ10 nQ4
VDD 12 25 Q6
13 14 15 16 17 18 19 20 21 22 23 24
Q11 Q5
GND
IREF
Q4
nQ4
VDD
Q5
nQ5
VDD
VDD
nc
VDD
GND

nQ11 nQ5

IREF
48-pin, 7mm x 7mm VFQFN Package

8V31012 REVISION 1 10/21/15 1 ©2015 Integrated Device Technology, Inc.

8V31012 DATA SHEET

Pin Description and Pin Characteristic Tables

Table 1. Pin Descriptions
Number Name Type Description

1 Q0 Output Differential output pair. Differential HCSL interface levels.

2 nQ0 Output Differential output pair. Differential HCSL interface levels.

3 VDD Power Power supply pin.

4 Q1 Output Differential output pair. Differential HCSL interface levels.

5 nQ1 Output Differential output pair. Differential HCSL interface levels.

6 GND Power Power supply ground.

7 Q2 Output Differential output pair. Differential HCSL interface levels.

8 nQ2 Output Differential output pair. Differential HCSL interface levels.

9 VDD Power Power supply pin.

10 Q3 Output Differential output pair. Differential HCSL interface levels.

11 nQ3 Output Differential output pair. Differential HCSL interface levels.

12 VDD Power Power supply pin.

13 GND Power Power supply ground.

External fixed precision resistor (950) from this pin to ground provides a reference current
14 IREF Input
used for differential current-mode Qx, nQx clock outputs.

15 Q4 Output Differential output pair. Differential HCSL interface levels.

16 nQ4 Output Differential output pair. Differential HCSL interface levels.

17 VDD Power Power supply pin.

18 Q5 Output Differential output pair. Differential HCSL interface levels.

19 nQ5 Output Differential output pair. Differential HCSL interface levels.

20 VDD Power Power supply pin.

21 VDD Power Power supply pin.

22 nc unused No connect.

23 VDD Power Power supply pin.

24 GND Power Power supply ground.

25 Q6 Output Differential output pair. Differential HCSL interface levels.

26 nQ6 Output Differential output pair. Differential HCSL interface levels.

27 VDD Power Power supply pin.

28 Q7 Output Differential output pair. Differential HCSL interface levels.

29 nQ7 Output Differential output pair. Differential HCSL interface levels.

30 VDD Power Power supply pin.

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 8V31012 DATA SHEET

Table 1. Pin Descriptions

Number Name Type Description

31 Q8 Output Differential output pair. Differential HCSL interface levels.

32 nQ8 Output Differential output pair. Differential HCSL interface levels.

33 GND Power Power supply ground.

34 Q9 Output Differential output pair. Differential HCSL interface levels.

35 nQ9 Output Differential output pair. Differential HCSL interface levels.

36 VDD Power Power supply pin.

37 GND Power Power supply ground.

38 CLK Input Non-inverting differential input.

39 nCLK Input Inverting differential clock input.

40 VDD Power Power supply pin.

41 nc unused No connect.

42 Q10 Output Differential output pair. Differential HCSL interface levels.

43 nQ10 Output Differential output pair. Differential HCSL interface levels.

44 VDD Power Power supply pin.

45 Q11 Output Differential output pair. Differential HCSL interface levels.

46 nQ11 Output Differential output pair. Differential HCSL interface levels.

47 nc unused No connect.

48 VDD Power Power supply pin.

Output Driver Current

The 8V31012 outputs are HCSL differential current dr ive with
the current being set with a resistor from IREF to ground. For
a single load and a 50 PC board trace, the drive current would IREF
typically be set with a RREF of 950 which products an IREF of 1.16mA.
The IREF is multiplied by a current mirror to an output drive of
12*1.16mA or 13.90mA. See Figure 1 for current mirror and output
drive details. RREF RL RL
950Ω

Figure 1. HCSL Current Mirror and Output Drive

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8V31012 DATA SHEET

Absolute Maximum Ratings

NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. 
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond 
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for 
extended periods may affect product reliability.

Item Rating
Supply Voltage, VDD 4.6V
Inputs, VI -0.5V to VDD + 0.5V
Outputs, IO -0.5V to VDD + 0.5V
Maximum Junction Temperature 125°C
Storage Temperature, TSTG -65C to 150C

DC Electrical Characteristics
Table 2A. Power Supply DC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD Core Supply Voltage 3.135 3.3 3.465 V
IDD Power Supply Current Output Unterminated 105 mA

Table 2B. Differential DC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C

Symbol Parameter Test Conditions Minimum Typical Maximum Units
Input
IIH CLK, nCLK VDD = VIN = 3.465V 5 µA
High Current
Input
IIL CLK, nCLK VDD = 3.465V, VIN = 0V 5 µA
Low Current
VPP Peak-to-Peak Voltage1 0.15 1.3 V
1, 2
VCMR Common Mode Input Voltage GND + 0.5 VDD – 0.85 V
NOTE 1. VIL should not be less than -0.3V.
NOTE 2. Common mode input voltage is defined as VIH.

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 8V31012 DATA SHEET

AC Electrical Characteristics
Table 3. HCSL AC Characteristics, VDD = 3.3V±5%, TA = -40°C to 85°C1, 2, 3
Symbol Parameter Test Conditions Minimum Typical Maximum Units
fMAX Output Frequency 250 MHz
4
tPD Propagation Delay Measured on at VOX 2.35 2.75 ns
tsk(o) Output Skew5, 6 Measured on at VOX 265 395 ps
tsk(pp) Part-to-Part Skew6, 7 335 ps
Buffer Additive Phase Jitter, RMS; refer CLK = 200MHz, Integration
tjit 0.15 ps
to Additive Phase Jitter Section Range: 12kHz – 30MHz
VMAX Absolute Max Output Voltage8 ƒ  150MHz 500 850 mV
VMIN Absolute Min Output Voltage 8
ƒ  150MHz -150 150 mV
VCROSS Absolute Crossing Voltage9, 10, 11 250 550 mV
Total Variation of VCROSS over all
VCROSS 140 mV
edges9, 10, 12
Rise/Fall Edge Rate13, 14 0.6 4.0 V/ns
15
Rise/Fall Time Matching 20 %
odc Output Duty Cycle16 45 55 %
NOTE 1. Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 2. Current adjust set for VOH = 0.7V. Measurements refer to PCIEX outputs only.
NOTE 3. Characterized using an RREF value of 950 resistor.
NOTE 4. Measured from the differential input cross point to the differential output crossing point.
NOTE 5. Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential output
cross point.
NOTE 6. This parameter is defined in accordance with JEDEC Standard 65.
NOTE 7. Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross point.
NOTE 8. Measurement using RREF = 950, RLOAD = 50.
NOTE 9. Measurement taken from single-ended waveform.
NOTE 10. Measured at crossing point where the instantaneous voltage value of the rising edge of Qx equals the falling edge of nQx.
See Parameter Measurement Information Section.
NOTE 11. Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement. See Parameter Measurement Information Section.
NOTE 12. Defined as the total variation of all crossing voltage of rising Qx and falling nQx. This is the maximum allowed variance in the
VCROSS for any particular system. See Parameter Measurement Information Section.
NOTE 13. Measurement taken from differential waveform.
NOTE 14. Measurement from -150mV to +150mV on the differential waveform (derived from Qx minus nQx). The signal must be monotonic
through the measurement region for rise and fall time. The 300mV measurement window is centered on the differential zero crossing.
NOTE 15. Matching applies to rising edge rate for Qx and falling edge rate for nQx. It is measured using a ±75mV window centered on the
median cross point where Qx rising meets nQx falling.
NOTE 16. Assuming 50% input duty cycle. Data taken at ƒ  200MHz, unless otherwise specified.

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 8V31012 DATA SHEET

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental of the power in the 1Hz band to the power in the fundamental. When
compared to the power of the fundamental is called the dBc Phase the required offset is specified, the phase noise is called a dBc value,
Noise. This value is normally expressed using a Phase noise plot which simply means dBm at a specified offset from the fundamental.
and is most often the specified plot in many applications. Phase noise By investigating jitter in the frequency domain, we get a better
is defined as the ratio of the noise power present in a 1Hz band at a understanding of its effects on the desired application over the entire
specified offset from the fundamental frequency to the power value of time record of the signal. It is mathematically possible to calculate an
the fundamental. This ratio is expressed in decibels (dBm) or a ratio expected bit error rate given a phase noise plot.
SSB Phase Noise dBc/Hz

Offset from Carrier Frequency (Hz)

As with most timing specifications, phase noise measurements have The additive phase jitter for this device was measured using a
issues relating to the limitations of the measurement equipment. The Stanford Research Systems CG635 input source and an Agilent
noise floor of the equipment can be higher or lower than the noise E5052 phase noise analyzer.
floor of the device. Additive phase noise is dependent on both the
noise floor of the input source and measurement equipment.

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 8V31012 DATA SHEET

Applications Information

Recommendations for Unused Output Pins

Outputs:
Differential Outputs
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.

Wiring the Differential Input to Accept Single-Ended Levels

Figure 2 shows how a differential input can be wired to accept single equal the transmission line impedance. For most 50 applications,
ended levels. The reference voltage V1= VDD/2 is generated by the R3 and R4 can be 100. The values of the resistors can be increased
bias resistors R1 and R2. The bypass capacitor (C1) is used to help to reduce the loading for slower and weaker LVCMOS driver. When
filter noise on the DC bias. This bias circuit should be located as close using single-ended signaling, the noise rejection benefits of
to the input pin as possible. The ratio of R1 and R2 might need to be differential signaling are reduced. Even though the differential input
adjusted to position the V1in the center of the input voltage swing. For can handle full rail LVCMOS signaling, it is recommended that the
example, if the input clock is driven from a single-ended 2.5V amplitude be reduced while maintaining an edge rate faster than 
LVCMOS driver and the DC offset (or swing center) of this signal is 1V/ns. The datasheet specifies a lower differential amplitude,
1.25V, the R1 and R2 values should be adjusted to set the V1 at however this only applies to differential signals. For single-ended
1.25V. The values below are for when both the single ended swing applications, the swing can be larger, however VIL cannot be less
and VDD are at the same voltage. This configuration requires that the than -0.3V and VIH cannot be more than VDD + 0.3V. Though some
sum of the output impedance of the driver (Ro) and the series of the recommended components might not be used, the pads
resistance (Rs) equals the transmission line impedance. In addition, should be placed in the layout. They can be utilized for debugging
matched termination at the input will attenuate the signal in half. This purposes. The datasheet specifications are characterized and
can be done in one of two ways. First, R3 and R4 in parallel should guaranteed by using a differential signal.

Figure 2. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels

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8V31012 DATA SHEET

Differential Clock Input Interface

The CLK/nCLK accepts HCSL, LVDS, LVPECL and LVHSTL and Please consult with the vendor of the driver component to confirm the
other differential signals. Both differential signals must meet the VPP driver termination requirements. For example in Figure 3A, the input
and VCMR input requirements. Figure 3A to Figure 3E show interface termination applies for IDT open emitter LVHSTL drivers. If you are
examples for the CLK, nCLK input driven by the most common driver using an LVHSTL driver from another vendor, use their termination
types. The input interfaces suggested here are examples only. recommendation.

3.3V
1.8V

Zo = 50Ω
CLK

Zo = 50Ω
nCLK

LVHSTL Differential
Input
R1 R2
IDT 50Ω 50Ω
LVHSTL Driver

Figure 3A. CLK/nCLK Input Driven by an IDT Figure 3D. CLK/nCLK Input Driven by a 
Open Emitter LVHSTL Driver 3.3V LVPECL Driver

3.3V
3.3V
3.3V 3.3V
R3 R4 3.3V
125 125 Zo = 50Ω
Zo = 50Ω
CLK
CLK
Zo = 50Ω R1
100
nCLK
nCLK
LVPECL Differential Zo = 50Ω
Input Differential
R1 R2 LVDS
Input
84 84

Figure 3B. CLK/nCLK Input Driven by a  Figure 3E. CLK/nCLK Input Driven by a 3.3V LVDS Driver
3.3V LVPECL Driver

3.3V 3.3V

*R3
CLK

nCLK
*R4 Differential
HCSL Input

Figure 3C. CLK/nCLK Input Driven by a

3.3V HCSL Driver

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 8V31012 DATA SHEET

Recommended Termination
Figure 4A is the recommended source termination for applications All traces should be 50Ω impedance single-ended or 100Ω
where the driver and receiver will be on a separate PCBs. This differential.
termination is the standard for PCI Express™and HCSL output types.

Rs
0.5" Max 0-0.2" 1-14" 0.5 - 3.5"
22 to 33 +/-5%
L1 L2 L4 L5

L1 L2 L4 L5
PCI Expres s
PCI Expres s
Connector
Driver PCI Expres s
0-0.2" L3 L3
Add-in Card

Rt 49.9 +/- 5%

Figure 4A. Recommended Source Termination (where the driver and receiver will be on separate PCBs)

Figure 4B is the recommended termination for applications where a be minimized. In addition, a series resistor (Rs) at the driver offers
point-to-point connection can be used. A point-to-point connection flexibility and can help dampen unwanted reflections. The optional
contains both the driver and the receiver on the same PCB. With a resistor can range from 0Ω to 33Ω. All traces should be 50Ω
matched termination at the receiver, transmission-line reflections will impedance single-ended or 100Ω differential.

Rs
0.5" Max 0-18" 0-0.2"
0 to 33
L1 L2 L3

0 to 33
L1 L2 L3

PCI Expres s
Driver Rt 49.9 +/- 5%

Figure 4B. Recommended Termination (where a point-to-point connection can be used)

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8V31012 DATA SHEET

EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and and dependent upon the package power dissipation as well as
the electrical performance, a land pattern must be incorporated on electrical conductivity requirements. Thus, thermal and electrical
the Printed Circuit Board (PCB) within the footprint of the package analysis and/or testing are recommended to determine the minimum
corresponding to the exposed metal pad or exposed heat slug on the number needed. Maximum thermal and electrical performance is
package, as shown in Figure 5. The solderable area on the PCB, as achieved when an array of vias is incorporated in the land pattern. It
defined by the solder mask, should be at least the same size/shape is recommended to use as many vias connected to ground as
as the exposed pad/slug area on the package to maximize the possible. It is also recommended that the via diameter should be 12
thermal/electrical performance. Sufficient clearance should be to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is
designed on the PCB between the outer edges of the land pattern desirable to avoid any solder wicking inside the via during the
and the inner edges of pad pattern for the leads to avoid any shorts. soldering process which may result in voids in solder between the
exposed pad/slug and the thermal land. Precautions should be taken
While the land pattern on the PCB provides a means of heat transfer to eliminate any solder voids between the exposed heat slug and the
and electrical grounding from the package to the board through a land pattern. Note: These recommendations are to be used as a
solder joint, thermal vias are necessary to effectively conduct from guideline only. For further information, refer to the Application Note
the surface of the PCB to the ground plane(s). The land pattern must on the Surface Mount Assembly of Amkor’s Thermally/Electrically
be connected to ground through these vias. The vias act as “heat Enhance Leadframe Base Package, Amkor Technology.
pipes”. The number of vias (i.e. “heat pipes”) are application specific

SOLDER
SOLDER SOLDER
PIN EXPOSED HEAT SLUG PIN

PIN PAD GROUND PLANE LAND PATTERN PIN PAD

THERMAL VIA (GROUND PAD)

Figure 5. Assembly for Exposed Pad Thermal Release Path - Side View (drawing not to scale)

1-TO-12, DIFFERENTIAL HCSL FANOUT BUFFER 10 REVISION 1 10/21/15

 8V31012 DATA SHEET

Power Considerations
This section provides information on power dissipation and junction temperature for the 8V31012. 
Equations and example calculations are also provided.

1. Power Dissipation.
The total power dissipation for the 8V31012 is the sum of the core power plus the power dissipated in the load(s). 
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.

Power (core)MAX = VDD_MAX * (IDD_MAX) = 3.465V *(105mA) = 363.825mW
• Power (outputs)MAX = 44.5mW/Loaded Output pair
If all outputs are loaded, the total power is 12 * 44.5mW = 534mW

Total Power_MAX = (3.465V, with all outputs switching) = 363.825mW + 534mW = 897.825mW

2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature

In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 29°C/W per Table 4 below.

Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.898W *29°C/W = 111°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).

Table 4. Thermal Resistance JA for 48Lead VFQFN, E-Pad, Forced Convection
JA vs. Air Flow
Meters per Second 0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 29.0°C/W 25.4°C/W 22.7°C/W

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8V31012 DATA SHEET

3. Calculations and Equations.

The purpose of this section is to calculate power dissipation on the IC per HCSL output pair.
HCSL output driver circuit and termination are shown in Figure 6.

VDDO

IOUT = 17mA
➤

VOUT
RREF =
475Ω ± 1%

RL
50Ω

IC
Figure 6. HCSL Driver Circuit and Termination

HCSL is a current steering output which sources a maximum of 17mA of current per output. To calculate worst case on-chip power dissipation,
use the following equations which assume a 50 load to ground.

The highest power dissipation occurs when VDDO_MAX.

Power = (VDDO_MAX – VOUT) * IOUT, 

since VOUT – IOUT * RL

= (VDDO_MAX – IOUT * RL) * IOUT

= (3.465V – 17mA * 50) * 17mA

Total Power Dissipation per output pair = 44.5mW

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 8V31012 DATA SHEET

Reliability Information
Table 5. JA vs. Air Flow Table for a 48 Lead VFQFN, E-Pad, Forced Convention
JA vs. Air Flow
Meters per Second 0 1 2.5
Multi-Layer PCB, JEDEC Standard Test Boards 29.0°C/W 25.4°C/W 22.7°C/W

Transistor Count
The transistor count for 8V31012 is: 843

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8V31012 DATA SHEET

48-Lead VFQFN (NL) Package Outline and Package Dimensions

Table 6. Package Dimensions for 48-Lead Package1

DIMENSIONS
SYMBOL MIN NOM MAX
D 7.00 BSC
E 7.00 BSC
D2 5.50 5.65 5.80
E2 5.50 5.65 5.80
L 0.35 0.40 0.45
e 0.50 BSC
N 48
A 0.80 0.85 0.90
A1 0.00 0.02 0.05
A3 0.2 REF
b 0.18 0.25 0.30
NOTE 1. The drawing and dimension data originates from IDT
Package Outline Drawing PSC-4203, Rev 04.
All dimensions are in millimeters. All angles are in
degrees.

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 8V31012 DATA SHEET

Package Outline and Package Dimensions (Continued)

RECOMMENDED LAND PATTERN

NOTE:

THE RECOMMENDED LAND PATTERN ORIGINATES FROM IDT PACKAGE 
OUTLINE DRAWING PSC‐4203, REV04.

1. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN 
DEGREES.

2. TOP DOWN VIEW. AS VIEWED ON PCB.

3. COMPONENT OUTLINE SHOW FOR REFERENCE IN BLACK.

4. LAND PATTERN IN BLUE. NSMD PATTERN ASSUMED.

5. LAND PATTERN RECOMMENDATION PER IPC‐7351B GENERIC 
REQUIREMENT FOR SURFACE MOUNT DESIGN AND LAND 
PATTERN.

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8V31012 DATA SHEET

Ordering Information
Table 7. Ordering Information
Part/Order Number Marking Package Shipping Packaging Temperature
8V31012NLGI IDT8V31012NLGI 48 Lead VFQFN, Lead-Free Tray -40°C to 85°C
8V31012NLGI8 IDT8V31012NLGI 48 Lead VFQFN, Lead-Free Tape & Reel -40°C to 85°C

1-TO-12, DIFFERENTIAL HCSL FANOUT BUFFER 16 REVISION 1 10/21/15

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