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    CSE369 Wi22 Quiz1 Soln

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    Deniz Melek Türk
    This 3-sentence summary provides the key details from the document: The document is a quiz for a computer science course covering combinational logic gates, Karnaugh maps, and Verilog. It contains 3 questions - the first asks students to write Boolean expressions and minimize logic circuits, the second asks them to find minimum sum-of-products solutions using a Karnaugh map, and the third evaluates Verilog code and asks students to draw logic circuits based on given gate delays.

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    CSE369 Wi22 Quiz1 Soln

    Uploaded by

    Deniz Melek Türk
    17 views3 pages
    This 3-sentence summary provides the key details from the document: The document is a quiz for a computer science course covering combinational logic gates, Karnaugh maps, and Verilog. It contains 3 questions - the first asks students to write Boolean expressions and minimize logic circuits, the second asks them to find minimum sum-of-products solutions using a Karnaugh map, and the third evaluates Verilog code and asks students to draw logic circuits based on given gate delays.

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    This 3-sentence summary provides the key details from the document: The document is a quiz for a computer science course covering combinational logic gates, Karnaugh maps, and Verilog. It contains 3 questions - the first asks students to write Boolean expressions and minimize logic circuits, the second asks them to find minimum sum-of-products solutions using a Karnaugh map, and the third evaluates Verilog code and asks students to draw logic circuits based on given gate delays.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    17 views3 pages

    CSE369 Wi22 Quiz1 Soln

    Uploaded by

    Deniz Melek Türk
    This 3-sentence summary provides the key details from the document: The document is a quiz for a computer science course covering combinational logic gates, Karnaugh maps, and Verilog. It contains 3 questions - the first asks students to write Boolean expressions and minimize logic circuits, the second asks them to find minimum sum-of-products solutions using a Karnaugh map, and the third evaluates Verilog code and asks students to draw logic circuits based on given gate delays.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 3

    U niversity of W ashington – C om puter Science & Engineering

    Winter 2022 Instructor: Justin Hsia 2022-02-01

    N am e: _Perry_Perfect_______________
    Student ID
    N um ber: _1234567______

    P lease do not turn the page until 1 2:30.

    Instructions
    • This quiz contains 3 pages, including this cover page. You may use the backs of the
    pages for scratch work.
    • Please clearly indicate (box, circle) your final answer.
    • The quiz is closed book and closed notes.
    • Please silence and put away all cell phones and other mobile or noise-making devices.
    • Remove all hats, headphones, and watches.
    • You have 20 (+5) minutes to complete this quiz.

    A dvice
    • Read questions carefully before starting. Read all questions first and start where you
    feel the most confident to maximize the use of your time.
    • There may be partial credit for incomplete answers; please show your work.
    • Relax. You are here to learn.

    Question P oints Score


    (1) CL Gates 8 8
    (2) K-map 5 5
    (3) Waveforms & Verilog 12 12
    Total: 25 25
    Question 1: Combinational Logic Gates [8 pts]
    (A) Write out a Boolean expression for the circuit diagram below. No need to simplify.
    Remember to use + (OR), ⋅ (AND), and ̅ (NOT) as well as any necessary parentheses
    to make your answer unambiguous. [2 pts] 𝐅 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
    (𝐀 ⋅ 𝐁̅ ) + (𝐁 + ̅̅̅̅̅̅
    𝐀 ⋅ 𝐂)

    X X=A⋅B ̅ [0.5 pt]


    Y = ̅̅̅̅̅̅
    A⋅C [0.5 pt]
    Z Z=B+Y [0.5 pt]
    Y
    F = ̅̅̅̅̅̅̅
    X+Z [0.5 pt]

    (B) Find a minimal implementation of the function below using only 2-input N OR gates.
    We will only accept circuit diagrams. [6 pts]

    ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
    𝐹 = (A + B)̅̅̅̅
    C̅D

    [2 pt] Valid gate conversion


    from expression
    [2 pt] DeMorgan’s
    applications (either in
    expression or gates)
    [2 pt] Conversion of extra
    NOTs to NORs

    Question 2: Karnaugh Maps [5 pts]


    Find the minimum sum-of-products solution for the K-map shown below.

    1 0 0 1

    0 0 0 0
    D
    1 0 1 1 [2 pt] X choices
    C [1 pt each] correct term/grouping
    1 0 1 1 [-0.5 pt each] smaller grouping used
    [-0.5 pt each] extra grouping included
    B

    2
    Question 3: Waveforms & Verilog [12 pts]
    (A) Consider the Verilog simulated testbench waveforms shown. If we know that X and Y
    are outputs of 2-input logic gates, complete the module Mystery below. [7 pt]

    For both X and Y:


    [2 pt] Correct input signals
    [1 pt] Correct gate used
    Overall:
    [1 pt] Correct Verilog syntax

    module Mystery (F, A, B, C);


    output F;
    input A, B, C;
    wire X, Y;
    nor G1 (X, A, C); or assign X = ~(A | C);
    and G2 (Y, B, X); or assign Y = B & X;
    xnor G3 (F, X, Y);
    endmodule

    (B) We only have the 2-input logic gates at right X OR NAND OR


    available to us. Given the logic delays shown, 6 ns 7 ns 10 ns
    draw out the circuit diagram of the fastest
    implementation of the Verilog statement below. [5 pts]
    Hint: Build a truth table first.

    assign F = B ^ (~A | B);

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