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Mips Ref Sheet

This document provides a reference sheet for the MIPS instruction set architecture including: - Instruction names, formats, and operations for common instructions like add, load, store, branch, and others. - Register names and numbers for common registers like $zero, $v0, $t0, $ra. - Pseudoinstruction names, examples, and equivalent basic instructions like la, li, move, nop. - Assembler directive names for declaring data sections, strings, word/byte values, and alignment.

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Dimas Azi
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0% found this document useful (0 votes)
67 views1 page

Mips Ref Sheet

This document provides a reference sheet for the MIPS instruction set architecture including: - Instruction names, formats, and operations for common instructions like add, load, store, branch, and others. - Register names and numbers for common registers like $zero, $v0, $t0, $ra. - Pseudoinstruction names, examples, and equivalent basic instructions like la, li, move, nop. - Assembler directive names for declaring data sections, strings, word/byte values, and alignment.

Uploaded by

Dimas Azi
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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MIPS)Reference)Sheet)) David#Broman,#KTH#Royal#InsZtute#of#Technology#

Version#1.12,#November#6,#2015#

INSTRUCTIONS)(SUBSET)) REGISTERS)
) )
Name)(format,)op,)funct))) )Syntax) ) )Opera<on) Name) )Number) )Descrip<on)
add#(R,0,32) # #add rd,rs,rt #reg(rd)#:=#reg(rs)#+#reg(rt);## $0,#$zero #0 #constant#value#0#
add#immediate#(I,8,na) #addi rt,rs,imm #reg(rt)#:=#reg(rs)#+#signext(imm);# $at #1 #assembler#temp#
add#immediate#unsigned#(I,9,na) #addiu rt,rs,imm #reg(rt)#:=#reg(rs)#+#signext(imm);# $v0 #2 #funcZon#return##
add#unsigned#(R,0,33)# #addu rd,rs,rt #reg(rd)#:=#reg(rs)#+#reg(rt);# $v1 #3 #funcZon#return#
and#(R,0,36) # #and rd,rs,rt #reg(rd)#:=#reg(rs)#&#reg(rt);# $a0 #4 #argument#
and#immediate#(I,12,na) #andi rt,rs,imm #reg(rt)#:=#reg(rs)#&#zeroext(imm);# $a1 #5 #argument#
branch#on#equal#(I,4,na) #beq rs,rt,label #if#reg(rs)#==#reg(rt)#then#PC#=#BTA#else#NOP;# $a2 #6 #argument#
branch#on#not#equal#(I,5,na) #bne rs,rt,label #if#reg(rs)#!=#reg(rt)#then#PC#=#BTA#else#NOP;# $a3 #7 #argument#
jump#and#link#register#(R,0,9) #jalr rs # #$ra#:=#PC#+#4;###PC#:=#reg(rs);# $t0 #8 #temporary#value#
jump#register#(R,0,8) # #jr rs # #PC#:=#reg(rs);# $t1 #9 #temporary#value#
jump#(J,2,na) # #j label #PC#:=#JTA;### $t2 #10 #temporary#value#
jump#and#link#(J,3,na) # #jal label #$ra#:=#PC#+#4;###PC#:=#JTA;# $t3 #11 #temporary#value#
load#byte#(I,32,na) # #lb rt,imm(rs) #reg(rt)#:=#signext(mem[reg(rs)#+#signext(imm)]7:0);) $t4 #12 #temporary#value#
load#byte#unsigned#(I,36,na) #lbu rt,imm(rs) #reg(rt)#:=#zeroext(mem[reg(rs)#+#signext(imm)]7:0);# $t5 #13 #temporary#value#
load#upper#immediate#(I,15,na) #lui rt,imm #reg(rt)#:=#concat(imm,#16#bits#of#0);# $t6 #14 #temporary#value#
load#word#(I,35,na) # #lw rt,imm(rs) #reg(rt)#:=#mem[reg(rs)#+#signext(imm)];) $t7 #15 #temporary#value#
mulZply,#32[bit#result#(R,28,2) #mul rd,rs,rt #reg(rd)#:=#reg(rs)#*#reg(rt);# $s0 #16 #saved#temporary#
nor#(R,0,39) # #nor rd,rs,rt reg(rd)#:=#not(reg(rs)#|#reg(rt));# $s1 #17 #saved#temporary#
or#(R,0,37)# # #or rd,rs,rt #reg(rd)#:=#reg(rs)#|#reg(rt);# $s2 #18 #saved#temporary#
or#immediate#(I,13,na) #ori rt,rs,imm #reg(rt)#:=#reg(rs)#|#zeroext(imm);# $s3 #19 #saved#temporary#
set#less#than#(R,0,42) # #slt rd,rs,rt #reg(rd)#:=#if#reg(rs)#<#reg(rt)#then#1#else#0;# $s4 #20 #saved#temporary#
set#less#than#unsigned#(R,0,43) #sltu rd,rs,rt #reg(rd)#:=#if#reg(rs)#<#reg(rt)#then#1#else#0;# $s5 #21 #saved#temporary#
set#less#than#immediate#(I,10,na)#slti rt,rs,imm #reg(rt)#:=#if#reg(rs)#<#signext(imm)#then#1#else#0;# $s6 #22 #saved#temporary#
set#less#than#immediate# #sltiu rt,rs,imm #reg(rt)#:=#if#reg(rs)#<#signext(imm)#then#1#else#0;# $s7 #23 #saved#temporary#
####unsigned#(I,11,na) # # # #(inequality#<#compares#using#unsigned#values)# $t8 #24 #temporary#value#
shia#lea#logical#(R,0,0) #sll rd,rt,shamt #reg(rd)#:=#reg(rt)#<<#shamt;# $t9 #25 #temporary#value#
shia#lea#logical#variable#(R,0,4) #sllv rd,rt,rs reg(rd)#:=#reg(rt)#<<#reg(rs4:0);# $k0 #26 #reserved#for#OS#
shia#right#arithmeZc#(R,0,3) #sra rd,rt,shamt #reg(rd)#:=#reg(rt)#>>>#shamt;# $k1 #27 #reserved#for#OS#
shia#right#logical#(R,0,2) #srl rd,rt,shamt #reg(rd)#:=#reg(rt)#>>#shamt;# $gp #28 #global#pointer#
shia#right#logical#variable#(R,0,6) #srlv rd,rt,rs reg(rd)#:=#reg(rt)#>>#reg(rs4:0); ## $sp #29 #stack#pointer#
store#byte#(I,40,na) # #sb rt,imm(rs) #mem[reg(rs)#+#signext(imm)]7:0#:=#reg(rt)7:0;# $fp #30 #frame#pointer#
store#word#(I,43,na) # #sw rt,imm(rs) #mem[reg(rs)#+#signext(imm)]#:=#reg(rt);# $ra #31 #return#address#
subtract#(R,0,34) # #sub rd,rs,rt reg(rd)#:=#reg(rs)#[#reg(rt);#
subtract#unsigned#(R,0,35) #subu rd,rs,rt #reg(rd)#:=#reg(rs)#[#reg(rt);#
xor#(R,0,38) # #xor rd,rs,rt reg(rd)#:=#reg(rs)#^#reg(rt);# Defini<ons))
xor#immediate#(I,14,na) #xori rt,rs,imm #reg(rt)#:=#rerg(rs)#^#zeroext(imm);# !  Jump#to#target#address:##
# JTA#=#concat((PC#+#4)31:28,#
PSEUDO)INSTRUCTIONS)(SUBSET)) address(label),#002)#
!  Branch#target#address:##
#

Name ) ) )Example ) )))))))))Equivalent)Basic)Instruc<ons)


load#address# # #la $t0,label lui $at,hi-bits-of-address BTA#=#PC#+#4#+#signext(imm)#*#4#
# # # ori $t0,$at,lower-bits-of-address# #
load#immediate # #li $t0,0xabcd1234 lui $at,0xabcd Clarifica<ons)
ori $t0,$at,0x1234 !  All#numbers#are#given#in#decimal#
branch#if#less#or#equal# #ble $t0,$t1,label slt $at,$t1,$t0 form#(base#10).#
beq $at,$zero,label !  FuncZon#signext(x)#returns#a#32[bit#
move # # #move $t0,$t1 addi $t0,$t1,$zero sign#extended#value#of#x#in#two’s#
no#operaZon # #nop sll $zero,$zero,0 complement#form.#
#
!  FuncZon#zeroext(x)#returns#a#32[bit#
ASSEMBLER)DIRECTIVES)(SUBSET)) value,#where#zero#are#added#to#the#
data#secZon# # #.data most#significant#side#of#x.#
ASCII#string#declaraZon# #.ascii "a string" !  FuncZon#concat(x,#y,#…,#z)#
word#alignment # #.align 2 concatenates#the#bits#of#expressions#
word##value#declaraZon# #.word 99 x,#y,#…,#z.##
byte#value#declaraZon #.byte 7 !  Subscripts,#for#instance#X8:2,#means#
global#declaraZon # #.global foo that#bits#with#index#8#to#2#are#spliced#
allocate#X#bytes#of#space .space X out#of#the#integer#X.#
code#secZon######### .text !  FuncZon#address(x)#means#the#
address#of#label#x.#
!  NOP#and#na#mean#“no#operaZon”#
INSTRUCTION)FORMAT) and#“not#applicable”,#respecZvely.#
)))))) 31) 26) 25) 21) 20) 16) 15) 11) 10) 6) 5) 0) !  shamt#is#an#abbreviaZon#for#“shia#
))))))RPType) op) rs) rt) rd) shamt) funct) amount”,#i.e.#how#many#bits#that#
) should#be#shiaed.#
) 6)bits) 5)bits) 5)bits) 5)bits) 5)bits) 6)bits) !  addu#and#addiu#are#misnamed#
)
31) 26) 25) unsigned#because#an#add#operaZon#
) 21) 20) 16) 15) 0)
handles#both#signed#and#unsigned#
))))))IPType) op) rs) rt) immediate) numbers#in#the#same#way.#The##term#
) unsigned#is#actually#used#to#describe#
6)bits) 5)bits) 5)bits) 16)bits)
) that#the#instrucZon#does#not#throw#
) 31) 26) 25) 0) overflow##excepZons.#
) #
op) address) #

))))))JPType) #
#
)
6)bits) 26)bits) #

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