14ECPU0 ASIC DESIGN

Dr.N.B.BALAMURUGAN,
Professor
ECE Department
Thiagarajar College of Engineering
Madurai-15
Email : [email protected],
9894346320
 An Introduction
ASIC - Application Specific Integrated Circuit

2
 18EC7PY0 : ASIC DESIGN

• Preamble
• 14EC270 : Digital Logic Circuit Design
• 14EC520 : Digital CMOS Systems

• Objective
This course provide the students, the knowledge about
– Physical design flow
• Logic synthesis, Floor-planning, Placement and Routing
– Experiments explore complete digital design flow of
programmable ASIC through VLSI EDA tools.
– Students work from design entry using verilog code to GDSII file
generation of an ASIC.

3
Concept MAP

4
 Course Outcomes
CO1 Describe the design flow, types and the programming Understand
technologies of an ASIC and its construction.
CO2 Describe the goals, objectives, measurements and Apply
algorithms of partitioning then apply those algorithms to
partition the network to meet the objectives.
CO3 Describe the goals, objectives, measurements and Apply
algorithms of floorplanning & placement then apply those
algorithms to place the logic cells inside the flexible blocks
of an ASIC to meet the objectives.
CO4 Describe the goals, objectives, measurements and Analyze
algorithms of routing then apply those algorithms to route
the channels then describing various circuit extraction
formats and Investigate the issues and discover solutions in
each step of physical design flow of an ASIC.
CO5 Design an ASIC for digital circuits with ASIC design flow Analyze
steps consists of simulation, synthesis, floorplanning,
placement, routing, circuit extraction and generate GDSII
File for fabrication of an ASIC, then analyze the ASIC to
meet the performance in terms of area, speed and power
using EDA tools. 5
6
 Integrated Circuit
 Wafer : A circular piece of pure silicon (10-15 cm in dia, but
wafers of 30 cm dia are expected soon)
 Wafer Lot: 5 ~ 30 wafers, each containing hundreds of
chips(dies) depending upon size of the die
 Die: A rectangular piece of silicon that contains one
IC design
 Mask Layers: Each IC is manufactured with successive
mask layers(10 – 15 layers)
 First half-dozen or so layers define transistors
 Other half-dozen define Interconnect

7
Integrated Circuit (IC) in a package

(a) A pin-grid array (PGA) package.

(b) The silicon die or chip is under the package lid.

8
 Evolution of IC
• SSI (Small-Scale Integration)-(1962)
– Tens of Transistors
– NAND, NOR

• MSI (Medium-Scale Integration)-(late 1960)

– Hundreds of Transistors
– Counters

• LSI (Large-Scale Integration)-(mid 1970)

– Tens of Thousands of Transistors
– First Microprocessor

• VLSI (Very Large-Scale Integration)-(1980)

– started Hundreds of Thousands of Transistors-several billion transistors in 2009
– 64 bit Microprocessor with cache memory and floating-point arithmetic units

• ULSI (Ultra Large-Scale Integration)-(late 1980)

– More than about one million circuit elements on a single chip.
– The Intel 486 and Pentium microprocessors, use ULSI technology
9
 IC technologies
• Bipolar
– More accuracy
• MOS
– Gate-Aluminium
– Low power consumption
– Low cost
• CMOS
– Gate-Poly-Silicon
– Low power consumption
– Low cost
• BiCMOS 10
 Types of IC
• Standard ICs
• Glue Logic- a special form of digital circuitry that
allows different types of logic chips or circuits to
work together by acting as an interface between
them.
• ASIC
• ASSP (Application-Specific Standard Products)

11
12
 ASIC and Non ASIC
• Examples of ICs that are not ASICs include standard parts such as:
– memory chips sold as a commodity item—ROMs, DRAM, and SRAM;
microprocessors;
– TTL or TTL-equivalent ICs at SSI, MSI, and LSI levels.

• Examples of ICs that are ASICs include:

– a chip for a toy bear that talks;
– a chip for a satellite;
– a chip designed to handle the interface between memory and a
microprocessor for a workstation CPU;
– a chip containing a microprocessor as a cell together with other logic.

• ASSP (two ICs that might or might not be considered ASICs )

– controller chip for a PC and a chip for a modem.
– Both of these examples are specific to an application (shades of an ASIC)
but are sold to many different system vendors (shades of a standard part).
ASICs such as these are sometimes called application-specific standard13
products ( ASSPs ).
 Measurement of IC
• Gate Equivalent
– Number of gates or transistors
– Gate refer to two input NAND Gate
– In CMOS, each NAND gate consist of 4 transistors
– Example : 10k gate IC
– (10,000 two-input NAND gates or 40,000 transistors in
CMOS)

• Feature Size (smallest feature size =  )

– Half of smallest transistor length
– Example: 0.5µm IC
– Feature size,  = 0.25µm
14
 Types of ASICs – Cont’d

• Full-Custom ASICs: Possibly all logic cells and all mask layers customized
• Semi-Custom ASICs: all logic cells are pre-designed and some (possibly all)
mask layers customized
15
 Types of ASICs – Cont’d
Full-Custom ASICs
 Include some (possibly all) customized logic cells

 Have all their mask layers customized

Manufacturing lead time is typically 8 weeks (time taken to make the IC

does not include design time)

 Full-custom ASIC design makes sense only

 When no suitable existing libraries exist or

 Existing library cells are not fast enough or

 The available pre-designed/pre-tested cells consume too much power

that a design can allow or

 The available logic cells are not compact enough to fit or

16
 ASIC technology is new or/and so special that no cell library exits.
 Types of ASICs – Cont’d
Full-Custom ASICs
 Advantages:
Offer highest performance
lowest cost (smallest die size)

Disadvantages
Increased design time
Increased Complexity
 Higher design cost
 Higher risk.

 Some Examples:
Microporcessor,
High-Voltage Automobile Control Chips
 Ana-Digi Communication Chips
 Sensors and Actuators
17
 Types of ASICs – Cont’d
 Semi-Custom ASICs
 Standard-Cell based ASICs (CBIC- “sea-bick”)

 Use predesigned logic cells (Called standard cells) from

standard cell libraries

other mega-cells (Microcontroller or Microprocessors)

full-custom blocks

System-Level Macros(SLMs)

 Functional Standard Blocks (FSBs)

 cores etc

 Get all mask layers customized- transistors and interconnect

 Manufacturing lead time is about 8 weeks

Custom blocks can be embedded

18
 Types of ASICs – Cont’d
 Semi-Custom ASICs – Cont’d
 Standard-Cell based ASICs
(CBIC- “sea-bick”) – Cont’d

19
 Types of ASICs – Cont’d
 Standard Cell in Flexible block of CBIC

• Std cell in library is constructed using full-custom design

methodology-
– Same performance and flexibility but reduce time and risk.

• ASIC designer defines only placement of standard cells

– It can be placed anywhere on silicon.

 Flexible blocks in CBIC

– Standard cells are designed like bricks in a wall.
– Groups of standard cells fit horizontally to form rows.

– The rows stack vertically to form flexible blocks- reshape during design

– Flexible blocks connected with other std cell blocks or full custom block

20
 Types of ASICs – Cont’d
 Wiring cells in Standard Cell based ASICs
•Feedthrough cell:
•Piece of metal that is used to pass a signal through a cell or to a space in a cell waiting
to be used as a feedthrough

•Spacer cells
•The width of each row of standard cells is adjusted so that they may be aligned
using spacer cells .

•Row end cells

•The power buses, or rails, are then connected to additional vertical power rails
using row-end cells at the aligned ends of each standard-cell block.

• Power cells
•If the rows of standard cells are long, then vertical power rails can also be run in
metal2 through the cell rows using special power cells that just connect to VDD
and GND.
•Usually the designer manually controls the number and width of the vertical 21
power rails connected to the standard-cell blocks during physical design.
 Types of ASICs – Cont’d
 Advantages of CBIC
– Save time, money, reduce risk

– Standard cell optimized individually for speed or area

 Disadvantages of CBIC:
– Time to design standard cell library

– Expenses of designing std cell library

– Time needed to fabricate all layers of the ASIC for new design

22
 Types of ASICs – Cont’d
 Semi-Custom ASICs – Cont’d
 Gate Array based ASICs
Transistors are predefined on the silicon wafer
Predefined pattern of transistors on a gate array is base array.
Smallest element repeated to form base array is base cell.
Only the top few layers of metal, which define the interconnect between
transistors, are defined by the designer using custom masks.It is often called a
masked gate array ( MGA ).
Less turnaroundtime: fewdays or couple of weeks.

23
Similar to CBIC –but here space is fixed
 Types of ASICs – Cont’d
 Semi-Custom ASICs – Cont’d
 Chanelless Gate Array ASIC

•The key difference between a channelless gate array and channeled

gate array
•there are no predefined areas set aside for routing between cells on
a channelless gate array.
•Use an area of transistors for routing in a channelless array, we do
not make any contacts to the devices lying underneath; we simply
leave the transistors unused.
•The logic density—the amount of logic that can be implemented
in a given silicon area is higher for channelless gate array
24
 Types of ASICs – Cont’d
 Semi-Custom ASICs – Cont’d
 Difference between Channeled and Chanelless Gate Array ASIC

•This is usually attributed to the difference in structure

between the two types of array. In fact, the difference occurs
because the contact mask is customized in a channelless
gate array, but is not usually customized in a channeled gate
array. This leads to denser cells in the channelless
architectures.

•Customizing the contact layer in a channelless gate array

allows us to increase the density of gate-array cells because
we can route over the top of unused contact sites. 25
 Types of ASICs – Cont’d
 Semi-Custom ASICs – Cont’d
 Structured Gate Array based ASICs
- Cont’d

•An embedded gate array or structured gate array (also known as masterslice or
masterimage ) combines some of the features of CBICs and MGAs.
•One of the disadvantages of the MGA is the fixed gate-array base cell. This
makes the implementation of memory, for example, difficult and inefficient.
• In an embedded gate array we set aside some of the IC area and dedicate it to
a specific function.
• This embedded area either can contain a different base cell that is more
suitable for building memory cells, or it can contain a complete circuit block,
such as a microcontroller.
26
Channelled gate array
Adv: Specific space for interconnection
Disadv: compared to CBIC space is not adjustable
Channelless gate array
Adv :
• Logic density is higher for channelless gate array
• Contact layers are customized
Disadv:
• No specific area for routing
• Rows of transistors used for routing are not used for other purpose.
Structured Gate Array
Adv:
• Embedded gate array set in some of IC area and dedicate to specific
function-customized.
• Increase area efficiency, performance of CBIC
• low cost and fast turn around of MGA
Disadv: 27
Embedded function is fixed
 Types of ASICs – Cont’d
 Semi-Custom ASICs – Cont’d
 Programmable ASICs
 PLDs - PLDs are low-density devices
which contain 1k – 10 k gates and are
available both in bipolar and CMOS
technologies [PLA, PAL or GAL]
 CPLDs or FPLDs or FPGAs -
FPGAs combine architecture of gate arrays
with programmability of PLDs.
User Configurable
 Contain Regular Structures -
circuit elements such as AND, OR,
NAND/NOR gates, FFs, Mux, RAMs,
Allow Different Programming
Technologies
 Allow both Matrix and Row-
based Architectures

28
 Programmable Logic Devices
• Programmable logic devices ( PLDs ) are standard ICs
– Available in standard configurations

– Sold in very high volume to many different customers.

– PLDs may be configured or programmed to create a part customized to a specific

application

– PLDs use different technologies to allow programming of the device.

• The important features of PLDs:

– No customized mask layers or logic cells

– Fast design turnaround

• Structure of programmable logic device (PLD)

– A single large block of programmable interconnect

– A matrix of logic macrocells that usually consist of programmable array logic

followed by a flip-flop or latch

29
 Type of PLDs-PLA and PAL
• Place a logic array as a cell on a custom
ASIC. This type of logic array is called a
programmable logic array (PLA).

• A PLA has a programmable AND logic

array, or AND plane , followed by a
programmable OR logic array, or OR
plane

• A PAL has a programmable AND plane

and, in contrast to a PLA, a fixed OR
plane.

• Depending on how the PLD is

programmed, we can have an
– Erasable PLD (EPLD),
– Mask-programmed PLD (called as
masked PLD but usually just PLD).

• The first bipolar based PALs, PLAs, and

PLDs used programmable fuses or links.

30
• CMOS PLDs usually employ floating-gate
transistors
 Types of ASICs – Cont’d
 Semi-Custom ASICs – Cont’d
 Programmable ASICs - Cont’d
 Structure of a CPLD / FPGA

31
 Essential characteristics of FPGA

• None of the mask layers are customized

• A method of programming the basic logic cells and interconnect

• Core-regular array of Programmable basic logic cells implement

combinational or sequential logic

• Matrix of programmable interconnects surround the basic logic cells

• Programmable I/O cells surround the core

• Design turnaround is few hours.

• Difference between PLD and FPGA:

– FPGA are larger and more complex than PLD

32
 Why FPGA-based ASIC Design?
 Choice is based on Many
Factors ;
Requirement FPGA/FPLD Discrete Logic Custom Logic
 Speed Speed

 Gate Density Gate Density

 Development Time Cost

 Prototyping and Simulation Development Time

Time Prototyping and Sim.

 Manufacturing Lead Time Manufacturing

 Future Modifications
Future Modification

 Inventory Risk Inventory

 Cost Development Tools

Very Effective Adequate Poor

33
Different Categorizations of FPGAs
 Based on Functional Unit/Logic
Cell Structure
 Transistor Pairs
 Basic Logic Gates: NAND/NOR
 MUX
 Look –up Tables (LUT)
 Wide-Fan-In AND-OR Gates
 Programming Technology
 Anti-Fuse Technology
 SRAM Technology
 EPROM Technology
 Gate Density
 Chip Architecture (Routing Style)

34
Different Types of Logic Cells

35
 Different Types of Logic Cells – Cont’d
 Actel Act Logic Module Structure
 Use Antifuse Programming Tech.
 Based on Channeled GA Architecture
 Logic Cell is MUX which can be configured as multi-input logic gates

The Actel ACT 2 and ACT 3 Logic Modules. (a) The C-

Module for combinational logic. (b) The ACT 2 S-Module.
(c) The ACT 3 S-Module. (d) The equivalent circuit
(without buffering) of the SE (sequential element). (e) The
sequential element configured as a positive-edge–triggered
D flip-flop. (Source: Actel.)

36
 Different Types of Logic Cells – Cont’d
 Xilinx XC4000 CLB Structure

37
Different Types of Logic Cells – Cont’d
 Altera Flex / Max Logic
Element Structure
Flex 8k/10k Devices – SRAM Based LUTs, Logic
Elements (LEs) are similar to those used in XC5200
FPGA

The Altera MAX architecture. (a) Organization of logic and

interconnect. (b) A MAX family LAB (Logic Array Block).
(c) A MAX family macrocell. The macrocell details vary
between the MAX families—the functions shown here are
closest to those of the MAX 9000 family

38
Different Types of Logic Cells – Cont’d
To SUMMARIZE, FPGAs from various vendors differ in
their
 Architecture (Row Based or Matrix Based Routing
Mechanism)

 Gate Density (Cap. In Equiv. 2- Input NAND Gates)

 Basic Cell Structure
 Programming Technology

Vendor/ Product Architechture Capacity Basic Cell Programming Technology

Actel Gate Array 2-8 k MUX Antifuse
QuickLogic Matrix 1.2-1.8 k MUX Antifuse
Xilinx Matrix 2-10 k RAM Block SRAM
Altera Extended PLA 1- 5 k PLA EPROM
Concurrent Matrix 3-5 k XOR, AND SRAM
Plessy SOG 2-40 k NAND SRAM

39
 Programming Technologies
 Three Programming Technologies
The Antifuse Technology
Static RAM Technology
EPROM and EEPROM Technology

40
 Antifuse

[a] [b]

[c] [d]
41
 Programming Technologies – Cont’d
 The Antifuse Technology
Invented at Stanford and developed by
Actel
Opposite to regular fuse Technology
Normally an open circuit until a
programming current (about 5 mA) is
forced through it [a] [b]

Two Types:
Actel’s PLICE [Programmable Low-
Impedance Circuit Element]- A High-
Resistance Poly-Diffusion Antifuse
QuickLogic’s Low-Resistance metal-
metal antifuse [ViaLink] technology [c] [d]
Direct metal-2-metal connections
Higher programming currents reduce
Actel Antifuse [b] Actel Antifuse Resistance [c] QuickLogic
antifuse resistance
Antifuse [d] QL Antifuse Resistance
Disadvantages:
Unwanted Long Delay
OTP Technology

42
 Programming Technologies – Cont’d
 Static RAM Technology
 SRAM cells are used for
As Look-Up Tables (LUT) to
implement logic (as Truth Tables)
As embedded RAM blocks (for
buffer storage etc.)
As control to routing and
configuration switches

 Advantages
Allows In-System Programming
(ISP)
Suitable for Reconfigurable HW

 Disadvantages
Volatile – needs power all the time /
use PROM to download configuration
data
43
Programming Technologies – Cont’d
 EPROM and EEPROM Technology-

 EPROM Cell is almost as small as Antifuse

 Floating-Gate Avalanche MOS (FAMOS) Tech.
Under normal voltage, transistor is on
With Programming Voltage applied, we can turn it off (configuration) to
implement our logic
Exposure to UV lamp (one hour) we can erase the programming
Use EEPROM for quick reconfiguration, also, ISP possible

44
 Programming Technologies – Cont’d
 Summary Sheet

45
 ASIC Design Process
S-1 Design Entry: Schematic entry
or HDL description
S-2: Logic Synthesis: Using
Verilog HDL or VHDL and
Synthesis tool, produce a netlist-
logic cells and their interconnect
detail
S-3 System Partitioning: Divide a
large system into ASIC sized pieces
S-4 Pre-Layout Simulation: Check
design functionality
S-5 Floorplanning: Arrange netlist
blocks on the chip
S-6 Placement: Fix cell locations in
a block
S-7 Routing: Make the cell and
block interconnections
S-8 Extraction: Measure the
interconnect R/C cost
S-9 Post-Layout Simulation

46
 ASIC Design Flow
1.Design entry. Enter the design into an ASIC design system, either
using a hardware description language ( HDL ) or
schematic entry .
2. Logic synthesis. Use an HDL (VHDL or Verilog) and a logic synthesis
tool to produce a netlist —a description of the logic
cells and their connections.
3. System partitioning. Divide a large system into ASIC-sized pieces.
4. Prelayout simulation. Check to see if the design functions correctly.
5. Floorplanning. Arrange the blocks of the netlist on the chip.
6. Placement. Decide the locations of cells in a block.
7. Routing. Make the connections between cells and blocks.
8. Extraction. Determine the resistance and capacitance of the
interconnect.
9. Postlayout simulation. Check to see the design still works with the added loads
of the interconnect.
Steps 1–4 are part of logical design , and steps 5–9 are part of physical design .

• There is some overlap. For example, system partitioning might be considered as either logical or
physical design. To put it another way, when we are performing system partitioning we have to 47
consider both logical and physical factors.
 ASIC Design Process – Cont’d
 Altera FPGA Design Flow – A Self-Contained System that does all
from Design Entry, Simulation, Synthesis, and Programming of Altera Devices

48
 ASIC Design Process – Cont’d
 Xilinx FPGA Design Flow – Allows Third-Party Design Entry SW,
Accepts their generated netlist file as an input

 Use Pin2xnf and wir2xnf SW to

convert the netlist file to .XNF

 xnfmap and xnfmerge programs

convert .xnf files to create a
unified netlist file (Nand/Nor Gates)
.MAP file are generated

 map2lca program does fitters job,

produces un-routed .LCA file

 apr or ppr SW does the routing

job, post-layout netlist generated

 makebits SW generates BIT files

49