Category L T P Credit

18ECPY0 ASIC DESIGN

PE 3 0 0 3

Preamble
The course aims at ASIC physical design flow, including partitioning, floor-planning,
placement, routing and testing. Also the objective is to give the student an understanding of
basics of System on Chip.
Prerequisite
Nil
Course Outcomes
On the successful completion of the course, students will be able to
CO# Course Outcome Statement Weightage
in %
CO1 Describe the ASIC Design flow, ASIC types and Library design 15
CO2 Use algorithms to partition the ASIC to meet the given objectives 15
CO3 Use floorplanning and placement algorithms to place the logic cells inside 20
the flexible blocks of an ASIC
CO4 Use global and detailed routing algorithms to route the channels in ASIC 20
and apply techniques for circuit extraction
CO5 Use techniques to test ASIC 15
CO6 Explain System on Chip, On chip communication architectures and utilizing 15
Platform based design.
CO Mapping with CDIO Curriculum Framework
CO TCE Learning Domain Level CDIO Curricular
# Proficiency Cognitive Affective Psychomotor Components
Scale (X.Y.Z)
CO1 TPS2 Understand Respond - 1.3, 2.1.2, 2.4.1, 2.4.2
CO2 TPS3 Apply Value - 1.3, 2.1.1, 2.1.2, 2.4.1,
2.4.2, 3.2.5
CO3 TPS3 Apply Value - 1.3, 2.1.1, 2.1.2, 2.4.1,
2.4.2, 3.2.5
CO4 TPS3 Apply Value - 1.3, 2.1.1, 2.1.2, 2.4.1,
2.4.2, 3.2.5
CO5 TPS3 Apply Value - 1.3, 2.1.1, 2.1.2, 2.4.1,
2.4.2, 3.2.5
CO6 TPS2 Understand Respond - 1.3, 2.1.1, 2.1.2, 2.4.1,
2.4.2

Mapping with Programme Outcomes and Programme Specific Outcomes

COs PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO PO PO PSO1 PSO2 PSO3
10 11 12
CO1 M L - - - - - L L L - L L - L
CO2 S M L - - - - L L L - L M - L
CO3 S M L - - - - L L L - L M - L
CO4 S M L - - - - L L L - L M - L
CO5 S M L - - - - L L L - L M - L
CO6 M L - - - - - L L L - L L - L
S- Strong; M-Medium; L-Low
Assessment Pattern: Cognitive Domain
Cognitive Continuous Assessment Assignment End Semester
Levels Tests Examination
1 2 3 1 2 3
Remember 10 0 0 0 0 0 0
Understand 40 20 40 50 0 50 30
Apply 50 80 60 50 100 50 70
Analyse 0 0 0 0 0 0 0
Evaluate 0 0 0 0 0 0 0
Create 0 0 0 0 0 0 0

Psychomotor
Assessment Skill Psychomotor
Pattern: Assignment-1 Assignment-2 Assignment-3
Perception - - -
Set - - -
Guided Response - - -
Mechanism - - -
Complex Overt Responses - - -
Adaptation - - -
Origination - - -

Sample Questions for Course Outcome Assessment

Course Outcome 1 (CO1):
1. Draw the flowchart for ASIC design flow.
2. Explain the different types of ASICs
3. Discuss about the significance of ASIC libraries.
Course Outcome 2 (CO2):
1. Explain about the steps in the iterative partitioning improvement algorithm.
2. Apply constructive partitioning algorithm to partition the given network to meet the
following objectives.
 Use no more than three ASICs
 Each ASIC is to contain no more than three logic cells.
 Use minimum number of external connections for each ASIC

A B C

D E F

G H I

3. Use Kernighan-Lin algorithm to optimally partition the graph shown in figure below.
The dotted line represents the initial partitioning. Assume all nodes have the same
weight and all edges have the same priority.
Course Outcome 3 (CO3)
1. Discuss about the goals and objectives of floorplanning.
2. Explain the steps involved in Mincut placement algorithm.
3. Represent the floorplan shown in the figure below as its
a) Floorplan tree.
b) Polar horizontal graph
c) Polar vertical graph

Course Outcome 4 (CO4)

1. With neat diagrams, explain about ‗a cycle‘ in vertical constraint graph for channel
routing.
2. Three block a, b and c are given below along with their size options. Determine the
shape function for each block a, b, c and construct the minimum area top level
floorplan.
𝑎: 𝑤𝑎 = 5, ℎ𝑎 = 4 , 𝑏: 𝑤𝑏 = 3, ℎ𝑏 = 1 𝑜𝑟 𝑤𝑏 = 1, ℎ𝑏 = 3,
𝑐: 𝑤𝑐 = 2, ℎ𝑐 = 1 𝑜𝑟 𝑤𝑐 = 1, ℎ𝑐 = 2
3. Use Dogleg Left-Edge Algorithm to route a channel with the following pin
connections (ordered left to right).
𝑇𝑂𝑃 = [𝐴 𝐵 0 𝐵 𝐴 𝐷 𝐶 𝐸] , 𝐵𝑂𝑇 = [𝐵 0 𝐶 𝐴 𝐶 𝐸 𝐷 𝐷]
Course Outcome 5 (CO5)
1. Discuss about Design for Testability.
2. With neat diagram, explain about Boundary Scan Test.
3. Use Automatic Test Pattern Generation (ATPG) technique to test a typical circuit.
Course Outcome 5 (CO5)
1. Draw the flowchart of a typical SoC design flow.
2. Discuss about the parameters that has to be considered for Low-Power SoC design.
3. Explain about the features of a typical Mobile processor.
Concept Map
Syllabus
ASIC Types and Library Design: ASIC Design Flow, Types of ASIC - Full Custom, Semi
Custom – Standard Cell Based ASIC and Gate Array ASIC - Library cell design - Library
architecture. System Partitioning: Measurement of Partitioning, Partitioning Algorithms -
Constructive Partitioning, Iterative Partitioning Improvement Algorithms - Kernighan-Lin
Algorithm, Ratio-Cut Algorithm, FPGA Partitioning. Floorplanning and Placement: Floor
Planning Measurement and tools, I/O, Power and clock planning, Measurement of
Placement, Placement Algorithms – Min-cut Placement, Eigen value Placement, Iterative
Placement Improvement, Timing Driven Placement algorithms. Routing and Circuit
Extraction: Global Routing Measurement – Measurement of Interconnect Delay using
Elmore‘s constant, Global routing for CBIC and GA, Detailed Routing Measurement -
Measurement of Channel Density, Detailed routing Algorithms – Lee Maze and High tower
Algorithms, Circuit extraction process, Layout Design Rules, Technology related issues.
ASIC TESTING: Fault Simulation, Test Pattern Generation, Design for Testability, Boundary
Scan Test, Built-in-Self-Test. Modern ASICs: SoC Design Flow, Platform-based and IP
based SoC Designs, On-Chip Communication Architecture Standards, Low-Power SoC
Design, Case Studies - Canonic Signed Digit Arithmetic, Distributed Arithmetic, Modular
Arithmetic, Mobile processor.
Learning Resources
 Michael John Sebastian Smith, ―Applications Specific Integrated Circuits‖, Pearson
Education, 2013.
 H.Gerez, ―Algorithms for VLSI Design Automation‖, John Wiley, 1999.
 Andrew B.Khang, Lienig, Markov and Hu, ‖ VLSI Physical Design: From Graph
Partitioning to Timing Closure ―, Springer, 2011.
 J..M.Rabaey, A. Chandrakasan, and B.Nikolic, ‖Digital Integrated Circuit Design
Perspective (2/e)‖, PHI 2003.
 Hoi-Jun Yoo, Kangmin Leeand Jun Kyong Kim, ―Low-Power NoC for High-
Performance SoC Design‖, CRC Press, 2008.
 S.Pasricha and N.Dutt,‖ On-Chip Communication Architectures System on Chip
Interconnect, Elsveir‖, 2008.
 Wayne Wolf, ―Modern VLSI design‖ - Addison Wesley, 1998.
 Prof. Santosh Biswas, IIT Guwahati, NPTEL Video Lecture on ―Optimization Techniques
for Digital VLSI Design‖, weblink:
 https://nptel.ac.in/courses/108/103/108103108/www.asic-design.com.
 Prof. Santosh Biswas, IIT Guwahati, NPTEL Video Lecture on ―Design Verification and
Test of Digital VLSI Circuits‖, weblink: https://nptel.ac.in/courses/106/103/106103116/
 Website: www.asic-world.com
Course Contents and Lecture Schedule
No. Topic No. of COs
Hours
1 ASIC Types and Library Design
1.1 ASIC Design Flow 1 CO1
1.2 Types of ASIC - Full Custom, Semi Custom 1 CO1
1.3 Standard Cell Based ASIC and Gate Array ASIC 2 CO1
1.4 Library cell design 1 CO1
1.5 Library architecture 1 CO1
2 System Partitioning
2.1 Measurement of Partitioning 1 CO2
2.2 Partitioning Algorithms - Constructive Partitioning 1 CO2
2.3 Iterative Partitioning Improvement Algorithms- Kernighan-Lin 2 CO2
algorithm
2.4 Ratio-Cut Algorithm 1 CO2
2.5 FPGA Partitioning 1 CO2
3 Floorplanning and Placement
3.1 Floor Planning Measurement and tools 1 CO3
3.2 I/O, Power and clock planning 1 CO3
3.3 Measurement of Placement 1 CO3
3.4 Placement Algorithms – Min-cut Placement 1 CO3
3.5 Eigen value Placement, Iterative Placement Improvement 1 CO3
3.6 Timing Driven Placement algorithms 1 CO3
4 Routing and Circuit Extraction
4.1 Global Routing Measurement 1 CO4
4.2 Measurement of Interconnect Delay using Elmore‘s constant 1 CO4
4.3 Global routing for CBIC and GA 1 CO4
4.4 Detailed Routing Measurement-Measurement of Channel Density, 1 CO4
4.5 Detailed routing Algorithms – Lee Maze and High tower 1 CO4
Algorithms,
4.6 Circuit extraction process, Layout Design Rules, Technology 1 CO4
related issues
5 ASIC TESTING
5.1 Fault Simulation 1 CO5
5.2 Test Pattern Generation Test 1 CO5
5.3 Design for Testability, Boundary Scan Test 2 CO5
5.4 Built-in-Self-Test 2 CO5
6. Modern ASICs
6.1 SoC Design Flow 1 CO6
6.2 Platform-based and IP based SoC Designs 1 CO6
6.3 On-Chip Communication Architecture Standards 1 CO6
6.4 Low-Power SoC Design 1 CO6
6.5 Case Studies - Canonic Signed Digit Arithmetic, Distributed 1 CO6
Arithmetic
6.6 Modular Arithmetic, Mobile processor 1 CO6
Total 36

Course Designers:
 Dr.V.R.Venkatasubramani [email protected]
 Dr.S.Rajaram [email protected]
 Dr.N.B.Balamurugan [email protected]
 Dr.V.VinothThyagarajan [email protected]
 Dr.D.GraciaNirmala Rani [email protected]