Unit 9: Logic Synthesis and Verification

˙Course contents
 Logic synthesis basics
 Binary-decision diagram (BDD)
 Verification
 Logic optimization
 Technology mapping
˙Readings
 Chapter 11

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Logic Synthesis & Verification

˙Logic synthesis programs transform Boolean
expressions or register-transfer level (RTL) description
(in Verilog/VHDL/C) into logic gate networks (netlist) in a
particular library.
 Three different tasks
„ two-level combinational synthesis

„ multilevel combinational synthesis

„ sequential synthesis

 Optimization goals: minimize area, delay, and power, etc

˙Verification: Checks the equivalence of a specification
and an implementation.

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 Logic Synthesis & Verification
˙Technology-independent optimization
 Works on Boolean expression equivalent.
 Estimates size based on # of literals.
 Uses don't-cares, common factor extraction (factorization), etc.
to optimize logic.
 Uses simple delay models.
˙Technology-dependent optimization: technology
mapping/library binding
 Maps Boolean expressions into a particular cell library.
 May perform some optimizations in addition to simple mapping.
 Uses more accurate delay models based on cell structures.

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Boolean Functions
˙B = {0,1}, Y = {0,1,D}
˙A Boolean function f: Bm → Yn
 f = x1 x2 + x1 x3 + x2 x3 + x1 x2 + x2 x3 + x1 x3
˙Input variables: x1, x2, …
˙The value of the output partitions Bm into three sets
 the on-set
 the off-set
 the dc-set (don’t-care set)

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 Minterms and Cubes
˙A minterm is a product of all input variables or their
negations.
 A minterm corresponds to a single point in Bn.
˙A cube is a product of the input variables or their
negations.
 The fewer the number of variables in the product, the
bigger the space covered by the cube.

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Implicant and Cover

˙An implicant is a cube whose points are either in the
on-set or the dc-set.
˙A prime implicant is an implicant that is not included in
any other implicant.
˙A set of prime implicants that together cover all points
in the on-set (and some or all points of the dc-set) is
called a prime cover.
˙A prime cover is irredundant when none of its prime
implicants can be removed from the cover.
˙An irredundant prime cover is minimal when the cover
has the minimal number of prime implicants.

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 Cover Examples
˙f = x1 x3 + x2 x3 + x1 x2
˙f = x1 x2 + x2 x3 + x1 x3

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Canonical Forms
˙A canonical form of a Boolean function is a unique
representation of the function.
 It can be used for verification purposes.
˙The truth table or the sum of minterms are canonical
forms
 They grow exponentially with the number of input variables.
˙A prime irredundant cover is not a canonical form.
˙Reduced ordered binary decision diagram (ROBDD):
a canonical form that is interesting from a practical point
of view.

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 Logic Synthesis in Practice
˙Specify the logic-level behavioral description of the
circuit in some hardware-description language.
˙Extract from this description the Boolean expressions
related to the logic and represent them in some suitable
internal form.
˙Manipulate these expressions to obtain an optimized
representation (two-level or multilevel).
˙Perform technology mapping, a mapping from the
abstract optimized representation to a netlist of cells
from a library.

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Binary-Decision Diagram (BDD) Principles

˙Restriction resulting in the positive and negative
cofactors of a Boolean function:

 f = x1 x2 x3 + x1 x2 x3 + x1 x2 x3 + x1 x2 x3 + x1 x2 x3 + x1 x2 x3
fx1 = x2 x3 + x2 x3 + x2 x3
fx1 = x2 x3 + x2 x3 + x2 x3
˙Shannon expansion (already known to Boole) states:

˙A complete expansion can be obtained by successively

applying Shannon expansion on all variables of a
function until either of the constant functions ’0’ or ’1’ are
reached.
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 Example Ordered Binary-Decision Diagram (OBDD)
˙The complete Shannon expansion can be visualized as
a tree (solid lines correspond to the positive cofactors
and dashed lines to negative cofactors).

f = x1 x2 x3 + x1 x2 x3 + x1 x2 x3 + x1 x2 x3 + x1 x2 x3 + x1 x2 x3

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Creating A Reduced OBDD (ROBDD)

˙An OBDD is a directed tree G(V,E).
˙Each vertex v ∈ V is characterized by an associated
variable φ(v), a high subtree η(v) (high(v)) and a low
subtree λ(v) (low(v)).
˙Procedure to reduce an OBDD:
 Merge all identical leaf vertices and appropriately redirect
their incoming edges;
 Proceed from bottom to top, process all vertices: if two
vertices u and v are found for which φ(u) = φ(v), η(u) =
η(v), and λ(u) = λ(v), merge u and v and redirect
incoming edges;
 For vertices v for which η(v) = λ(v), remove v and redirect
its incoming edges to η(v).

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 Reduction Example

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ROBDD Properties
˙The ROBDD is a canonical representation, given a
fixed ordering of the variables.
˙The ROBDD is a compact representation for many
Boolean functions used in practice.
˙Variable ordering can greatly affect the size of an
ROBDD. k

 E.g., the parity function of k bits: f = ∏ x2 j − 1 ⊕ x2 j

j =1

x2

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 A BDD Package
˙A BDD package refers to a software program that can
manipulate ROBDDs. It has the following properties:
 Interaction with BDDs takes place through an abstract
data type (functionality is independent from the internal
representation used).
 It supports the conversion of some external
representation of a Boolean function to the internal
ROBDD representation.
 It can store multiple Boolean functions, sharing all
vertices that can be shared.
 It can create new functions by combining existing ones
(e.g., h = f • g).
 It can convert the internal representation back to an
external one.

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BDD Data Structures

˙A triple (φ,η,λ) uniquely ˙A unique table
identifies an ROBDD (implemented by a hash
vertex. table) that stores all
triples already processed.

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 Building an ROBDD

˙The procedure directly

builds the compact
ROBDD structure.
˙A simple symbolic
computation system is
assumed for the derivation
of the cofactors.
˙π(i) gives the ith variable
from the top

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robdd_build Example

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 ROBDD Manipulation
˙Separate algorithms could be designed for each
separate operator on ROBDDs, such as AND, NOR, etc.
˙However, the universal if-then-else operator ‘ite’ is
sufficient. z = ite(f,g,h), z equals g when f is true and
equals h otherwise:
˙Examples:

˙The ite operator is well-suited for a recursive algorithm

based on ROBDDs (φ(v) = x):

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The ite Algorithm

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 Comments on the ite Algorithm
˙The algorithm processes the variables in the order
used in the BDD package.
 π(i) gives the i variable from the top; π
th -1(x) gives the

index position of variable x from the top.

˙Computation of the restrictions: suppose that F is the
root vertex of the function for which Fx should be
computed:
Fx = η(F) if π -1(φ(F)) = i

˙The calculation of is done in an analogous way.

˙The time complexity of the algorithm is O(|F|*|G|*|H|).

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ROBDD Example: Computing G from G

G = ite(G, 0, 1)

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 ROBDD Example: Computing H from F, G, G

H=F⊕G
= ite(F, G, G)

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Composition
˙The composite problem is
the ROBDDs of two functions f and g are known


 the output of g is connected to an input of f

 compute the ROBDD of the composed function h,

where
h = f(x1, …, xi-1, g, xi+1, …,xn).
˙Using Shannon expansion, one finds that

˙Now, the restrictions have to be calculated by

dedicated algorithms.

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 Positive Cofactor

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Positive Cofactor Example: Computing Fx3

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 Variable Ordering
˙Reorder adjacent variables only has a local effect on
the ROBDD.

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Variable Ordering (cont’d)

˙Finding the ordering that minimizes the ROBDD size for
some function is intractable.
 The optimal ordering may change as ROBDDs are being
manipulated.
˙So, an ROBDD package will try to reorder the variables
at distinct moments.
 It could move one variable to the top and back to the
bottom and remember the best position. It could then
repeat the procedure for the other variables.
˙Another ‘‘invisible’’ feature of an ROBDD package is
garbage collection.

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 The Verification Problem
˙The issue is to compare a specification f to an
implementation g.
˙They can both be represented by ROBDDs (F resp. G).
˙In case of a fully specified function, verification is trivial
(pointer comparison) because of the strong canonicity
of the ROBDD data structure.
 Strong canonicity: the representations to identical
functions are the same.
˙If there is a dc-set, use two functions f and d. The
implementation g is correct when
is a tautology (the expression evaluates to ’1’).

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ROBDDs and Satisfiability

˙A Boolean function is satisfiable if an assignment to its
variables exists for which the function becomes ‘1’
˙Any Boolean function whose ROBDD is unequal to ‘0’ is
satisfiable.
˙Suppose that choosing a Boolean variable xi to be ‘1’
costs ci. Then, the minimum-cost satisfiability
problem asks to minimize:

where µ(xi) = 1 when xi = ‘1’ and µ(xi) = 0 when xi = ‘0’.

˙Solving minimum-cost satisfiability amounts to
computing the shortest path in an ROBDD, which can
be solved in linear time.
 Weights: w(v, η (v)) = ci, w(v, λ (v)) = 0, variable xi = φ(v).

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 Applications to Combinatorial Optimization
˙Zero-one integer linear programming can be
formulated as a minimum-cost satisfiability problem.
˙Consider the (standard form) constraint: x1 + x2 + x3 +
x4 = 3.
˙It can be written as:

 The first 6 sums in the product: at least 3 of the 4

variables are 1.
 The last sum: at least one of the variables is 0.
˙Many combinatorial optimization problems can also be
directly formulated in terms of the satisfiability problem.

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Set Covering
˙Given a set S = {s1, …,sm} and a set K = {K1, …,Kn}
where each Kj (1 ≤ j ≤ n) is a subset of S, find a subset
Γ of K such that the union of the elements Γ covers S.
˙The cost of a cover is the sum of the costs cj of the
elements Kj of Γ.
˙Multiple cost functions are possible. E.g., cj = 1 or
cj = |Kj|.
˙The problem is NP-complete for most cost functions.

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 Covering Matrix

• Γ = {K3,K6} is the optimal

solution when cj = |Kj|.
• K3 is redundant in Γ =
{K1,K2,K3}.

˙A covering problem can be formulated as a satisfiability

problem by associating variables xj with the sets Kj: (x1
+ x2 + x6) • (x1 + x4 + x5 + x6) • (x2 + x3 + x5) • (x2 + x4 +
x6).
˙This type of covering is called unate.
˙A binate covering problem has an expression where
complemented variables are allowed.

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Example Simplification Rules in Covering

K5 dominates K4
s2 dominates s3
K3 is essential

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 Technology-Independent Logic Optimization
˙Two-level: minimize the # of product terms.


˙Multi-level: minimize the #'s of literals, variables.

 E.g., equations are optimized using a smaller number of literals.

˙Methods/CAD tools: The Quine-McCluskey method

(exponential-time exact algorithm), Espresso (heuristics
for two-level logic), MIS (heuristics for multi-level logic),
Synopsys, etc.
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Two-Level Logic Synthesis

˙Any Boolean function can be realized in two levels:
AND-OR (sum of products), NAND-NAND, etc.
˙Direct implementation of two level logic using PLAs
(programmable logic arrays) is not as popular as in the
nMOS days.
˙Classic problems, solved e.g. by the Quine-McCluskey
algorithm.
˙Popular cost function: the number of literals in the sum
of products expression.
˙The goal is to find a minimal irredundant prime cover.

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 Optimality in Two-Level Logic Synthesis

A local and a global minimum

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The Quine-McCluskey Algorithm

˙Calculate all prime implicants (of the union of the on-set
and dc-set).
˙Find the minimal cover of all minterms in the on-set by
prime implicants.
˙Construct the covering matrix.
˙Simplify the covering matrix by detecting essential
columns, row and column dominance.
˙What is left is the cyclic core of the covering matrix.
 The covering problem can then be solved by a branch-
and-bound algorithm.
˙Other methods do not first enumerate all prime
implicants; they use an implicit representation by
means of ROBDDs.

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 The Quine-McCluskey Algorithm
˙ F(a, b, c, d) = ∑m(2, 3, 7, 9, 11, 13) + ∑d(1, 10, 15)
˙ Step 1: Group minterms to find prime implicants by applying
xy + xy ' = x.
˙ Step 2: Select a minimum set of prime implicants (minimum
# of literals) to implement the original function.
˙ Exponential-time exact algorithm, huge amounts of memory!

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Technology Mapping

˙Library-based technology mapping: standard cell

design.
 Map a function to a limited set of pre-designed cells
˙Lookup table-based technology mapping: Lucent,
Xilinx FPGAs, etc.
 Each lookup table (LUT) can implement a very large number of
functions (e.g., all functions with 4 inputs and 1 output)
˙Multiplexer-based technology mapping: Actel FPGAs,
etc.
 Logic modules are constructed with multiplexers.
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 Standard Cell Revisited

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Pattern Graphs for an Example Library

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 Technology Mapping
˙Technology Mapping: The optimization problem of
finding a minimum cost covering of the subject graph by
choosing from the collection of pattern graphs for all
gates in the library.
˙A cover is a collection of pattern graphs such that
every node of the subject graph is contained in one (or
more) of the pattern graphs.
˙The cover is further constrained so that each input
required by a pattern graph is actually an output of
some other pattern graph.

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Trivial Covering
˙Mapped into 2-input NANDs and 1-input inverters.
˙8 2-input NAND-gates and 7 inverters for an area cost
of 23.
˙Best covering?

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 Optimal Tree Covering by Dynamic Programming
˙If the subject directed acyclic graph (DAG) is a tree,
then a polynomial-time algorithm to find the minimum
cover exists.
 Based on dynamic programming: optimal substructure?
overlapping subproblems?
˙Given: subject trees (networks to be mapped), library
cells
˙Consider a node n of the subject tree
 Recursive assumption: For all children of n, a best match
which implements the node is know.
 Cost of a leaf is 0.
 Consider each pattern tree which matches at n, compute
cost as the cost of implementing each node which the
pattern requires as an input plus the cost of the pattern.
 Choose the lowest-cost matching pattern to implement n.
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Tree-Covering by Dynamic Programming

˙ If the subject DAG is not a tree
 Partition the subject graph into forest of trees
 Cover each tree optimally using the dynamic programming.
 Overall solution is only an approximation.
˙ Optimality
 An optimal sequence of decisions has the property that
whatever the initial state and decision are, the remaining
decisions must constitute an optimal decision sequence with
regard to the state resulting from the first decision.
 The minimum area cover for a tree T can be derived from the
minimum area covers for every node below the root of T.

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 Best Covering
˙A best covering with an area of 15.
˙Obtained by the dynamic programming approach.

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Conceptual FPGA Architecture

Routing resources I/O cell
logic module

L L L L

L L L L

L L L L

L L L L

Logic modules + Routing resources + I/O cells = FPGAs

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 Xilinx XC4000 FPGA Logic Module Architecture
˙ Each contains two 4-input LUTs, one 3-input LUT, and two DFFs.
˙ Can implement any 2 functions of up to 4 variables, one function of
up to 5 variables, or selected functions of up to 9 variables.

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Lookup Table-Based Technology Mapping

˙A k-input LUT (k-LUT) can implement any function of
up to k inputs.

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 Multiplexer-Based Technology Mapping
˙To implement f = ab + ac, set d0 = d1 = s3 = x, d2 = c,
d3 = b, s0 = a, s1 = s2 = 1.

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