COMBINATIONAL CIRCUITS

The characteristics of combinational circuits:

➢ The output of combinational circuit is depends on present inputs.

➢ The combinational circuit do not use any memory.

➢ The previous state of input does not have any effect on the present state of the
circuit.

➢ A combinational circuit can have an n number of inputs and m number of outputs.

BLOCKDIAGRAM
Classification of combinational circuits

• Adder, Subtractor

• Code converters

• Parity Checkers and Parity Generators

• Multiplexer and De-multiplexer

• Encoder and Decoder

• Comparators.
Adders
Half Adder

S=A XOR B

C=AB
Full Adder RCA

S=A XOR B XOR CIN

COUT=AB+BCIN+CINA
CARRY LOOKAHEAD ADDERS

• To reduce the computation time, there are faster ways to add two binary
numbers by using carry lookahead adders.

• The carry propagator is propagated to the next level whereas the carry generator
is used to generate the output carry ,regardless of input carry.

o carry propagator(P)

o and carry generator(G),

• Pi = Ai ⊕ Bi

• Gi = Ai · Bi

• C1 = G0 + P0 · C0

• C2 = G1 + P1 · C1 = G1 + P1 · G0 + P1 · P0 · C0

• C3 = G2 + P2 · C2 = G2 P2 · G1 + P2 · P1 · G0 + P2 · P1 · P0 · C0

• C4 = G3 + P3 · C3 = G3 P3 · G2 P3 · P2 · G1 + P3 · P2 · P1 · G0 + P3 · P2 · P1 · P0 · C0
SUBTRACTORS
HALF SUBTRACTOR
Inputs Outputs

X Y D Bout

0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0
FULL SUBTRACTOR
MULTIPLEXERS SEL OUT
2:1 Multiplexer 0 IN 1
1 IN 2

Logic diagram of 2x1 mux Schematic symbol of 2x1 mux

4:1 Multiplexer SEL OUT
00 IN 0
01 IN 1
10 IN 2
11 IN 3
4:1 MUX IMPLEMENTING USING 2:1 MUX
8:1 MUX IMPLEMENTING USING 2:1 MUX
16:1 MUX IMPLEMENTING USING 4:1 MUX
Construct a 16 × 1 multiplexer with two 8 × 1 and one 2 × 1 multiplexers.
Realization of logic gates using 2:1 MUX

Implementation of NOT gate using 2 : 1 Mux

Implementation of AND gate using 2 : 1 Mux
Implementation of OR gate using 2 : 1 Mux
Implementation of NAND gate using 2 : 1 Mux
Implementation of NOR gate using 2 : 1 Mux
Implementation of EX-OR gate using 2 : 1 Mux
Implementation of EX-NOR gate using 2 : 1 Mux
Implementation of adders using mux
Half adder A B S C

0 0 0 0
B 0 0 1 1 0
2X1 MUX S 2X1 MUX C 1 0 1 0
B’ B 1 1 0 1

A A
SUM CARRY
 A B C S C0
Full Adder 0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

SUM CARRY
Implement the function F= Σ(0,2,4,5,7,8,10,11,15) using MUX .
F(A,B,C,D) = AB'C+A'B'CD+A'BCD'+ABC. What are the multiplexer’s inputs
(I0,...,I7) for the multiplexer ? A B C D F
0 0 0 0 0 F=0
0 0 0 1 0 00 01 11 10
0 0 1 0 0 F=D 00 1
0 0 1 1 1
01 1
0 1 0 0 0 F=0
11 1 1
0 1 0 1 0
10 1 1
8X1 MUX 0 1 1 0 1 F=D
0 1 1 1 0 ’
1 0 0 0 0 F=0
1 0 0 1 0
1 0 1 0 1 F=1
1 0 1 1 1
1 1 0 0 0 F=0
1 1 0 1 0
1 1 1 0 1 F=1
1 1 1 1 1
Implement using mux
DEMUX

• The process of getting information from one input and transmitting the same over
one of many outputs is called DE multiplexing.
• A DE multiplexer is a combinational logic circuit that receives the information on
a single input and transmits the same information over one of 2n possible output
lines.
• DE multiplexers are also called as data distributors, since they transmit the same
data which is received at the input to different destinations.
1: 4 DE multiplexer
Design 1:4 demux using 1:2 demux
FULL ADDER, FULL SUBTRACTOR USING DEMUX
ENCODER
• An Encoder is a device used to change a signal (such as a bit stream) or other
codes into a binary code. The simplest encoder is a 2n -to-n binary encoder.
4 : 2 Encoder

A1 = Y3 + Y2
A0 = Y3 + Y1
8 : 3 Encoder
A2 = Y7 + Y6 + Y5 + Y4
A1 A0 = Y7 + Y5 + Y3 + Y1
A0= Y7 + Y6 + Y3 + Y2
• Decimal to BCD Encoder
• Priority Encoder
DECODER
• It is a combinational circuit that converts n lines of input into 2n lines of output.
2:4 decoder E A B Y0 Y1 Y2 Y3
0 X X 0 0 0 0

1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
3:8 DECODER

A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
3:8 DECODER USING 2:4 DECODER

A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
4:16 DECODER USING 3:8 DECODER
4:16 DECODER USING 2:4 DECODER
HALF ADDER, HALF SUBTRACTOR USING 2:4 DECODER
FULL ADDER, FULL SUBTRACTOR USING 3:8 DECODER
Implement using decoder
COMPARATOR

1-Bit Magnitude Comparator

2-Bit Magnitude Comparator