CS3352- DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION

II YEAR / III SEMESTER - B.TECH IT, AI&DS

UNIT I

COMBINATIONAL LOGIC

PREPARED BY

Mr.G.SYED ZABIYULLAH, AP/MEE

VERIFIED BY

HOD PRINCIPAL CEO / CORRESPONDENT

DEPARTMENT OF MEDICAL ELECTRONICS

SENGUNTHAR COLLEGE OF ENGINEERING – TIRUCHENGODE

1
 ANNA UNIVERSITY, CHENNAI

AFFILIATED INSTITUTIONS
B.TECH INFORMATION TECHNOLOGY
REGULATIONS – 2021
CHOICE BASED CREDIT SYSTEM

SEMESTER III

PERIODS TOTAL
S. COURSE CATE- PER WEEK
COURSE TITLE CONTAC CREDITS
NO CODE GORY L T P T
.
PERIODS
THEORY
1. MA3354 Discrete Mathematics BSC 3 1 0 4 4
2. CS3352 Digital Principles and
ESC 3 0 2 5 4
Computer Organization

3. CS3353 Foundations of Data

PCC 3 0 0 3 3
Science

4. CD3291 Data Structures and

Algorithms PCC 3 0 0 3 3
5. CS3391 Object Oriented 3 0 0 3 3
Programming PCC
PRACTICALS
6. CD3281 Data Structures and
PCC 0 0 4 4 2
Algorithms Laboratory
7. CS3381 Object Oriented
PCC 0 0 3 3 1.5
Programming Laboratory
8 CS3362 Data Science Laboratory PCC 0 0 4 4 2
9 GE3361 Professional Development$ EEC 0 0 2 2 1
TOTAL 15 1 15 31 23.5

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 SYLLABUS

CS3352 DIGITAL PRINCIPLES AND COMPUTER ORGANIZATION L T P C

3 0 2 4
COURSE OBJECTIVES:
 To analyze and design combinational circuits.
 To analyze and design sequential circuits
 To understand the basic structure and operation of a digital computer.
 To study the design of data path unit, control unit for processor
and to familiarize with the hazards.
 To understand the concept of various memories and I/O interfacing.

UNIT I COMBINATIONAL LOGIC 9

Combinational Circuits – Karnaugh Map - Analysis and Design Procedures –
Binary Adder – Subtractor – Decimal Adder - Magnitude Comparator –
Decoder – Encoder – Multiplexers - Demultiplexers

UNIT II SYNCHRONOUS SEQUENTIAL LOGIC 9

Introduction to Sequential Circuits – Flip-Flops – operation and excitation
tables, Triggering of FF, Analysis and design of clocked sequential circuits –
Design – Moore/Mealy models, state minimization, state assignment, circuit
implementation - Registers – Counters.

UNIT III COMPUTER FUNDAMENTALS 9

Functional Units of a Digital Computer: Von Neumann Architecture – Operation
and Operands of Computer Hardware Instruction – Instruction Set Architecture
(ISA): Memory Location, Address and Operation – Instruction and Instruction
Sequencing – Addressing Modes, Encoding of Machine Instruction –
Interaction between Assembly and High Level Language.

UNIT IV PROCESSOR 9
Instruction Execution – Building a Data Path – Designing a Control Unit –
Hardwired Control, Microprogrammed Control – Pipelining – Data Hazard –
Control Hazards.
UNIT V MEMORY AND I/O 9
Memory Concepts and Hierarchy – Memory Management – Cache Memories:
Mapping and Replacement Techniques – Virtual Memory – DMA – I/O –
Accessing I/O: Parallel and Serial Interface – Interrupt I/O – Interconnection
Standards: USB, SATA
45 PERIODS
PRACTICAL EXERCISES: 30 PERIODS
1. Verification of Boolean theorems using logic gates.
2. Design and implementation of combinational circuits using gates for arbitrary
functions.

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 3. Implementation of 4-bit binary adder/subtractor circuits.
4. Implementation of code converters.
5. Implementation of BCD adder, encoder and decoder circuits
6. Implementation of functions using Multiplexers.
7. Implementation of the synchronous counters
8. Implementation of a Universal Shift register.
9. Simulator based study of Computer Architecture

COURSE OUTCOMES:
At the end of this course, the students will be able to:
CO1 : Design various combinational digital circuits using logic gates
CO2 : Design sequential circuits and analyze the design procedures
CO3 : State the fundamentals of computer systems and analyze the execution of
an instruction
CO4 : Analyze different types of control design and identify hazards
CO5 : Identify the characteristics of various memory systems and I/O
communication

TOTAL:75 PERIODS

TEXT BOOKS
1. M. Morris Mano, Michael D. Ciletti, “Digital Design : With an Introduction to
the Verilog HDL, VHDL, and System Verilog”, Sixth Edition, Pearson
Education, 2018.
2. David A. Patterson, John L. Hennessy, “Computer Organization and
Design, The Hardware/Software Interface”, Sixth Edition, Morgan
Kaufmann/Elsevier, 2020.

REFERENCES
1. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Naraig Manjikian,
“Computer Organization and Embedded Systems”, Sixth Edition, Tata
McGraw-Hill, 2012.
2. William Stallings, “Computer Organization and Architecture – Designing
for Performance”, Tenth Edition, Pearson Education, 2016.
3. M. Morris Mano, “Digital Logic and Computer Design”, Pearson Education,
2016.

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 SENGUNTHAR COLLEGE OF ENGINEERING - TIRUCHENGODE
DEPARTMENT OF MEDICAL ELECTRONICS
LECTURE PLAN
SUBJECT CODE : CS3352
SUBJECT NAME : DIGITAL PRINCIPLES AND COMPUTER
ORGANIZATION
NAME OF THE FACULTY : MR.G.SYED ZABIYULLAH
DESIGNATION : ASSISTANT PROFESSOR
COURSE : III SEMESTER - B.TECH. IT,AI&DS
ACADEMIC YEAR : 2022-2023

RECOMMENDED TEXT BOOKS/REFERENCE BOOKS

S.NO. TITLE OF THE BOOK AUTHOR REFERENCE
Digital Design : With an
Introduction to the Verilog M. Morris Mano, Michael D.
1 T1
HDL, VHDL, and System Ciletti,
Verilog

Computer Organization and

David A. Patterson, John L.
2 Design, The Hardware/ T2
Hennessy
Software Interface

Carl Hamacher, Zvonko

Computer Organization
3 Vranesic, Safwat Zaky, R1
and Embedded Systems
Naraig Manjikian

Computer Organization and

4 William Stallings R2
Architecture – Designing for
Performance

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S.N REFERENC NO. OF
TOPIC TEACHING AIDS
O. E HOURS

UNIT I COMBINATIONAL LOGIC

1 Combinational Circuits T1 BLACK BOARD 2
Karnaugh Map - Analysis and
2 T1 BLACK BOARD 2
Design Procedures
3 Binary Adder – Subtractor T1 BLACK BOARD 1
Decimal Adder Magnitude
4 T1 BLACK BOARD 1
Comparator
5 Decoder – Encoder T1 BLACK BOARD 2
6 Multiplexers - Demultiplexers T1 BLACK BOARD 1
UNIT II SYNCHRONOUS SEQUENTIAL LOGIC
Introduction to Sequential
7 T1 BLACK BOARD 2
Circuits
Flip-Flops- operation and
8 excitation tables T1 BLACK BOARD 2

9 Triggering of FF, T1 BLACK BOARD 1

Analysis and design of
10 clocked sequential circuits T1 BLACK BOARD 1

Design – Moore/Mealy
11 models, T1 BLACK BOARD 2

state minimization, state

12 assignment, circuit T1 BLACK BOARD 1
implementation

13 Registers T1 BLACK BOARD 1

14 Counters. T1 BLACK BOARD 1

UNIT III COMPUTER FUNDAMENTALS

Functional Units of a Digital
15 Computer T2 BLACK BOARD 1

16 Von Neumann Architecture – T2 BLACK BOARD 1

Operation and Operands of
17 T2 BLACK BOARD 1
Computer Hardware Instruction
Instruction Set Architecture
18 T2 BLACK BOARD 1
(ISA):
Memory Location, Address and
19 T2 PPT 1
Operation

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 Instruction and Instruction
20 T2 PPT 1
Sequencing

21 Addressing Modes, T2 PPT 1

Encoding of Machine
22 T2 PPT 1
Instruction
Interaction between Assembly
23 T2 PPT 1
and High Level Language

UNIT IV PROCESSOR

24 Instruction Execution T2 BLACK BOARD 1

25 Building a Data Path T2 BLACK BOARD 1

26 Designing a Control Unit T2 BLACK BOARD 1
Hardwired Control, Micro
27 T2 BLACK BOARD 1
programmed Control
28 Pipelining T2 BLACK BOARD 2
29 Data Hazard. T2 BLACK BOARD 1

30 Control Hazards. T2 BLACK BOARD 1

UNIT V MEMORY AND I/O

Memory Concepts and

31 T2 BLACK BOARD 1
Hierarchy
32 Memory Management T2 BLACK BOARD 1
Cache Memories: Mapping and
33 T2 PPT 1
Replacement Techniques
34 Virtual Memory T2 PPT 1
35 DMA – I/O T2 PPT 1
Accessing I/O: Parallel and
36 T2 PPT 1
Serial Interface
37 Interrupt I/O T2 BLACK BOARD 1
Interconnection Standards:
38 USB, SATA T2 BLACK BOARD 1

TOTAL 45
PRACTICAL 30
TOTAL 75

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 UNIT - I

COMBINATIONAL LOGIC

 Combinational Circuits
 Karnaugh Map
 Analysis and Design Procedures
 Binary Adder – Subtractor
 Decimal Adder
 Magnitude Comparator
 Decoder – Encoder
 Multiplexers - Demultiplexers

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 LIST OF IMPORTANT QUESTIONS
PART-A
1. Construct a full adder using two half adders and OR gates. (A/M 19)
2. Write the truth table of 2 to 4 line decoder and draw its logic diagrams (A/M
19)
3. What is propagation delay. (N/D 18 )
4. Draw 1:8 demultiplexer using two 1:4 demultiplexers. (N/D 18)
5. State the different modeling techniques used in HDL (A/M 2018)
6. Draw the truth table of full adder (A/M 2018)
7. What is priority encoder? (A/M 2017) (N/D 2014) (N/D 16)
8. Draw the circuit 2 to 1 line multiplexer. (A/M 2017) (M/J 2014) (N/D 16)
9. What are binary adder. (N/D 2017)
10. Write the truth table for full subtractor. . (N/D 2017)
11. Design the combinational circuit with 3 inputs and 1 output. The output is 1
when the binary value of the inputs is less than 3. The output is 0
otherwise. (M/J 2016)
12. Draw the truth table for half adder. (N/D 2015)
13. Implement the function G = ∑m(0,3) using a 2 x 4 decoder.(M/J 2014)
14. Draw the circuit 2 to 1 line multiplexer. (M/J 2014)
15. List out the advantages and disadvantages of K-map method?
16. Define Encoder.
17. Define decoder.
18. Define multiplexer.
19. What do you mean by comparator?
20. What is priority encoder? (N/D 16)
21. Distinguish between decoder and demultiplexer.
22. What is a combinational circuit? Give an example (M/J 2016)
23. Write down the design procedure for combinational circuits

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 LIST OF IMPORTANT QUESTIONS
PART-B

1. Explain in detail about the half adder and full adder. (A/M 19,16)
2. Explain in detail about the half subtractor and full subtractor.
3. Explain in detail about K-map.
4. (i) Minimize the expression (A/M 18)
(ii) Reduce the following expression in K map technique

(iii) Reduce the following function in K map technique f(A,B,C,D) =

Σm(0,1,4,8, 9,10)
(iv) Simplify the Boolean function
f (A,B,C,D,E)=Σm (0,2,4,6,9,11,13,15,17,21,25,27,29,31)

(v) Reduce the following function in K map technique f(A,B,C) =

Σm(0,1,3,7)+ Σd(2,5)
5. (I) Reduce the following function in K map technique f(A,B,C,D) =
πM(0,2,3,8,9,12,13,15)
(ii) Reduce the following function in K map technique f(A,B,C,D) = πM
(0,3,4,7,8,10,12,14)+d(2,6) (A/M 18)
(iii) Given F(A,B,C,D)= πM(1,3,6,9,11,12,14) draw the K map and obtain the
simplified expression (Nov / Dec 2019)
6. simplify and implement F(A,B,C,D)=∑m(0,4,8,9,10,11,12,14) using only NOR
– OR logic(N/D 19)
7. Use Karnaugh map method to simplify the following Boolean function
F(A,B,C,D) = m(2,4,6,10,12)+d(0,8,9,13). Implement the Boolean function, F
using NOR gates. (A/M 19)
8. With suitable illustration explain the operation of BCD Adder (Decimal
Adder) (A/M 18,17)
9. What is magnitude comparator? Explain in detail.
10. What is decoder? Explain the types with necessary logic diagrams.(N/D 18)
11. What is Encoder? Explain any two types. (N/D 18)
12. With neat sketch elaborate about multiplexers.
13. Design 16:1 multiplexer using two 8:1 multiplexer

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14. (i) Implement the following Boolean function using 4:1Multiplexer.
F(A,B,C)= Σm(1,3,5,6)
(ii) Implement the following Boolean function using 8:1 Multiplexer.
F(A,B,C,D)= Σm(0,1,3,4,8,9,15)(N/D 17)
15. What is mean by Demultiplexer? Explain.

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 ANSWERS
PART-A

1. Construct a full adder using two half adders and OR gates. (A/M 19)

2. Write the truth table of 2 to 4 line decoder and draw its logic diagrams (A/M 19)

3. What is propagation delay. (N/D 18 )

The propagation delay for an integrated circuit (IC) logic gate may differ for each
of the inputs. If all other factors are held constant, the average propagation delay in a
logic gate IC increases as the complexity of the internal circuitry increases.

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4. Draw 1:8 demultiplexer using two 1:4 demultiplexers. (N/D 18)

5. State the different modeling techniques used in HDL (A/M 2018)

 Gatelevel modeling / Structural modeling
 Behavioral modeling
 Dateflow modeling
6. Draw the truth table of full adder (A/M 2018)

7. What is priority encoder? (A/M 2017) (N/D 2014)

A priority encoder is an encoder that includes the priority function. The operation

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of the priority encoder is such that if two or more inputs are equal to 1 at the same time,
the input having the highest priority will take precedence.

8. Draw the circuit 2 to 1 line multiplexer. (A/M 2017) (M/J 2014)

9. What are binary adder. (N/D 2017)

 Half adder
 Full adder
10. Write the truth table for full subtractor. . (N/D 2017)

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11. Design the combinational circuit with 3 inputs and 1 output. The output is 1
when the binary value of the inputs is less than 3. The output is 0 otherwise.
(M/J 2016)

12. Discuss NOR operation with a truth table. (N/D 2015)

This is a NOT-OR gate which is equal to an OR gate followed by a NOT

gate. The outputs of all NOR gates are low if any of the inputs are high.
The symbol is an OR gate with a small circle on the output. The small circle
represents inversion.
13. Draw the truth table and logic diagram for half adder. (N/D 2015)

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14. Implement the function G = ∑m(0,3) using a 2 x 4 decoder.(M/J 2014)

15. Draw the circuit 2 to 1 line multiplexer. (M/J 2014)

16. Draw the logic diagram of a 4 line to 1 line multiplexer.

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17. Design half subtractor using basic gates.

18. How logic circuits of a digital system are classified?

Logic circuits of a digital system are classified into two types as combinational
and sequential.
19. Define Decoder. (N/D 16)
A decoder is a multiple input multiple output of combinational circuit that converts
binary information from n input lines to a maximum of 2 n outputs, such that each output
line will be activated for only one of possible combination of outputs.

20. Define Encoder. (N/D 16)

An encoder is a digital circuit that performs the inverse operation of a decoder.
An encoder has 2n input lines and n output lines. In encoder the output lines generate
the binary code corresponding to the input value.

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21. Define multiplexer.
Multiplexer is a digital switch. If allows digital information from several sources to
be routed onto a single output line.
22. What do you mean by comparator?
A comparator is a special combinational circuit designed primarily to compare the
relative magnitude of two binary numbers
23. What is priority encoder?(N/D 16)
A priority encoder is an encoder circuit that includes the priority function. The
operation of the priority encoder is such that if two or more inputs are equal to 1 at the
same time, the input having the highest priority will take precedence.
24. Distinguish between decoder and demultiplexer.

Decoder Demultiplexer
A decoder is a combinational circuit that A demultiplexer is a circuit that
converts binary information from n input lines receives information from a single line
to a maximum of 2n unique output lines. It is and transmits this information on one 2 n
sometimes called as n-to-m-line decoder, possible output lines.
where m  2n

25. What is a combinational circuit? Give an example(M/J 2016)

Combinational logic circuits are circuits in which the output at any time depends
upon the combination of the input signals present at that instant only and does not
depend upon the past conditions .
 Decoder
 Multiplexer

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  Adder
26. What is look-ahead carry addition?(or) Suggest a solution to overcome the
limitation on speed of an adder.
The speed with which an addition is performed is limited by the time required for
the carries to propagate or ripple through all of the adder. One method of speeding up
the process is by eliminating the ripple carry delay and this is called look-ahead
carryaddition. This method is based on two functions of the full adder, called the carry
generate and carry propagate function.

27. Write down the design procedure for combinational circuits

The problem definition
 Determine the number of available input variables & required O/P variables.
 Assigning letter symbols to I/O variables
 Obtain simplified Boolean expression for each O/P.
 Obtain the logic diagram.
29. List out the advantages and disadvantages of K-map method?
The advantages of the K-map method are
i. It is a fast method for simplifying expression up to four variables.
ii. It gives a visual method of logic simplification.
iii. Prime implicants and essential prime implicants are identified fast.
iv. Suitable for both SOP and POS forms of reduction.
v. It is more suitable for class room teachings on logicsimplification.
The disadvantages of the K-map method are
i. It is not suitable for computer reduction.
ii. K-maps are not suitable when the number of variables involvedexceed four.
iii. Care must be taken to fill in every cell with the relevant entry, suchas a 0, 1 (or)
don’t care terms.

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 ANSWERS
PART-B
1. Explain in detail about the half adder and full adder. (A/M 19,16 )
Adder
Adder is a combinational logic circuit which performs the addition of two binary
bits. For any adder produces two outputs; sum and carry. Adder circuits can be
classified into two types depending on the number of bits in the input variable
Half adder
A combinational circuit that performs the addition of two bits is called half adder.
This circuit needs two binary inputs and two binary outputs. The input variables
designate the augend and addend bits; the output variables produce the sum and carry.
Block diagram

Truth table for Half adder

K map simplification

Logic Diagram

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Limitations of Half adder
In multi digit addition, we have to add two bits along with the carry of previous
digit addition. Effectively such addition requires addition of three bits. This is not possible
with half adders. Hence half adders are not used in practice.
Full adder
A combinational circuit that performs the addition of three bits (two significant bits
and a previous carry) is a full adder. Two half adders can be used to implement a full
adder. It consists of three inputs and two outputs.
Two of the input variable denoted by A and B, represent the two
significant bits added. The third input, Cin represents the carry from the previous lower
significant position. The two outputs are designated by sum and carry.
Block diagram Truth table for Full adder

K Map simplification

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The Boolean function for sum can be further simplified as

Logic diagram

Implementation of full adder with two Half adders and an OR gate

A full adder can also be implemented with two half adders and one OR gate as
shown in fig. The sum output from the second half adder is the exclusive OR of Cin and
the output of the first half adder, giving

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 Implementation of full adder with two half adders and an OR gate

2. Explain in detail about the half subtractor and full subtractor.

Subtractor
Subtractor is a combinational logic circuit which performs the subtraction oftwo
binary bits. For any subtractor will produce a difference and borrow. Subtractor is
classified based on the number of bits performed.
Half subtractor
Half subtractor is a combinational circuit that subtracts the two bits and produces
their difference. It also has an output to specify if a 1 has been borrowed. It has two
inputs x (minuend) and y (subtrahend). It has two outputs, one generates the
difference (D) and other designated as (B0) for borrow.
Block diagram

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Truth table for Half subtractor

K map simplification

Logic Diagram

Limitations of Half Subtractor

In multi digit subtraction, we have to subtract two bits along with the borrow of
previous digit addition. Effectively such subtraction requires subtraction of three bits.
This is not possible with half subtractors. Hence half subtractors are not used in
practice.
Full subtractor
A full subtractor is a combinational circuit that performs a subtraction between two
bits, taking into account that 1 may have borrowed by a lower significant stage. The
circuit has three inputs and two outputs.
The three inputs A, B and Bin denotes the minuend, subtrahend and previous
borrow respectively. The two outputs, D and B0, represent the difference and output
borrow respectively.
Block Diagram

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Truth table for Full subtractor

K Map simplification

The Boolean function for difference can be further simplified as

Logic diagram

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Implementation of full subtractor with two Half subtractor and an OR gate
A full subtractor can also be implemented with two half subtractors and one OR
gate as shown in Fig. The difference output from the second half subtractor is the
exclusive OR of Bin and the output of the first half subtractor, which is same as
difference output of full subtractor.
The borrow output for the circuit shown in fig can be given as

Implementation of full subtractor with two half subtractor andan OR gate

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3. Explain in detail about K-map.
Karnaugh map (K-map)
The Karnaugh map (KM or K-map) is a method of simplifying Boolean algebra
expressions. The Karnaugh map reduces the need for extensive calculations by taking
advantage of human’s pattern-recognition capability. It also permits the rapid
identification and elimination of potential race conditions.
The required Boolean results are transferred from a truth table onto a two-
dimensional grid where, in Karnaugh maps, the cells are ordered in Gray code, and
each cell position represents one combination of input conditions, while each cell
value represents the corresponding output value. Optimal groups of 1s or 0s are
identified, which represent the terms of a canonical form of the logic in the original
truth table. These terms can be used to write a minimal Boolean expression
representing the required logic.
Karnaugh maps are used to simplify real-world logic requirements so that they
can be implemented using a minimum number of physical logic gates. A sum- of-
products expression can always be implemented using AND gates feeding into an OR
gate, and a product-of-sums expression leads to OR gates feeding an AND gate.
Karnaugh maps can also be used to simplify logic expressions in software design.
K Maps for 1,2,3,4 variables
The basis of this method is a graphical chart known as K map. It contains boxes
called cells. Each of the cell represents one of the 2n possible products that can be
formed from n variables. Thus a 2 variable K map contains 22=4 cells, a 3 variable K
map contains 23 = 8 cells and so on.

1, 2, 3 and 4 variables with product terms

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Grouping of cells
Grouping of two adjacent cells

In K map we can group tow adjacent 1s, the resultant group is called pair.
Possible combinations

Possible combinations of grouping of two adjacent cells

Grouping of four adjacent cells
In K map we can group four adjacent 1s, the resultant group is called quad.
Possible combinations

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 Possible combinations of grouping of four adjacent cells
Grouping of eight adjacent cells
In K map we can group eight adjacent 1s, the resultant group is called octet.
Possible combinations

Possible combinations of grouping of eight adjacent cells

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4.(i) Minimize the expression (A/M 18)

(ii) Reduce the following expression in K map technique

(iii) Reduce the following function in K map technique

f(A,B,C,D) = Σm(0,1,4,8, 9,10)

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(iv) Simplify the Boolean function
f (A,B,C,D,E)=Σm (0,2,4,6,9,11,13,15,17,21,25,27,29,31)

(v) Reduce the following function in K map techniquef(A,B,C) = Σm(0,1,3,7)+

Σd(2,5)

5.(i) Reduce the following function in K map technique f(A,B,C,D) =

πM(0,2,3,8,9,12,13,15)

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(ii) Reduce the following function in K map technique
f(A,B,C,D) = πM (0,3,4,7,8,10,12,14)+d(2,6) (A/M 18)

(iii) Given F(A,B,C,D)= πM(1,3,6,9,11,12,14) draw the K map and obtain the
simplified expression (Nov / Dec 2019)

32
6. simplify and implement F(A,B,C,D)=∑m(0,4,8,9,10,11,12,14) using only NOR –
OR logic(Nov / Dec 2019)

33
7.Use Karnaugh map method to simplify the following Boolean function
F(A,B,C,D) = m(2,4,6,10,12)+d(0,8,9,13). Implement the Boolean function, F using
NOR gates. (Apr/May -2019)

34
8. With suitable illustration explain the operation of BCD Adder (Decimal Adder)
(A/M 2018,17)
BCD Adder
The digital systems can handle the decimal number in the form of binary coded
decimal numbers (BCD). A BCD adder is a circuit that adds two BCD digits and
produces a sum digit also in BCD.
To implement BCD Adder Circuit we require :
 4-bit binary adder for initial addition
 Logic circuit to detect sum greater than 9 and
 One more 4-bit adder to add 01102 in the sum if sum is greater than 9 or carry is
1.
The logic circuit to detect sum greater than 9 can be determined by simplifying
the Boolean expression of given truth table.

Truth Table

 Y=1 indicates sum is greater than 9, we can put one more term, Cout in the
above expression to check whether carry is one. Of any condition is satisfied we
add 6(0110) in the sum.

35
K map simplification

 With this design information we can draw the block diagram of BCD adder as
shown in the fig.
Block Diagram
 The two BCD numbers, together with input and carry are first added in the top 4-
bit binary adder to produce a binary sum.
 When the output carry is equal to zero (when sum ≤9 and Cout=0) nothing (zero)
is added to the binary sum.
 When it is equal to one (when sum >9 or Cout=1), binary added to the binary
sum through the bottom 4-bit binary adder.
 The output carry generated from the bottom binary adder can be ignored, since it
supplies information already available at the output carry terminal.

Block diagram of BCD adder

36
9. What is magnitude comparator? explain in detail.
Magnitude comparator
A comparator is a special combinational circuit designed to compare the relative
magnitude of two binary numbers. It receives two n bit numbers A and B as inputs and
outputs are A>B, A=B and A<B. Depending upon the relative magnitudes of the two
number, one of the outputs will be high.
Block Diagram

Truth Table
Inputs Outputs
A1 A0 B1 B0 A>B A=B A<B
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

37
K Map simplification

Logic diagram

38
10. What is decoder? Explain the types with necessary logic diagrams.(N/D 18)
Decoder
A decoder is a multiple input multiple output of combinational circuit that converts
binary information from n input lines to a maximum of 2 n outputs, such that each output
line will be activated for only one of possible combination of outputs.

General structure of decoder

2 to 4 line decoder
In this decoder, 2 inputs are decoded into four outputs, each output representing
one of the minterms of two input variables. The two inverters provide the complement
of the inputs, and each one of four AND gates generates one of the min terms.
Truth table

Logic Diagram

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3 to 8 line decoder
In this decoder, 3 inputs are decoded into eight outputs, each output representing
one of the minterms of three input variables. The three inverters provide the complement
of the inputs, and each one of eight AND gates generates one of the min terms.

Truth Table

Logic Diagram

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11. What is Encoder? Explain any two types.(N/D 18)

Encoder
An encoder is a digital circuit that performs the inverse operation of a decoder.
An encoder has 2n input lines and n output lines. In encoder the output lines generate
the binary code corresponding to the input value.

General structure of encoder

Octal to binary encoder
It has eight inputs, one for each octal digit, and three outputs that generate the
corresponding binary code. In encoders, it is assumed that only one input has a value of
1 at any given time.
Truth table of Octal to binary encoder

Logic Diagram

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Priority Encoder
A priority encoder is an encoder that includes the priority function. If two or more
inputs are equal to 1 at the same time, the input having the highest priority will take
precedence.

Truth table of Priority encoder

The table shows the D3 input with highest priority and D0 input with lowest priority.
When D3 input is high, regardless of other inputs, output is 11. The D2 has the next
priority. When D3=0 and D2=1, regardless of other two lower priority input, output is 10.
The output for D1 is generated only if higher priority inputs are 0 and so on. The output V
indicates one or more of the inputs are equal to 1. If all inputs are equal to 0, V is equal
to 0, and other two outputs of the circuits are not used.

K- Map simplification

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Logic Diagram

12. With neat sketch elaborate about multiplexers.

Multiplexer
Multiplexer is a digital switch which allows digital information from several
sources to be routed into a single output line. The basic multiplexer has several data-
input lines and a single output line.
A multiplexer is also called as a data selector. The fig shows the general
structure of multiplexer. Normally, there are 2n input lines and n selection lines and one
output line. The selection of a particular input line is controlled by the set of select lines.
The size of the multiplexer is specified by number 2n input lines.

General Structure of Multiplexer

4 to 1 Multiplexer
The 4 to 1 multiplexer, the 4 represent the number of inputs and one represent
the output line. The select lines (2n=4; n=2) S1 and S0 to select one of the four inputs.

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Block Diagram

Truth Table of 4 to 1 Multiplexer

Logic Diagram

 Each of four lines D0 to D3 is applied to one input of an AND gate. Selection

lines are decoded to select the particular AND gate.
 When S1S0=01, the AND gate associated with data input D 1 has two of its inputs
equal to 1 and the third input connected to D 1. The other three AND gates have at

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 least one input equal to 0, which makes their outputs equal to 0. The OR gate
output is equal to the value of D1.

8 to 1 Multiplexer
For the combination of selection input, the data line is connected to the output
line. The circuit shown below is an 8 to 1 multiplexer. The 8 to1 multiplexer requires 8
AND gates, one OR gate and 3 selection lines.
As an input, the combination of selection inputs are giving to the AND gate with
the corresponding input data lines. In a similar fashion, all the AND gates are given
connection. In this 8 to 1 multiplexer, for any selection line input, one AND gate gives a
value of 1 and the remaining all AND gates give 0. and, finally, by using OR gate, all the
AND gates are added; and, this will be equal to the selected value.

Block Diagram

Truth Table of 8 to 1 Multiplexer

Enable Select inputs Output
A B C Y
0 X X X 0
1 0 0 0 D0
1 0 0 1 D1
1 0 1 0 D2
1 0 1 1 D3
1 1 0 0 D4
1 1 0 1 D5
1 1 1 0 D6
1 1 1 1 D7

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Logic Diagram

13. Design 16:1 multiplexer using two 8:1 multiplexer

Solution
Step 1: Connect the select lines (S2,S1,S0) of two multiplexers in parallel
Step 2: Connect Least significant bit select line (S3) such that when S3=0 MUX 1 is
enabled and when S3=1 MUX 2= is enabled.
Step 3: Logically OR the outputs of two multiplexers to obtain the final output Y.

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Logic Diagram

Fig: 16:1 multiplexer using two 8:1 multiplexer

14.(i) Implement the following Boolean function using 4:1Multiplexer.

F(A,B,C)= Σm(1,3,5,6)
Solution
Step 1: Connect least significant variables as a select inputs of multiplexer. Here
connect C to S0 and B to S1.
Step 2: Derive inputs for multiplexer using implementation table.

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Step 3: The first row lists all those minterms where A is complemented and the second
row lists all the minterms with A complemented. The minterms given in the function are
circled and the n each column is inspected separately as follows
 If both minterms in a column are not circled, apply 0 to the corresponding input.
 If both minterms in a column are circled, apply 1 to the corresponding input.
 If the minterm of second row is circled and the minterm of first row is not circled,
A is applied to the corresponding multiplexer input
 If the minterm of first row is circled and the minterm of second row is not circled,
A applied to the corresponding multiplexer input.

(ii) Implement the following Boolean function using 8:1 Multiplexer. F(A,B,C,D)=
Σm(0,1,3,4,8,9,15)
Solution
Step 1: Connect least significant variables as select inputs of multiplexer. Here connect
D to S0 ,C to S1 and B to S2.
Step 2: Derive inputs for multiplexer using implementation table.

Step 3: Multiplexer Implementation

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15. What is mean by Demultiplexer? Explain.
Demultiplexers
A demultiplexer is a circuit that receives information on a single line and transmits
this information one of 2n possible output lines. The selection of specific output line is
controlled by the values of n selection lines.

1:2 Demultiplexer
In this DEMUX, we have one input line and two output lines. There is one select
line S and this could be 0 or 1. When S=0, the AND gate A1 is selected and A2 is
disabled. Date from X (input line) flows to output line. When S=1, X flows to line B.

1:4 Demultiplexer

The 1 to 4 demultiplexer consists of one input, four outputs, and two control lines
to make selections. The input bit is Data D in with two select lines S1 and S0. The input bit
Din is transmitted to four output bits Y0, Y1, Y2, and Y3. When S1 S0 is 01 The upper
second AND gate is enabled while the other AND gate is disabled.
Thus, only one data is transmitted at Y1. If Din is low, then Y1 is low and if Din is
high, Y1 is high. The value of Y1 depends on the value of Din. If the control input changes
to S1 S0 =10 all the gates are disabled except third AND gate from the top, then Din is
transmitted to output Y2.

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Truth table

Logic Diagram

1:8 Demultiplexer

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 The 1 to 8 demultiplexer consists of one input, eight outputs, and three control
lines to make selections. The input bit is Data Din with three select lines S2, S1 and S0.
The input bit Din is transmitted to eight output bits Y0, Y1, Y2, Y3, Y4, Y5, Y6 and Y7.

Logic Diagram

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Table: Truth table of 1:8 Demultiplexer

1:16 Demultiplexer
The 1 to 16 demultiplexer consists of one input, sixteen outputs, and four control
lines to make selections. The input bit is Data Din with four select lines S3, S2, S1 and S0.
Logic Diagram

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