THE EFFECT OF SHALLOW TRENCH ISOLATION (STI) TOPOLOGY, SIDEWALL

DOPING AND LAYOUT-RELATED STRESS ON RADIATION-INDUCED LEAKAGE

CURRENT

By

Nadia Rezzak

Thesis

Submitted to the Faculty of the

Graduate school of Vanderbilt University

in partial fulfillment of the requirements

for the degree of

MASTER OF SCIENCE

in

Electrical Engineering

May, 2010

Nashville, Tennessee

Approved by:

Professor Ronald D. Schrimpf

Professor Michael L. Alles

i
 ACKNOWLEDGEMENTS

I would first of all like to thank Dr. Schrimpf for his continual support, confidence, and

guidance throughout this project. Not only has Dr. Schrimpf been a tremendous source of

assistance and encouragement, but I would not even be a graduate student if it were not for Dr.

Schrimpf’s quick responses to my numerous e-mails, and his support of my application prior to

entering Vanderbilt University.

I would also like to thank Professor Michael Alles who basically acted like a second

advisor to me throughout this work. His useful comments and support for my research helped

me to have a clear idea on whatever needed to be done.

I thank Yanfeng Li from Accelicon for providing wafers and allowing me to complete

this work. I thank ISDE, DTRA, NRL, USAF MURI and Vanderbilt School of Engineering for

providing the funds for this work. I also would like to thank John Sochacki and Professor

Barnaby from (Arizona State University) who contributed to this work. I would like to thank all

the friends from graduate school: Enxia, Mike, Nelson, John, Vishwa, Tania, David, Daniel,

Ashley, Jonny, Megan, Andrew, Wole, Cher, for their friendship. Last but not least I thank my

mother and my father, my sister Myriam, and Pierre for everything they have done for me.

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 TABLE OF CONTENTS

Page

ACKNOWLEDGMENTS ............................................................................................... ii

LIST OF FIGURES ........................................................................................................ v

LIST OF TABLES ......................................................................................................... ix

Chapter

I. INTRODUCTION ....................................................................................... 1

A. Overview ........................................................................................................... 1
B. CMOS Isolation Techniques .................................................................... 3
1. Shallow Trench Isolation ............................................................. 6
a. STI variability ................................................................... 6
b. TID response variation ...................................................... 7
c. STI edge topology............................................................. 9
d. Sidewall doping .............................................................. 11
C. Channel engineering techniques ............................................................. 13
1. Short channel effects: Punch through & DIBL ........................... 14
2. Anti-Punch Through (APT) implantation ................................... 15
3. Halo implantation ...................................................................... 15
4. LDD (lightly doped drain) implants ........................................... 16

II. DEVICE, SIMULATIONS AND EXPERIMENTS ................................. 18

A. Overview ......................................................................................................... 18
B. Simulation approach .............................................................................. 19
C. Device structures.................................................................................... 20
D. Experiments ........................................................................................... 21

III. THE SENSITIVITY OF RADIATION-INDUCED LEAKAGE TO STI

TOPOLOGY AND SIDEWALL DOPING ............................................... 24

A. Overview ......................................................................................................... 24
B. Bulk CMOS ........................................................................................... 24
1. Device-to-device variability....................................................... 24
2. Simulation details ...................................................................... 26
3. Simulation results ...................................................................... 28
a. Pre-irradiation results ...................................................... 29

iii
 i. Trench recess depth and sidewall doping.. 29
ii. Effect of oxide thinning ........................... 32
b. Post-irradiation results ......................................... 33
i. Planar trench and recessed by 36 nm ........ 33
ii. Drain bias effect on leakage current ......... 36
iii. Non uniform sheet charge distribution ..... 38
4. Conclusion ................................................................................ 41

IV. LAYOUT EFFECTS ................................................................................. 43

A. Overview ............................................................................................... 43
B. Introduction ........................................................................................... 43
C. Experiment details ................................................................................. 44
D. Effect of gate layout on TID induced leakage current ............................. 44
1. Technology description ............................................................. 44
2. Rectangular gate: HVT/AVT/LVT comparison.......................... 45
3. Annular gate devices ................................................................. 48
4. GAS/GAD type of hardening ..................................................... 49
E. I/O devices vs. core devices ................................................................... 51
F. Layout dependence effect on TID induced leakage current ..................... 54
1. Active space distance effect on TID induced leakage current ..... 55
2. Channel width effect on TID induced leakage current ................ 60
G. Conclusion ............................................................................................. 63

V. CONCLUSION .......................................................................................... 64

VI. REFERENCES .......................................................................................... 67

iv
 LIST OF FIGURES

Figure Page

Fig. 1.1. (a) Illustration of drain-source leakage path in nFET and (b) its cause: oxide
trapped charge buildup in the isolation oxide (assumed interfacial sheet charge) [3] ........ 2

Fig. 1.2. Transmission electron micrograph (TEM) images of (a) LOCOS and (b)
Trench regions (STI), showing less encroachment on the channel width (Weff ) for
Trench than LOCOS. [4] ................................................................................................. 5

Fig. 1.3. Yield versus scaling size for LOCOS versus Trench, showing reduced yield
for LOCOS for channel scaling below 0.4 µm [4] ........................................................... 5

Fig. 1.4. Potential variability in the total dose hardness of two identically processed
lots (without hardening) .................................................................................................. 7

Fig. 1.5. Leakage current evolution with TID of NMOS core transistors from different
foundries [10].................................................................................................................. 8

Fig. 1.6. TEM of shallow trench isolation that has recessed below the silicon active
region and the trench comer shows the gate oxide and gate electrode wrapping around
the comer [2] .................................................................................................................. 9

Fig. 1.7. TEM cross-section at the active-to-field oxide region highlighting the
differences in STI recess for two isolation processes [11] ................................................ 9

Fig 1.8. Simulated I-V characteristics for three different trench profiles. For the
overfilled trench profile, the trench insulator extends 100 nm above the trench
corner [2] ...................................................................................................................... 10

Fig. 1.9. I-V curves, pre- and post-radiation, for unhardened devices, with either (a)
long STI polish time, or (b) short STI polish time. Device size is 10/0.4 um [2] ........... 11

Fig. 1.10. “As drawn” and parasitic sidewall devices [3] ............................................... 12

Fig 1.11. Simulated subthreshold I-V characteristics of both the active transistor and
the parasitic sidewall transistors. The impact of using enhanced sidewall doping
and n+ pullback on the parasitic sidewall transistors is shown [2] .................................. 13

Fig. 1.12. Drain current vs. gate voltage with an increased VDS [12] ............................ 14

Fig. 1.13. Anti-punch-through implantation process [13] ............................................... 15

Fig. 1.14. Halo implantation process [13] ...................................................................... 16

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Fig. 1.15. LDD implantation [13] ................................................................................. 17
Fig. 2.1. Structure in which the STI fill is recessed by 72 nm. There is thinning of
the oxide at the sidewall corner. The right figure gives a more detailed view of the
rounded corner .............................................................................................................. 19
Fig. 2.2. (a) Example layout of annular gate. (b) Example layout of a gate around
source (GAS) ................................................................................................................ 21
Fig. 2.3. 2X12 Pad Arrangement ................................................................................... 22
Fig. 2.4. Tile arrangement example ............................................................................... 23
Fig. 3.1. Off-state leakage current evolution with TID of a 90 nm NMOS core
transistors from different dies ........................................................................................ 25
Fig. 3.2. NMOS device with gate/STI overlap and the edge of interest identified
by the black dotted line. The outer STI region shows the shallow trench isolation oxide.
Active silicon and gate polysilicon are also identified. The red dotted line will serve
as the cut-line for future figures ..................................................................................... 26

Fig. 3.3 (a) Left: Active region/STI transition with planar geometry; the brown region
represents the STI and gate oxide. The red region represents the polysilicon. The blue
region represents the active silicon, and the right figure gives a more detailed view of
the corner. (b): The left figure shows a structure in which the STI fill is recessed by
72 nm. There is thinning of the oxide at the sidewall corner. The right figure gives a
more detailed view of the corner ................................................................................... 27
Fig. 3.4. Id-Vg pre-radiation curves for 90 nm NMOS device with planar STI fill,
as well as variations in which the top of the fill is recessed by 10.8, 18, 36, 54 and
72 nm ............................................................................................................................ 30
Fig. 3.5. Impact of active region doping on the pre-irradiation off state leakage
current evolution with trench recess depth ..................................................................... 31
Fig. 3.6. Net doping vs. depth (left axis) and simulated leakage (right axis) vs. trench
recess depth. The leakage is high when the top of the trench fill occurs at a depth
where the doping is relatively light ................................................................................ 32
Fig. 3.7. Simulated Id-Vg characteristics for two different “Oxide thinning” ................. 33
Fig. 3.8 (a). Radiation response for structures with the STI fill recessed by 36 nm and
no sidewall doping. 3.8 (b). Radiation response for structure with the STI fill recessed
by 36nm , with excess sidewall doping of 5  1018 cm-3 of boron .................................. 34

Fig. 3.9. Leakage current evolution with trench recess depth for both pre-radiation and
post-radiation case......................................................................................................... 35

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Fig. 3.10. Leakage current evolution with charge concentration of a planar and
recessed by 36 and 72nm devices .................................................................................. 36

Fig. 3.11. Drain current vs. gate voltage for two drain bias conditions (50mV and
1.2V) for the recessed by 36 nm case ............................................................................ 37
Fig. 3.12. The pre- and post-irradiation results before and after the addition of excess
sidewall doping to the case in which the trench fill is recessed by 36 nm, at Vd =1.2V ... 38
Fig. 3.13. 2D REM simulations for planar and recessed by 36 nm devices..................... 39
Fig. 3.14. Comparison of uniform and non uniform charge distribution for the
recessed by 36 nm device, showing that the concentration near the surface dominates
the response .................................................................................................................. 40
Fig. 3.15. Non uniform charges distribution for the recessed by 36 nm device, showing
that charge trapped along the top half of the sidewall have the most impact on the
leakage current .............................................................................................................. 41
Fig. 4.1. Example layout of typical NMOS transistor.................................................... 45

Fig. 4.2. Id-Vg pre- and post-irradiation characteristics of two AVT devices with
different W/L ................................................................................................................ 46
Fig. 4.3. Id-Vg pre- and post-irradiation characteristics of three different device types:
a) HVT, b) AVT, c) LVT .............................................................................................. 47
Fig. 4.4. Example layout of typical NMOS annular gate transistor ................................ 48

Fig. 4.5. Id-Vg pre- and post-irradiation characteristics of three different device types:
a) HVT, b) AVT, c) LVT, with annular type of hardening and W/L=10/0.08 ................. 49
Fig. 4.6. Example layout of a NMOS transistor with GAS type of hardening ................ 50

Fig. 4.7. Id-Vg pre- and post-irradiation characteristics three different device types:
a) HVT, b) AVT, c) LVT, with GAS/GAD type of hardening and W/L=10/0.08 ........... 51
Fig. 4.8. Id-Vg pre- and post-irradiation characteristics of AVT device with
W/L=2/0.1 .................................................................................................................... 52
Fig. 4.9. Id-Vg pre- and post-irradiation characteristics of I/O device with
W/L=2/0.24................................................................................................................... 52
Fig. 4.10. Doping profile as a function of depth along the sidewall [8] .......................... 53

Fig. 4.11. Id-Vg pre- and post-irradiation characteristics of two IO devices with
annular type of hardening. (a) IO device operating at 2.5 V, with W/L=10/0.72.
(b) IO device operating at 3.3 V, with W/L=10/1.0 ........................................................ 54
Fig. 4.12. Typical MOS layout top view ........................................................................ 56

vii
Fig. 4.13. Pre-irradiation threshold voltage versus the active space distance (SA) .......... 57
Fig. 4.14. Pre-irradiation leakage current evolution with active space (SA) ................... 57
Fig. 4.15. (a) Top view of nMOS device showing two different cutlines, where
“Cutline X” gives the 2D view on the right and “Cutline Y” gives a 2D view showing
the leakage path (edge of interest) along the STI sidewall. (b) Schematic mechanism
of increasing Vth in nMOS [3] ....................................................................................... 58
Fig. 4.16. Pre-irradiation and post-irradiation leakage current evolution with active
space distance (SA) ....................................................................................................... 59

Fig. 4.17. Pre-irradiation and post-irradiation leakage current evolution with channel
width ............................................................................................................................. 60
Fig. 4.18. Id-Vg pre-irradiation curves for three different widths .................................... 62
Fig. 4.19. Id-Vg post-irradiation curves for three different widths ................................... 62

Fig. 5.1. Normalized leakage currents to the planar pre-rad case (Ileak0), versus the
percentage recess .......................................................................................................... 65

viii
 LIST OF TABLES

Table Page

Table 2.1. Possible device types in modern bulk CMOS technologies .......................... 21

ix
 CHAPTER I

INTRODUCTION

A. Overview

Scaling of gate oxides in bulk complementary metal–oxide–semiconductor (CMOS) devices

to thinner dimensions has reduced, almost to elimination, the significance of threshold-voltage

shifts due to total-ionizing dose (TID) radiation-induced charge buildup in the thin oxides [1]. As

a result, the dominant TID effect in most CMOS technologies is now charge buildup in the

shallow-trench isolation (STI) [2]. Charge trapped in the isolation dielectric, particularly at the

Si/SiO2 interface along the sidewalls of the trench oxide, creates a leakage path that becomes the

dominant contributor to off-state drain-to-source leakage current in n-channel MOSFETs [3].

This effect is illustrated schematically in Fig. 1.1, which shows (a) the edge leakage path from

drain-to-source on the planar (top) view of the nMOS and (b) the device cross-section with the

oxide trapped charge buildup in the STI, which induces the leakage path.

1
 Fig. 1.1. (a) Illustration of drain-source leakage path in nFET and (b) its cause: oxide
trapped charge buildup in the isolation oxide (assumed interfacial sheet charge) [3].

Also, scaling is making the use of some (radiation hardened by design) RHBD structures,

namely edgeless devices, prohibitive due to design rules for manufacturability and lithography

limitations. Wider devices are often laid out with fingers, creating multiple active/STI edges.

Understanding factors that determine the edge-related leakage current and possible variability in

it, is important since characterization of a process for TID response often involves measurement

on a relatively small number of devices.

Chapter 2 of this work examines the TID sensitivity of edge-related leakage current in

CMOS devices to a key parameter: the STI contour at the active-to-isolation transition, combined

with sidewall doping variations. These characteristics may in part account for observed

differences among supposedly identically processed devices, between devices from various

vendors at the same technology node, and between low power and high performance process

variants. Implications for characterizing variations in TID sensitivity due to processing are noted,

2
and reduction of sensitivity to STI variation using sidewall doping is quantified. In Chapter 3, the

STI-stress effect on TID-induced leakage current is examined using experimental results. The

physical mechanisms that affect the TID sensitivity are considered, particularly changes in the

doping profile of the channel edges and at the STI sidewall, due to STI stress.

This work first started with a simulation-based study on 90 nm CMOS, based on the IBM

process, where the STI edge topology (specifically the amount of trench recess) and sidewall

doping aspects (presented and discussed in Chapter 3) were examined. This was motivated by

published work (discussed in Chapter 1) and also measured on some 90 nm CMOS devices that

were accessible later during this work (shown in chapter 3, to motivate the simulation study). An

experiment was planned to support the simulation study (devices with purposefully varied trench

recess were supposed to be fabricated); however the planned experimental devices were not

available in the timeframe originally projected (due to issues in the fabrication).

However, 90 nm CMOS devices from another vendor became available. While these devices

were not simulated explicitly, the trends observed in experimental characterization were both

interesting and relevant to the simulation results at the same technology node. Specifically two

very interesting results were discovered: the active space (SA) distance effect, as well as the

channel width effect on TID-induced leakage current (presented in chapter 4). Finally

conclusions related to 90 nm process variables (STI variability, sidewall doping and layout

related stress effects) examined throughout this work are drawn (in chapter 5).

B. CMOS Scaling and Bulk Isolation Technologies

The evolution of IC density requires that device geometries scale proportionately. Not only

is the geometry changing from one device generation to the next, but also the processing

3
techniques, materials, and processing tools are changing. Commercial requirements (density)

have driven the basic isolation methods, impacting MOS radiation hardness. Therefore hardening

requirements have had to develop methods to harden the corresponding approaches.

To meet increasing demand for hardened ICs of greater device density, a hardened field

oxide structure smaller than the direct-moat type (which is a type of radiation-hard field oxide

developed by Sandia National Laboratory) was necessary [4]. The semiconductor industry

pursued various new lateral oxide isolation approaches, such as local oxidation of silicon

(LOCOS), poly-buffered LOCOS, and selected poly-Si oxidation (SEPOX), each having

hardening advantages and disadvantages. Of major concern to the IC builder is the extent of

oxide encroachment, such as the LOCOS “bird’s beak,” that reduces active device area and

causes increased radiation sensitivity due to the mechanical stress in the oxide. To meet the

scaling requirements, STI approaches, with no bird’s beak encroachment, were commonly used.

Fig. 1.2 shows a comparison of LOCOS and STI structures, where you can see how the effective

channel width (Weff) is reduced by the “bird’s beak” inherent to LOCOS. As it can be seen from

Fig. 1.3, due to yield problems, LOCOS lateral isolation needed to be abandoned for technology

generations below 0.4 µm [5].

4
Fig. 1.2. Transmission electron micrograph (TEM) images of (a) LOCOS and (b) Trench
regions (STI), showing less encroachment on the channel width (Weff ) for Trench than
LOCOS. [4]

Fig. 1.3. Yield versus scaling size for LOCOS versus Trench, showing reduced yield for
LOCOS for channel scaling below 0.4 µm [4]

5
 However, there is a wide variation in the radiation hardness of STI. In some cases, TID

failure levels for STI were observed at less than 10 krad(SiO2) [2], while in other cases radiation

hardness levels of greater than 100 krad(SiO2) were measured on commercial technologies. It is

understood that the hardness of the STI region depends on a number of features, including

geometry and type of trench refill oxide, which will be investigated in detail in chapter 3.

1. Shallow Trench Isolation

a. STI variability

One of the motivating factors in this research was the observation that different

fabrication lots with supposedly identical processing, and nearly identical pre-irradiation leakage

currents, could exhibit vastly different TID response with one lot showing a minimal increase in

leakage and the other a dramatic increase as shown in Fig. 1.4 [6]. This difference was

hypothesized to be related to differences in the STI.

6
 Fig. 1.4. Potential variability in the total dose hardness of two identically processed lots
(without hardening).

Key parameters that may affect edge leakage, as well as TID response, are the shape of

the transition from the active to the isolation region and the doping of the active silicon region

along the sidewall [2]-[3]-[8].

b. TID response variation

In [2] it was demonstrated that recessed STI fill could exacerbate the TID response in a

0.5 µm CMOS technology. The concept of recessed fill is discussed in detail below. More

recently it was demonstrated that radiation-induced leakage current and threshold-voltage shifts

in narrow transistors may depend strongly on the details of edge effects [9], and that significant

differences in degradation of NMOS transistor characteristics can be observed at the 130 nm

technology node from different manufacturers, as shown in Fig. 1.5 [10].

7
 Fig. 1.5. Leakage current evolution with TID of NMOS core transistors from
different foundries [10].

This large foundry-to-foundry variation may be attributed to differences in the nominal

fabrication processes, namely in the STI oxide growth/deposition process and planarity, and/or in

the doping profiles of the devices [10]. Further, within a given manufacturer’s process, it is

possible that the degree of recess may vary across a wafer depending on device widths and inter-

device spacing (process loading) for a specific design, or from lot to lot or fabrication location.

Such subtle variations may not affect standard electrical monitor measurements or be important

for normal electrical operation, but may have implications for the TID response of a large circuit.

Finally, a single manufacturer may have variations in nominal processes to target high

performance vs. low power applications, typically including differences in doping to adjust

leakage and threshold voltages; such doping differences may have implications for the TID

response.

8
 c. STI edge topology

During the fabrication process it is challenging to control planarity precisely, and trench

fill can be recessed unintentionally. If the trench oxide becomes recessed below the silicon active

region the gate oxide will wrap around the silicon corner as illustrated in Fig. 1.6.

Fig. 1.6. TEM of shallow trench isolation that has recessed below the silicon active
region and the trench comer shows the gate oxide and gate electrode wrapping
around the comer [2].

Fig. 1.7. TEM cross-section at the active-to-field oxide region highlighting the
differences in STI recess for two isolation processes [11].

9
 An example of variation in amount of trench recess, of two STI with different amount of

recess is shown in Fig. 1.7. The recess depth from STI-B is 2X that of STI-A, leading to

corresponding increase in sidewall gate [11]. The peak electric fields at the trench corner region

are further enhanced if the trench fill is recessed below the trench corner, and high electric fields

in the trench corner region have been shown to create anomalous humps even for non-irradiated

devices [2]. Fig. 1.8 shows the subthreshold I-V characteristics of three different trench profiles:

planar, recessed and overfilled, and the results show a large hump for the recessed trench; for a

planar trench the hump is significantly reduced and no hump exists for an overfilled trench.

Fig 1.8. Simulated I-V characteristics for three different trench profiles. For the
overfilled trench profile, the trench insulator extends 100 nm above the trench corner
[2].

10
 The effects of polishing time are explicitly shown in Figs. 1.9(a) and 1.9(b), which shows

the pre- and post-radiation I-V curves for devices from lots with two extremes of polishing time.

These two devices are from the same lot, with a processing split at STI polish representing the

expected polishing time process window. The device with the longer STI polish has two orders

of magnitude greater leakage at 100 krad(SiO2) than the device with reduced polish time. The

reduced amount of trench recess for reduced polish times translates into less radiation-induced

edge leakage. However, it should be noted that there is a process trade-off, since the shorter

polish may leave trench fill oxide over the pad nitride. This oxide will prevent the nitride from

being stripped off, resulting in non-functional devices in those areas [2]. The change in polish

time also affects the variability of the total dose response for unhardened STI.

(a) (b)

Fig. 1.9. I-V curves, pre- and post-radiation, for unhardened devices, with either (a) long
STI polish time, or (b) short STI polish time. Device size is 10/0.4 um [2].

d. Sidewall doping

The primary cause for radiation-induced off-state drain-to-source leakage is:

11
 • The reduction in the threshold voltage

• The increase in current for the parasitic n-channel MOSFET associated with the

edges of the “as drawn” device shown in Fig. 1.10.

Prior to radiation exposure, the leakage current of the parasitic devices is low due to the

relatively large effective gate oxide thickness (high threshold voltage of the parasitic devices)

relative to the “as drawn” structure and small effective width. After irradiation, the threshold

voltage shift in the parasitic edge transistors ultimately leads to an increase in the off-state

leakage current.

Fig. 1.10. “As drawn” and parasitic sidewall devices [3].

Fig. 1.11 illustrates the impact of using enhanced sidewall doping and n+ pullbacks on

the simulated I-V characteristics of both the active transistor and the parallel parasitic sidewall

transistors. The simulations were performed by physically splitting the gate contact at the trench

corner to separate the contributions due to active and parasitic transistors [2]. Also shown are the

12
simulated parasitic sidewall I-V curves with enhanced sidewall doping, and with combined

sidewall implants and a 0.3 µm n+ pullback. Increased sidewall doping alone increases the

parasitic threshold voltage above the active gate threshold and thus no noticeable hump is

observed in the pre-irradiation I-V curve.

Fig 1.11. Simulated subthreshold I-V characteristics of both the active transistor and
the parasitic sidewall transistors. The impact of using enhanced sidewall doping and
n+ pullback on the parasitic sidewall transistors is shown [2].

C. Channel engineering techniques

Typically, channel engineering techniques, an effective method to improve device

performance, is accomplished by implants, which can also impact local sidewall doping. In this

section, different implants used to increase device performance are presented.

13
 1. Short channel effects: Punch through & DIBL

The source and drain space charge regions could be problematic in short channel transistors

as Leff gets smaller [12]. Even though the surface doping concentration is engineered to control

the device parameters, the sub-surface behavior of these junctions could lead to significant

current. This phenomenon is known as “punch through,” where the zero gate-bias drain current

increases with increasing VDS as shown in Fig. 1.12. A high energy anti-punch through implant is

necessary to influence the channel profile deep in the silicon. Drain induced barrier lowering

(DIBL) is a secondary effect in MOSFETs referring originally to a reduction of threshold voltage

of the transistor at higher drain voltages, and plays a stronger role if there is a lower gate bias

present.

Fig. 1.12. Drain current vs. gate voltage with an increased VDS [12].

14
 2. Anti-Punch Through (APT) implantation

An APT (Anti Punch Through) implant is used to reduce punch through in short channel

MOSFETS. It can also play the role of the VT adjust implant, where it gets implanted right under

the gate oxide, changing the substrate doping concentration. The anti-punch-through

implantation process is shown in Fig. 1.13

Fig. 1.13. Anti-punch-through implantation process [13]

3. Halo implantation

Halo implantation, also called pocket implantation, is a technique used to reduce punch

through (substrate DIBL) in short channel MOSFETS. This implant is locally introduced at low-

energy and low current with an implantation angle of 45° (as shown in Fig 1.14) at the tip of the

LDD regions to better control the substrate doping concentration. As a result, the substrate

doping concentration can be locally increased, thus reducing the depletion region between the

source/drain regions and the substrate.

15
 Fig. 1.14. Halo implantation process [13]

4. LDD (lightly doped drain) implants

As Leff gets smaller and the drain voltage increases, the longitudinal electric field on the drain

side gets higher and the electrons continue to gain kinetic energy. Electrons with high energy in

the depletion region are called “Hot” carriers, potentially leading to “Hot Carrier Injection”. Hot

carrier injection could cause long term reliability issues such as long term VT changes, and

saturation and leakage current increases. A common approach in reducing this phenomenon is to

reduce the maximum electric field on the drain side, which reduces available electrons for

tunneling and suppresses the hot electron effect. This is typically done with LDD (lightly doped

drain) implants. The LDD implantation is shown in Fig. 1.15.

16
Fig. 1.15. LDD implantation [13]

17
 CHAPTER II

DEVICES, SIMULATIONS, AND EXPERIMENTS

A. Overview

In this chapter, the different devices and structures used in this study are presented and

described. Simulation details and the experiment setup are detailed. As stated in chapter 1, this

work first started with a simulation based study using 90 nm CMOS devices based on the IBM

process. STI edge topology and sidewall doping aspects were examined in detail, since trench

fill can be recessed unintentionally during the fabrication process, and therefore it is very

important to understand how much variability in the leakage current can occur due to the

variations in the trench fill recess (presented and discussed in Chapter 3). An experiment was

planned to support the simulation study, however the planned experimental devices were not

available in the timeframe originally projected (due to issues in the fabrication).

However, 90 nm CMOS devices from another vendor became available. While these devices

were not simulated explicitly, the trends observed in experimental characterization were both

interesting and relevant to the simulation results at the same technology node. The devices had

variation on the layout parameters and were characterized experimentally. Surprisingly the

devices showed some very interesting novel results related to the layout variations that were not

expected. Two very interesting results related to the layout variations were discovered: 1) the

active space (SA) distance effect on TID induced leakage current, and 2) the channel width

effect on TID-induced leakage current (presented in chapter 4).

18
 B. Simulation approach

As stated in the overview section, this work first started with simulation based study using 90

nm CMOS devices based on the IBM process; however the results are representative of other

sub-100 nm technology nodes as the STI structure does not change significantly as the

technology scales. The structures were simulated in three dimensions using the Synopsis Tools,

DEVISE and DESSIS. The gate/STI overlap length is 200 nm. The gate oxide thickness is 1.4

nm and the depth of the STI is 360 nm. Structures in which the trench fill is recessed below the

surface by 10.8, 18, 36, 54, and 72 nm, corresponding to 3, 5, 10, 15, and 20% of the nominal

trench depth, respectively were simulated. The STI corner region near the gate polysilicon was

rounded to be as close as possible to reality. The left part of Fig. 2.1 shows the STI structure with

the fill recessed by 72 nm, and the right part of Fig. 2.1 is a detailed view of the rounded corner

with oxide thinning.

Fig. 2.1. Structure in which the STI fill is recessed by 72 nm. There is
thinning of the oxide at the sidewall corner. The right figure gives a more
detailed view of the rounded corner.

19
 C. Device structures

Later on in this project devices form another vendor with slightly different parameters were

accessible. All devices were fabricated in a 90 nm commercial bulk CMOS technology using

shallow trench isolation (STI). The operating voltage is 1.2 V for core transistors, and the gate

oxide thickness is 2.2 nm. High voltage I/O devices are characterized by a thicker gate oxide for

2.5 and 3.3V operation. The test structures used in this experiment consist of symmetric nMOS

transistors with different active space distance (SA), different width and gate length, and also

three different process options (HVT, AVT, LVT) described in Table 2.1. RHBD techniques

have been widely used in advanced CMOS circuit designs to minimize total dose radiation

effects. One well established RHBD layout technique is to use edgeless transistors. In this work

hardened structures such as annular gate or GAD/GAS (gate around drain/source) types of

hardening for core and I/O devices are studied. The minimum W/L ratio of annular devices is

large and hardened devices can be laid out with smaller ratios by surrounding the source and/or

drain with the gate and overlapping the field oxide along much of the perimeter for a reduced

effective width. An example layout of a gate-around-source (GAS) and annular gate is shown in

Fig. 2.2. The only difference between a GAS and a GAD device is the location of the source and

drain node.

20
 Table 2.1. Possible device types in modern bulk CMOS technologies

Devices Description

LVT (Low voltage threshold) Low threshold voltage FETs

AVT (Average voltage threshold) Regular threshold voltage FETs

HVT (High voltage threshold) High threshold voltage FETs

I/O devices Thick oxide devices for 2.5, 3.3 V operation

Hardened Annular gate and GAS/GAD (gate around source/drain) types of

devices hardening

(a) (b)

Fig. 2.2. (a) Example layout of annular gate. (b) Example layout of a gate-around-
source (GAS).

D. Experiments

Measurements and irradiations were carried out at Vanderbilt University. During the

measurements the drain was biased at 1.2 V. Irradiation was performed at room temperature up

to a TID of 500 krad(SiO2), at a dose rate of 31.5 krad(SiO2)/min using an ARACOR 10-keV x-

ray irradiation source. The devices were irradiated under typical worst-case bias conditions, i.e.,

all terminals of the transistors were grounded, except the gates of the NMOS transistors, which

21
were kept at Vdd (i.e., 1.2 V). A custom-developed probe card with 24 probe tips (2  12 arrays,

to match the size and pitch of the pads) was used. The test structures are arranged into tiles of 2 

12 pad arrays for probing. Structures are routed to pads that are sized 100 µm  63 µm. Pad

spacing is 5 µm in the x-direction and 100 µm in the y-direction, as shown in Fig. 2.3.

Fig. 2.3. 2  12 Pad Arrangement.

This combination of a 2  12 pad array and its related structure set is called a “TILE”.

Fig. 2.4 shows an example of the tile arrangement for a SPICE model tile. A semiconductor

parameter analyzer (HP 4156A) performs the static transistor measurements, applying and

measuring currents and/or voltages (typically, Id is measured as a function of Vgs and Vds).

22
Fig. 2.4. Tile arrangement example.

23
 CHAPTER III

THE SENSITIVITY OF RADIATION-INDUCED LEAKAGE TO STI TOPOLOGY AND

SIDEWALL DOPING

A. Overview

In this chapter, the TID sensitivity to the STI contour, including variations in the sidewall

doping profile is quantified. Technology Computer-Aided Design (TCAD) simulations are used

to simulate bulk structures, and to study the effects of variation in the degree of STI trench recess

on resulting TID response and estimate the sidewall doping dose required to prevent sidewall

inversion [7] for the recessed trench cases. Implications for characterizing variations in TID

sensitivity due to processing are noted, and reduction of sensitivity to STI variation using

sidewall doping is quantified. Experiments on 90 nm bulk devices are also included in this

chapter to demonstrate the device-to-device variability.

B. Bulk CMOS

1. Device-to-device variability

In [6], it was demonstrated that different fabrication lots with supposedly identical

processing, and nearly identical pre-irradiation leakage currents, could exhibit vastly different

TID response, with one lot showing a minimal increase in leakage and the other a dramatic

increase. Variability was also measured in the 90 nm bulk CMOS devices that were available to.

The devices were irradiated at room temperature up to a TID of 500 krad(SiO2) at a dose rate of

31.5 krad(SiO2)/min using an ARACOR 10-keV x-ray irradiation source. The nominal operating

24
voltage is 1.2 V, the gate oxide thickness is 2.2 nm, and W/L is 0.12 µm/10 µm. The devices

were irradiated under typical worst-case bias conditions, i.e., all terminals of the transistors were

grounded, except the gates of NMOS transistors, which were biased at Vdd (i.e., 1.2 V). The off-

state leakage current evolution with TID of NMOS core transistors from different dies is shown

in Fig. 3.1. The results show similar pre-irradiation off state leakage current (Ioff), but very

different post-irradiation Ioff.

Fig. 3.1. Off-state leakage current evolution with TID of a 90 nm NMOS

core transistors from different dies.

Key parameters that may affect pre-irradiation edge leakage, as well as TID response, are

the shape of the transition from the active to the isolation region and the doping of the active

silicon region along the sidewall [2]-[3]-[8].

25
 2. Simulation details

The specific devices analyzed are based on a commercial 90-nm CMOS technology; the

results are representative of other sub-100 nm technology nodes as the STI structure does not

change significantly as the technology scales. The structures were simulated in three dimensions

using the Synopsis Tools, DEVISE and DESSIS. Fig. 3.2 shows the area of interest and the

cutline for all succeeding cross-sectional views.

STI
Drain

•Gate Poly

Source
Edge of
interest Cutline

Fig. 3.2. NMOS device with gate/STI overlap and the edge of interest
identified by the black dotted line. The outer STI region shows the shallow
trench isolation oxide. Active silicon and gate polysilicon are also identified.
The red dotted line will serve as the cut-line for future figures.

A two dimensional cross-section of the device examined here is shown in Fig. 3.3(a). The

gate/STI overlap length is 200 nm. The gate oxide thickness is 1.4 nm and the depth of the STI is

360 nm. During the fabrication process it is very difficult to control planarity precisely, and

trench fill can be recessed unintentionally. The maximum amount of variability seen in a typical

process is 20% of the nominal trench depth, and for this sensitivity study a window with a

maximum of 20 % recess corresponding to a recess by 72 nm is a reasonable consideration. Also

26
if fully depleted SOI devices are considered for example, the silicon film is about 70 to 80 nm,

which also corresponds to the depth of the STI, so 72 nm trench recess would be considering that

the whole trench is recessed.

Therefore it is very important to understand how much variability in the leakage current

can occur due to the variations in the trench fill recess. Structures in which the trench fill is

recessed below the surface by 10.8, 18, 36, 54, and 72 nm, corresponding to 3, 5, 10, 15, and

20% of the nominal trench depth, respectively were simulated. The left part of Fig. 3.3b) shows

the STI structure with the fill recessed by 72 nm, and the right part of Fig. 3.3b) is a detailed

view of the corner.

Fig. 3.3 (a) Left: Active region/STI transition with planar geometry; the brown region
represents the STI and gate oxide. The red region represents the polysilicon. The blue region
represents the active silicon, and the right figure gives a more detailed view of the corner.
(b): The left figure shows a structure in which the STI fill is recessed by 72 nm. There is
thinning of the oxide at the sidewall corner. The right figure gives a more detailed view of the
corner

Unless otherwise noted, the I-V sweeps shown were simulated at a constant drain voltage

of 50 mV and a maximum gate voltage of 1.2 V (higher drain bias is discussed later). Uniform

27
 and non-uniform radiation-induced charge distributions along the STI/trench sidewall are

considered.

The TID response of devices with different sidewall doping profiles was simulated for

variants including: (1) no additional sidewall doping other than the well doping and the

threshold-voltage implant doping, (2) differing amounts of uniform doping added to the profile

described in (1), and (3) the profile described in (1), plus halo and punch through implants that

extend all the way to the sidewall. In the second case described above, a constant excess doping

profile was used along the entire STI sidewall, extending 70 nm into the Si body from the

sidewall. A range of sidewall doping concentrations was simulated, from 5  1016 cm-3 to 1 

1019 cm-3. The excess sidewall doping reduces leakage current at volume doping densities above

5  1017 cm-3, as the lowest well doping level of 1017 cm-3 is exceeded. No additional

improvement is obtained for doping densities above 5  1018 cm-3 for the range of radiation-

induced charge considered here. In practice, details of a particular process, including effects such

as boron depletion into the oxide, affect the doping at the device sidewalls.

3. Simulation results

Advanced CMOS fabrication processes use extensive engineering of junction, channel,

well, and substrate doping profiles to control leakage current, junction capacitance, drive current,

and reliability (hot electron effects and latchup). The details of a particular process, such as the

sidewall shape (corner, angle, etc.) and the doping process parameters, as well as thermal cycles,

determine the details of the sidewall doping in the absence of any specific sidewall doping steps.

The doping details along the sidewall vary, depending on the particular process flow (including

the energy and angle of the implants), and also on the details of device size and layout. Here, the

28
edge leakage is considered for devices in which the implants used to control channel

characteristics (halo, punch through, etc.) extend all the way to the STI sidewall, as well as

devices in which the sidewall doping profile is determined only by the well doping and

threshold-adjust implant. Both the halo and punch through implants are similar to the threshold

voltage implant, where the doping along the sidewall is increased, and are located below the

threshold voltage implant as shown in the 2D view in Fig. 3.5.

a) Pre-irradiation results

i. Trench recess depth and sidewall doping effect

The pre-irradiation subthreshold characteristics are shown in Fig. 3.4 for planar devices

(amount of recess, X = 0 nm), as well as those in which the top of the fill is recessed by X = 10.8,

18, 36, 54, and 72 nm. The pre-irradiation leakage current increases with the amount of trench

recess due to modulation of the sidewall potential by the gate poly where it extends over the STI

[2].

29
 Fig. 3.4. Id-Vg pre-radiation curves for 90 nm NMOS device with planar STI
fill, as well as variations in which the top of the fill is recessed by 10.8, 18, 36,
54 and 72 nm.

Increasing the doping to 5  1018 cm-3 uniformly along the trench sidewall (designated

case (2) in the “Simulation details” section) suppresses the pre-irradiation leakage in the recessed

device (Fig. 3.5 “green curve”). In the case without the excess sidewall doping, the non-linear

trend in the leakage with recess depth is due to the threshold-adjust implant. If the trench is

recessed by less than 10.8 nm, the threshold voltage implant dominates since the depth of the

threshold implant is ~10 nm, as shown in Fig. 3.6 (blue curve). In this case, the threshold-adjust

doping serves as higher sidewall doping.

As noted, the junction engineering doping profiles may or may not extend to the sidewall.

Fig. 3.5 also shows the impact of extending the halo and punch through doping profiles all the

way to the sidewall (black and red curve). The results show that the magnitude of the off-state

leakage depends strongly on the contour and doping profile of the upper portion of the device.

30
 Fig. 3.5. Impact of active region doping on the pre-irradiation off state leakage
current evolution with trench recess depth.

Fig. 3.6 shows the p-type sidewall doping profile (which includes the well doping,

threshold voltage adjust doping, halo and punch through doping, designated case (3) in the

“Simulation details” section), as well as the simulated leakage current corresponding to trench

recess depths obtained from Fig. 3.5 (red curve). Since the p-type doping varies with depth, the

leakage current is affected by the doping at the trench-recess depth. The leakage variation with

recess depth maps to the doping at this point. These results indicate that the active region doping

has a significant effect on the sidewall leakage for recessed trenches.

31
 Fig. 3.6. Net doping vs. depth (left axis) and simulated leakage (right axis) vs.
trench recess depth. The leakage is high when the top of the trench fill occurs at a
depth where the doping is relatively light.

ii. Effect of oxide thinning

High electric fields present in trench corner regions have been shown to reduce gate

oxide integrity [2] and to cause anomalous humps in the subthreshold Id-Vg characteristics of

non-irradiated devices. This problem is worsened if the trench isolation is recessed below the

trench corner, causing the gate oxide to thin as it wraps around the corner. To develop a radiation

hardened STI structure, these high electric fields at the trench corner should be reduced. To

reduce the electric fields at the trench corners commercial manufacturers have investigated

processing techniques that round the trench corner or increase the gate oxide thickness at the

corner. Simulations were performed for different amounts of “Oxide thinning”, and the results

show a significant improvement in the off-state leakage current as the gate oxide thickness

32
around the corner increases from 1 nm to 6 nm, as shown in Fig. 3.7. Also the hump in the

subthreshold region is reduced by increasing the oxide thickness.

Fig. 3.7. Simulated Id-Vg characteristics for two different “Oxide thinning”.

b) Post-irradiation results

i. Planar trench and recessed by 36 nm

The post-irradiation results with and without the excess sidewall doping ( designated case

(2) in the “Simulation details” section) for the case in which the trench is recessed by 36 nm are

presented in Figs. 3.8 (a) and (b), respectively. Radiation-induced charge was simulated by

varying the areal charge density uniformly at the silicon/STI interface (Not) along the entire STI

sidewall. The improvement in the radiation-induced leakage current resulting from the increased

sidewall doping is approximately three orders of magnitude for a radiation-induced charge

concentration of 2  1012 cm-2, which is a typical areal charge concentration that can be reached
33
in isolation oxides. The particular total dose at which a given charge density is reached depends

on the details of the oxide processing, particularly the maximum temperature seen by the oxide

[14]-[15]. The improvement for the device in which the fill is recessed by 36 nm is almost four

orders of magnitude for the same excess sidewall doping and radiation-induced charge density.

Fig. 3.8 (a). Radiation response for structures with the STI fill recessed by 36 nm and
no sidewall doping. 3.8 (b). Radiation response for structure with the STI fill recessed
by 36nm , with excess sidewall doping of 5  1018 cm-3 of boron.

The off-state drain-to-source leakage current versus the trench recess depth is presented

in Fig. 3.19 for uniform sheet charge concentrations of 0, 5  1011 cm-2, and 1012 cm-2. The

leakage current increases by approximately three orders of magnitude as the trench recess depth

increases from 0 nm (planar) to 72 nm (recessed by 20%) for a sheet charge concentration of 5 

1011 cm-2, and by more than two orders of magnitude for the pre-radiation case.

34
 Fig. 3.9. Leakage current evolution with trench recess depth for both pre-
radiation and post-radiation case.

Fig. 3.10 shows the off-state leakage current evolution with dose (represented by the

sheet charge concentration) of a planar structure and those in which the trench fill is recessed by

36 and 72 nm, for different sheet charge concentrations varying from 5  1011 to 5  1012 cm-2.

35
 Fig. 3.10. Leakage current evolution with charge concentration of a planar and
recessed by 36 and 72nm devices.

ii. Drain bias effect on leakage current

The results presented so far are for a drain bias of 50 mV since this is a sensitivity study

looking at the trends, which are the same for low and high drain bias. In this section, results for

high drain bias are presented to show that drain bias does not affect the trends. Drain biases of

50 mV and 1.2 V are compared in Fig. 3.11, which shows the pre-irradiation results of the

structure with a recess of 36 nm for the two drain bias conditions. These results are for the

structure with no excess sidewall doping (case (1) described in the “Simulation details” section).

The off-state drain to source leakage current increases approximately one order of magnitude for

a drain bias of 1.2 V compared to 50 mV.

36
 Fig. 3.11. Drain current vs. gate voltage for two drain bias conditions
(50mV and 1.2V) for the recessed by 36 nm case.

The pre- and post-irradiation results before and after the addition of the uniform excess

sidewall doping of 5  1018 cm-3 are presented in Fig.3.12. At higher drain voltage the enhanced

sidewall doping mitigates the sub-threshold leakage current for both pre-irradiation (red curve

located below the green curve) and post-irradiation (green curve) cases. The improvement is

about two orders of magnitude for the pre-irradiation case, and approximately four orders of

magnitude for Not = 5  1011 cm-2.

37
 Fig. 3.12. The pre- and post-irradiation results before and after the addition of excess
sidewall doping to the case in which the trench fill is recessed by 36 nm, at Vd =1.2V.

iii. Non uniform sheet charge distribution

In order to gain insight into the relative impact of the fringing electric fields in the STI on

the charge density, 2D simulations of the volumetric radiation-induced charge buildup were

kindly performed by John Sochacki from (Arizona State University, Tempe, AZ, USA) with the

Radiation Effects Module (REM), which is part of Silvaco's Atlas device simulator [16]. This

module simulates charge yield, hole transport, and hole trapping in dielectrics based on the local

electric field and trap density. The precursor trap density was assumed uniform with depth along

the sidewall and Gaussian from the interface into the STI bulk. In practice, actual trap density

magnitudes and distributions will depend on the details of the process parameters, and can be

calibrated to data for a particular process. Here gaining insight into the relative impact of the E-

fields for the planar and recessed trench cases is sought. The results indicate that the enhanced

38
electric field due to the STI recess increases the charge density near the top of the device

compared to the planar device, as shown in Fig. 3.13.

Fig. 3.13. 2D REM simulations for planar and recessed by 36 nm devices.

The charge distribution provided by REM (shown in Fig. 3.14 for the recessed-by-36 nm

case) is used in the device simulations to evaluate the effect of charge location on leakage

current, as shown in Fig. 3.14. The blue curve represents a uniform sheet charge concentration of

5  1011 cm–2. The results show that the charge concentration near the top of the sidewall (near

the recess) dominates the response; the charge density deeper along the trench has little impact

on the leakage current. These results are for the structure with no excess sidewall doping

(designated case (2) in the “Simulation details” section). These results are consistent with [1], in

which it was shown that charge at the bottom of the trench induces less leakage current.

39
 Fig. 3.14. Comparison of uniform and non uniform charge distribution for the
recessed by 36 nm device, showing that the concentration near the surface
dominates the response.

More leakage current is produced by charges trapped along the sidewalls near the top of

the trench, as shown in Fig. 3.15. These results are for the structure with no excess sidewall

doping (designated case (2) in the “Simulation details” section). The simulations show that a

given density of oxide trapped charge along the top half of the sidewall (green curve) gives the

same result as if the same charge density exists along the entire sidewall (red curve). Charges

trapped at the top half of the sidewall have the most impact on the leakage current, while oxide

trapped charges at the bottom half of the sidewall have no significant effect on the leakage

current. The observed results are consistent with [1], where they found that charge at the bottom

of the trench induces less leakage current and matches their experimental data more accurately.

40
 Fig. 3.15. Non uniform charges distribution for the recessed by 36 nm device,
showing that charge trapped along the top half of the sidewall have the most
impact on the leakage current.

4. Conclusion

Radiation-induced leakage current depends on the planarity of the STI fill and also on the

spatial distribution of the sidewall doping. In cases where enhanced sidewall doping is not used

to reduce or eliminate the sensitivity to trench profile, variation of the amount by which the

trench fill is recessed may lead to variation in the TID response of a technology. The radiation-

induced charge located near the top of the trench (specifically in the first quart of the trench

which corresponds to a 90 nm depth from the surface) dominates the response.

Because characterization of a process for TID response often involves measurement on a

relatively small number of devices, and from a limited number of fabrication lots, it is important

to understand how much variability in the leakage current may occur due to normal process

variations. This type of insight is best gained through simulation because of the ability to vary

41
structure and process parameters independently. The results are useful for interpreting

experimental data and have implications for testing and process qualification.

42
 CHAPTER IV

LAYOUT EFFECTS

A. Overview

In this chapter the layout related-stress effect on TID-induced leakage current are analyzed

using experimental results. Physical mechanisms that affect the TID sensitivity are considered,

particularly changes in the doping profile of the channel edges and at the STI sidewall, due to

STI stress. Effect of gate layout is also investigated for both core and I/O devices.

B. Introduction

Modern bulk CMOS foundry technologies typically offer several device types. A possible

list of devices for a 90-nm foundry is provided in Tab. 2.1. This allows IC designers to choose a

specific device type that fits the needs of a given application. For instance, low voltage threshold

(LVT) devices can be used to increase chip performance, while regular threshold (AVT) and

high threshold (HVT) devices can be used to minimize leakage and power. Two commonly used

types of MOS devices for CMOS ICs are AVT MOSFETs and high voltage I/O transistors. High

voltage I/O devices are characterized by a thicker gate oxide and higher threshold voltage and

are traditionally available to allow the integration of low power ICs within systems requiring

higher logic levels. As MOS technologies continue to scale below 100 nm, device geometries,

doping concentrations, and supply voltages are adjusted from one generation to the next. Scaling

is performed in an effort to improve MOSFET device and circuit parameters (such as density,

43
speed, and/or power) for a given technology [8]. However changing these device parameters has,

to varying degrees, an influence on the total ionizing dose (TID) response of MOS devices.

C. Experiment details

All devices were fabricated in a 90 nm commercial bulk CMOS technology using shallow

trench isolation (STI). The operating voltage is 1.2 V; the gate oxide thickness is 2.2 nm. The

test structures used in this experiment consist of symmetric nMOS transistors with different

active space distance (SA), different width and gate length, and also three different process

options (HVT, AVT, LVT). Hardened structures such as Annular or GAD/GAS types of

hardening are also studied. Radiation exposure and electrical measurements were carried out at

Vanderbilt University. Irradiation was performed at room temperature up to a TID of 500

krad(SiO2), at a dose rate of 31.5 krad(SiO2)/min using an ARACOR 10-keV x-ray irradiation

source. The devices were irradiated under typical worst-case bias conditions, i.e., all terminals of

the transistors were grounded, except the gates of the transistors, which were kept at Vdd (i.e., 1.2

V).

D. Effect of gate layout on TID induced leakage current

1. Technology description

The principal design elements for this process and test chip are as follows:

• Triple-well structure is used.

• Use maximum density of source and drain contacts.

• Substrate guard rings are implemented.

44
 • Use gate protection diodes to safeguard against in-process ESD or Antenna effects, and

one impact that the ESD diodes had on the device response is that it increased the pre-

irradiation gate leakage current.

• Common gate, source and body are used to reduce chip area.

• “Dummy” poly load lines are added to improve line width and etch consistency.

Fig. 4.1 shows an example layout of a NMOS transistor showing how the device is connected.

Fig. 4.1. Example layout of typical NMOS transistor.

2. Rectangular gate: HVT/AVT/LVT comparison

AVT devices with rectangular gate implementation exhibit a high degree of radiation

tolerance with no dependence on the W/L ratio, as shown in Fig. 4.2. The results show 2 set of

data: the first set of data shows the pre- and post-irradiation Id-Vg characteristics at high (Vd = 1.2

V) and the second set of data shows the pre- and post-irradiation Id-Vg characteristics at low

drain bias (50 mV), for two different widths: 0.12 µm (left figure) and 10 µm (right figure).

45
Fig. 4. 2. Id-Vg pre- and post-irradiation characteristics of two AVT devices with different W/L
(0.12 µm shown in the left, and 10 µm shown in the right).

Fig. 4.3 shows three plots representing three device types (HVT, AVT and LVT). HVT

and LVT transistors are more sensitive to TID than AVT (the AVT data at Vd = 1.2 V shown in

Fig. 4.3 are the same as the one on Fig. 4.2 at high Vd ), and the degree of sensitivity to TID

depends strongly on the channel width, more details about the channel width dependence will be

given in the section “Channel width effect on TID induced leakage current”.

The difference between the three types of devices is the threshold voltage, where:

 HVT device has Vth = 0.45 V and the threshold voltage shifted with TID

 AVT device has Vth = 0.35 V and no threshold voltage shift with TID were observed.

 LVT device has Vth = 0.31 V and the threshold voltage shifted with TID.

46
 (b)
(a)

(c)

Fig. 4.3. Id-Vg pre- and post-irradiation characteristics of three different device types: a) HVT, b)
AVT, c) LVT.

For this advanced technology, TID is still a problem (as shown in Fig. 4.3 for the HVT

and LVT transistors) and the devices that exhibit post-radiation leakage appear to behave as

expected for STI-related leakage paths. Therefore, hardened structures are needed to assure

better reliability.

47
 3. Annular Gate Device

When bulk NMOS transistors are exposed to the total ionizing dose (TID) radiation, the edge

effect will take place by turning ON the parasitic sidewall transistor. The induced high off-state

current in the subthreshold characteristic severely limits the radiation tolerance of conventional

CMOS circuits [1]. Hardness-by-design (HBD) layout techniques may be used to eliminate this

limitation, such as annular gate or GAS/GAD type of hardening. Fig. 4.4 shows a layout of a

typical NMOS annular gate transistor.

Fig. 4.4. Example layout of typical NMOS annular gate transistor

In general “Annular gate” devices are very resistant to TID effects for the three types of

devices AVT and HVT and LVT, with no dependence on W/L. Fig.4.5 shows the pre- and post-

irradiation characteristics for three different device types, (HVT, AVT and LVT), with annular

gate and fixed W/L = 10/0.08.

48
 (a) (b)

(c)

Fig. 4.5. Id-Vg pre- and post-irradiation characteristics of three different device
types: a) HVT, b) AVT, c) LVT, with annular type of hardening and W/L=10/0.08.

4. GAS/GAD type of hardening

In the previous section the radiation sensitivity of annular gate device was illustrated, where

annular gate devices are shown to be very immune to TID, as expected from previous published

results. In this section the GAS/GAD devices respond to TID is presented.

49
 Fig. 4.6. Example layout of a NMOS transistor with GAS type of hardening.

Fig. 4.6 shows a layout of a typical NMOS transistor with GAS type of hardening, GAS

stands for gate around source and GAD for gate around drain, which is a type of hardening

similar to the RHBD technique "Enclosed ringed-source". Fig. 4.7 shows the pre- and post-

irradiation characteristics for three different device types, (HVT, AVT and LVT), with

GAS/GAD layouts and fixed W/L = 10/0.08. In general GAS/GAD devices are very immune to

TID for the three types of devices (HVT, AHVT and LVT) with no dependence on W/L.

50
 (a) (b)

(c)

Fig. 4.7. Id-Vg pre- and post-irradiation characteristics three different device types: a)
HVT, b) AVT, c) LVT, with GAS/GAD type of hardening and W/L=10/0.08.

E. I/O devices vs. core devices

High voltage I/O devices are characterized by a thicker gate oxide for 2.5 and 3.3V

operation, higher threshold voltage and are available to allow the integration of low power ICs

within systems requiring higher logic levels. Despite being fabricated in a deep submicron

process, the 90 nm I/O transistors exhibit a TID response more similar to previous generation

technologies. The results show enhanced TID susceptibility in I/O devices, as shown in Fig. 4.9.

As illustrated in the plot, the radiation response of the I/O devices is considerably different from

51
 that of the AVT device represented in Fig. 4.8. The data demonstrate a significant increase of the

off state drain to source leakage current with dose. These results indicate that the I/O devices are

considerably softer than the AVT core transistors. This can severely impact the performance of

I/O driver circuits that require high voltage devices.

Fig. 4.8. Id-Vg pre- and post-irradiation Fig. 4.9. Id-Vg pre- and post-irradiation
characteristics of AVT device with W/L=2/0.1. characteristics of I/O device with W/L=2/0.24.

Possible explanation to the enhanced susceptibility to TID in the I/O devices is the lower

p-type doping concentration near the corners of the STI sidewall [8]. Doping profiles for the

RVT (which is similar to AVT device), and I/O devices were generated as a function of depth

along the sidewall as shown in Fig. 4.10.

52
 Fig. 4.10. Doping profile as a function of depth along the sidewall [8].

Hardened I/O devices structures were also provided for both voltage operation 2.5 V and

3.3 V. I/O devices with annular gate are immune to TID as shown in Fig. 4.11 for both operating

voltages. Despite being fabricated in a deep submicron process, the unhardened 90 nm I/O

transistors exhibit radiation responses more similar to old generation technologies. However the

hardened structures show no sensitivity to TID.

53
 Fig. 4.11. Id-Vg pre- and post-irradiation characteristics of two IO devices with annular
type of hardening. (a) IO device operating at 2.5 V, with W/L = 10/0.72. (b) IO device
operating at 3.3 V, with W/L = 10/1.

F. Layout dependence effect on TID induced leakage current

Mechanical stress plays an important role in process modeling in advanced technologies. It

controls the structural integrity of the device; the yield from the process depends on stresses; and

the mobility of charged carriers is changed by stresses [17]. In addition, leakage currents are also

a function of the stress in the system. While the effects of stress on device performance are well

established before irradiation, the effects of stress on the TID response are not fully understood.

STI-induced mechanical stress increases with the reduction of the device active area. Many

processing steps individually or collectively contribute to the development of STI stress [18],

such as liner oxidation, high density-plasma (HDP) oxide deposition, thermal oxidation

processes after STI formation, etc. STI stress results in a strained region in the active area, thus

affecting the silicon band gap, the diffusivity of impurities in silicon, and the mobility of both

electrons and holes [18]. MOSFET characteristics become more sensitive to the device layout

54
pattern [19]. The threshold voltage (Vth), saturation drain current (Isat), and most importantly the

leakage current (Ioff) are affected by the layout pattern. Higher integration requires more compact

STI structures and thus induces higher stress. Mechanical stress in the device affects many

parameters, such as carrier mobility and dopant diffusion [20]. It was reported in [21] that

different STI stress and size may change the doping profile of the devices, leading to threshold-

voltage shifts and changes of other second-order effects, such as DIBL and body effect. In this

section the STI-stress effect on TID-induced leakage current is analyzed. The physical

mechanisms that affect the TID sensitivity are considered, particularly changes in the doping

profile of the channel edges and at the STI sidewall, due to STI stress.

1. Active space distance effect on TID induced leakage current

All devices were fabricated in a 90 nm commercial bulk CMOS technology using shallow

trench isolation (STI). The operating voltage is 1.2 V, the gate oxide thickness is 2.2 nm, and

W/L is 0.2 µm/0.08 µm. The test structures used in this experiment consist of symmetric nMOS

transistors with different active space distance (SA) = 0.24 µm, 0.48 µm, 0.72 µm, and 2 µm. SA

is the distance of poly to STI edge (end of active channel) on each side; varying SA changes the

STI stress. Fig. 4.12 represents a typical MOSFET layout view showing the SA distance.

Electrical measurements and radiation exposure were carried out at Vanderbilt University.

Irradiation was performed at room temperature up to a TID of 500 krad(SiO2), at a dose rate of

31.5 krad(SiO2)/min using an ARACOR 10-keV x-ray irradiation source. The devices were

irradiated under typical worst-case bias conditions, i.e., all terminals of the transistors were

grounded, except the gates of NMOS transistors, which were kept at Vdd (i.e., 1.2 V).

55
 Fig. 4.12. Typical MOS layout top view.

Figs. 4.13 and 4.14 show the pre-irradiation threshold voltage (Vth) and off-state leakage

current (Ioff) versus SA. Vth was extracted using the linear extrapolation method, where IdVg

characteristics are plotted in linear scale and Vth is determined by extrapolating at the point of

maximum slope on the IdVg characteristics.

56
Fig. 4.13. Pre-irradiation threshold voltage versus the active space
distance (SA).

Fig. 4.14. Pre-irradiation leakage current evolution with active space

distance (SA).

57
 The threshold voltage increases with decreasing SA, and Ioff decreases with decreasing

SA. The results are consistent with previously published data illustrating the effects of MOSFET

layout on pre-irradiation edge leakage [22],[23]. This is due to the effect of mechanical stress

from the STI edge [22], which reduces impurity diffusion in the channel region [19], [24]. The

STI stress effect is higher when SA decreases [22]; therefore, at higher STI stress Ioff decreases.

It has been shown that the origin of increasing Vth in nMOSFETs with smaller SA is the large

compressive stress originating in the STI edge [19], [24], which reduces the diffusion of pocket

ion implants (boron) and the doping concentrations at the edges of the channel become higher (as

shown in Fig. 4.15(b), obtained along “Cutline X” shown in Fig. 4.15(a). The doping

concentration also becomes higher at the STI sidewall (along “Cutline Y”), which explains the

decrease of the off-state leakage current with smaller SA, since higher doping at the STI sidewall

reduces the off-state leakage current.

Fig. 4.15. (a) Top view of nMOS device showing two different cutlines, where “Cutline X”
gives the 2D view on the right and “Cutline Y” gives a 2D view showing the leakage path
(edge of interest) along the STI sidewall. (b) Schematic mechanism of increasing Vth in
nMOS [3].

58
 In [19] the authors estimated the dependence of compressive stress on SA at the center of

the channel region. Devices with SA = 0.3 µm have compressive stress of 750 MPa, which is

about 550 MPa higher than that of devices with SA = 2 µm. Fig. 4.16 shows the post-irradiation

leakage current variation with SA, showing that TID induced leakage current increases with

increasing SA.

Fig. 4.16. Pre-irradiation and post-irradiation leakage current evolution with

active space distance (SA).

The TID-induced current is smaller for smaller SA, since the sidewall doping

concentration is higher compared to devices with larger SA due to the impurity diffusion in the

channel region and at the STI sidewall.

59
 2. Channel width effect on TID induced leakage current

The results presented in Fig. 4.17 show a strong dependence of TID-induced current on

channel width, with the narrow devices exhibiting less leakage pre-irradiation, but more leakage

post-irradiation. These results can be explained by two mechanisms: the compressive stress

dependence on the space between adjacent STI edges and doping-profile differences at the

device edges.

Fig. 4.17. Pre-irradiation and post-irradiation leakage

current evolution with channel width.

Figs 4.18 and 4.19 show the pre- and post-irradiation drain current vs. gate voltage for three

different channel widths. The on-state current does not change after irradiation; only the off-state

current changes. In a symmetric layout, the stresses from adjacent STI edges (STI space) are

added to the original STI stress [19]. For narrow devices where the STI spacing is smaller, there

is more compressive stress, which increases the doping concentration at the STI sidewall,

60
reducing the off-state leakage current. The second mechanism that contributes to the dependence

of the off-state leakage current on channel width is the doping profile differences at the device

edges (or “edge of interest” shown by the black dotted line in Fig. 3a). The distribution of dopant

atoms within a device depends on parameters including implant dose, energy, and angle, as well

as subsequent diffusion during the activation anneals and other thermal cycles in the process.

The diffusion can be affected by the local strain, which varies with width [19]. In addition,

dopant depletion and pile up at the semiconductor-insulator (isolation) interfaces can impact the

local doping profiles. For narrow width devices, since the width is smaller it is likely that the

implants will reach the STI sidewall due to diffusion, (assuming a 4X rotation implant), thereby

increasing the sidewall doping. However, for wider devices, considering similar implants and

diffusion rate as for narrow devices, the implants may not extend all the way to the sidewall,

leading to higher off-state leakage current for wider devices compared to the narrow devices.

The amount of radiation-induced positive charge trapped in oxides has been shown to depend

on the stress in the oxide [26], [27]. The enhanced radiation sensitivity for narrow devices may

be related to the influence of stress in the STI oxide on the amount of positive trapped charge.

However, the thin gate oxides, which trapped less charge when they were irradiated under stress,

may behave qualitatively differently from STI oxides. Moreover, the fringing fields may be

higher at the STI edge for narrower width devices, depending on the details of the processing,

which can also increase the radiation-induced leakage.

61
Fig. 4.18. Id-Vg pre-irradiation curves for three different widths.

Fig. 4.19. Id-Vg post-irradiation curves for three different widths.

62
G. Conclusion

In general the hardened structures (annular gate and GAS/GAD) are very immune to TID for

the three types of devices (HVT, AHVT and LVT) with no dependence on the W/L.

Despite being fabricated in a deep submicron process, the unhardened 90 nm I/O transistors

exhibit radiation responses more similar to old generation technologies. However the hardened

structures proved to be very immune to TID.

TID-induced leakage current of sub-micron nMOSFETs is demonstrated to increase with

increasing active-to-isolation spacing. Mechanical stress reduces impurity diffusion at the STI

sidewall, affecting the TID sensitivity. Channel width effect on TID induced leakage current was

also investigated; there is a strong dependence of TID-induced current on channel width, with

the narrow devices exhibiting less leakage pre-irradiation, but more leakage post-irradiation. The

compressive stress dependence on the space between adjacent STI edges and doping-profile

differences at the device edges affects the pre-radiation leakage current. The enhanced radiation

sensitivity for narrow devices may be related to the influence of stress in the STI oxide on the

amount of positive trapped charge. Moreover, the fringing fields may be higher at the STI edge

for narrower width devices, which can also increase the radiation-induced leakage.

63
 CHAPTER V

CONCLUSIONS

Variability has been shown in the literature and was also measured on the 90 nm CMOS

devices that were accessible. The purpose of this work was to understand and quantify the

sensitivity of TID induced leakage current to variables that have not been examined in details

(such as variation of the amount by which the trench fill is recessed, sidewall doping and layout

related stress effects). A set of conclusions related to 90 nm process variables examined

throughout this work are drawn in this chapter.

Radiation-induced leakage current depends on the planarity of the STI fill and also on the

spatial distribution of the sidewall doping. In cases where enhanced sidewall doping is not used

to reduce or eliminate the sensitivity to trench profile, variation of the amount by which the

trench fill is recessed may lead to variation in the TID response of a technology.

The radiation-induced charge located near the top of the trench dominates the response.

Fig 5.1 shows a direct sensitivity of leakage current to the percent variability, the figure

quantifies the impact of process variability on TID leakage current in a sub 100-nm technology.

For example at 5% recess, well within what might be expected in reality, the nominal pre-

irradiation leakage current only increased by about 4, but the post-irradiation leakage current

increased by 250.

64
 Fig. 5.1. Normalized leakage currents to the planar pre-rad case (Ileak0),
versus the percentage recess.

Because characterization of a process for TID response often involves measurement on a

relatively small number of devices, and from a limited number of fabrication lots, it is important

to understand how much variability in the leakage current may occur due to normal process

variations. This type of insight is best gained through simulation because of the ability to vary

structure and process parameters independently.

Despite being fabricated in a deep submicron process, the experiment results showed that

unhardened 90 nm I/O transistors exhibit radiation responses more similar to old technologies.

However the hardened structures proved to be very immune to TID.

TID-induced leakage current of sub-micron nMOSFETs is demonstrated to increase with

increasing active-to-isolation spacing. Mechanical stress reduces impurity diffusion at the STI

sidewall, affecting the TID sensitivity.

65
 A strong dependence of TID-induced current on channel width was demonstrated with

the narrow devices exhibiting less leakage pre-irradiation, but more leakage post-irradiation. The

compressive stress dependence on the space between adjacent STI edges and doping-profile

differences at the device edges affects the pre-radiation leakage current. The enhanced radiation

sensitivity for narrow devices may be related to the influence of stress in the STI oxide on the

amount of positive trapped charge, as well as, fringing fields that might be higher at the STI edge

for narrower width devices, which can also increase the radiation-induced leakage.

The simulation results are useful for interpreting experimental data and have implications

for testing and process qualification. The performance of the device depends not only upon the

gate length and width but also on the exact layout of the individual transistor. Therefore it is very

important to consider and take into account the exact layout of the transistor when interpreting

experimental data. Furthermore stresses in the system should not be ignored and must be taken

into consideration and examined carefully.

66
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