EC8353-ELECTRONIC DEVICES AND CIRCUITS

UNIT-I PN JUNCTION DEVICES

PART - B
PN junction diode: structure, operation & V-I characteristics

1. With a neat diagram explain the working of a PN junction diode in forward bias
And reverse bias and show the effects of temperature on its VI characteristics
(NOV/DEC 2012), (May / June 2016), (Nov / Dec 2015)
(OR)
Outline the charge carrier diffusion phenomenon across a PN junction. Explain the effect of
forward and reverse biasing on the depletion region. (Nov/Dec 2018 R-13) (April / May 2019-R17)

A PN junction is formed from a piece of semiconductor (Ge or Si) by diffusing p-type material
(Acceptor impurity Atoms) to one half side and N type material to (Donar Impurity Atoms) other half
side. The plane dividing the two zones is known as 'Junction'.

The P-region of the semiconductor contains a large number of holes and N region, contains a large
number of electrons. A PN junction just immediately formed is shown in Fig.

When PN junction is formed, there is a tendency for the electrons in the N-region to diffuse into the p-
region, and holes from P-region to N-region. This process is called diffusion. While crossing the junction,
the electrons and holes recombines with each other, leaving the immobile ions in the neighborhood of the
junction neutralized as shown in Fig.

These immobile + ve and –ve ions, set up a potential across the junction. This potential is called
potential barrier or junction barrier. Due to the potential barrier no further diffusion of electrons and holes
takes place across the junction. Potential barrier is defined as a potential difference built up across the PN
junction which restricts further movement of charge carriers across the junction. The potential barrier for
a silicon PN junction is about 0.7 volt, whereas for Germanium PN junction is approximately 0.3 volt.

Symbol of Diode:
The symbol of PN junction diode is shown in Fig. The P-type and N-type regions are referred to as Anode
and Cathode respectively. The arrowhead shows the conventional direction of current flow when the
diode is forward biased.
Working of PN Junction Diode:

Forward Bias:
When the positive terminal of the external battery is connected to the P-region and negative terminal to
the N-region, the PN junction is said to be forward biased as shown in Fig.

When the junction is forward biased, the holes in the p-region are repelled by the
positive terminal of the battery and are forced to move towards the junction. similarly, the electrons in the
N-region are repelled by the negative terminal of the battery and are forced to move towards the-junction.

This reduces the width of the depletion layer and barrier potential. If the applied voltage is greater than
the potential barrier vr, then the majority carriers namely holes in P-region and electrons in N-region,
cross the barrier. During crossing some of the charges get neutralized the remaining charges after
crossing, reach the other side and constitute current in the forward direction. The PN junction offers very
low resistance under forward biased condition.

Since the barrier potential is very small (nearly 0.7 V for silicon and 0.3 V for Germanium junction), a
small forward voltage is enough to completely eliminate the barrier. once the potential barrier is
eliminated by the forward voltage, a large current start flowing through the PN junction.

Reverse Bias:

When the positive terminal of the external battery is connected to the N-region and negative terminal to
the p-region, the PN junction is said to be reverse biased. When the junction is reverse biased, the holes in
the P-region are attracted by the negative terminal of the battery. Similarly, the electrons in the N-region

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are attracted by the positive terminal of the external battery. This increases the width of the depletion
layer and barrier potential (Vs).

The increased barrier potential makes it very difficult for the majority carriers to diffuse across the
junction. Thus, there is no current due to majority carriers in a reverse biased PN junction. In other words,
the PN junction offers very high resistance under reverse biased condition.

In a reverse biased PN junction, a small amount of current (in µA) flows through the junction because of
minority carriers. ( i.e., electrons in the P-region and holes in the N region).The reverse current is small
because the number of majority carrier in both regions is small.

V-l characteristics of PN-Junction Diode:

A graph between the voltage applied across the PN junction and the current flowing through the junction
is called the V-I characteristics of PN junction diode. Fig. shows the V-I characteristics of PN junction
diode.

Forward Characteristics:
Fig. (a) shows the circuit arrangement for drawing the forward V-I characteristics of PN junction diode.
To apply a forward bias, the +ve terminal of the battery is connected to Anode (A) and the negative
terminal of the battery is connected to Cathode (K). Now, when supply voltage is increased the circuit
current increases very slowly and the curve is nonlinear (region-OA).

The slow rise in current in this region is because the external applied voltage is used to overcome the
barrier potential (0.7 V for Si; 0.3V for Ge ) of the PN junction' However once the potential barrier is
eliminated and the external supply voltage is increased further, the current flowing through the PN
junction diode increases rapidly (region AB). This region of the curve is almost linear. The applied
voltage should not be increased beyond a certain safe limit, otherwise the diode will burnout.

The forward voltage at which the current through the PN junction starts increasing rapidly is called by
knee voltage. It is denoted by the letter VB.

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 Reverse Characteristics:

Fig (b) shows the circuit arrangement for drawing the reverse V-I characteristics of PN junction diode. To
apply a reverse bias, the +ve terminal of the battery is connected to cathode (K) and - ve terminal of the
battery is connected to anode (A).

Under this condition the potential buried at the junction is increased. Therefore, the junction resistance
becomes very high and practically no. current flows through the circuit. However, in actual practice, a
very small current (of the order of µA) flows in the circuit. This current is called reverse current and is
due to minority carriers. It is also called as reverse saturation current (I). The reverse current increases
slightly with the increase in reverse bias supply voltage.

If the reverse voltage is increased continuously at one state (marked by point C on the reverse
characteristics) breakdown of junction occurs and the resistance of the barrier regions falls suddenly.
Consequently, the reverse current increases rapidly (as shown by the curve CD in the current) to a large
value. This may destroy the junction permanently. The reverse voltage at which the PN junction breaks is
called as break down voltage.

Temperature effects
The cut in voltage decreases as the temperature increases. The reverse saturation current increases.
(∆𝑇⁄
𝐼02 =2 10 ) 𝐼01

𝐼01 ,𝐼02 are the reverse current at T1◦C, T2◦C

∆𝑇 = T2- T1.
The voltage equivalent of temperature VT also increases. The reverse breakdown voltage increases.

2. Derive the PN diode current equation.

The applied voltage and current though diode are related by the equation
𝑉⁄
𝐼 = 𝐼0 (𝑒 𝜂𝑉𝑇 − 1)

Where,

Io = Reverse saturation current

V = Applied voltage
I = Diode current
VT = Volt equivalent temperature
𝑘̅𝑇
𝑉𝑇 =
𝑞
𝑘̅ = 1.38*10-23 J/K
T = temperature of the diode junction
I = diode current
Q = change of electron 1.602*10-19 C
At any temperature

4
 𝑘̅𝑇 1.38 × 10−23 𝑇
𝑉𝑇 = = =
𝑞 1.602 × 10−19 11600
At room temperature
300
𝑉𝑇 = = 26𝑚𝑉
11600
The value of η=1 for germanium and 2 for silicon.

For forward bias voltage the current equation reduces to

𝑉⁄
𝐼 = 𝐼0 (𝑒 𝜂𝑉𝑇 )

At room temperature for germanium transistor

𝐼 = 𝐼0 (𝑒 40 )

When the diode is reverse biased

𝑉⁄
𝐼 = 𝐼0 (𝑒 𝜂𝑉𝑇 − 1)

𝐼 ≅ 𝐼0

Diffusion and transient capacitance

3. Explain diffusion and transition capacitance of diode

Depletion layer capacitance (or) transition capacitance (or) space charge capacitance (May / June
2016)(Nov/Dec 2016)(May 2017)

• When a PN junction is reverse biased, a layer of positive and negative immobile ions, called depletion
layer, is formed on either side of the junction. It is also known as depletion-region, space-charge region or
transition region. The depletion-layer acts as a dielectric (i.e., non-conductive) medium between P-region
and N-region. We know that the P-region and N-region on either side of the junction, has a low
resistance. Therefore, these regions act as two plates of a capacitor, separated by a dielectric (i.e.,
depletion layer) as shown in Fig.

The capacitance formed in a junction area is called depletion layer capacitance. It is also called depletion
region-capacitance, space charge capacitance, transition region capacitance or simply junction
capacitance.

• Since the depletion layer width (d) increases with the increase in reverse bias voltage, the resulting
depletion layer capacitance will decrease with the increased reverse bias.

• The depletion layer capacitance depends upon the nature of a PN junction, semiconductor material and
magnitude of the applied reverse voltage. It is given by the relation,

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Where
K = A constant, depending upon the nature of semiconductor material
VB = barrier voltage. 0.6V for silicon and 0.3V for germanium
V = applied reverse voltage
n a constant depending upon the nature of junction.
The value of the K is

• The value of ‘n’ is taken as 1/2 for step or abrupt junction, 1/3 for linearly graded junction.

• It is the evident from the above relation that the value of depletion layer capacitance (CT) can be
controlled by varying the applied reverse voltage. This property of variable capacitance, possessed by
reverse biased PN junction, is used in the concentration of a device called varactor.
Reverse biased.

Derivation:

Connection P side is less

Doping less in P side (NA )
N side (ND )
Potential & change density Relation
d2 V
NA < ND dx2 -----------------------1
X – distance measured from junction
𝜀 → 𝜀𝑜 𝜀𝑟
d2 V qND
NA < ND = ------------------2
dx2 ε
Integrating 2
d2 V qND
∫ = ∫
dx 2 ε
dv qNA X
=
dx ε
To get potential from 0 to w
VB w
dv qNA X
∫ =∫ dx
o dx o ε
Where V=VB
X=w

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 qNA w2
VB = × ----------------3
ε 2
W=√VB
Q=No of change particle × change on each particle
=(NA × volume) × q
Q=qNA AW------------------2
Diff 3 w.r.to V
qNA w 2
VB = ×
ε 2
qNA 1 dw
1= ×2 2w
ε dv
dw ε
=
dv qNA w
Diff 2
dQ dw
= qNA A
dv dv
ε Aε
CT = qNA A =
qNA w w

Ex : Varactor diode (or) Tuning diode

Diffusion capacitance 𝐂𝐃 :(May 2017)

The junction behaves like a capacitor. The capacitance, which exists in a forward-biased junction is called
a diffusion or storage capacitance. It is different from the transition or depletion layer capacitance, which
exists in a reverse-biased junction. The diffusion capacitance arises due to the arrangement of minority
carrier density. And its value is much larger than the depletion layer capacitance.
Width of depletion region ↓ As applied voltage ↑, the concentration of injected charged particle also
increases. This rate of change of injected change with applied voltage is capacitance.
𝜏 = mean lifetime of the carrier
I = value of forward current
𝜂 = A constant (1 for Ge and 2 for Si)
VT=volt equivalent of temperature.

dQ
CD =
dv

CD is >CT
I=Ipn(0) + Inp (0)
Ipn(0) → hole diffusion current n region
Inp (0) → electron diffusion current in p region

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 Inp (0) ⋍ 0
P side heavily doped
dpn
Jp(x) = −qDp
dx
I
J=
A
dp
Ip (X)=−qADp dxn ---------------1
Pn (X) = Pn(0) e−X/LP ----------------2
Hole concentration in the right side of p material Pn(0) ie junction
Diff 2
dpn (x) 1
= Pn(0) e−X/LP ( )
dx LP
Ip (X)=−qADp Pn(0) e−X/LP . -1/LP
At x=0 Ip (X)=Ipn(0) =I
QADP
I= Pn (0)
LP
IL
Pn(0) = QADP -------------------------- A
P
Now the excess minority charge exists only on n side and given by
∞
Q=∫0 Aq Pn(0)e−X/LP dx
∞
e−X/LP
=AqPn(0) [ −1 ]
LP
0
=AqLpPn(0)[e−∞ − e−0 ]
Q=−AqLpPn(0)
Q=AqLpPn(0)------------------B
Put A in B
AqLpILP LP 2
Q= = .I
qADp Dp
Assume
LP 2
=𝜏
Dp
dQ
Q=𝜏I ⇒ dI = 𝜏
W.K.T
dQ dI
CD = .
dI dV
dI
CD = 𝜏.
dV
I = Io (eV/DVT )
dI 1
= I.
dV ηVT
I
CD = 𝜏.
ηVT
It is evident from the above relation, that diffusion capacitance is directly proportional to the forward
current (I).

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 Rectifiers – Half Wave and Full Wave

Half Wave
4. What is halfwave rectifier? Explain the working principle with neat sketch? (Nov / Dec 2015)
(Nov/Dec 2016)
Rectifiers are a class of circuits whose purpose is to convert ac waveforms (usually sinusoidal
and with zero average value) into a waveform that has a significant non-zero average value (dc
component). Simply stated, rectifiers are ac-to-dc energy converter circuits. Most rectifier circuits employ
diodes as the principal elements in the energy conversion process; thus, the almost inseparable notions of
diodes and rectifiers.

Uncontrolled rectifier: uncontrolled refers to the absence of any control signal necessary to operate the
primary switching elements (diodes) in the rectifier circuit. (The discussion of controlled rectifier circuits,
and the controlled switches themselves, is more appropriate in the context of power electronics
applications). Rectifiers are the fundamental building block in dc power supplies of all types and in dc
power transmission used by some electric utilities.

There are two types of rectifiers:

(a) Half Wave (HW) rectifier (b) Full Wave (FW) rectifier

Half -wave Rectifier:

It consists of a single diode in series with a load resistor. The input to half wave rectifier is supplied from
the 50 Hz a.c supply. The circuit diagram for halfwave rectifier is shown in fig.

Positive half cycle:

During the positive half cycle of the input signal the anode of the diode becomes positive with respect to
the cathode and hence the diode D conducts. For an ideal to the cathode and hence the diode D conducts.
For an ideal diode, the forward voltage drop is zero. So the whole-input voltage will appear across load
resistance RL.

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Negative half cycle:
During negative half cycle of the input signal, the anode of the diode becomes negative with respective to
the cathode and hence the diode D does not contact. For an ideal diode the impedance by the diode is
infinity. So the whole input voltage appears across the diode D. hence the voltage drop across R, is zero.

Analysis of Half wave rectifier:

Let Vi be the input voltage to the rectifier

𝑉𝑖 = 𝑉𝑚 𝑠𝑖𝑛𝜔𝑡
Where,
𝑉𝑚 = Maximum value of the input voltage.
Let I be the current flowing though the circuit when the diode is conducting.
𝐼 𝑠𝑖𝑛𝜔𝑡 𝐹𝑜𝑟 0 ≤ 𝜔𝑡 ≤ 𝜋
𝑖={𝑚 }
0 𝐹𝑜𝑟 𝜋 ≤ 𝜔𝑡 ≤ 2𝜋
Where
𝐼𝑚 = 𝑀𝑎𝑥𝑖𝑚𝑢𝑚 𝑣𝑎𝑙𝑢𝑒 𝑜𝑓 𝑡ℎ𝑒 𝑐𝑢𝑟𝑟𝑒𝑛𝑡
𝑉𝑚
𝐼𝑚 =
𝑅𝐹 + 𝑅𝐿
Where
𝑅𝐹 -Forward dynamic resistance of diode.
𝑅𝐿 -Load resistance.

(a) Average or DC value of output current (Idc):

From Fig., it is seen that the output current is not steady but contains fluctuations even though it is DC
current. The average value of this fluctuating current is called DC current (Idc). It can be calculated as
follows.

Average value = (Area under the curve / Period )

1 2π
Idc = ∫ i d(ωt)
2π 0
π
1
Idc = [∫ Im ∗ sinωt d(ωt)]
2π 0

1 Im Im Im
Idc = [−cosωt]π0 = [−cosπ − (−cos0)] = [−(−1) − (−1)] =
2π 2π 2π π
Vm
Idc =
π(R F + R L )

(b) Average or DC output voltage (Vo):

Im Vm
Vdc = × RL =
π π

(c) RMS value of output current (Irms):

1 π2 1 π Im 2 π 1 − cos2ωt
𝑰𝒓𝒎𝒔 = √ ∫ i d(ωt) = √ ∫ Im 2 sin2 ωt ∗ d(ωt) = √ ∫ ( ) ∗ d(ωt)
2π 0 2π 0 2π 0 2

10
 Im 2 π π
Im 2 π
sin2ωt π
=√ ∫ d(ωt) − ∫ cos2(ωt) ∗ d(ωt) = √ [ωt 0 − ( ) ]
4π 0 0 4π 2 0

Im 2 sin2π sin0 Im 2 Im 2 Im
= √ [(π − 0) − ( − )] = √ [(π − 0) − 0] = √ =
4π 2 2 4π 4π 2

(d) Rectification Efficiency (η):

Im 2
Idc 2 ×RL π
×RL Im 2 /π2 ×RL 4
Rectification efficiency (η) = 2 = 2 = 2 = = 0.406
Irms ×RL Im
×RL Im /4×RL π2
2

(e) Ripple Factor (γ):

′
Irms 2
Irms 2
− Idc Irms 2 Irms /2 2 π2
𝛄= =√ 2 = √( ) − 1 = √ ( ) − 1 = √ − 1 = 𝟏. 𝟐𝟏
Idc Idc Idc Im /π 4

(f) Peak inverse Voltage (PIV):

Peak inverse voltage is defined as the maximum voltage that is applied across the
Diode when the diode is reverse biased. [n case of half wave rectifier, maximum
Voltage across the diode when it is not conducting is equal to Vm.
𝑷𝑰𝑽 = 𝑽𝒎
(g) From factor:

𝑟𝑚𝑠 𝑣𝑎𝑙𝑢𝑒 𝜋
𝐹𝐹 = = = 1.57
𝑎𝑣𝑒𝑟𝑎𝑔𝑒 𝑣𝑎𝑙𝑢𝑒 2
(h) Peak factor:

𝑉𝑚
𝑃𝐹 = =2
𝑉
( 2𝑚 )
(i) Transformer utilization factor:

𝑃𝑑𝑐
𝑇𝑈𝐹 = (𝑇𝑟𝑎𝑛𝑠𝑓𝑜𝑟𝑚𝑒𝑟 𝑠𝑒𝑐𝑜𝑛𝑑𝑎𝑟𝑦 𝑟𝑎𝑡𝑒𝑑) = 0.287
𝑃𝑎𝑐

Disadvantages of HWR:
➢ Low output because one half cycle only delivers output
➢ A.C. component more in the output
➢ Requires heavy filter circuits to smooth out the output Peak inverse Voltage.

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 Rectifiers – Full Wave using center tap Transformer
5. Explain the operation of full wave rectifier with center tap transformer. Also derive the following
for this rectifier. (Apr/May 2018)

i) DC output voltage (average value) ii) DC output current (average value) iii) RMS
output voltage.

In FWR, current flows through the load during both half cycles of the input a.c. supply. Like the
half wave circuit, a full wave rectifier circuit produces an output voltage or current which is purely DC or
has some specified DC component. Full wave rectifiers have some fundamental advantages over their half
wave rectifier counterparts. The average (DC) output voltage is higher than for half wave, the output of
the full wave rectifier has much less ripple than that of the half wave rectifier producing a smoother
output waveform.

Full Wave Rectifier:

A full wave rectifier is an electronic circuit which converts AC voltage into a pulsating DC voltage using
both half cycles of the applied AC voltage. A full wave rectifier is a circuit which allows a unidirectional
current to flow through the load during the entire input cycle as shown in fig. The result of full wave
rectification is a d.c. output voltage that pulsates every half-cycle of the input. On the other hand a half
wave rectifier allows the current to flow through the load during positive half-cycle only.

Positive half cycle:

The circuit uses two diodes which are connected to secondary winding of the transformer. The input
signal is applied to the primary winding of the transformer. During the positive input half cycle, the
polarities of the secondary voltage is shown in fig. This forward bias the diode D, and reverse biases the
diode D1. As a result of this, the diode D, conducts some current whereas the diode D, is off.

The current through load R1 is as indicated in through D1, and the voltage Drop across RL will the fig.
The load current flows be equal to the input voltage.

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Negative half cycle:

During the negative input half cycle, the polarities of the secondary voltage are interchanged. The
reverse-bias the diode D, and forward Biases the diode D2. As a result of this, the diode D1 is OFF and the
diode D2 conducts some current. The current through the load R, is an indicated in the fig. The load
current flows through D2 and the voltage drop across R1 will be equal to the input voltage. The maximum
efficiency of a fall-wave rectifier is 8l,2℅Vo and ripple factor is 0.48.

Analysis of Full Wave Rectifier:

Let Vi be the input voltage to the rectifier, 𝑉𝑖 = 𝑉𝑚 𝑠𝑖𝑛𝜔𝑡
Where, 𝑉𝑚 = Maximum value of the input voltage.
Let I be the current flowing though the circuit when the diode is conducting.
𝐼 𝑠𝑖𝑛𝜔𝑡 𝐹𝑜𝑟 0 ≤ 𝜔𝑡 ≤ 𝜋
𝑖={𝑚 }
0 𝐹𝑜𝑟 𝜋 ≤ 𝜔𝑡 ≤ 2𝜋
𝑉𝑚
Where, 𝐼𝑚 = 𝑀𝑎𝑥𝑖𝑚𝑢𝑚 𝑣𝑎𝑙𝑢𝑒 𝑜𝑓 𝑡ℎ𝑒 𝑐𝑢𝑟𝑟𝑒𝑛𝑡; 𝐼𝑚 = 𝑅 +𝑅
𝐹 𝐿
Where, 𝑅𝐹 -Forward dynamic resistance of diode; 𝑅𝐿 -Load resistance.

Input and output waveforms:

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(a) Average or DC value of output current ( Idc ):

Average value = (Area under the curve / Period )

1 π
Idc = ∫ i d(ωt)
π 0
π
1
Idc = [∫ Im ∗ sinωt d(ωt)]
π 0
1 Im Im 2Im
Idc = [−cosωt]π0 = [−cosπ − (−cos0)] = [−(−1) − (−1)] =
π π π π
2Vm
Idc =
π(R F + R L )

(b) Average or DC value of output voltage ( Vdc ) :

2Im 2Vm
Vdc = × RL =
π π

(c) RMS value of output current (Irms):

1 π2 1 π 2 2 Im 2 π 1 − cos2ωt
𝑰𝒓𝒎𝒔 = √ ∫ i d(ωt) = √ ∫ Im sin ωt ∗ d(ωt) = √ ∫ ( ) ∗ d(ωt)
π 0 π 0 π 0 2

Im 2 π π
Im 2 π
sin2ωt π
= √ ∫ d(ωt) − ∫ cos2(ωt) ∗ d(ωt) = √ [ωt 0 − ( ) ]
2π 0 0 2π 2 0

Im 2 sin2π sin0 Im 2 Im 2 Im
=√ [(π − 0) − ( − )] = √ [(π − 0) − 0] = √ =
2π 2 2 2π 2 √2

(d) Rectification Efficiency (η):

2Im 2
Idc 2 ×RL π
×RL 4Im 2 /π2 ×RL 0.812
Rectification efficiency (η) = 2 = Im 2
= 2 = R
= 81.2%
Irms ×RL ×RL Im /2×RL (1+ F )
√2 RL

(e) Ripple Factor (γ):

2
RMS value of Ac component Irms 2 Im /√2 π2
𝛄= = √( ) − 1 = √( ) − 1 = √ − 1 = 𝟎. 𝟒𝟖
Dc value of wave Idc 2Im /π 8

(f)Peak inverse Voltage (PlV):

Peak inverse voltage is the maximum possible voltage across a diode when it is not
conducting. During positive half cycle of the AC input voltage Diode D1, is conducting and Diode D, is
not conducting. In this case a voltage V, is developed across the load resistor R1. Now the voltage across
the non-conducting Diode D, is the sum of the voltage across R1 and voltage across the lower half of
transformer secondary Vm.
Hence, PIV of Diode D2 = Vm + Vm = 2Vm
Similary, PIV of Diode D1 = Vm + Vm = 2Vm

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 Advantages:
1. The D.c load voltage and current are more than halfwave.
2. No D.c current thro transformer windings hence no possibility of saturation.
3. TUF is better.
4. Efficiency is higher.
5. Ripple factor less.

Disadvantages:
1. PIV rating of diode is higher
2. Higher PIV diodes are larger in size ad costlier.
3. Cost of transformer is high.

Rectifiers – Full Wave Bridge type

6. (a) Draw the circuit diagram and explain the working of full wave bridge rectifier & derive the
expansion for average amount current & rectification efficiency. (May 2017) (Nov/Dec 2017)
(Nov/Dec 2018)

Bridge rectifier (Full Wave Bridge rectifier):

Another type of circuit that produces the same output waveform as the full wave rectifier circuit
above is that of the Full Wave Bridge Rectifier. This type of single-phase rectifier uses four individual
rectifying diodes connected in a closed loop "bridge" configuration to produce the desired output. The
main advantage of this bridge circuit is that it does not require a special center tapped transformer,
thereby reducing its size and cost. The single secondary winding is connected to one side of the diode
bridge network and the load to the other side as shown below.

The four diodes labeled D1 to D4 are arranged in "series pairs" with only two diodes conducting
current during each half cycle. During the positive half cycle of the supply, diodes D1 and D2 conduct in
series while diodes D3 and D4 are reverse biased and the current flows through the load as shown below.

During the negative half cycle of the supply, diodes D3 and D4 conduct in series, but diodes D1
and D2 switch of as they are now reverse biased. The current flowing through the load is the same
direction as before. As the current flowing through the load is unidirectional, so the voltage developed
across the load is also unidirectional the same as for the previous two diode full-wave rectifier.

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 Positive half cycle

Negative half cycle

Waveform:

16
Analysis of Full Wave Rectifier:

Let Vi be the input voltage to the rectifier, 𝑉𝑖 = 𝑉𝑚 𝑠𝑖𝑛𝜔𝑡

Where,
𝑉𝑚 = Maximum value of the input voltage.
Let I be the current flowing though the circuit when the diode is conducting.
𝐼 𝑠𝑖𝑛𝜔𝑡 𝐹𝑜𝑟 0 ≤ 𝜔𝑡 ≤ 𝜋
𝑖={𝑚 }
0 𝐹𝑜𝑟 𝜋 ≤ 𝜔𝑡 ≤ 2𝜋
Where
𝐼𝑚 = 𝑀𝑎𝑥𝑖𝑚𝑢𝑚 𝑣𝑎𝑙𝑢𝑒 𝑜𝑓 𝑡ℎ𝑒 𝑐𝑢𝑟𝑟𝑒𝑛𝑡
𝑉𝑚
𝐼𝑚 =
𝑅𝐹 + 𝑅𝐿
Where, 𝑅𝐹 -Forward dynamic resistance of diode; 𝑅𝐿 -Load resistance.

(a) Average or DC value of output current ( Idc ):

Average value = (Area under the curve / Period )

1 π 1 π
Idc = ∫ i d(ωt) Idc = [∫ Im ∗ sinωt d(ωt)]
π 0 π 0

1 Im Im 2Im
Idc = [−cosωt]π0 = [−cosπ − (−cos0)] = [−(−1) − (−1)] =
π π π π
2Vm
Idc =
π(R F + R L )
2Im 2Vm
(b) Average or DC value of output voltage (Vdc): Vdc = × RL =
π π

(c) RMS value of output current (Irms):

1 π2 1 π 2 2 Im 2 π 1 − cos2ωt
𝑰𝒓𝒎𝒔 = √ ∫ i d(ωt) = √ ∫ Im sin ωt ∗ d(ωt) = √ ∫ ( ) ∗ d(ωt)
π 0 π 0 π 0 2

Im 2 π π
Im 2 π
sin2ωt π
= √ ∫ d(ωt) − ∫ cos2(ωt) ∗ d(ωt) = √ [ωt 0 − ( ) ]
2π 0 0 2π 2 0

Im 2 sin2π sin0 Im 2 Im 2 Im
=√ [(π − 0) − ( − )] = √ [(π − 0) − 0] = √ =
2π 2 2 2π 2 √2

(d) Rectification Efficiency (η):

2Im 2
Idc 2 ×RL π
×RL 4Im 2 /π2 ×RL 0.812
Rectification efficiency (η) = 2 = Im 2
= 2 = R
= 81.2%
Irms ×RL ×RL Im /2×RL (1+ F )
√2 RL
(e) Ripple Factor (γ):
2
RMS value of Ac component Irms 2 Im /√2 π2
𝛄= = √( ) − 1 = √( ) − 1 = √ − 1 = 𝟎. 𝟒𝟖
Dc value of wave Idc 2Im /π 8

17
(f)Peak inverse Voltage (PlV):

Peak inverse voltage is the maximum possible voltage across a diode when it is not
Conducting. During positive half cycle of the AC input voltage Diode D1, is conducting and Diode D, is
not conducting. In this case a voltage V, is developed across the load resistor R1. Now the voltage across
the non-conducting Diode D, is the sum of the voltage across R1 and voltage across the lower half of
transformer secondary Vm.
Hence, PIV of Diode D2 = Vm + Vm = 2Vm
Similary, PIV of Diode D1 = Vm + Vm = 2Vm

Advantages:

1. The D.c load voltage and current are more than half wave.
2. No D.c current thro transformer windings hence no possibility of saturation.
3. TUF is better.
4. Efficiency is higher.
5. Ripple factor less.
6. No centre tapped is required.

Disadvantages:

4 diodes are used therefore voltage drop across the diode is increased. This reduces output voltage.

Applications:
1. In power supply circuits.
2. Used as rectifier in power circuits to convert A.C to D.C

(b) In a bridge rectifier circuit, input supply is 230V, 50 Hz. Primary to secondary
turns ratio is 4:1, load resistance is 200 Ω. The diodes are ideal. Find DC output
voltage, PIV and output signal frequency. (Nov / Dec 2018-R17)
Solution: 𝑬𝒑𝒚 (𝒓𝒎𝒔) = 𝟐𝟑𝟎𝑽, 𝑵𝑵𝟐 = 𝟏𝟒 , 𝑹𝑳 = 𝟐𝟎𝟎Ω 𝑹𝒇 = 𝑹𝒔 = 𝟎Ω 𝒂𝒔 𝒊𝒅𝒆𝒂𝒍
𝟏

𝑬𝒑𝒚 (𝒓𝒎𝒔) 𝑵𝟏 𝑵𝟏 𝟏
= , 𝑬𝒔𝒚 (𝒓𝒎𝒔) = 𝑿 𝑬𝒑𝒚 (𝒓𝒎𝒔) = 𝑿 𝟐𝟑𝟎 = 𝟓𝟕. 𝟓 𝑽,
𝑬𝒔𝒚 (𝒓𝒎𝒔) 𝑵𝟐 𝑵𝟐 𝟒

𝑬𝒔𝒚 (𝒎𝒂𝒙) = √𝟐 𝑬𝒑𝒚 (𝒓𝒎𝒔) = √𝟐 𝑿 𝟓𝟕. 𝟓 = 𝟖𝟏. 𝟑𝟏 𝑽

𝑬𝒔𝒎 𝟖𝟏. 𝟑𝟏 𝟐 𝑰𝒎 𝟐 𝑿 𝟎. 𝟒𝟎𝟔𝟓

𝑰𝒎 = = = 𝟎. 𝟒𝟎𝟔𝟓 𝑨𝑰𝑫𝑪 = = = 𝟎. 𝟐𝟓𝟖𝟕 𝑨
𝑹𝒔 + 𝟐𝑹𝒇 + 𝑹𝑳 𝟐𝟎𝟎 𝝅 𝝅

𝑬𝑫𝑪 = 𝑰𝑫𝑪 𝑹𝑳 = 𝟎. 𝟐𝟓𝟖𝟕 𝑿 𝟐𝟎𝟎 = 𝟓𝟏. 𝟕𝟒 𝑽

PIV = 𝑬𝒔𝒎 = 81.31V (for full wave rectifier)

Output signal frequency = 2fs = 2 X 50 = 100Hz

𝐑𝐢𝐩𝐩𝐥𝐞 𝐅𝐚𝐜𝐭𝐨𝐫 (𝐟𝐨𝐫 𝐅𝐮𝐥𝐥 𝐁𝐫𝐢𝐝𝐠𝐞 𝐑𝐞𝐜𝐭𝐢𝐟𝐢𝐞𝐫) = 𝟎. 𝟒𝟖𝟐,

𝑨𝑪 𝒓𝒎𝒔 𝒐𝒖𝒕𝒑𝒖𝒕 𝑹𝒊𝒑𝒑𝒍𝒆 𝑽𝒐𝒍𝒕𝒂𝒈𝒆 𝑹𝒊𝒑𝒑𝒍𝒆 𝑽𝒐𝒍𝒕𝒂𝒈𝒆
𝐑𝐢𝐩𝐩𝐥𝐞 𝐅𝐚𝐜𝐭𝐨𝐫 = 𝑫𝑪 𝒐𝒖𝒕𝒑𝒖𝒕
= 𝑬𝑫𝑪
𝟎. 𝟒𝟖𝟐 = 𝟓𝟏.𝟕𝟒

i.e. Ripple voltage = 51.74 X 0.482 = 24.94 V

18
 7. Compare different types of rectifiers?

Type HW CT FW FW BR

No of diodes used 1 2 4

Need of transformer Not necessary Necessary Not necessary

Ripple factor 1.21 0.48 0.48

Efficiency 40.6% 81.2% 81.2%

PIV Vm 2Vm Vm

TUF 0.287 0.812 0.693

From factor 1.57 1.11 1.11

Peak factor 2 √2 √2

Ripple frequency f 2f 2f

Display devices- LED

8. Discuss the working principle, characteristics and application of LED in detail. (NOV/DEC 2012)
(Apr/May 2018)
Explain the principle and operation of light emitting diode (LED) with necessary expressions for
current densities and efficiency of light generation. (April / May 2019-R17)

A light-emitting diode(LED) is a semiconductor light source LEDs are used as indicator lamps in many
devices and are increasingly used for other lighting. Introduced as a practical electronic component in
1962, early LEDs emitted low-intensity red light, but modern versions are available across the visible,
ultraviolet, and infrared wavelengths, with very high brightness.

When a light-emitting diode is forward-biased (switched on), electrons are able to recombine with
electron holes within the device, releasing energy in the form of photons. This effect is called
electroluminescence and the color of the light (corresponding to the energy of the photon) is determined
by the energy gap of the semiconductor.

LEDs are often small in area (less than 1 mm2), and integrated optical components may be used to
shape its radiation pattern.[5] LEDs present many advantages over incandescent light sources including
lower energy consumption, longer lifetime, improved robustness, smaller size, and faster switching. LEDs
powerful enough for room lighting are relatively expensive and require more precise current and heat
management than compact fluorescent lamp sources of comparable output.

Light Emitting Diodes are made from exotic semiconductor compounds such as Gallium Arsenide
(GaAs), Gallium Phosphide (GaP), Gallium Arsenide Phosphide (GaAsP), Silicon Carbide (SiC) or Gallium
Indium Nitride (GaInN) all mixed together at different ratios to produce a distinct wavelength of colour.

19
Different LED compounds emit light in specific regions of the visible light spectrum and therefore produce
different intensity levels.

• Gallium Arsenide Phosphide (GaAsP) - red to infra-red, orange

• Aluminium Gallium Arsenide Phosphide (AlGaAsP) - high-brightness red, orange-red, orange, and
yellow
• Gallium Phosphide (GaP) - red, yellow and green
• Aluminium Gallium Phosphide (AlGaP) - green
• Gallium Nitride (GaN) - green, emerald green
• Gallium Indium Nitride (GaInN) - near ultraviolet, bluish-green and blue
• Silicon Carbide (SiC) - blue as a substrate
• Zinc Selenide (ZnSe) - blue
• Aluminium Gallium Nitride (AlGaN) - ultraviolet

Light-emitting diodes are used in applications as diverse as aviation lighting, automotive lighting,
advertising, general lighting, and traffic signals. LEDs have allowed new text, video displays, live video,
and sensors to be developed, while their high switching rates are also useful in advanced communications
technology. Infrared LEDs are also used in the remote control units of many commercial products
including televisions, DVD players, and other domestic appliances.
20
Laser diodes

9. Explain in detail about LASER DIODE? (May / June 2016) (April/May 2018)
The term laser comes from the acronym for light amplification for stimulated emission of
radiation. The laser medium can be a gas, liquid, amorphous solid or semiconductor.

Laser Action
The light travelling through a semiconductor, then a single photon is able to generate an identical second
photon. This photon multiplication is the key physical mechanism of lasing. The carrier inversion is the
first requirement of lasing. It is achieved at the PN junction by providing the conduction bandwith
electrons from the N-doped side and the valence band with holes from the P-doped side as shown in Fig.
The photon energy is given by the band gap, which depends on the semiconductor material. The optical
feedback and the confinement of photon in an optical resonator are the second basic requirement of
lasing.

PN Homojunction Laser
It has the material GaAs on both sides of the junction. A pair of parallel planes perpendicular to the plane of the
junction are cleared and polished under appropriate biasing in off condition, laser light is emitted from these planes.
The other two sides are deliberately roughened to prevent lasing in those directions. Such a cavity is called a
Fabryperot resonant cavity with a typical cavity length of 300 |J.m. It is a thin layer of material with a narrow band
gap. GaAs is sandwiched between layers of a material with band gap. This is usually realized by epitaxy. In such a
structure the carrier are better confined in the active region due to the heterojunction barriers. Optical confinement
is also better in DH laser. The propagation of the electromagnetic radiation is confined in a direction parallel to the

Stimulation
Emission
Region

layer interface. The current density required for lasing in lower for DH lasers compared to homojunction lasers.
The double preferred for continuous operation at room temperature.

21
Characteristics of Laser Diode

The Ideal light output against current characteristics for semiconductor laser is shown in Fig.4.28.
The solid line represents the laser characteristics. It may be observed that the device gives low light
output in the region, the threshold with corresponds to spontaneous emission only within the structure.
After the threshold current value the light output increases substantially for small increases in current
through the device.

22
 ZENER DIODE
10. Explain the construction & working principle of Zener diode.
Explain the Break down mechanisms in semiconductor devices. (May/June 2016), (Nov / Dec 2015)
(OR) Explain the Concept of Zener Breakdown and its VI characteristics. (Nov/Dec 2018-R-13)

ZENER DIODE:
The Zener Diode is a PN junction semiconductor device.
It is fabricated with precise breakdown voltages, by controlling the doping level during manufacturing.
Practically, Zener Diodes are operated in reverse biased mode.

Fig.20 Zener Diode

CHARACTERISITCS OF ZENER DIODE:

FORWARD CHARACTERISITCS:

In forward biased condition, the normal rectifier diode and the Zener diode operate in similar fashion.
(Refer: PN diode forward characteristics)

Zener reverse characteristics

REVERSE CHARACTERISITCS:

Zener diode is designed to operate in the reverse biased condition.

In reverse biased condition, the diode carries reverse saturation current till the reverse voltage applied is
less than the reverse breakdown voltage.

When the reverse voltage exceeds reverse breakdown voltage, the current through it changes drastically
but the voltage across it remains almost constant.

Such a breakdown region is a normal operating region for a Zener diode.

The normal operating regions for both diode and Zener are shown in below Fig.

23
 Fig. The normal operating region for a rectifier diode and Zener diode
When the applied reverse voltage is increased then, the current through it is very small (few µA) and it is called
Reverse Leakage Current (Io)
At certain reverse voltage, the current will increase rapidly. The breakdown occurs and the current at this point
(knee or Zener knee) is called Zener knee current (IZK or IZmin).
Zener knee current is the minimum Zener current which is must to carry out the operate in Reverse Breakdown
Region.
The reverse voltage at which the breakdown occurs is called Zener Breakdown Voltage or Zener Voltage (VZ).
The VZ is set by controlling the doping level during manufacturing process.

Below the knee, the reverse breakdown voltage increases slightly as Zener current (IZ) increases but, remains
almost CONSTANT.
The current at which the nominal Zener breakdown voltage is specified is called Zener Test Current (IZT).

As the current increases, the power dissipation (PZ = VZ IZ) will be increased and if this power dissipation is
increased beyond a certain current value, the Zener diode may get damaged. So, there is a maximum current that a
Zener diode can carry safely is called Zener Maximum Current (IZM or IZmax).

In practical circuits, a current limiting resistor is used in series with Zener diode in order to limit the current
between IZmin to IZmax.

The complete VI characteristics of Zener Diode is shown in Fig.

Fig. VI characteristics of Zener Diode

24
EQUIVALENT CIRCUIT OF ZENER DIODE:

When the breakdown occurs then IZ may increase from IZmin to IZmax but voltage across Zener remains
almost constant. The internal impedance decreases as current increases in Zener region. But this
impedance is very small and hence ideally Zener diode is indicated by a battery of voltage VZ. This VZ
remains almost constant in the Zener region which is shown in Fig.

Fig. Ideal equivalent circuit of Zener diode

In practical circuit, the Zener internal resistance is to be considered (even though it is very small) and
called as Zener Dynamic Resistance ZZ. Due to this resistance the Zener region is not exactly vertical,
i.e., for the small change in the Zener current ∆IZ produces a small change in Zener voltage ∆VZ. The
ratio of VZ to IZ is called Zener resistance ZZ.
Hence, the practical Zener diode equivalent circuit should be indicated with a battery of V Z along with
series resistance ZZ as shown in Fig.

∆𝑉𝑍 1
Dynamic Resistance, 𝑍𝑍 = = ∆𝐼
∆𝐼𝑍 [∆𝑉𝑍 ]
𝑍

1
𝑍𝑍 =
[𝑠𝑙𝑜𝑝𝑒 𝑜𝑓 𝑡ℎ𝑒 𝑟𝑒𝑣𝑒𝑟𝑠𝑒 𝑐ℎ𝑎𝑟𝑎𝑐𝑡𝑒𝑟𝑖𝑠𝑡𝑖𝑐𝑠 𝑖𝑛 𝑧𝑒𝑛𝑒𝑟 𝑟𝑒𝑔𝑖𝑜𝑛]

25
BREAKDOWN MECHANISM IN ZENER DIODE:

Two distinct breakdown mechanism:

✓ Zener Breakdown
✓ Avalanche Breakdown

For devices with breakdown voltage less than 5V - Zener Breakdown

For devices with breakdown voltage between 5V and 8V - Zener Breakdown and Avalanche Breakdown
For devices with breakdown voltage above 8V - Avalanche Breakdown

ZENER BREAKDOWN:
Zener breakdown occurs at Reverse biased condition because of heavy doping;
Practically, Zener breakdown is observed in the Zener diodes with breakdown voltage less than 6V.
In Zener breakdown, the value of the breakdown voltage decreases as PN junction temperature increases, i.e.
Negative Temperature Coefficient (NTC)

For applied reverse biased voltage of less than 6V causes a high magnitude electric
field (3 X 105 V/cm) across the depletion region, at the PN junction.
This electric field applies a large force on the valence electron of the atom, tending it
to separate them from their respective nuclei. Electron-hole pairs are generated in
large numbers and there will be a sudden increase in current. (To limit this current, a
current limiting resistor is used in order to protect the Zener diode from being
destroyed because of excessive heating at the junction)

AVALANCHE BREAKDOWN:
Avalanche Breakdown occurs at Reverse biased condition due to ionization of electron and hole pairs
Practically, Avalanche breakdown is observed in the Zener diodes with breakdown voltage greater than 6V.
In avalanche breakdown, the value of the breakdown voltage increases as PN junction temperature increases, i.e.
Positive Temperature Coefficient (PTC)

For applied reverse biased voltage of greater than 6V causes increased acceleration
of minority charge particles. Thus, collision between accelerated charge particles
with high velocity and kinetic energy with adjacent atom is involved in breaking the
covalent bonds of the crystal structure. This process is called Carrier
Multiplication.
At this stage, junction is said to be in breakdown and current starts increasing
rapidly. To limit this current below IZmax, a current limiting resistor is necessary.

Fig. Breakdown Mechanism in Zener Diode

26
 ZENER AS REGULATOR
11. (a) Explain the working of a Zener diode as a regulator? (May 2017) (Nov/Dec 2017) (Nov/Dec
2018 – R17)

The Zener Diode is used to regulate the Load Voltage. Here, the Zener is used in reverse biased condition.

Fig. Zener Diode as a shunt regulator

{Under reverse biased condition, the current through the zener

diode is very small of the order of few µA, up to certain limit.
When enough reverse bias voltage is applied, electrical
breakdown occurs and large current flows through the zener
diode. The voltage at which the breakdown occurs is called
Zener Voltage (VZ). Fig. VI characteristics of Zener Diode
Under this condition, whatever may be the current, the voltage across the Zener is constant and equal to
VZ}

Since, voltage across the Zener Diode is CONSTANT & equal to VZ, it is connected across the load.
⸫ The Load Voltage (Vo) is equal to Zener Voltage (VZ).
i.e. The Zener Diode acts as an ideal voltage source which maintains a constant load voltage,
independent of the current.

REGULATION WITH VARYING INPUT VOLTAGE (Line Regulation)

Zener Regulator under varying input voltage condition is
shown in Fig.

Vo = VZ is constant
𝑉 𝑉
IL = 𝑜 = 𝑍 = 𝑐𝑜𝑛𝑠𝑡𝑎𝑛𝑡
𝑅𝐿 𝑅𝐿
And 𝐼 = 𝐼𝑍 + 𝐼𝐿
Fig. Varying input condition

As long 𝑰𝒁 is between 𝑰𝒁𝒎𝒊𝒏 and 𝑰𝒁𝒎𝒂𝒙 , the VZ i.e. output voltage Vo is constant. Thus, the changes
in the input voltage is get compensated and output is maintained constant.
The maximum power dissipation for the zener diode is fixed, 𝑷𝑫 = 𝑽𝒁 𝑰𝒁𝒎𝒂𝒙

27
REGULATION WITH VARYING LOAD (Load Regulation)
Zener Regulator under varying load condition (RL is variable) and constant input voltage (Vin is constant)
is shown in Fig.

Fig. Varying load condition

Vo = VZ is constant and Vin is Constant, then for constant R, the current (I) is
constant.
𝑉 −𝑉
I = 𝑖𝑛 𝑍 (constant); I = 𝐼𝐿 + 𝐼𝑍
𝑅

As long 𝑰𝒁 is between 𝑰𝒁𝒎𝒊𝒏 and 𝑰𝒁𝒎𝒂𝒙 , the VZ i.e. output voltage Vo is constant. Thus, the changes
in the load is get compensated and output is maintained constant.

(b) For the following circuit, find the maximum and minimum values of Zener diode
current. (Nov/Dec 2018 – R17)

Solution:𝑉𝑖𝑛 (𝑚𝑖𝑛) = 80𝑉, 𝑉𝑖𝑛 (𝑚𝑎𝑥) = 120𝑉, 𝑉𝑍 = 50𝑉, 𝑅𝐿 = 10𝐾Ω, 𝑅 = 5𝐾Ω

𝑉𝑍 50
𝐼𝐿 = = = 5 𝑋 10−3 = 5𝑚𝐴
𝑅𝐿 10 𝑋 103
𝑉𝑖𝑛 (𝑚𝑖𝑛) = 𝑉𝑍 + 𝐼𝑅𝑉𝑖𝑛 (𝑚𝑎𝑥) = 𝑉𝑍 + 𝐼𝑅

𝑉𝑖𝑛 (min) − 𝑉𝑍 𝑉𝑖𝑛 (max) − 𝑉𝑍

𝐼= 𝐼=
𝑅 𝑅

80 − 50 120 − 50
𝐼(𝑚𝑖𝑛) = = 6𝑚𝐴 𝐼(𝑚𝑎𝑥) = = 14𝑚𝐴
5 𝑋 103 5 𝑋 103

𝐼𝑍 (𝑚𝑖𝑛) = 𝐼(𝑚𝑖𝑛) − 𝐼𝐿 𝐼𝑍 (𝑚𝑎𝑥) = 𝐼(𝑚𝑎𝑥) − 𝐼𝐿

𝐼𝑍 (𝑚𝑖𝑛) = 6 𝑋 10−3 − 5 𝑋 10−3 = 1𝑚𝐴 𝐼𝑍 (𝑚𝑎𝑥) = 14 𝑋 10−3 − 5 𝑋 10−3 = 9𝑚𝐴

⸫𝑴𝒊𝒏𝒊𝒎𝒖𝒎 𝒛𝒆𝒏𝒆𝒓 𝒄𝒖𝒓𝒓𝒆𝒏𝒕, 𝑰𝒁 (𝒎𝒊𝒏) = 𝟏𝒎𝑨 ⸫𝑴𝒂𝒙𝒊𝒎𝒖𝒎 𝒛𝒆𝒏𝒆𝒓 𝒄𝒖𝒓𝒓𝒆𝒏𝒕, 𝑰𝒁 (𝒎𝒂𝒙) = 𝟗𝒎𝑨

28
Problems: (Anna University Exam - Solved Problems)

1. For the zener regulator shown in Fig. 5, calculate the range of input voltage for which output
will remain constant.
𝑰𝒁 (𝒎𝒊𝒏) = 𝟐. 𝟓𝒎𝑨, 𝑰𝒁 (𝒎𝒂𝒙) = 𝟐𝟓𝒎𝑨, 𝑽𝒁 = 𝟔. 𝟏𝑽, 𝒓𝒁 = 𝟎 𝑲Ω

Solution:
𝐼𝑍 (𝑚𝑖𝑛) = 2.5𝑚𝐴, 𝐼𝑍 (𝑚𝑖𝑛) = 25𝑚𝐴, 𝑉𝑍 = 6.1𝑉, 𝑟𝑍 = 0 𝐾Ω, 𝑅 = 2.2 𝐾Ω, 𝑅𝐿 = 1 𝐾Ω
𝑉𝑍 6.1
𝐼𝐿 = = = 6.1 𝑋 10−3 = 6.1𝑚𝐴 (𝑪𝑶𝑵𝑺𝑻𝑨𝑵𝑻)
𝑅𝐿 1 𝑋 103
𝐹𝑜𝑟 𝑉𝑖𝑛 (𝑚𝑖𝑛) ; 𝐼 (𝑚𝑖𝑛) = 𝐼𝑧(𝑚𝑖𝑛) + 𝐼𝐿 𝐹𝑜𝑟 𝑉𝑖𝑛 (𝑚𝑧𝑥) ; 𝐼 (𝑚𝑎𝑥) = 𝐼𝑍(𝑚𝑎𝑥) + 𝐼𝐿
𝐼 = 2.5 𝑋 10−3 + 6.1 𝑋 10−3 = 8.6𝑚𝐴 𝐼 = 25 𝑋 10−3 + 6.1 𝑋 10−3 = 31.1𝑚𝐴
𝑉𝑖𝑛 (𝑚𝑖𝑛) = 𝑉𝑍 + 𝐼𝑅𝑉𝑖𝑛 (𝑚𝑎𝑥) = 𝑉𝑍 + 𝐼𝑅

𝑉𝑖𝑛 (𝑚𝑖𝑛) = 6.1 + 8.6 𝑋 10−3 𝑋 2.2 𝑋 10−3 = 25.02𝑉 𝑉𝑖𝑛 (𝑚𝑖𝑛) = 6.1 + 31.1 𝑋 10−3 𝑋 2.2 𝑋 10−3 = 74.52𝑉
⸫ 𝑽𝒊𝒏 (𝒎𝒊𝒏) = 𝟐𝟓. 𝟎𝟐𝑽 ⸫ 𝑽𝒊𝒏 (𝒎𝒂𝒙) = 𝟕𝟒. 𝟓𝟐𝑽

2. A silicon diode has a saturation current 7.5𝝁 A at room temperature 300K.Find the saturation
current at 400k. Io1=7.5 x 10-6 A at T1=300⁰ K=27⁰ C and T2=400 ⁰K=127⁰ C. (Nov/Dec 2016 – R13)
Solution: The saturation current at 400⁰K is
∆𝑇
𝐼02 =𝐼01 × 210 =7.5 X 10-6 X 2(127-27)/10 =7.68mA

3. Find the current I in the following circuit. (Nov/Dec 2017 – R13)

Assume the diodes to be of silicon and forward resistance of diodes to be zero.

I = (E1-E2)/R I = (24-4)/2000
I = 1 mA Current I is 1mA.

4. An AC voltage of peak value 20V is connected in series with a silicon diode and load resistance of
500Ω. If the forward resistance of diode is 10Ω find the peak current through the diode.
(Nov/Dec 2018-R17)
Solution: 𝐸𝑚 = 20𝑉, 𝑅𝐿 = 500Ω, 𝑅𝑓 = 10Ω
𝐸𝑚 20
𝐼𝑚 = 𝐼𝑚 =
𝑅𝑓 + 𝑅𝐿 500 + 10
⸫ 𝐼𝑚 = 39.22 𝑚𝐴

29
5. (a) Determine the peak output voltage of a half wave rectifier, if the diode has V F =
0.7V and the AC input is 22V. (April / May 2019-R17)

Solution: 𝑉𝑝𝑜 = 𝑉𝑝𝑖 − 𝑉𝐹

𝑉𝐹 = 0.7 𝑉, 𝑉𝑝𝑖 = √2𝑉𝑖 = √2 𝑋 22, 𝑉𝑝𝑖 = 31.1 𝑉
𝑉𝑝𝑜 = 31.1 − 0.7, 𝑉𝑝𝑜 = 30.4 𝑉

(b) If load resistance is given as 500Ω, calculate peak output current of the above given half wave
rectifier.
𝑉𝑝𝑜 30.4
Solution: 𝑅𝐿 = 500Ω 𝐼𝑝 = = 𝐼𝑝 = 60.8 𝑚𝐴
𝑅𝐿 500
(c) Determine the diode peak reverse voltage (PIV). PIV = 𝑉𝑝𝑖 = 31.1 V

6. What value of series resistor is required to limit the current through a LED to 20 mA with a forward
voltage drop of 1.6 V when connected to a 10V supply? (Nov/Dec 2017)

7. In a semiconductor at room temperature(300oK), the intrinsic carrier concentration and resistivity

are1.5 * 1016/cm3 and 2 *103Ω-mrespectively. It is to an extrinsic semiconductor with a doping
concentration of 1020/cm3 for the extrinsic semiconductor.
Calculate (a) Majority carrier concentration, (b) Shift in fermilevel due to doping (c) Minority carrier
concentration when its temperature is increased to a value at which the intrinsic concentration ‘ni’
doubles. (NOV/DEC 2012)

Assume the mobility of majority and minority carriers are same and KT=26 meT at room temperature.
i n2
a) Minority carrier concentration=Doping concentration

(1.5×1016 ) atoms
= 1020
= 2.25 × 1012 m3
We knowσ = nq(μn + μp )
σ 1
or(μn + μp ) = nq = ρnq
1 1
=(2×103 )(1.5×1016 )(1.6×10−19 ) = 4.8
In this case the concentration of majority and minority carriers are same, thus
1 m2
μn + μp = 2μn = or μn = o. 1042
4.8 Volt − sec

b) Because of doping concentration>> minority concentration conductivity.

σ = qn μn = (1.6 × 10−19 )(1020)(0.10242)=1.6672
1
Thus resistivity R=σ = 0.599Ωcm
Shift interm level EF computed as follows

no 1020
C) EA − Ei = KT log e = 0.026log e ( )
ni 1016 ×15
=0.229e V.
Thus EF lies0.229e V above from fermilevel.
2
(2ni)2 [2(1.5×1016 ) ] 9×1032
d) Minority carrier concentration=doping concentration = 1020
= 1020
=9× 1012 atoms/cm3 .

30
Additional Questions: PART-A
1. Define valence electron.
Electrons that are in shells close to nucleus are tightly bounced to the atom and have low energy. Whereas
electrons that are in shells farther from the nucleus have large energy and less tightly bound to the atom.
Electrons with highest energy level exist in the outermost shell of an atom. These electrons determine the
electrical and chemical characteristic of each particular type of atom. These electrons are known as valence
electrons.

2. What is meant by energy band?

In a single isolated atom, the electron in any orbit possesses define energy. Due to an interaction between atoms
the electrons in a particular orbit of one atom have slightly different energy levels from electrons in the same
orbit of an adjoining atom. This is due to the fact that no two electrons see exactly the same pattern of
surrounding charges. Since there are billions of electrons in any orbit, slightly different energy levels form a
cluster or band known as energy band.

3. Define conduction band & valence band.

o The conduction band is defined as the range of energies possessed by conduction electrons.
o Valence band is defined as the range of energies possessed by valence electros.

4. What are conductors, Insulators and semiconductors?

o A conductor is a material, which easily allows the flow of electric current. The best conductors are copper,
silver, gold and aluminum.
o An Insulator is a material that does not conduct electric current. In these materials valence electrons are
tightly bound to the atoms.
o A semiconductor is a material that has an electrical conductivity that lies between conductors and
insulators. A semiconductor in it’s pure state is neither a good conductor not a good insulator. The most
common semiconductors are silicon, Germanium, and carbon.

5. What are the classifications of semiconductors?

Semiconductors are classified as intrinsic and extrinsic semiconductors. A pure semiconductor is called
intrinsic semiconductor. A doped semiconductor is called extrinsic semiconductor.

6. What is meant by doping? How the extrinsic semiconductors are classified?

The process of adding impurities to a semiconductor is known as doping.
o n-type semiconductor
o p-type semiconductor

7. How a n-type semiconductor & p-type semiconductor can be obtained?

o A n-type semiconductor can be obtained by adding pentavalent impurities to an intrinsic
semiconductor. These are atoms with five valence electrons. Typical examples for pentavalent atoms
are Arsenic. Phosphorous, Bismuth and Antimony.

o A p-type semiconductor can be obtained by adding trivalent impurities to an intrinsic semiconductor.

These are atoms with three valence electrons. Typical examples for trivalent atoms are boron(B),
indium (In) and gallium (Ga).

8. Define Fermi level.

Fermi level is the energy at which the probability of occupation by an electron is exactly 0.5.

9. What is the energy band gap of silicon and Germanium at 300°K?

For Germanium: 0.66e and for Silicon: 1.12ev
10. What are the different types of voltage regulators?
Based on how regulating element is connected to the load, voltage regulators are classified as
o Series regulator
o Shunt regulator
o Switch-mode regulators or switched mode power supply (SMPS)

31
Additional Questions (PART-B)
1. Draw and explain the energy band diagram for the following
(i) conductors (ii) Insulators (iii) semiconductors
Insulators :
The materials in which the condition band and valence bands are seperated by a wide energy gap (≈ 15 eV) as
shown in figure.
A wide energy gap means that a large amount of energy is required, to free the electrons, by moving them from the
valence band into the condition band ;
Since at room temperature, the valence electrons of an insulator do not have enough energy to jump in to the
condition, therefore insulator do not have an ability to conduct current. Thus insulators have very high resistively
(or extremely low conductivity) at room temperatures.
However if the temperature is raised, some of the valence electrons may acquire energy and jump in to the
conduction band. It causes the resistively of insulators to decrease.Therefore an insulator have negative temperature
co-efficient of resistance.

Conductors :-
The materials in which conduction and valence bands overlap as shown in figure are called conductors.
The overlapping indicates a large number of electrons available for conduction.Hence the application of a small
amount of voltage results a large amount of current.

Semiconductors :-
The materials, in which the conduction and valence bands are separeated by a small energy gap (1eV) as
shown in figure are called semiconductors.
Silicon and germanium are the commonly used semiconductors.
A small energy gap means that a small amount of energy is required to free the elctrons by moving them from the
valence band in to the conduction band.
The semiconductors behave4 like insulators at 0K, because no electrons are available in the conduction band.
If the temperature is further increased, more valence elctrons will acquire energy to jump into the conduction
band.Thus like insulators, semiconductors also have negative temperature co-efficient of resistance. It means that
conductivity of semiconductors increases with the increases tempertature.

2. Explain the classification of semi-conducteurs.

Classification of semi-conducteurs :-
Semiconductors are classified in to two types
o Intrinsic Semiconductors
o Exterinsic semi-conducteurs
➢ n-type semi-conductor
➢ p-type semi-conductor

o Intrinsic seiconductor
A semiconductor in an extremely pure form is known as an intrinic semiconductor. An Intrinsic
semiconductor, even at room temperature, hole-electron pairs all created. When electric field is applied across an
semiconductor intrinisic semiconductor, the current conduction takes place by two process, namely by free
electrons and holes.

32
 Free electrons are produced due to the breeding up of fome co-valent bonds by thermal energy. At the same
time holes are created in the co-valent bond itself.When electric field is applied across the semi-conducteurs
material electrons will move towards the positive terminal of supply, holes will move towards negative terminal of
the supply.
Thus current conduction inside this intrinisic semiconductor material is due to movement of holes & electrons.
But the current in the external wire is only because of electrons. Since while applying electric field, holes
are attracted towards negative terminal. There one new electron is introduced. This electron will combine with the
hole, thus cancelling them.
At the same time electrons are moving towards positive terminal, while leacing from this intrinisic
material it leaves a hole. Again this holes are attracted towards negative terminal.

o Extrinisic semiconductor :

The current conduction capability of intrinisic semiconductor is very low at rom temperature. So we can
not use it in electric devices.
Hence the current conduction capability must be increased. This can be achieved by adding impurities to the
intrinisic semiconductor. So that it become impurity semiconductor (or) Extrinisic semiconductor.The process of
adding impurity is known as doping.
The amount & type of impurities have to be closely controlled during the preparation of extrinisic
semiconductor. Generally, for 108 atoms of semiconductor, one impurity atom is added.
The purpose of adding impurity is to increase either the number of free electrons or holes in the semiconductor
crystal. If the pentavalent impurity is adding to the semiconductor, a large number of free electrons are produced in
the semiconductor.
On the other hand if the trivalent impurtiy is added it introdued large number of holes. Depending upon the type of
impurity added, extrisic semiconductors are classified into

➢ n – type Semiconductor
➢ p – type Semiconductor

n – type Semiconductor :

The number of free electrons in an instrinsic silicon can be increased by adding a pentavalent atom to it.
These are atoms with five valence electrons. Typical example for pentavalent atoms are Arsenic, Phosphorous,
Bismuth and Antimony.

Four of the pentavalent atoms valence electrons form covalent bond with the valence electrons of Silicon
atom, leaving an extra electron. Since valence orbit cannot hold no more than eight electrons the extra electron
becomes a conduction electron.

33
 Since the pentavalent atom donnates this extra conduction electron it is often called as a donor atom. For
each pentavalent atom added, one free electron exists in a silicon crystal. A small amount of pentavalent impurity is
enough to get more number of free electrons is greater than the nuumber of holes this extrinsic semiconductor is
known as an n type semiconductor.
When a pentavalent atom is added a number of conduction band electrons are produced. Only a few holes
exist in the valence band, created by thermal energy. Therefore in an n-type semiconductor, electrons are majority
carriers and holes are minority carriers.

p-type semiconductor

A p-type semiconductor (p for Positive) is obtained by carrying out a process of doping by adding a certain
type of atoms (acceptors) to the semiconductor in order to increase the number of free charge carriers (in this case
positive holes).

When the doping material is added, it takes away (accepts) weakly bound outer electrons from the
semiconductor atoms. This type of doping agent is also known as an acceptor material and the vacancy left behind
by the electron is known as a hole.

The purpose of p-type doping is to create an abundance of holes. In the case of silicon, a trivalent atom
(typically from Group 13 of the periodic table, such as boron or aluminium) is substituted into the crystal lattice.
The result is that one electron is missing from one of the four covalent bonds normal for the silicon lattice. Thus the
dopant atom can accept an electron from a neighboring atom's covalent bond to complete the fourth bond. This is
why such dopants are called acceptors.

The dopant atom accepts an electron, causing the loss of half of one bond from the neighboring atom and
resulting in the formation of a "hole". Each hole is associated with a nearby negatively charged dopant ion, and the
semiconductor remains electrically neutral as a whole. However, once each hole has wandered away into the
lattice, one proton in the atom at the hole's location will be "exposed" and no longer cancelled by an electron.

This atom will have 3 electrons and 1 hole surrounding a particular nucleus with 4 protons. For this reason
a hole behaves as a positive charge. When a sufficiently large number of acceptor atoms are added, the holes
greatly outnumber thermal excited electrons. Thus, holes are the majority carriers, while electrons become minority
carriers in p-type materials.

34
 EC8353-ELECTRONIC DEVICES AND CIRCUITS

UNIT-II TRANSISTORS & THYRISTORS

PART – A
BJT (Bipolar Junction Transistor)

1. What is transistor (BJT)? What are the types of circuit connections known as configurations, for operating a
transistor?
Transistor (BJT) is a three-terminal device: Base (B), Emitter (E) & Collector (C).
Transistor can be operated in three configurations Common Base (CB), Common Emitter (CE) & Common
Collector (CC).
According to configuration it can be used for voltage as well as current amplification.

2. Brief the types of transistors?

1. UJT (Unipolar Junction Transistor): In unipolar transistor, the current conduction is only due to one type
of charge carriers (majority carriers).
2. BJT (Bipolar Junction Transistor): In bipolar transistor, the current conduction is only due to both the
types of charge carriers (Holes and Electrons).

3. Why an ordinary transistor is called bipolar?

Because the transistor operation is carried out by two types charge carriers (both majority and minority
carriers).

4. What are the types of BJT?

Types of BJT:
1. NPN
2. PNP

5. Brief the construction of BJT. Draw the symbol and structure and of BJT.
BJT is a three- layer semiconductor device consisting of two PN junctions.
If a layer of P-type material is sandwiched between two layers of N-type the transistor is known as NPN
transistor.

Fig. Symbol of BJT (NPN type) Fig. Structure of BJT (NPN type)

On the other hand, if a layer of N-type material is sandwiched between two layers of P-type, the transistor is known
as PNP transistor.

Fig. Symbol of BJT (PNP type) Fig. Structure of BJT (PNP type)

6. Why collector is made larger than emitter and base?

Collector is made physically larger than emitter and base because collector is to dissipate much power.

7. Why the width of the base region of a transistor is kept very Small as compared to other regions?
Base region of a transistor is kept very small and lightly doped so as to pass most of the injected charge
carriers to the collector.
1
8. How transistor is used as an amplifier? (OR) Explain the word transistor.
The amplification in the transistor is achieved by passing input current signal from a region of low resistance to a
region of high resistance.
{This concept of transfer of resistance has given the TRANSfer-resISTOR (TRANSISTOR)}

9. Why silicon is preferred to germanium while manufacturing semiconductor devices?

As the knee voltage of silicon is higher (0.7V) than the knee voltage of germanium (0.3V), silicon will be more
stable for temperature variation than germanium.

10. Why transistor (BJT) is called current controlled device?

The output voltage, current or power is controlled by the input current in a transistor. So, it is called the Current
Controlled device.

11. State the advantages of a transistor.

1. Low operating voltage
2. Higher efficiency
3. Small size and ruggedness
4. 4. Does not require any filament power

12. Compare the performance of a transistor in three different configurations. (Nov/Dec 2012) (OR) Compare
the input resistance, output resistance and voltage gain of CB, CC and CE configuration. (OR) Compare the
performance of CE and CC configuration. (May 2017)

Property CB CE CC
Input resistance Low (about 100) Moderate (about 750 ) High (about 750 k)
Output resistance High (about 450 ) Moderate (about 45 ) Low (about 25)
Current gain 1 High High
Voltage gain About 150 About 500 Less than 1
Phase shift 0 or 360o 180o 0 or 360o
Between input & output For high frequency For audio frequency For impedance matching
voltages Applications circuits circuits

13. Define Early effect? (Nov/Dec 2016)

As the collector voltage VCC is made to increase the reverse bias, the space charge width between collector and
base tends to increase, with the result that the effective width of the base decreases. This known as early effect or
base width modulation.

14. What is peak point Voltage?

When VEE exceeds the value (VD+ɳVBB), the diode is forward biased and starts to conduct. The value of emitter
voltage which makes diode to conduct is called Peak Point Voltage.
Vp=(VD+ɳVBB)

JFET (Junction Field EffectnTransistor)

15. What are the different types of FET?

Types of FET:
1. Junction Field Effect Transistor (JFET)
2. Metal Oxide Semiconductor Field Effect Transistor (MOSFET)

16. Draw the symbol and structure of JFET.

Fig. Structure and for n-channel JFET Fig. Structure and for p-channel JFET
2
17. What are the features of JFET?
a) The operation of JFET depends upon the flow of majority carriers only.
b) The input impedance of JFET is very high, in the order of MΩ.
c) The JFET is less noisy than BJT.
d) It exhibits no offset voltage at zero drain current.
e) It is simple to fabricate.
F) It occupies less space in an integrated circuit.

18. Draw the transfer and drain characteristics curves of JFET? (May / June 2016)

Drain Characteristics:
Transfer Characteristics:

Fig. Drain VI characteristics of n-channel JFET

Fig. Transfer characteristics of n-channel JFET

Drain Characteristics: Transfer Characteristics:

Fig. Drain VI characteristics of p-channel JFET

Fig. Transfer characteristics of p-channel JFET

19. Define pinch-off voltage of a FET? (Nov/Dec-2012, May/June-2013)

Pinch-off voltage (VP) is defined as the drain to source voltage above which drain current becomes almost
constant.

20. Mention the disadvantages of FET compared to BJT. (Nov/Dec-2012)

Gain bandwidth product of FET is relatively small as compared to BJT.

3
21. Define drain resistance.
The drain resistance or output (rd) is defined as the ratio between change in drain-source voltage (VDS)
and change in drain current (ID) at constant gate-source voltage (VGS).

𝜕𝑉𝐷𝑆
rd = 𝑉𝐺𝑆
𝜕𝑖𝐷

22. Differentiate FET and BJT (Nov/Dec 2018)

S.No FET BJT

Unipolar device (that is current conduction by only one Bipolar device (current conduction by both
1
type of either electron or hole). electron and hole).
2 High input impedance due to reverse bias. Low input impedance due to forward bias.
Gain is characterized by voltage
3 Gain is characterized by trans conductance
gain.
4 Low noise level High noise level

23. What are the applications of JFET?

a) JFET is used as a buffer in measuring instruments since it has high input impedance and low output
impedance.
b) JFET is used in RF amplifier in FM tuners and communication equipment.
c) JFET is used in digital circuit’s ii computers and memory circuits because of its small size.
d) It is used oscillators because the frequency drift is low.

24. FET has lower thermal noise than BJT - Justify. (April / May 2019-R17)
The FET has high gate-to-main current resistance, on the order of 100MΩ or more providing a
high degree of isolation between control and flow. Because base current noise will increase with shaping
time, a FET typically produces less noise than a Bipolar Junction Transistor (BJT).
Thus, found in noise-sensitive electronics such as tuners and low noise amplifiers for VHF and satellite
receivers. It is relatively immune to radiation.

25. What is the difference between BJT and JFET? (Nov/Dec 2017) (Apr/May 2018) (Nov/Dec 2018-R17)

S.
Bipolar junction transistor (BJT) Junction field effect transistor (JFET)
No.
Bipolar device (current conduction is by Unipolar device (current is by only one type of
1
both electrons and holes) carrier-either electrons or holes)
2 Low input impedance due to forward bias High input impedance due to reverse bias
3 Current control device Voltage control device
4 Gain is characterized by voltage gain Gain is characterized by Tran conductance.
5 High noise level Low noise level

MOSFET
26. What are the different types of MOSFET? (May/June-2012, 2013)
The modes of operation of the MOSFET are divided into two types.
a) Depletion mode MOSFET
b) Enhancement mode MOSFET

27. What is the other name for MOSFET? (May/June-2012, 2013)

Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is also called as Insulated Gate Field Effect
Transistor (IGFET)
4
28. If the gate-to-source voltage in an Enhancement MOSFET is zero, what is the current from drain to source?
In an Enhancement MOSFET if the gate-to-source voltage is zero, then the current from drain to source is also
zero.

29. What is the major difference in construction of the D-MOSFET and the E-MOSFET?
The depletion MOSFET has a structural channel, whereas the enhancement-MOSFET does not.

30. If the gate-to-source voltage in depletion MOSFET is zero, what is the current from drain to source?
When gate –source voltage is zero for depletion MOSFET, the drain-source current is equal to IDSS. (ID_IDSS)

31. What are the precautions to be taken when handling MOSFET?

a) MOSFET should be shipped and stored in a conduction foam rubber.
b) Prior to soldering, the technician should use a shorting strap to discharge his static electricity.
c) The soldering iron tip to be grounded. d) MOSFETs should never be inserted into or removed from a circuit with
the power on.
e) The assembler should wear antistatic clothes and ground wrist beads.
f) All the instruments and metal benches used to test the MOS devices should be connected to ground.
g) Always avoid touching the device terminals and pick up the transistor by its casing.

32. What are the applications of MOSFET?

a) It can be used as input amplifiers in oscilloscope, electric voltmeters etc.
b) It is used in logic circuits.
c) It is used in computer memories.
d) It is used in phase shift oscillators.
e) It is used in FM and TV receivers.

33. Depletion MOSFET is commonly known as “Normally-ON” MOSFET why?

The depletion MOSFET can conduct even if the gate to source voltage (VGS) is zero. Because of this
reason depletion MOSFET is community known as “Normally-ON” MOSFET.

34. What is the difference between JFET and MOSFET? (May / Jun 2016)

S. No. JFET MOSFET

1 Reverse bias for gate Positive or negative gate voltage
2 Gate is formed as a diode Gate is formed as a capacitor
3 Operation only depletion mode Can be operated either in depletion mode or in enhancement mode.
4 High input impedance Very high input impedance due to capacitive effect.

UJT
35. Draw the structure of UJT. (Nov/Dec 2017)

B2 B2

Eta-point +
B2
RB2
Eta-point
RB2
p-type
E
E A A VBB
E +
RB1
n-type RB1
Ve Ie VBB

- -
B1 B1 B1
5
(a) (b) (c)
36. What is UJT?
Uni junction transistor is a three terminal semiconductor device consisting of only one PN junction. It differs from
ordinary PN diode in the sense that it has three terminals namely Emitter, Base 1 and Base 2.

37. Describe the construction of UJT?

UJT consists of lightly doped TV type is semiconductor bar with a heavily doped P type material.
N type bar is called base and P type region is called emitter. Hence PN junction is formed between emitter and
base region.
Since base is lightly doped the resistivity of the base material is very high.
The direction of arrowhead in the UJT symbol represents the conventional direction of current flow when UJT is in
conduction state.

38. State two applications of UJT. (Nov/Dec 2018)

1. UJT is used to trigger other devices like SCR.
2. Also used in sawtooth wave generators and some timing circuits.
3. It is used as relaxation oscillator to obtain short pulses for triggering of SCR.

39. What is intrinsic stand OFF ratio of UJT and its equivalent circuit? (May 2017)
The intrinsic stand OFF radio (r|) is defined as the ratio between the internal dynamic resistance (RBl) and
the inter base resistance (RBB)-
𝑹
η = 𝑹𝑩𝟏
𝑩𝟐
Where,
RBB = RB1 + RB2
RB1 – internal dynamic resistance
RB2 – inter base resistance

40. What are the different regions in characteristics of UJT?

• Cut off Region
• Negative Resistance Region
• Saturation Region

THYRISTOR
41. Describe the basic structure of SCR?
SCR consist of four semiconductor layers forming a PNPN structure. It has three PN junctions namely J1 , J2
anode (A), cathode ( K ) and the gate (G).

42. What are the different methods used to turn ON SCR?

1. Gate triggering
2. Forward break over voltage
3. Light triggering
4. Rate - effect (or) triggering

43. What is forward break over voltage? (Apr/May 2018)

SCR is forward bias with a small voltage, it is in 'OFF' and no current flows through the SCR. The
applied forward voltage is increased, a certain critical voltage called forward break over voltage ( V B 0 ) .

44. Define holding current? What is the latching current in SCR? (April / May 2019-R17)
Holding current is the current below which the SCR switches from the conduction state (ON state) to
the forward blocking state.
Latching Current is the minimum current required to trigger the device from its OFF state to ON state.
6
45. What is the forward blocking region?
This region corresponding to the OFF condition of the SCR when anode is positives.
46. What is the turn OFF mechanism used for SCR?
To turn OFF a SCR, the following methods are applied.
(i) Reversing polarity of anode-to-cathode voltage called as Gate turn OFF
switch (GTO).
(ii)The second method is anode current interruption. Changing anode current
by means of momentarily series or parallel switching arrangement.
(iii)Third method is forced commutation. In this, the current through SCR
is reduced below the holding current

47. Give the applications of SCR.

Main applications of an SCR are as a power control device. Common areas of applications include
(a). As over light detector (f). Battery charges
(b). Relay control (g). Heater controls
(c). Regulated power supplies (h). Phase controls
(d). Static switches (i). For speed control of DC shunts motor.
(e). Motor control

48. What are the advantages of SCR?

> SCR controls large current in the load by means of a small gate current.
> SCR size is very compact.
> Switching speed is high.

49. Show how an SCR can be triggered on by the application of a pulse to the gate terminal. (Nov / Dec
2015)
SCR is forward bias with a small voltage, it is in 'OFF' and no current flows through the SCR. The
applied forward voltage is increased, a certain critical voltage called forward break over voltage
( V B 0 ) . Th e fo r wa rd b r ea k o ve r vo lta g e i s red u c ed b y a p p l ica t io n o f g a t e p u ls es .

IGBT, DIAC & TRIAC

50. IGBT is a voltage controlled device. Why?

Because the controlling parameter is gate-emitter voltage.
51. Why IGBT is very popular nowadays? MAY/JUNE-2012
1. Lower gate requirements 2. Lower switching losses 3. Smaller snubbed circuit requirements

52. What is DIAC?

A DIAC is two terminal semiconductor device and three-layer bidirectional device, which can be
switched from of its OFF to ON state for either negative or positive polarity of applied voltage.

7
53. What are the applications of DIAC?
The DIAC is used as a triggering device; it is not a control device. It is used in.
• Temperature control
• Triggering of TRIAC
• Light diming circuits
• Motor speed control
54. What is TRIAC?
TRIAC is a three terminal semiconductor switching device which can conduct in either forward or
reverse direction. The TRIAC is the combination of two SCR's connected in parallel but in opposite
direction.

55. What are the applications of TRIAC?

▪ Heater control
▪ Phase control
▪ Light dimming control
▪ Static switch to turn A.C power ON and OFF.
▪ Speed control of motor.

PART-B
BJT-Structure, Operation & Characteristics
1. Explain about the transistor (BJT) operation.

Structure:

Symbol:

Two-diode transistor analogy

Applying external voltage to a transistor is called biasing. In order to operate transistor properly as an
amplifier, it is necessary to correctly bias the two PN junctions with external voltages. Depending upon
external bias voltage polarities used, the transistor works in one of the three regions.

1. Active region 2. Cut-off region 3. Saturation region

8
 S. No. Region Emitter Base Collector Base Operation of a transistor
1 Active Forward biased Reverse biased Acts as an amplifier
2 Cut off Reverse biased Reverse biased Acts as an open switch
3 Saturation Forward biased Forward biased Acts as a closed switch

To bias the transistor in its active region the emitter base junction is forward biased, while the collector-
base junction in reverse-biased as shown in Fig. The Fig. shows the circuit connections for active region
for both NPN and PNP transistors.

Operation of NPN transistor:

As shown in fig. the forward bias applied to the emitter base junction of an NPN transistor causes
a lot of electrons from the emitter region to cross over to the base region. As the base is lightly doped
with P-type impurity, the number of holes in the base region is very small and hence the number of
electrons that combine with holes in the P – type base region is also very small. Hence a few electrons
combine with holes to constitute a base current IB. The remaining electrons (more than 95%) crossover
into the collector region to constitute a collector current IC. Thus the base and collector current summed
up give the emitter current i.e. IE=-(IC+IB).

Fig. Current in NPN transistor

In the external circuit of the NPN bipolar junction transistor, the magnitudes of the emitter current IE, the
base current IB and the collector current IC are related by IE=IC+IB.

Operation of PNP transistor:

As shown in fig. the forward bias applied to the emitter – base junction of a PNP transistor causes
a lot of hoses from the emitter regions to cross over to the base region as the base is lightly doped with N-
type impurity. The number of electrons in the base regions is very small and hence the number of holes
combined with electrons in the N – type base region is also very small. Hence a few holes combined with
electrons to constitute a base current IB.

9
 Fig. Current in PNP transistor

The remaining holes (more than 95%) cross over into the collector region to constitute a collector
current IC. Thus, the collector and base current when summed up gives the emitter current.

i.e. IE= - (IC+IB).

In the external circuit of the PNP bipolar junction transistor, the magnitudes of the emitter current
IE, the base current IB and the collector current IC are related by

IE=IC+IB

The equation gives the fundamental relationship between the currents in a bipolar transistor
circuit. Also, this fundamental equation shows that there are current amplification factors  and  in
common base transistor configuration and common emitter transistor configuration respectively for the
static (d.c) currents, and for small changes in the currents.

Large – signal current gain (). The large signal current gain of a common base transistor is
defined as the ratio of the negative of the collector – current increment to the emitter – current change
from cut off (IE=0) to IE,i.e.

 =−
(Ic − ICBO )
IE − 0

where ICBO (or ICO) is the reverse saturation current flowing through the reverse biased collector –
base junction. i.e. the collector to base leakage current with emitter open. As the magnitude of ICBO is
negligible when compared to IE, the above expression can be written as

IC
=
IE

Since IC and IE are flowing in opposite directions,  is always positive. Typical value of  ranges
from 0.90 to 0.995. Also,  is not a constant but varies with emitter current IE, collector voltage VCB and
the temperature.

10
2. (a) Explain various characteristics of BJT in Common Base configuration with neat
diagram.

Common Base Configuration (CB configuration):

This configuration is also called the grounded base configuration. In this case the
input is connected between emitter and base while the output is taken across the collector and base. Thus
the base of the transistor is common to both input and output circuits and hence the name, common base
configuration. The common base circuit arrangement for NPN transistors is shown in Fig.

Current Amplification Factor (α):

The current amplification factor is defined as the ratio of changes in Collector current (∆IC) to the change
in emitter current (∆IE) when the collector to base voltage (VCB) is maintained at a constant value.
α=(∆IC)/ (∆IE) (at constant VCB)

The value of α is always less than unity. The practical value of transistors lie between 0.95 and 0.99.

Characteristics of Common Base Configuration:

The circuit arrangement for determining the characteristics of a common base NPN transistors is shown in
Fig.In this circuit, the collector to base voltage (VCB) can be
varied by adjusting the potentiometer R2. The emitter to base voltage (VEB) can be varied by adjusting the
potentiometer Rl. The DC voltmeters and DC milliammeters are connected in the emitter and collector
circuits to measure the voltages and currents.

a). Input Characteristics:

The curve plotted between the emitter current (IE) and the emitter to base voltage (VEB) at constant
collector to base voltage (VCB) are known as input characteristics of a transistor in common base
configuration.

11
 Input Resistance (Ri):

It is the ratio of change in emitter to base voltage (∆VEB) to the corresponding change in emitter
current (∆IE) for a constant collector to base voltage (VCB).

b). Output Characteristics:

The curve plotted between the collector current (IC) and the collector to base voltage
(VCB) at constant emitter current (IE) are known as output characteristics of a transistor is common base
configuration.

The output characteristics are as shown in Fig. and it can be divided into three
important regions namely (i) Saturation region (ii) Active region (iii) Cut-off region.

(i). Saturation Region:

In this region, collector to base voltage (VCB) is negative for a NPN transistor. A small change in
collector to base voltage (VCB) results in a large valve of collector current.

(ii). Active Region:

In this region the collector current (IC) is almost equal to the emitter current (IE). The
transistor is always operated in this region. In the active region, the curves are almost flat. A very
large change in VCB produces only a very small change in IC. It means that the circuit has very high
output resistance about 500 K Ω.

(iii). Cut-off Region:

It is the region along the X-axis as shown by shaded or dotted portion. This corresponds to the curve
marked IE=0. In the cut-off region both the junctions of a
Transistor are reverse biased. A small collector current flows even when the emitter
Current (IE) is equal to zero.
If the collector to base voltage (VCB) is increased beyond a certain large value, the
collector current (IC) increases rapidly due to avalanche breakdown and the transistor
action is lost. This region is called breakdown region.

12
(b) For a transistor connected in CE configuration, sketch the typical output and input
characteristics and explain the shape of characteristics.

Common Emitter Configuration (CE Configuration):

This configuration is also called the grounded emitter configuration. In this case the
input is connected between base and emitter, while the output is taken across the collector and emitter.
Thus emitter of the transistor is common to both input and output circuits and hence the name, common
emitter configuration. The common emitter arrangement for NPN transistor is as shown in Fig.

Base Current Amplification Factor (β):

The base current amplification factor is defined as the ratio of change in collector
current (∆IC) to the change in emitter current (∆IE) when the collector to emitter voltage(VCE) is
maintained at a constant value.

The value of β is always greater then unity. Practical value of β in commercial

transistors lie between 20 to 500.

Characteristics of common Emitter configuration:

The circuit arrangement for determining the characteristics of a common emitter NPN transistor is shown
inFig.In this circuit, the collector to emitter voltage (VEC) can be varied by adjusting the potentiometer R2.
The base to emitter voltage (VBE) can be varied by adjusting the potentiometer R1. The DC voltmeters and
milliammeters are connected in the base and collector circuits to measure the voltages and currents.

1. Input Characteristics:

The curve plotted between the base current (IB) and the base to emitter voltage (VBE) at constant
collector to emitter voltage (VCE) at constant collector to emitter voltage (VCE )are known as input
characteristics of a transistor in common emitter configuration.
13
Input Resistance (Ri): It is the ratio of change in base to emitter voltage (VBE) to the
Corresponding change in base current (∆IB) for a constant collector to emitter voltage
(vCE).

When the collector to emitter voltage (VCE) is increased, the value of base current (IB) decreased slightly
as shown in Fig.

2. Output Characteristics:

The curves plotter between the collector current (IC) and the collector to emitter
Voltage (VCE) at constant base current (IB) is known as output characteristic of a
transistor in common emitter configuration.
The output characteristic may be divided into three important regions namely
saturation region, active region, and cut-off region.

(i) Saturation Region:

In this region (shown by dotted area) a small change in collector to emitter voltage
(VCE) results in a large value of collector current.

(ii) Active Region:

It is the region between saturation and cut-off region. In this region the curves are almost flat. When the collector to
emitter voltage (VCE) is increased. Further, the collector current I. slightly increases. The slope of the curve is little
bit more than the output characteristics of common base configuration. Therefore, the output resistance (Ro) of this
configuration is less as compared to common base configuration.

(iii) Cut-off Region:

It is the region along the X-axis is shown by shaded area. This corresponds to the curve marked IB = 0. In the cut-
off region both the junctions of a transistor are reverse biased. A small collector current flows even when the base
current (IB) is equal to zero. It is the reverse leakage current (ICEo)that flows in the collector circuit.

If the collector to emitter voltage (VCE) is increased beyond a certain large collector current (IC) increases rapidly
due to avalanche breakdown and the action is lost. This region is called breakdown region.
14
(c) Explain various characteristics of BJT in Common Collector configuration with
neat diagram.
Common collector configuration (CC configuration):

This configuration is also called the grounded collector configuration' In this case the input is common
between base and Collector. While the output is taken across the emitter and collector. Thus the collector
of the transistor is common to both input and output circuits and hence the name common collector
configuration. The common collector circuit arrangement for NPN transistor as shown in Fig.

Current Amplification Factor (γ):

The current amplification is defined as the ratio of change in emitter current (∆IE) to
the change in base current (∆IB). It is generally denoted by γ.

The value of γ is nearly equal to β.

Characteristics of common Collector configuration:

The circuit arrangement for determining the characteristics of a common collector
NPN transistor is shown in Fig. In this circuit, the emitter to collector voltage (VEC)
can be varied by adjusting the potentiometer R2. The base to collector voltage (VBC) can be varied by
adjusting the potentiometer R1. The DC voltmeter and millimeters are connected in the base and emitter
circuits to measure the voltages and currents.

1. Input Characteristics:

The curves plotted between the base current (IB) and the base to collector voltage (VBC) at
constant emitter to collector voltage (VEC) are known as input characteristics of a transistor in
common collector configuration.

15
 2. Output Characteristics:

The curves plotted between the emitter current (IE) and the emitter to collector voltage (VEC) at
constant base current (IB) are known as output characteristics of a transistor is common collector
configuration.

3. Explain the emitter bias method used in transistor amplifier circuits. (Nov/Dec 2017)

Emitter Bias
This biasing network uses two supply voltages, VCC and VEE, which are
equal but opposite in polarity. Here VEE forward biases the base-emitter
junction through RE while VCC reverse biases the collector-base junction.
Moreover

In this kind of biasing, IC can be made independent of both β and VBE by choosing RE >> RB/β and VEE
>> VBE, respectively; which results in a stable operating point.

16
4. Explain the selection of Q point for transistor bias circuits and discuss the limitations on the output
voltage swing. (Nov / Dec 2015)

The dc load line for a transistor circuit is a straight line drawn on the transistor output characteristics.
For a common emitter CE circuit. The load line is a graph of collector current versus collector emitter voltage for a
given value of collector resistance and a given supply voltage. The load lines show all corresponding levels of Ic
and VCE that can exist in a particular circuit.

Consider the common emitter circuit in fig. Note that the polarities of the transistor terminal voltage are such that
the base emitter junction is forward biased and the collector base junction is reverse biased. These are the normal
bias polarities for the transistor junctions. The dc load line for the circuits in fig drawn on the device common
emitter characteristics in fig.

VCE = (Supply voltage) – (Voltage drop across RC)

VCE = VCC - ICRC

If the base emitter voltage is zero, the transistor is not conducting and IC = 0. Substituting the VCC and RC values
from fig into equal 5-1

VCE = 20V – (0*10k ohms) =20V

Plot point A on the common emitter characteristics in fig. 5-2 at Ic = 0 and VCE = 20V. This is one point on the dc
load line.

Now assume a collector current of 2mA, and calculate the corresponding collector emitter voltage level.

VCE = 20V-(2mA*10k ohms) =0V

Plot point B fig 5-2 at VCE = 0 and IC = 2mA. The straight line drawn though point A and point B is the dc load
line for RC = 10kohms and VCC = 20V. If either of these two quantities is changed, a new load line must be drawn.

17
 As already stated the dc load line represents all corresponding IC and VCE levels that can exist in the
circuit as represented by Eq. 5-1 for example a point plotted at VCE = 16V and IC = 1.5mA on fig 5-2 does
not appear on the load line. This combination of voltage and current cannot exist in this particular circuit.
Knowing any one of IB, IC, or VCE, it is easy to determine the other two from a dc load line drawn on the
device characteristics. It is not always necessary to have the device characteristics in order to draw the dc
load line. A simple graph of IC versus VCE can be used as demonstrated in example 5-1.

Limitation on the output voltage swing:

The maximum possible transistor collector emitter voltage swing for a given circuit can be
determined without using the transistor characteristics. For convenience, it may be assumed that Ic can be
driven to zero at one extreme and to Vcc / Rc at the other extreme, [see fig]. This changes the collector
emitter voltage from VCE = Vcc to VCE = 0, as illustrated in fig. thus with the Q point at the center of the
load line, the maximum possible collector voltage swing is seen to be approximately ∓𝑉𝑐𝑐 /2.

JFET- Structure, Operation & Characteristics

5. (a) Explain construction and operation of Junction Field Effect Transistor (JFET)? (NOV/DEC
2012) (May/June-2012)
(b) Explain drain and transfer characteristics of JFET? (May 2017)

(a) Construction and operation:

The basic construction of an n-channel JFET is shown in fig. It consists of an n-type silicon bar
referred as the channel. Two small pieces of p-type material are attached to its sides forming pn junctions.
If the bar is of n-type the JFET is called as on n-channel JFET, and if the bar is of p-type it is called a p-
type channel JFET fig shows schematic diagram of both types of FET’s with their symbols.

N-channel JFET Symbol

The channel ends are designated as source(S) and drain (D). The source S is the terminal through
which the majority carriers enters the bar and drain D is the terminal through which the majority carriers
leave the bar. The two p-regions, which are formed by alloying or by diffusion, are connected together
and their terminal is called gate. When no bias applied to JFET, depletion regions are formed at two pn
junctions as shown in fig. Recall that depletion region is a region depleted of charge carriers and therefore
behaves insulators

18
 P-channel JFET

Operation of N-channel JFET

When Vds is of some fixed positive value and reverse bias on Vgs increasing.

Operation of N-channel JFET

Let us assume that the gate is not biased and a fixed positive voltage is applied between the drain
and source terminals as shown in fig. Due to this applied voltage will move through the n-type
channel from source to drain. When the gate is negative biased with respect to source, the pn
junction are reverse biased and the depletion region are formed. Since the channel is lightly doped
compared to heavily doped p-region, the depletion region penetrates deeply into the channel. As a
result, the effective channel resistance significantly and reduces the drain current ID. If the reverse
biased on the gate is increased further the depletion will cover the entire width of the channel and
ID is cut off completely fig.

2.VGS=0, VDS is varied

First assume that the gate source voltage (VGS) is set to the zero. When the drain source voltage
VDS is also zero, the current flowing through FET is also zero that is ID=0.The instant the voltage
VDS is applied, electrons starts flowing from source to drain terminals establishing the current ID
under this condition the channel between drain and source act as a resistance.

19
(b) Characteristics of JFET:-
The circuit diagram to obtain the characteristics of JFET is shown in fig.

The characteristics that we consider are

i) Drain characteristics ii) Transfer characteristics
In drain characteristics the relation between Id and VDS for different values of VGS is plotted. In transfer
characteristics the relation between ID and VDGS for constant is plotted.

(i) Drain characteristics with VGS=0 (May 2017)

The drain characteristics for VGS=0 is shown in fig. To plot this characteristic the gate to source
voltage is kept at zero and VDS is varied from zero. When VDS is zero the drain current ID is also zero.
When VDS is increased the drain, current starts flowing through the channel and FET behaves like a
resistor till point A. That is for low values of VDS, current varies directly with voltage following ohm’s
law. The portion of characteristics where the FET behaves like a resistor is known as ohms region. The
FET can be used as a voltage variable resistor in this region if we increase VDS, a stage is reached at
which pinch off occurs and the drain current reaches a saturation level. The drain to source voltage at
which pinch off occurs is known as pinch off voltage VP, and corresponding ID is known as IDSS. The
point B at which pinch-off occurs is shown in fig. Even if we increase VDS above VP the drain current VDS
above Vp the drain current does not increase. The region where the drain current is constant inspite of the
variation in VDS is known as pinch-off region. If we increase VDS for there a stage is reached at which the
gate channel junction FET breakdown and increase rapidly. This region in the characteristics is known as
breakdown region. When a bias (-1V) is applied between gate source the pinch off occurs at less drain
current less than IDSS. The drain characteristics for different values of VGS shown fig.

Characteristics of JFET for VGS=0

20
 Characteristics of JFET for different values of VGS

(ii) Transfer characteristics

It is a plot of drain current Id versus VGS constant values. To plot the characteristics VDS is kept
constant and VGS is varied. When VGS= the current flowing the FET is Equal to IDSS and when VGS=VGS
(off), the drain current is zero.
Shockley’s equation:-
The relation between VGS and ID can be represented by Shockley’s equation
ID =IDSS(1-VGS/Vp)2------------------------------3.1
Using this mathematically expression, we can develop the plot of ID versus VGS for any JFET,
provide the two parameters IDSS and Vp are known.

Transfer characteristics of JFET.

MOSFET- Structure, Operation & Characteristics

6. With neat diagram explain the construction & working of depletion MOSFET and enhancement
MOSFET with its necessary characteristics curve. (Nov/Dec 2018 R-13) (May/June 2016) (Apr/May 2018)
OR
Brief about the construction and operation of n-channel depletion type MOSFET with a neat
diagram. Enumerate the characteristics of depletion type MOSFET with a suitable graph.
(April/May 2019-R17)

Depletion MOSFET:
• The construction of an N-channel depletion MOSFET is shown in fig. If consists of a lightly
doped p-type substrate in which two highly doped n-regions are diffused. The two heavily doped n-
21
 regions act as the source and drain. A lightly doped n-type channel is introduced between the two
heavily doped source and drain. A thin layer of (1µm thick) silicon dioxide is coated on the surface.
Holes are cut in the oxide layer to make contact with n-regions due to sio2 layer the gate is completely
insulated from the channel. This permits operation with gate source or gate channel voltages above and
below zero. In addition the insulated layer of sio2 accounts for very high input impedance of MOSFET.
In some MOSFETS the p-type substrate is internally connected to source, whereas in many discrete
devices an additional terminal is provided for substrate labeled SS.

SS substrate
Basic operation:
In fig a voltage VDS is applied between the drain and source terminals and the gate to source
voltage is set to zer. As a result, current is established from drain to source (conventional direction)
similar to JFET like in JFET, the satuarated drain current IDSS flow during pinch-off and it is labeled as
IDSS.

If a negative voltage is applied to gate with repeat to source. These holes recombine with electrons
and reduce the number of free electrons in the n-channel available for conduction. The more negative the
bias, lesser the number of free electrons in the channel. Since the negative voltage on the gate deplete
channel, the device is referred to as depletion MOSFET. The depletion mode of operation is similar to
JFET operation. When sufficient negative voltage is applied to gate the channel may be completely cut
off and the corresponding VGS is called (VGS (OFF)).
If a positive voltage is applied to gate with respect to source then the electrons are induced in the
channel. The induced electrons constitute additional current from source to drain. If we increase V GS
more in positive direction more number of electrons is induced and hence the drain current increases.

22
That is, the application of a positive gate –to –source voltage has enhanced the number of charge carriers
compared to that of when VGS=0v. For this reason the mode in which the MOSFET. Operates for positive
values of gate-to-source voltage is known as enhancement mode.

It is a plot of drain current versus drain source voltage for various value of gate-source voltage. The drain
characteristics of depletion MOSFET is shown ii fig. Note that for negative of VGS the characteristics of
depletion MOSFET is similar to those N-channel JFET. If the gate is made positive additional carrier are
introduced in the channel and the channel conductivity increases. Therefore the depletion MOSFET
consists of two regions of operation
.
The transfer characteristics of deletion MOSFET is shown in fig. The general shape of the transfer
characteristics is similar to those for the JFET. However the deletion MOSFET can be operated with
VGS>0. As a result IDSS is not maximum drain current as it is for JFET. The equation fior transfer
characteristics curve of depletion MOSFET is same as that of JFET.

The three circuit symbols for n-channel MOSFET and p-channel MOSFET are shown in fig.

Symbol of N-channel and P-channel MOSFET’S

23
N-channel enhancement MOSFET (May/June-2013), (May/June2016), (Nov/Dec2015) (May
2017) (Apr/May 2018)
• The construction of n-channel enhancement MOSFET is shown in fig. like depletion MOSFET it also
consists of a p-type substrate and two heavily doped n-regions that act as source and drain. The sio2 layer is present
to isolate the gate from the region between the drain and source. The source and drain terminals are connected
through metallic contacts to n-doped regions. But the enhancement MOSFET does not contain diffused channel
MOSFET does not contain diffused channel between the source and drain

When the drain is made positive with repeat to source and no potential is applied to gate due to absence of the
channel, a small drain current (ie., a reverse leakage current) flows. The we apply a positive voltage to that gate
with respect to source and substrate, negative charge carriers are induced in the substrate the negative charge
carriers which are minority carriers in the p-type substrate form an “inversion layer”. As the gate potential is
increased more and more negative charge carriers are induced. There negative carriers that are accumulated
between source and drain current flows from source to drain through the induced channel. The magnetized of the
drain current depends on the gate potential. Since the conduction of the channel is enhanced by the positive bias
voltage on the gate the device known as enhancement MOSFET.

Drain characteristics :
The drain characteristics of enhancement MOSFET is shown in fig.
The current IDSS for VGS=0 is very small of the order of nano amperes shown in fig. Note that
the drain current increases with positive increases with positive increase in gate source have voltage.

24
 Transfer characteristics:

The n-channel enhancement MOSFET requires a positive gate to source voltage for its operation fig shows
the general transfer characteristics of an n-channel MOSFET. Since the drain current is zero for VGS=0, the IDSS
is zero for this device. As VGS is made positive the current ID increases slowly at first and then more rapidly with
an increase in VGS. The gate source voltage at which there is significant increase in drain current is called the
threshold voltage and is referred to as VT or VGS the equation for the transfer characteristics of enhancement
MOSFET differs as the curve states at VGS(th) rather than at VGS. The equation for transfer characteristics is
𝐼𝐷 =K(𝑉𝐺𝑆− 𝑉𝐺𝑆(𝑡ℎ)) 2

UJT (UNIJUNCTION FIELD EFFECT TRANSISTOR)

7. (a) Explain the construction operation and characteristics of UJT? (May/June2016), (Nov/Dec2015)
(Nov/Dec 2018)
(b) Describe the operation of UJT as a relaxation oscillator and derive its frequency of oscillation?
(Nov/Dec 2016)

(A) UNI-JUNCTION TRANSISTOR (UJT)

Construction: B2 B2

Eta-point +
B2
RB2
Eta-point
RB2
p-type
E
E A A VBB
E +
RB1
n-type RB1
Ve Ie VBB

- -
B1 B1 B1
(a) (b) (c)

Fig.: (a) Basic structure of UJT (b) Symbolic representation (c) Equivalent circuit

UJT is an n-type silicon bar in which p-type emitter is embedded. It has three terminals base1, base2 and
emitter ‘E’. Between B1 and B2 UJT behaves like ordinary resistor and the internal resistances are given as RB1
and RB 2 with emitter open RB B = RB1 + RB 2 . Usually the p-region is heavily doped and n-region is lightly doped.
The equivalent circuit of UJT is as shown. When VBB is applied across B1 and B2 , we find that potential at A is
VBB RB1  RB1 
VAB1 = = VBB  = 
RB1 + RB 2  RB1 + RB 2 

 is intrinsic standoff ratio of UJT and ranges between 0.51 and 0.82. Resistor RB 2 is between 5 to
10K.

25
 OPERATION

When voltage VBB is applied between emitter ‘E’ with base 1 B1 as reference and the emitter voltage VE
is less than (VD + VBE ) the UJT does not conduct. (VD + VBB ) is designated as VP which is the value of
voltage required to turn on the UJT. Once VE is equal to VP  VBE + VD , then UJT is forward biased and
it conducts.

The peak point is the point at which peak current I P flows and the peak voltage VP is across the UJT.
After peak point the current increases but voltage across device drops, this is due to the fact that emitter
starts to inject holes into the lower doped n-region. Since p-region is heavily doped compared to n-region.
Also holes have a longer life time, therefore number of carriers in the base region increases rapidly. Thus
potential at ‘A’ falls but current I E increases rapidly. RB1 Acts as a decreasing resistance.

The negative resistance region of UJT is between peak point and valley point. After valley point, the
device acts as a normal diode since the base region is saturated and RB1 does not decrease again.
Negative Resistance
Region
Ve
Cutoff Saturation
region region
VBB
R load line
Vp
Peak Point

Valley Point

Vv

0 Ip Iv Ie

Fig.: V-I Characteristics of UJT

(B) Operation of UJT as a relaxation oscillator and its derivation- frequency of oscillation. (Nov 2016)

UJT as a relaxation oscillator consists of UJT and a capacitor CE which is charged through RE as the
supply voltage VBB is switched ON. The voltage across the capacitor increases exponentially and when
the capacitor voltage reaches the peak point voltage Vp, the UJT starts conducting and the capacitor
voltage is discharged rapidly through EB1 and R1.After the peak point voltage of UJT is reached, it
provides negative resistance to the discharge path which is useful in working of the relaxation oscillator.
As the capacitor voltage reaches zero the device then cuts off and capacitor CE starts to charge again. This
cycle is repeated continuously generating a saw tooth waveform across CE.

The inclusion of external resistors R2 and R1 in series with B2 and B1 provides spike waveform. When the
UJT fires, the sudden surge of current through B1 causes drop across R1,which provides positive spikes.
At the time of firing fall of VEB1 causes I2 to increases rapidly which generates negative going spikes
across R2.

By changing the value of RE and CE the frequency of oscillation changes.

26
Frequency of oscillation:
Voltage across the capacitance prior to breakdown is given by
Vc=VBB(1- e−t/RE CE )
R E CE - Charging time constant
Discharge of capacitor occurs when VC is equal to the peak point voltage Vp,
Vp= 𝜂VBB=VBB(1- e−t/RECE )
Where 𝜂 =(1- e−t/RE CE )
e−t/RE CE =1- 𝜂
Taking Log on both side
t 1
= log e
R E CE (1 − 𝜂)
1
t = R E CE ln
(1 − 𝜂)
1
f = 1/t = 1
RE CE ln(1− )
𝜂

27
 THYRISTOR (SCR)
8. DRAW AND EXPLAIN THE V-I CHARACTERISTICS OF THYRISTOR (SCR) (or) DISCUSS THE
DIFFERENT MODES OF OPERATION OF THYRISTOR WITH THE HELP OF ITS STATIC V-I
CHARACTERISTICS. (Nov/Dec 2017) (Apr/May 2018) (OR)
Outline the structure of SCR and explain its operation. Also, illustrate its V-I characteristics.
(Apr/May 2019-R17)

RL

VAA K
VGG

Circuit diagram

Fig: V-I Characteristics of SCR

A typical V-I characteristics of a thyristor is shown above. In the reverse direction the thyristor appears similar to a
reverse biased diode which conducts very little current until avalanche breakdown occurs. In the forward direction
the thyristor has two stable states or modes of operation that are connected together by an unstable mode that
appears as a negative resistance on the V-I characteristics. The low current high voltage region is the forward
blocking state or the off state and the low voltage high current mode is the on state. For the forward blocking state
the quantity of interest is the forward blocking voltage VBO which is defined for zero gate current. If a positive
gate current is applied to a thyristor then the transition or break over to the on state will occur at smaller values of
anode to cathode voltage as shown. Although not indicated the gate current does not have to be a dc current but
instead can be a pulse of current having some minimum time duration. This ability to switch the thyristor by means
of a current pulse is the reason for wide spread applications of the device.

However once the thyristor is in the on state the gate cannot be used to turn the device off. The only way to turn off
the thyristor is for the external circuit to force the current through the device to be less than the holding current for
a minimum specified time period.

HOLDING CURRENT I H

After an SCR has been switched to the on state a certain minimum value of anode current is required to maintain
the thyristor in this low impedance state. If the anode current is reduced below the critical holding current value,
the thyristor cannot maintain the current through it and reverts to its off state usually I  is associated with turn off
the device.

LATCHING CURRENT I L

After the SCR has switched on, there is a minimum current required to sustain conduction. This current is called
the latching current. I L associated with turn on and is usually greater than holding current.
28
 Fig.: Effects on gate current on forward blocking voltage

9. Sketch the four layer construction of an SCR and the two transistor equivalent circuit explains the
device operation. (Non / Dec 2016)(May 2017)
A thyristor is the most important type of power semiconductor devices. They are extensively used in
power electronic circuits. They are operated as bi-stable switches from non-conducting to conducting
state.
A thyristor is a four layer, semiconductor of p-n-p-n structure with three p-n junctions. It has three
terminals, the anode, cathode and the gate.
The word thyristor is coined from thyratron and transistor. It was invented in the year 1957 at Bell Labs.
The Different types of Thyristors are

• Silicon Controlled Rectifier (SCR).

• TRIAC
• DIAC
• Gate Turn Off Thyristor (GTO)

SILICON CONTROLLED RECTIFIER (SCR)

The SCR is a four layer three terminal device with junctions J1 , J 2 , J 3 as shown. The construction of SCR
shows that the gate terminal is kept nearer the cathode. The approximate thickness of each layer and
doping densities are as indicated in the figure. In terms of their lateral dimensions Thyristors are the
largest semiconductor devices made. A complete silicon wafer as large as ten centimeter in diameter may
be used to make a single high power thyristor.

Two transistor model of SCR

29
OPERATION

When the anode is made positive with respect the cathode junctions 𝐽1 & 𝐽3 are forward biased and
junction J 2 is reverse biased. With anode to cathode voltage VAK being small, only leakage current flows
through the device. The SCR is then said to be in the forward blocking state. If VAK is further increased to
a large value, the reverse biased junction J 2 will breakdown due to avalanche effect resulting in a large
current through the device. The voltage at which this phenomenon occurs is called the forward
breakdown voltage VBO . Since the other junctions 𝐽1 & 𝐽3 are already forward biased, there will be free
movement of carriers across all three junctions resulting in a large forward anode current. Once the SCR
is switched on, the voltage drop across it is very small, typically 1 to 1.5V. The anode current is limited
only by the external impedance present in the circuit.

Fig.: Simplified model of a thyristor

Although an SCR can be turned on by increasing the forward voltage beyond VBO , in practice, the
forward voltage is maintained well below VBO and the SCR is turned on by applying a positive voltage
between gate and cathode. With the application of positive gate voltage, the leakage current through the
junction J 2 is increased. This is because the resulting gate current consists mainly of electron flow from
cathode to gate. Since the bottom end layer is heavily doped as compared to the p-layer, due to the
applied voltage, some of these electrons reach junction J 2 and add to the minority carrier concentration
in the p-layer. This raises the reverse leakage current and results in breakdown of junction J 2 even
though the applied forward voltage is less than the breakdown voltage VBO . With increase in gate current
breakdown occurs earlier.

30
 DIAC

10. Explain in detail about DIAC and its characteristics?

• The DIAC can be turned ON only when the applied voltage across it is main terminal reaches the
break - over voltage.
• The M.T.2 is positive with respect to M.T.1, the DIAC passes current through the DIAC
P 1 N 1 P 2 N 2 from M.T.2 to
• M.T.1 as shown in Fig. 5.12 (a). The DIAC turn 'ON' the applied voltage makes M.T.2 negative
with respect to the M.T.1, the DIAC current through the diode
• When the current drops below the holding value. It is used as a triggering device.

Characteristics of a DIAC
The DIAC is operated with M.T.2 positive with respect to M.T.1, the V I characteristics obtained is
as shown in Fig. 5.13 by the curve marked OAB. Similarly the DIAC is operated with its M.T.2
negative with respect to M.T.I, the V-l characteristics obtained as shown in Fig. 5.13 by the curve
marked OCD.
Applications
The DIAC is used as a triggering device; it is not a control device. It is used in,
• Temperature control
• Triggering of TRIAC
• Light diming circuits
• Motor speed control

31
 TRIAC
11. EXPLAIN THE CONSTRUCTION, OPERATION & STATIC CHARACTERISTICS OF TRIAC
A triac is a three terminal bi-directional switching thyristor device. It can conduct in both directions when it is
triggered into the conduction state. The triac is equivalent to two SCRs connected in anti-parallel with a common
gate. Figure below shows the triac structure. It consists of three terminals viz., MT2 , MT1 and gate G.
MT1

G N2
MT2
P2
N3
P2
N1

N1
P1 G MT1

P1
N4

MT2

Fig. TRIAC Structure Fig. TRIAC Symbol

The gate terminal G is near the MT1 terminal. Figure above shows the triac symbol. MT1 is the reference
terminal to obtain the characteristics of the triac. A triac can be operated in four different modes depending upon
the polarity of the voltage on the terminal MT2 with respect to MT1 and based on the gate current polarity.

The characteristics of a triac are similar to that of an SCR, both in blocking and conducting states. A SCR can
conduct in only one direction whereas triac can conduct in both directions.

MODE 1: MT2 positive, Positive gate current ( I + mode of operation)

When MT2 and gate current are positive with respect to MT1, the gate current flows through P2-N2 junction as
shown in figure below. The junction P1-N1 and P2-N2 are forward biased but junction N1-P2 is reverse biased.
When sufficient number of charge carriers is injected in P2 layer by the gate current the junction N1-P2 breakdown
and triac starts conducting through P1N1P2N2 layers. Once triac starts conducting the current increases and it’s V-I
characteristics is similar to that of thyristor. Triac in this mode operates in the first-quadrant.
MT2 (+)

P1

N1
P2
Ig
N2

MT1 (−)
G
V
(+)
Ig

32
MODE 2: MT2 positive, Negative gate current ( I − mode of operation)

MT2 (+)

P1
Initial Final
N1
conduction conduction
P2
N3 N2

MT1 (−)
G
V

Ig

When MT2 is positive and gate G is negative with respect to MT1 the gate current flows through P2-N3 junction as
shown in figure above. The junction P1-N1 and P2-N3 are forward biased but junction N1-P2 is reverse biased.
Hence, the triac initially starts conducting through P1N1P2N3 layers. As a result the potential of layer between P2-
N3 rises towards the potential of MT2. Thus, a potential gradient exists across the layer P2 with left hand region at
a higher potential than the right hand region. This results in a current flow in P 2 layer from left to right, forward
biasing the P2N2 junction. Now the right hand portion P1-N1 - P2-N2 starts conducting. The device operates in
first quadrant. When compared to Mode 1, triac with MT2 positive and negative gate current is less sensitive and
therefore requires higher gate current for triggering.

MODE 3: MT2 negative, Positive gate current ( III + mode of operation)

When MT2 is negative and gate is positive with respect to MT 1 junction P2N2 is forward biased and junction P1-
N1 is reverse biased. N2 layer injects electrons into P2 layer as shown by arrows in figure below. This causes an
increase in current flow through junction P2-N1. Resulting in breakdown of reverse biased junction N1-P1. Now
the device conducts through layers P2N1P1N4 and the current starts increasing, which is limited by an external
load.

MT 2 (−)

N4

P1
N1

P2
N2

G MT1 (+)
(+)

Ig

The device operates in third quadrant in this mode. Triac in this mode is less sensitive and requires higher gate
current for triggering.

33
MODE 4: MT2 negative, Negative gate current ( III − mode of operation)

MT 2 (−)

N4

P1
N1

P2
N3

G MT1 (+)
(+)

Ig

In this mode both MT2 and gate G are negative with respect to MT1, the gate current flows through P2N3 junction
as shown in figure above. Layer N3 injects electrons as shown by arrows into P2 layer. These results in increase in
current flow across P1N1 and the device will turn ON due to increased current in layer N1. The current flows
through layers P2N1P1N4. Triac is more sensitive in this mode compared to turn ON with positive gate current.
(Mode 3).

Triac sensitivity is greatest in the first quadrant when turned ON with positive gate current and also in third
quadrant when turned ON with negative gate current. When MT2 is positive with respect to MT1 it is

recommended to turn on the triac by a positive gate current. When MT2 is negative with respect to MT1 it is
recommended to turn on the triac by negative gate current. Therefore Mode 1 and Mode 4 are the preferred modes
of operation of a triac ( I + mode and III − mode of operation are normally used).

TRIAC CHARACTERISTICS
Figure below shows the circuit to obtain the characteristics of a triac. To obtain the characteristics in the third
quadrant the supply to gate and between MT2 and MT1 are reversed.

RL I
- +
A
MT2

Rg + +
+ -G
A MT1 V Vs
-
+ -
Vgg
-

Figure below shows the V-I Characteristics of a triac. Triac is a bidirectional switching
device. Hence its characteristics are identical in the first and third quadrant. When gate
current is increased the break over voltage decreases.

34
 VB01, VB01
MT2(+) - Breakover voltages
G(+) Ig2 > Ig21
 Ig2
I Ig1
VB02
V
→V VB01

MT2(−)
G(−)

Fig.: Triac Characteristic

Triac is widely used to control the speed of single-phase induction motors. It is also used in domestic lamp
dimmers and heat control circuits, and full wave AC voltage controllers.

IGBT-Structure, Operation & Characteristics

12. EXPLAIN THE CONSTRUCTION, OPERATION & STATIC CHARACTERISTICS OF INSULATED

GATE BIPOLAR TRANSISTOR (IGBT). (NOV/DEC-2012) (May/June2016) (May 2017) (Nov/Dec 2018 R-13)

IGBT is a voltage-controlled device. It has high input impedance like a MOSFET and low on-state conduction
losses like a BJT.

Figure below shows the basic silicon cross-section of an IGBT. Its construction is same as power MOSFET
except that n+ layer at the drain in a power MOSFET is replaced by P+ substrate called collector.
Collector

+ C
p
+
n Bufferlayer
−
n epi G
p
+ +
n n E
Gate Gate

Emitter

Structure Symbol
Fig.: Insulated Gate Bipolar Transistor
IGBT has three terminals gate (G), collector (C) and emitter (E). With collector and gate voltage positive with
respect to emitter the device is in forward blocking mode. When gate to emitter voltage becomes greater than the
threshold voltage of IGBT, a n-channel is formed in the P-region. Now device is in forward conducting state. In
this state p+ substrate injects holes into the epitaxial n − layer. Increase in collector to emitter voltage will result in
increase of injected hole concentration and finally a forward current is established.

35
CHARACTERISTIC OF IGBT
Figure below shows circuit diagram to obtain the characteristic of an IGBT. An output characteristic is a plot
of collector current IC versus collector to emitter voltage VCE for given values of gate to emitter voltage VGE .

IC
RC

RS G VCC
VCE

VG RGE VGE
E

Fig.: Circuit Diagram to Obtain Characteristics

IC
VGE4
VGE3 VGE4>VGE3>VGE2>VGE1
VGE2
VGE1

VCE

Fig. Output Characteristics

A plot of collector current IC versus gate-emitter voltage VGE for a given value of VCE gives the transfer
characteristic. Figure below shows the transfer characteristic.

Note

Controlling parameter is the gate-emitter voltage VGE in IGBT. If VGE is less than the threshold voltage VT then

IGBT is in OFF state. If VGE is greater than the threshold voltage VT then the IGBT is in ON state.

IGBTs are used in medium power applications such as ac and dc motor drives, power supplies and solid state
relays.
IC

VGE
VT

Fig. Transfer Characteristic

36
Solved Problems:
1. Design a voltage divider bias circuit for transistor to establish the quiescent point VCE=12v, Ic =
1.5mA, Stability factor S < 3, 𝜷 = 𝟓𝟎, 𝑽𝑩𝑬 = 𝟎. 𝟕𝑽, 𝑽𝑪𝑪 = 𝟐𝟐. 𝟓 𝑽 𝒂𝒏𝒅 𝑹𝒄 = 𝟓. 𝟔 𝑲Ω.
(May 2017) (Nov/Dec 2017)

𝛽 = 50, 𝑉𝐵𝐸 = 0.7 𝑉, 𝑉𝐶𝐶 = 22.5 𝑉, 𝑅𝐶 = 5.6 𝑘𝛺, 𝑉𝐶𝐸 = 12 𝑉, 𝐼𝐶 = 1.5 𝑚𝐴, 𝑆≤3
𝐸𝑚𝑖𝑡𝑡𝑒𝑟 𝑅𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒 (𝑅𝐸 )

𝑉𝐶𝐸 = 𝑉𝐶𝐶 − 𝐼𝐶 (𝑅𝐶 + 𝑅𝐸 )

12 = 22.5 − (1.5 × 10−3 ) (5.6 × 103 + 𝑅𝐸 ) = 14.1 − 1.5 × 10−3 𝑅𝐸

𝑅𝐸 = 1.4 × 103 𝛺 = 1.4𝑘 𝛺

𝑅𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒𝑠 𝑅1 𝑎𝑛𝑑 𝑅2
Stability factor (s)
𝛽+1 50 + 1 51
3= = =
𝑅 1.4 × 103 70 × 103
1 + 𝛽 (𝑅 +𝐸 𝑅 ) 1 + 50 × 1 +
𝑡ℎ 𝐸 𝑅𝑡ℎ + 1.4 × 103 𝑅𝑡ℎ + 1.4 × 103
(𝑅𝑡ℎ + 1.4 × 103 ) + 70 × 103
3[ ] = 51
𝑅𝑡ℎ + 1.4 × 103

3[(𝑅𝑡ℎ + 1.4 × 103 )] + (70 × 103 ) = 51 (𝑅𝑡ℎ + 1.4 × 103 )

48[𝑅𝑡ℎ + (1.4 × 103 )] = 210 × 103

(210 × 103 )
3
𝑅𝑡ℎ + 1.4 × 10 = = 4375
48
𝑅𝑡ℎ = 4375 − 1.4 × 103 ; 𝑅𝑡ℎ = 2975 𝛺; 𝑅𝑡ℎ = 2.98 𝑘𝛺
For good voltage divider the value of resistor

𝑅2 = 0.1𝛽. 𝑅𝐸 = 0.1 × 50 × (1.4 × 103 ) = 7 × 103 𝛺 = 7𝑘𝛺

Thevenin’s Resistance (𝑅𝑡ℎ )

𝑅1 . 𝑅2 7𝑅1
2.98 = 𝑅1 ⃦𝑅2 = =
𝑅1 + 𝑅2 𝑅1 + 7
2.98(𝑅1 + 7) = 7𝑅1 ; 4.02𝑅1 = 20.86
20.86
𝑅1 = = 5.2 𝑘𝛺
4.02
37
2. For an n channel silicon FET with a = 3*10-4 cm and ND = 1015 electronics/cm3 find (a) the pinch off
voltage and (b) the channel half width for VGS = ½ VP and ID = 0. (May / Jun 2016)

Solution:

The relative dielectric constant of silicon is given in table 5-1 as 12, and hence 𝜖 = 12𝜖0 . Using the value
of 𝑒 𝑎𝑛𝑑 𝜖0 from appendixes A and B, we have from Eq expressed in mks units,

1.60 × 10−19 × 1021 × (3 × 10−6 )2

𝑉𝑃 = = 6.8𝑉
2 × 12 × (36𝜋 × 109 )−1

b. Solution Eq for b, we obtain for VGS = ½ VP

1
𝑉𝐺𝑆 1/2 1 2
𝑏 = 𝑎 [1 − ( ) ] = (3 × 1−4 ) [1 − ( ) ] = 0.87 × 10−4 𝑐𝑚
𝑉𝑃 2

Hence the channel width has been reduced to about one third its value for VGS = 0

3. Determine the base current for the CB transistor circuit if IC =80 mA and 𝜷 = 170. (Nov/Dev
2016)
Given
IC =80 mA
𝛽 = 170.
𝐼 80 ×10−3 𝐼𝑐 80 ×10−3
𝛽 = 𝑐= =170 ∴ 𝐼𝐵 = = =0.4706 mA
𝐼𝐵 𝐼𝐵 𝛽 170

4. Draw the two-transistor equivalent circuit of SCR? (May 2017)

5. A transistor has a typical 𝜷 = 100. If the collector current is 40 mA. What is the value of emitter
current? (May 2017)
𝐼
Given: IC =40 mA 𝛽 = 100 𝛽 = 𝐼𝑐
𝐵

𝐼 40 ×10−3
∴ 𝐼𝐵 = 𝛽𝑐 = =0.0004 A
100

IE = IB+IC IE = 0.0004 + 40 × 10−3= 0.0404 A

38
6. If the collector current is 2mA and the base current is 25µA, what is the emitter current?
Solution: IC = 2mA, IB=25µA,
IE = IB+IC =2mA+25µA ⸫IE =2.025mA

7. Calculate IC and IE for a transistor that has 𝜶 = 𝟎. 𝟗𝟗 𝒂𝒏𝒅 𝑰𝑩 = 𝟏𝟓𝟎𝝁𝑨. Determine the value of 𝜷𝒅𝒄 for the
transistor? (Nov / Dec 2015)
𝛼 0.99
Solution: 𝛽= = = 99
1−𝛼 1−099
𝐼𝐶
𝛽 = ; 𝐼𝐶 = 𝛽 × 𝐼𝐵 = 99 × 150 𝜇𝐴 = 14 𝑚𝐴
𝐼𝐵
𝐼𝐶 𝐼𝑐 14
𝛼= ; 𝐼𝐸 = = = 14.14𝑚𝐴
𝐼𝐸 𝛼 0.99

8. A germanium transistor is to be operated at zero signal IC = 1mA. If the collector supply voltage
VCC = 12V, what is the value of RB in the base resistor method? Assume β = 100. If another
transistor of same batch with β = 50 is used, what will be new value of zero signal I C for same
RB? Comment on the results. (Nov/Dec 2018-R17)(13 Marks)
Solution:

Comment: It is clear from the above example that with the change in transistor parameter β,
the zero-signal collector current has changed from 1mA to 0.5 mA. Therefore, the base resistor
method cannot provide stabilization.

9. The intrinsic stand-off ratio for a UJT is 0.6. If the inter base resistance is 10KΩ, what are the
value of RB1 and RB2? (Nov/Dec 2018-R17) (4 Marks)

39
10. When VGS of a JFET changes from -3.1 V to -3 V, the drain current changed from 1 mA to 1.3
mA. Find the value of transconductance. (Nov/Dec 2018-R17) (2 Marks)

Solution:
∆𝐼𝐷 (1.3−1)×10−3
𝑔𝑚 = = (3.1−3)
= 3 𝑚𝐴/𝑉
∆𝑉𝐺𝑆

11. Find the Q point of the transistor shown below. Also draw the DC load line. Give β = 100 and
VBE = 0.7V. (Nov/Dec 2018-R17) (15 Marks)

40
12. In a self-bias n-channel JFET, the operating point is to be set at ID = 1.5mA and VDS =10V. The
parameters are IDSS = 5mA and VGS (off) = -2V. Find the values of RS and RD if VDD = 20V.
(Nov/Dec 2018-R17) (9 Marks)

41
 EC8353-ELECTRONIC DEVICES AND CIRCUITS

UNIT-III AMPLIFIERS

PART-A
BJT Small Signal Model

1. Which is the BJT configuration is suitable for impedance matching application and why?
CC configuration is suitable for impedance matching application because of very high input impedance and low
output impedance.

2. Draw the hybrid small signal model of BJT device. (MAY/JUNE2016)

.
3. What are the tools used for small signal analysis of BJT?
• h – Parameter circuit model.
• z – Parameter circuit model.
• y – Parameter circuit model.
• Trans-conductance parameter circuit model.
• Physical model
• T-model

4. What are the steps used for small signal analysis of BJT?
• Draw the actual circuit diagram
• Replace coupling capacitors and emitter bypass capacitor by short circuit.
• Replace dc source by a short circuit. In other words, short VCC and ground lines.

5. State the phase relationship between input / output currents and phase relationship between the input /
output voltages of various transistors configurations. (Nov/Dec 2018)
For all the transistor configurations, input and output currents are in phase.
The input and output voltages of both CB and CC configuration are in phase. But in common-emitter amplifier
the input and output voltages are 1800 out of phase.

1
6. Draw the low frequency hybrid model of BJT in common emitter configuration.

Vb = hieIb + hreVc
Ic = hfeIb + hoeVc

CE, CB, CC Amplifiers-Gain and frequency response

7. Draw the hybrid small signal model of CB configuration? (Apr/May 2018)

8. Why emitter is always forward biased and collector is always reverse biased with respect to base?
To supply majority charge carrier to base and to remove the charge carriers away from the collector-base
junction.

9. Why CE configuration is most popular in amplifier circuits?

Because it’s current, voltage and power gain are quite high and the ratio of output impedance and input impedance
are quite moderate.

10. Give the voltage gain for CE configuration including source resistance.
Avs = Ai x RL / RS + Ri
= (- hfe / 1+ hoe RL) x RL / (RS + Ri)

11. Define the hie and hfe for a common emitter transistor configuration.
From the h – parameter equivalent circuit of the common emitter configuration.
Hie = Δ VBE / Δ IB | VCE constant
Hfe = Δ IC / Δ IB | VCE constant

12. Give the current gain expression for a common emitter transistor configuration.
Current gain for common emitter configuration:
Ai = - IC/ Ib = - hfe / 1 + hoe RL

2
 MOSFET small signal model

13. What is trans-conductance? Give its expression for MOSFET. (Nov/Dec 2017)
The trans-conductance is a ratio of output current to input voltage and hence it represents the gain of the
MOSFET.
Tran conductance expression for MOSFET
gm = 2 √ (KIDQ)
IDQ = K (VGSQ – VT)2

14. State the values of Cgd and Cgs in various operating regions of MOSFET.
Values of gate capacitances in Triode Region:
Cgs =Cgd = (WL Cox) ½
Values of gate capacitances in Saturation Region:
Cgs = (WL Cox) 2/3
Cgd=0
Values of gate capacitances in Cut - off Region:
Cgs =Cgd=0
Cgd = WL Cox
Cox – Gate Capacitance.

15. List various gate capacitances in MOSFET.

There are three gate capacitances in MOSFET:
Cgs – gate source capacitance,
Cgd – gate drain Capacitance, and
Cgb - gate body Capacitance.

CS and Source follower

16. Explain the effect of source resistor on CS MOSFET amplifier.

The source resistor is introduced to stabilize the Q – point against variations in the MOSFET parameters. In BJT circuits,
a source resistor reduces the small gain.

17. What is source follower? (Apr/May 2018)

A common-drain amplifier, also known as a source follower, is one of three basic single-stage field effect
transistor (FET) amplifier topologies, typically used as a voltage buffer.

Gain and frequency response

18. What is the significance of octaves and decades in frequency response?

• Octaves and Decades are the measure of change in frequency.
• Ten times change in frequency is called a Decade. On the other hand, an Octave corresponds to a
doubling of the frequency.
• For example, an increase in frequency from 100Hz to 200Hz is an octave. Likewise, a decrease in
frequency from 100Hz to 50Hz is also an octave.
• If the frequency is reduced to one hundredth of fc (from fc to 0.01fc), the drop in the voltage gain is
– 40 dB. In each decade the voltage gain drops by – 20 db.

3
19. Draw general frequency response curve (or) half-power frequencies of an amplifier.

• In the above diagram the frequency f2 lies in high frequency region, while the frequency f1 lies in low frequency region.
• These two frequencies are also referred to as half power half – power frequencies since gain or output voltage drops
to 70.7% of maximum value and this represents a power level of one half the power at the reference frequency in mid
– frequency region.

Additional Questions
20. What is the relation between α and β of the transistor?
𝛽
α=𝛽+1

21. Why must the base be narrow for the transistor action?
β is the ratio of IC to IB. IB becomes less if the base width is narrow. Higher value of β can be obtained with lower value
of base current.

22. What are emitter efficiency and base transport factor of a transistor?
The ratio of current of injected carriers at emitter junction to the total emitter current is called the emitter injection efficiency.
Transport Factor, β= IC / IB

23. What is the relation between the current of a transistor?

IE = IB + IC

24. How many h-parameters are there for a transistor?

❖ hr–reverse voltage gain
❖ ho–output admittance.
❖ hi,-input impedance
❖ hf-forward current gain

25. Why h-parameters are called hybrid parameters?

Because they have different units are mixed with other parameters.

26. What are the advantages of the h-parameters? (Apr/May 2011)

(1) Real numbers up to radio frequencies
(2) Easy to measure
(3) Determined from transistor static characteristics curve
(4) Convenient to use in the circuit analysis and design
(5) Easily convertible from one configuration to other

4
27. Draw the hybrid model for a transistor. (Nov/Dec 2012)

28. What are h-parameters? Define the four h-parameters.

One of a set of four transistor equivalent circuit parameters that conveniently specify transistor performance for
small voltage and current in a particular circuit also known as hybrid parameter.

Input resistance with output short – circuited, in Ω.

h11 = Vi / Ii | Vo = 0
Fraction of output voltage at input with input open circuited. This parameter is ratio of similar quantities,
hence unitless.
h12 = Vi / Vo | Ii = 0
Forward current transfer ratio or current gain with output short circuited.
h21 = Io / Ii | Vo = 0
This parameter is a ratio of similar quantities, hence unitless. Output admittance with input open – circuited,
in mhos.
h22 = Io / Vo| Ii = 0

29. State Miller’s theorem. (Nov/Dec 2016)

Miller’s theorem states that, if Z is the impedance connected between two nodes node 1 and node 2, it can be
replaced by two separate impedance Z1 and Z2; where Z1 is connected between node - 1 and ground, and node Z2
is connected between node -2 and ground.
The Vi and Vo are the voltages at the node – 1 and node – 2 respectively, The values of Z1 an d Z2 can
be derived from the ratio of Vo and Vi, denoted as K. Thus it is not necessary to know the values of Vi and Vo
to calculate the values of Z1 and Z2
The values of impedance Z1 and Z2
Z1 = Z / (1 - K); Z2 = Z x K / (K – 1)

30. What do you mean by faithful amplification?

During the process of raising the strength of the input signal if the shape of the output voltage is exactly same as
that of the input signal, the amplification is called faithful amplification.

31. Define the various h-parameters for a common emitter transistor.

From the h – parameter equivalent circuit of the common emitter configuration.
Vbe = hie Ib + hre Vce
Ic = hfe Ib + hoe Vce
Δ VBE
Where, hie = Δ IB | VCE constant
Δ VBE
hre = Δ VCE | IB constant
Δ IC
hfe = Δ IB | VCE constant
Δ IC
hoe =Δ VC | IB constant

5
32. State the advantages of using h-parameters for analyzing transistor amplifiers.
i.) Real numbers at audio frequencies
ii.) Easy to measure
iii.) Can be obtained from the transistor static characteristics curves,
iv.) Convenient to use in circuit analysis and design,
v.) Most of the transistor manufacturers specify the h – parameters.

33. What is bandwidth of an amplifier.

The bandwidth of an amplifier is defined as the difference between the lower cut - off frequency and upper cut
off frequency.
BW = f2 – f1

34. State the effect of coupling and bypass capacitors on the frequency response of amplifier.
Reactance of a capacitor is given by Xc = 1 / 2πfc. At medium and high frequencies, the factor f makes Xc
very small, so that all coupling capacitors behave as short circuits. At low frequencies, Xc increases. This increase
in Xc drops the signal voltage across the capacitor and reduces the circuit gain. As signal frequencies decrease,
the capacitor reactance’s increase and circuit gain continues to fall, reducing the output voltage.

35. State the effect of internal transistor capacitance on the frequency response of amplifier.
At high frequencies, the reactance of the junction capacitance are low. As frequency increases, the reactance of
junction capacitances fall. When these reactance become small enough, they provide shunting effect as they are
in parallel with junctions. This reduces the circuit gain and hence the output voltage.

36. Give the expression for roof NMOS transistor.

ro = (∂iD/ ∂v DS)-1│vGS= VGSQ = const.
ro= [λ K [(vGSQ – VT)2]-1≈ [λ IDQ]-1

37. Draw the small signal equivalent circuit of CS JFET (Nov/Dec2015).

38. What is Gate capacitance in MOSFET.

Gate capacitance is a parallel – plate capacitance formed by a gate electrode with the channel, with the oxide
layer acts as a capacitor dielectric. It is denoted as Cox.

6
39. Draw the small signal equivalent circuit of PMOS transistor.

40. Explain the loading effect.

The small signal overall voltage gain is,
Gv = vo / vs = - gm(ro║ RD)(Ri / Ri+ Rsi) = Av (Ri / Ri+ Rsi)
Since Rsi is not zero, the amplifier input signal vi is less than the signal voltage, This is known as loading effect.
It reduces the voltage gain of the amplifier.

41. What do you mean by drain diffusion and source diffusion capacitance?
Drain and Source capacitances are due to the reverse – biased pn junctions formed by the n+ source region and
the p – type substrate, and the n+ drain region and the p- type substrate. These are denoted as source diffusion
capacitance and drain diffusion capacitance respectively.

42. Give the expression of unity gain frequency (fT)for MOSFET amplifier?
Unity gain frequency for MOSFET:
fT =gm / 2π (Cgs + Cgd)
From the above expression we can say that fT is proportional to gm and inversely proportional to the
internal capacitances.

43. Compare different amplifiers.

• Large Voltage gain
COMMON SOURCE Good voltage amplifier and better trans • High input resistance
AMPLIFIER conductance amplifier • High output resistance

• Voltage gain ≈ 1
COMMON DRAIN Good voltage buffer • High input resistance
AMPLIFIER
• Low input resistance
• Current Gain ≈ 1
COMMON GATE Good current buffer • Low input resistance
AMPLIFIERS
• High output resistance
44. What is the need of coupling capacitors in amplifier design? (Aril/May 2019) (Nov / Dec 2015)
Coupling capacitors isolates the DC condition of one stage from the following stages.
It is used to couple output of one stage to another stage.

45. Differentiate between power transistor and signal transistor. (May / Jun 2016)
S.No Power transistor Small signal transistor
1 n-1 drift layer is present 110 n-1 drift layer
2 Secondary breakdown occurs No secondary breakdown
3 Used in power circuits Used in amplifying circuits

7
 PART-B

BJT Small signal Model-Analysis of CE, CB, CC amplifiers

1. Draw the small signal model of BJT device (OR) Draw the parameters equivalent circuit or small
signal model of a transistor in CE, CB, CC configuration? (Apr/May 2018). (OR)
Draw the hybrid model of BJT in CE, CC and CB configuration.

h – Parameter model for CE, CC and CB configuration

The variable Ib , Ic , Vb , and Vc represent total instantaneous current and voltage.

Ib − Input current; Ic − Output current; Vbe − Input voltage; Vce − Output voltage

CE Configuration

h– Parameter equivalent circuit

Vbe = hie Ib + hre Vce --- (1)

Ic = hfe Ib + hoe Vce --- (2)

∆VBE
Where, hie = ⃒ VCE − constant ---- (3)
∆IB

∆V
hre = ∆VBE ⃒ IB − constant---- (4)
CE

∆I
hfe = ∆I c ⃒ VCE − constant---- (5)
B

∆I
hoe = ∆Vc ⃒ IB − constant ---- (6)
C

hie − Input resistance;

8
 hre − Reverse voltage gain;
hfe − Forward transfer gain;
hoe − Output admittance

Relationship between h-parameters of different transistor configuration:

9
 2. (A) Derive the expressions for current gain (AI ), voltage gain(AV ), input resistance (Ri ) and
output resistance (RO ) for CE amplifier using h – parameter model. (April/May 2015 & 18) (Nov / Dec’
2014& 16)
Illustrate the steps involved in analyzing a BJT amplifier circuit using small signal model.
(April/May 2019) (5 Marks)

Circuit diagram

h – Parameter model

IL
Current gain [AI ] AI =
Ib

IC = hfe Ib + hoe Vc ; IC = hfe Ib + hoe (−Ic R L ); {since, Vc = −Ic R L }

IC + hoe R L Ic = hfe Ib ; IC (1 + hoe R L ) = hfe Ib
IC hfe
=
Ib 1 + hoe R L
−IC hfe
AI = =−
Ib 1 + hoe R L
Vb
𝐈𝐧𝐩𝐮𝐭 𝐑𝐞𝐬𝐢𝐬𝐭𝐚𝐧𝐜𝐞 (R i )R i =
Ib
Vb = hie Ib + hre VC
VC = −IC R L ; VC = AI Ib R L

10
 Vb hie Ib +(AI Ib RL )
Now R i = = = hie + hre AI R L
Ib Ib

−hfe
Substituting, AI = to the above equation
1+hoe RL

−hfe
R i = hie + hre ( ) × RL
1 + hoe R L
hre hfe R L
R i = hie −
1 + hoe R L
V A I I b RL I 1
Voltage gain (𝐀 𝐕 ) AV = Vc = ⸫ Vb = R
b Vb b i

AI R L
AV =
Ri
I
Output admittance (𝐘𝐨 )Yo = Vc with Vs = 0
c
Ic = hfe Ib + hoe Vc (divide this equation by VC)
Ic hfe Ib + hoe Vc
=
Vc Vc
hfe Ib
Yo = + hoe
Vc
From h parameter circuit with 𝐕𝐬 = 𝟎
R s Ib + hie Ib + hre Vc = 0 (Apply KVL)

(R s + hie )Ib = −hre Vc

Ib −hre
=
Vc R s + hie
Ib −hre hfe Ib
Substitute, =R 𝑖𝑛 Yo = + hoe
Vc s +hie Vc

Ic −hre
Yo = = hfe ( ) + hoe
Vc R s + hie
hfe hre 1
𝑌o = hoe − and Ro =
Rs +hie 𝑌o

11
(B) Draw the circuit of CE amplifier with DC sources eliminated and deduce the small signal model for
amplifier operation. (April/May 2019) (8 Marks) (OR) Approximate analysis of CE amplifier using
simplified Hybrid Model.

Analysis of CE Amplifier using simplified Hybrid Model:

Fig. Simplified CE model

Fig. Approximate CE model

IL
Current gain [AI ] AI =
Ib
−IC
AI = = −hfe
Ib
Vb
𝐈𝐧𝐩𝐮𝐭 𝐑𝐞𝐬𝐢𝐬𝐭𝐚𝐧𝐜𝐞 (R i )R i =
Ib
R i = hie
V A I I b RL I 1
Voltage gain (𝐀 𝐕 ) AV = Vc = ⸫ Vb = R
b Vb b i

AI R L
AV =
Ri
Output admittance (𝐘𝐨 )Yo = 0
R o =1/Y= ∞

12
 3. (A) Derive the expressions for current gain, voltage gain, input impedance and output impedance
for an Emitter Follower (common collector) circuit.
Circuit diagram

h parameter equivalent circuit

I −Ie
Current gain (AI ) AI = IL =
b Ib
Apply KCL
Ie = hfc Ib + hoc Ve = hfc Ib + hoc (−Ie R L ) (𝑠𝑖𝑛𝑐𝑒, Ve = −Ie R L )
Ie hfc
Ie + Ie R L hoc = hfc Ib ; Ie (1 + hoc R L ) = hfc Ib ; =
Ib 1 + hoc R L
Ie −IL −hfc
Ai = = =
Ib Ib 1 + hoc R L
Vb
𝐈𝐧𝐩𝐮𝐭 𝐑𝐞𝐬𝐢𝐬𝐭𝐚𝐧𝐜𝐞 (𝐑 𝐢 )R i =
Ib
Apply KVL
Vb = hic Ib + hrc Ve ( Ve = −Ie R L )
−Ie
Ve = AI Ib R L {AI = }
Ib

Now
hic Ib +hre (AI Ib RL )
Ri = ; R i = hic + hre AI R L
Ib
h RL −hfc
R i = hic − hrc (1+hfc ) {AI = 1+h }
oc RL oc RL

13
 V
Voltage gain (AV ) AV = Ve {∵ Ve = −Ie R L ; Ie = AI Ib; Vb = Ib R 𝑖 }
b

A I I b RL A I I b RL Ib 1
AV = ⥤ {∵ =R}
Vb Ib R 𝑖 Vb i

AI R L
AV =
R𝑖
I
Output admittance (𝐘𝟎 ) Y0 = V2 with Vs = 0
2

Ie
𝑌𝑂 = with Vs = 0
Ve
Ie = hfc Ib + hoc Ve
Ie hfc Ib
Dividing the above equation by Ve , = + hoc − − − (1)
Ve Ve
From circuit Vs = 0
Apply KVL
R S Ib + hic Ib + hrc Ve = 0
(R S + hic )Ib = −hrc Ve
Ib −hrc
= − − − (2)
Ve R s + hic
Sub equation (2) in (1)
Ie −hrc
= hfc ( ) + hoc
Ve R s + hic
Ie hfc hrc 1
yo = = hoc − 𝑎𝑛𝑑 R o =
Ve R s + hic yo

(B) Draw the circuit of CC amplifier with DC sources eliminated and deduce the small signal model
for amplifier operation. (April/May 2019) (8 Marks) (OR) Approximate analysis of CC amplifier
using simplified Hybrid Model.

In simplified CE model, the input is applied to base and output is taken from collector, and emitter is
common between input and output. The same simplified model can be modified to get simplified CC
model.
For simplified CC model, make collector common and take output from emitter.

14
The hfb Ib current direction is now exactly opposite that of CE model because the current hfc Ib always points
towards emitter.
I −Ie
Current gain (AI ) AI = IL =
b Ib
Ai = 1 + hfe
Vb
𝐈𝐧𝐩𝐮𝐭 𝐑𝐞𝐬𝐢𝐬𝐭𝐚𝐧𝐜𝐞 (𝐑 𝐢 )R i =
Ib
Apply KVL
Vb = hie Ib + IO R L ; (divide both sides by Ib )
−Ie −I𝑂
{AI = = }
Ib Ib

Now
Vb
Ri = = hie + (1 + IO hfe )R L;
Ib
V
Voltage gain (AV ) AV = Ve
b

A I I b RL A I I b RL Ib 1
AV = ⥤ {∵ =R}
Vb Ib R 𝑖 Vb i

AI R L
AV =
R𝑖
A I I b RL A I I b RL
Substituting values of A𝐼 and R i 𝑤𝑒 𝑔𝑒𝑡, AV = ⥤
Vb I b R𝑖
I
Output admittance (𝐘𝟎 ) Y0 = V2 with Vs = 0
2

Ie
𝑌𝑂 = with Vs = 0
Ve
Ie = hfc Ib + hoc Ve
Ie hfc Ib
Dividing the above equation by Ve , = + hoc − − − (1)
Ve Ve
From circuit Vs = 0
Apply KVL
R S Ib + hic Ib + hrc Ve = 0
(R S + hic )Ib = −hrc Ve
Ib −hrc
= − − − (2)
Ve R s + hic
Sub equation (2) in (1)
Ie −hrc
= hfc ( ) + hoc
Ve R s + hic
Ie hfc hrc 1
yo = = hoc − 𝑎𝑛𝑑 R o =
Ve R s + hic yo

15
 4. Derive the expression for 𝐀 𝐢 , 𝐀 𝐯 , 𝐑 𝐜 𝐚𝐧𝐝 𝐑 𝐨 𝐟𝐨𝐫 𝐂𝐁 amplifier using h parameter model. (April/May
2016)

Circuit diagram

h parameter model

I −Ic
Current gain (𝐀 𝐈 ) AI = IL =
e Ie

Ic = hfb Ie + hob Vc
hfb Ie + hob (−Ic R L ) ∴ Vc = −Ic R L
Ic + hob Ic R L = hfb Ie
(1 + hob R L ) Ic = hfb Ie
Ic hfb −IL hfb
AI = =− ⥤ =−
Ie 1 + hob R L Ie 1 + hob R L
Ve
𝐈𝐧𝐩𝐮𝐭 𝐑𝐞𝐬𝐢𝐬𝐭𝐚𝐧𝐜𝐞 𝐑 𝐢 R i =
Ie
Ve = hib Ie + hrb Vc
Vc = −R L Ic
= AI Ie R L
Ve hib Ie + hrb AI Ie R L
Ri = =
Ie Ie
R i = hib + hrb AI R L
V A I I e RL
Voltage gain (𝐀 𝐕 ) AV = Vc =
e Ve

16
 AI R L Ie 1
= ⃒ =
Rc Ve R i
I
Output admittance(𝐘𝟎 ) Y0 = Vc with Vs = 0
c

Ic = hfb Ie + hob Vc
Ic hfb Ie
÷ Vc = + hob − − − (1)
Vc Vc
When Vs = 0
R s Ie + hib Ie + hrb Vc = 0
(R s + hib ) Ie = −hrb Vc
Ie hrb
=− − − − (2)
Vc R s + hib
Sub (2) in (1)
Ic −hrb
= hfb ( ) + hob
Vc R s + hib
Ic hfb . hrb
y0 = = hob −
Vc R s + hib
1
Ro =
y0

5. Explain the frequency response operation of BJT amplifier with suitable circuit diagram.
From the fig 9.1, the capacitors CS,CC and CE will determine the low-frequency response.
Cs is normally connected between the applied source and active device. In fig 9.2The total resistance is now RS
+ Ri ,the cutoff frequency is established as
1
fLS =
2𝛱(𝑅𝑆 + 𝑅𝑖 ) 𝐶𝑆

Fig Loaded BJT amplifier with capacitors that affect the low- frequency response

17
 Fig Determining the effect of Cs on the low frequency response

At mid or high frequency, the reactance of the capacitor will be small to permit short circuit approximation for
the element. the voltage Vi related to VS by
𝑅 𝑖 𝑉𝑆
Vi|mid =
𝑅𝑖 + 𝑅𝑆

The value of Ri is determined by Ri = R1 ║R2║βre

Fig Localized ac equivalent for Cs

The voltage Vi applied to the input of the active device can be calculated using the voltage divider rule: Vi
𝑅𝑖 𝑉𝑆
=
𝑅𝑆 + 𝑅𝑖 − 𝑗𝑋𝐶𝑠
Since the coupling capacitor is normally connected
between the output of the active device and the
applied load, the R-C configuration that determines
the low cutoff frequency due to CC.
From fig 9.4 the total series resistance is now R0 + RL and the cutoff frequency is determined by,
1
fLC =
2𝛱(𝑅0+ 𝑅𝐿 )𝐶𝐶
The resulting value for R0 , R0 = RC ║r0
To determine fLE, CE must be determined from
1
fLE =
2𝛱𝑅𝑒𝐶𝐸

Fig determining the effect of Cc on the low freq

response

Fig Localized ac equivalent for Cc with Vi=0 V

𝑅𝑆 ′
The value of Re is determined by Re = RE ║( + 𝑟𝑒 ).where RS'=RS║R1║R2
𝛽

18
 The effect of CE on the gain is given by,

AV = - RC / re + RE

The maximum gain is available where RE is 0Ω. At low

frequency with bypass capacitor CE in open circuit.
Fig .9.6 Localized ac equivalent of CE As the frequency increases, the reactance of the capacitor
CE will decrease, reducing the parallel impedance of RE
and CE until RE shorted out by CE.

At the midband frequency level, the Short circuit equivalents for the capacitors can be inserted. The highest low
frequency cutoff determined by CS, CC or CE.
If there are two or more high cutoff frequencies, the effect will be to raise the lower cutoff frequency and reduce
the resulting bandwidth of the system. there is an interaction between the capacitive elements that can affect the
resulting low cutoff frequency.

6. Discuss the factors involved in the selection of IC, RC and RE for a single stage common emitter BJT
amplifier circuit, using voltage divider bias (Nov/Dec2015)
It is also called potential divider bias or self-bias.
In all D.C bias discussed in the above sections clearly states that the values of D.C bias currents and voltage of collector
𝐼𝐶
depends on the currents gain𝛽(𝛽 = 𝐼𝐵). But we know it is purely a temperature sensitive one particularly in silicon type.
Hence the nominal value of 𝛽 is not well defined.
So it is not desirable to provide a D.C bias circuit which is independent of the transistor current gain (𝛽). This is avoided
by potential or voltage divider bias shown in the

Here R1 and R2 forms potential dividing Rc collector load resister and its equivalent thevinins circuits is as follows;

19
This method is widely used since its provides a stable Q-point.
In this method two resistors R1 and R2 connected across the supply voltage Vcc and it provide biasing.
Emitter resistance Re provides bias to BE junction. This causes the base current and hence collector current flows in zero
signal condition.
Applying KVL law to BE junction circuit we get fig.

VB is the voltage across R2 which is given by VB = VCC*(R2/ (R1+R2))

Jut by taking this value as a source voltage and RB = 𝑅1‖R2
𝑅1𝑅2
𝑅𝐵 =
𝑅1 + 𝑅2

We can draw the thevinins equivalent circuit which is shown in fig

Then as per KVL law,
VB-IBRB-VBE-IERE = 0
VB-IBRB-VBE-(IC+IB) RE = 0 (IE = IB + IC)
VB = IBRB + VBE + (IC + IB) RE
Then apply KVL to output side we get
VCC – ICRC – IE RE – VCE = 0 But IC=IE
VCC – ICRC – IC RE – VCE = 0
VCC – IC (RC + RE ) – VCE = 0
IC (RC + RE ) = VCC - VCE
IC = VCC- VCE / (RC + RE )
Also VCE = VCC- IC / (RC + RE )
Then put Ic into VB we get
VB = IB RB + VBE + RE [VCC- VCE / (RC + RE )+IB]
= IB RB + VBE + IB RE +[VCC- VCE / (RC + RE )]
VB = IB(RB+ RE)+ VBE +[VCC* VCE / (RC + RE )]- [VCE* RE / (RC + RE )]

20
 Gain and frequency response

7. Explain the frequency response of an amplifier with suitable characteristics.

The plot between the gain of the amplifier and frequency of the signal is known as frequency response of
the amplifier. The frequency covers a wide range from 0Hz to very high frequencies(> 100MHz).

Decibels: The decibel (dB) is a measure of the difference in magnitude between two power levels. The power
gain in decibel is given by,
𝑃2
GdB = 10 log10 dB
𝑃1
Where P2 = specified terminal power; P1 = reference power
If the power P2 is output power (P0) and P1 is input power (Pi) of an amplifier. Then the power
gain is given by,
𝑃0
GdB = 10 log10
𝑃𝑖
𝑉0
If V0 and Vi are output and input voltage of an amplifier then voltage gain,GdB = 20 log10
𝑉𝑖
The frequency response is divided into three region 1) Low frequency region 2) Mid frequency
region 3) High frequency region.

Fig: Frequency response of an amplifier

1) Mid frequency region: The gain of the amplifier is maximum AVmid intersecting the frequency response at point
A and B. The corresponding frequencies f1 ans f2 are generally called corner, cutoff or half power frequencies.
If the maximum voltage gain in mid-band is AVmid = V0 / Vi then the gain at half power frequencies is AVmid / √2
The output power in mid-band is, Po(mid) = V02 / R0 = (AVmid Vi)2 / R0
The power at half power frequency is, Po(HPF) = V02 / R0 = (AVmid Vi /√2)2 / R0
= P0(mid) / 2
2) Cutoff Frequency: The frequency at which the voltage gain is equal to 0.707 times of its maximum value is called
cutoff frequency.

3) Bandwidth: The bandwidth of the amplifier is defined as the difference between the two half power frequencies f1
and f2
Bandwidth = f2 – f1
Where f1= the lower cutoff frequency
f2=the upper cutoff frequency

4) Low frequency region: In midband frequencies the coupling and bypass capacitor are replaced by short circuits.

21
 1
Capacitive reactance Xc = 2𝛱𝑓𝐶
At Low frequency, the coupling and bypass capacitor are increased. Hence the voltage gain decreases.

5) High frequency region: Here the internal capacitance across the junction affects the performance of the amplifier.
The capacitance, Cb'e = feedback path from bias to emitter
Cce = feedback path from collector to emitter
These capacitors divert the signal to ground.
Cb'c = feedback path from base to collector
This provides a bypass path for the input ac signal.

MOSFET-Small Signal Model

8. Draw and explain the small signal model of MOSFET.

To operate as an small signal amplifier,we bias the MOSFET in saturation region.

• The DC bias Point

• The signal current in the drain
• The voltage gain

The DC bias Point: ID - ½ Kn'(W /L) (VGS – Vt)2

VD = VDD - IDRD
VD ≫VGS - Vt
The required signal depends on VD, which is sufficiently greater than (VGS - Vt).

The Voltage Gain:

VD = VDD – ID RD

VD = VDD – (ID + id)RD

VD = VDD – IDRD - id RD

Vd=- id RD = - gm vgs RD

Av= Vd / Vgs = - gm RD

In the small signal analysis, signal are superimposed on the DC quantities,

The drain current, i D = ID + i d .

The AC drain current id is related to vgs is so called transistor Trans conductance (gm).
22
 gm≡ id / vgs =½ Kn'(W /L) (VGS – Vt)[ S]

Sometimes expressed in terms of the overdrive voltage, VOV = VGS – Vt

gm= Kn'(W /L) VOV [S]

This gm depends on the bias. The Trans conductance gm equals the slope of iD- vgs characteristic.
Similarly drain voltage, VD = VD + Vd

In saturation mode, MOSFET acts a voltage controlled current source, The control voltage Vgs and output current
iD give rise to small signal Π-model.

For Operation in the saturation region VGD ≤Vt ==>VGS – VDS ≤ Vt

Where the total drain to source voltage is VDS = VDS + vd

• ig =0 and vgs→ infinite input resistance

• r0 models the finite output resistance in the range from ≈ 10KΩ to 1MΩ and depends on bias current ID.
gm= Kn'(W /L) (VGS – Vt)
it can be, gm = ID / (VGS - Vt)/2
Similar to gm = IC / VT for BJT. Hence the bias current gmis much larger for than for MOSFET.

MOSFET have these advantages over BJT:

✓ High input resistance.
✓ Small physical size.
✓ Low power dissipation.
✓ Relative ease of fabrication.

Becomes amplifiers combines the advantages of BJT and MOSFET, They provide very large input resistance
from MOSFET and a large output impedance from the BJT.

23
9. Explain Small signal model of P Channel MOSFET.

The above diagram shows the common source circuit with p-channel MOSFET and its A.C equivalent circuit.
The A.C equivalent circuit seen for n-channel MOSFET also applies to the p-channel MOSFET; however, there
is a change in current directions and voltage polarities compared to the circuit containing the n-channel MOSFET.
The above diagram shows the small signal equivalent circuit of the p-channel MOSFET amplifier.

10. Explain the Common – Source (CS) Configuration. (April/May 2019) (Nov/Dec 2017)
The diagram shows the common source circuit with voltage divider biasing and coupling capacitor. The MOSFET is biased
near the middle of the saturation region by R1 and R2 resistors to work as an amplifier.
Assume that,the signal frequency is sufficiently large for the coupling capacitor to act essentially as a short circuit. The
signal source is represented by a Thevenin equivalent circuit, in which the signal voltage source vs, is in series with an
equivalent source resistance Rsi.
Here Rsi should me much less than the amplifier input resistance,
Ri = R1║ R2 in order to minimize loading effects.
The following diagram shows the resulting small- signal equivalent circuit.

24
 vo= - gm vgs (ro║RD)
vi= vgs
Av = vo / vi= - gm vgs (ro║RD) / vgs = - gm(ro║RD)
The input gate to source voltage is
vi= (Ri/ Ri+ Rsi) vs
So the small signal overall voltage gain is,

Gv = vo / vs = - gm(ro║ RD)(Ri/ Ri+ Rsi) = Av (Ri / Ri+ Rsi)

Since Rsi is not zero, the amplifier input signal vi is less than the signal voltage, This is known as loading effect.
It reduces the voltage gain of the amplifier.
The input resistance is Ris = R1║ R2
The output resistance is Ro = RD║ro
We can also relate the A.C drain current to the A.C drain to source voltage, as
Vds = - Id (RD)

11. Analysis of Common – Drain (CD) or Source follower Amplifier.(Nov/Dec 2016)(May 2017)

The above diagram shows the common – drain amplifier circuit. It is also known as grounded drain amplifier.
In this amplifier circuit, drain is used as a signal ground and hence RD is not needed.
The input signal is coupled to via Cc1 to the MOSFET gate and the output signal at the output signal at the
MOSFET source is coupled via Cc2 to a load resistance RL.
Since RL is in effect connected in series with the source terminal of the MOSFET, it is more convenient to use
the MOSFET’s T model for the analysis. This is shown in the following diagram.
Ri = R G
vi = vsxRi / (Ri + Rsi)= vsxRG / (RG + Rsi)
From the following diagram it can be seen that the load resistance RL is in parallel with ro and resistance 1/gm
in series with RL║ro.

25
The input voltage vi appears across the total resistance and hence by applying the voltage divider rule, we have
vo = vix (RL║ro) / ( 1/gm) + (RL║ro)
Av = vo / vi = (RL║ro) / (1/gm) + (RL║ro)

The open circuit voltage gain Avo (RL = Infinity) is given as

Av = ro /(1 / gm) + ro
Since ro>> 1 / gm, the open circuit voltage gain tends to unity; however, it is always less than unity.
Usually, RL<< ro and hence the voltage gain given by above expression Av becomes
Av = vo / vi= RL/ (1 / gm) + RL (RL<< ro)
Avs = Gv = vo / vs= vo / viXvi / vs
= (RL║ro)/ (1 / gm) + (RL║ro)XRG / (RG + Rsi)
The output resistance is given by
Ro = 1 / gm║ ro = 1 / gm.

The above diagram shows the D.C load line, the transition point, and the Q- point, which is in the saturation
region.

26
 High Frequency Analysis

12. Explain High – Frequency MOSFET Model.

Following diagram shows the high frequency equivalent circuit model for MOSFET. In this model, capacitance
Cdb can be neglected to simplify the analysis. The resulted model is shown

13. Calculate the current gain of high frequency model. (OR)

Derive an expression for MOSFET unity gain frequency(fT). (April/May 2019)

The fT is the frequency at which the short – circuit current gain of the CS MOSFET amplifier becomes unity.

The above diagram shows the modified high – frequency equivalent circuit to determine the short – circuit current
gain. Here, the input is fed with a current – source signal Ii and the output terminals are shorted.
The short circuit current Io is given by
Io = gm Vgs – s Cgd Vgs
27
 The second term in the above equation is very small and can be neglected at the frequencies of interest and thus
Io = gm Vgs
The Vgs in terms of Ii can be given by
Vgs = Ii / s (Cgs + Cgd)
Substituting the values of Ii and Io from the above equations we have
Io / Ii = gm Vgs / Vgs.s(Cgs + Cgd) = gm / s(Cgs + Cgd)
For physical frequencies s=jω. From above equation it can be seen that the magnitude of the current becomes
unity at the frequency.
ωT=gm / Cgs + Cgd
fT=gm / 2π (Cgs + Cgd)
From the above expression we can say that fT is proportional togm and inversely proportional to the internal
capacitances.

14. Explain Frequency response of CS Amplifier. (Apr/May 2018) (OR) With neat circuit diagram, perform ac
analysis for common source using equivalent circuit NMOSFET AMPLIFIER (NOV/DEC2015)
The following diagram shows the CS MOSFET amplifier. Its gain falls at low frequency due to the effect of C c1
and Cs and Cc2. Its gain falls at high frequency due to the effect of Cgs and Cgd.

Above diagram shows frequency response of CS MOSFET amplifier.

28
High Frequency Response:

The above diagram shows equivalent circuit for CS MOSFET amplifier.

Let us consider the output node. The load current is gm Vgs – Igd, where gm Vgs is the output current of the
MOSFET and Igd is the current supplied through the very small capacitance Cgd.
At frequencies in the vicinity of fH, the Igd is very small and can be neglected.
Hence we can write
Vo≈ - ILRL = - gm Vgs RL`
Where RL = ro ║ Rd ║RL`
Now consider the input node. We can replace Cgd at the input side with the equivalent capacitance Ceq using
Miller’s theorem. This is shown in the following diagram.

By Miller’s theorem, equivalent capacitance is given by,

Ceq = (1 + Av)C = (1 + Av)Cgd
Since input voltage Vgs, we have
Av = Vo / Vi = -gm Vgs RL` / Vgs = - gm RL`
Ceq = (1 + gm RL`) = Total input capacitance Cin can be given by,
Cin = Cgs + Ceq = Cgs + (1 + gm RL`)Cgd
The total resistance is given by,
Rsi`= Rsi ║ RG
By considering input circuit as a simple- time constant circuit we have
Ʈ = RC = Rsi` Cin
ωH = ωo = 1/ Ʈ = 1 / Rsi`Cin
fH = 1 / 2π Rsi`Cin

29
15. Explain small signal model of MOSFET.

From the above diagram, we see that the output voltage is

vds = Vo = VDD – iDRD
vo =VDD - (IDQ + id) RD = (VDD – IDQ RD) – idRD
The output voltage is also a combination of D.C and A.C values. The time – varying output signal is the
time – varying drain to source voltage, or
Vo = Vds = – idRD
We have,
id = gmVgs
In summary, the following relationships exist between the time varying signals for the circuit. The
equations are given in terms of the instantaneous A.C values as well as the phasors. We have,
vgs = vi
(or)
Vgs = Vi and
Id = gm vgs
(or)
Id = gm Vgs also
vds = - id RD
(or)
Vds = - Id RD

The above diagram shows the A.C equivalent circuit. Here, the D.C sources are made zero.

From the equivalent circuit for the NMOS amplifier circuit, we can draw a small signal equivalent circuit for the
MOSFET.

30
The above diagram shows the small signal low frequency A.C equivalent circuit for n – channel MOSFET.

The relation of Id by Vgs is included as a current source gm vgs connected from drain to source.
The input impedance is represented by the open circuit at its input terminals, since gate current IG is zero.
We know that the circuit has the finite output resistance of a MOSFET biased in the saturation region because of
the nonzero slope in the ID versus VDS curve.

We also know that,

iD = K [(vCS – VT)2(1+λvDS)]

where λ is the channel length modulation parameter and is a positive quantity. The small signal output resistance,
is defined as,

ro =(∂iD/ ∂v DS)-1│vGS= VGSQ = const.

ro= [λ K [(vGSQ – VT)2 ]-1≈ [λ IDQ]-1

This small signal output resistance is also a function of the Q – point parameters. The following diagram shows
the small signal equivalent circuit of common – source circuit.

31
Problems

1. For the circuit below, find (i) dc bias levels (ii) dc voltage across the capacitors (iii) ac emitter resistance (iv)
voltage gain (v) state of the transistor. (Nov/Dec 2018)

Solution:
Given that,
Emitter resistance, RE=1 KΩ
Collector resistance, RC=2 KΩ
Load resistance, RL=1 KΩ
Collector input voltage, VCC=15V
Amplification factor, ß=100
Input resistance, R1=40 KΩ and R2=10 KΩ
Voltage gain, AV= ?
AC emitter resistance, re= ?
i. DC bias levels: DC bias levels of CE amplifier determined by calculating various dc voltages and dc currents.
DC voltage, V2 across resistor, R2 is
𝑉𝐶𝐶
𝑉2 = 𝑋 𝑅2
𝑅1 + 𝑅2
Substituting the corresponding values, V2 is obtained as,
15
𝑉2 = 𝑋 10
40 + 10

V2= 3 V
DC emitter voltage, VE across emitter resistor, RE is,
VE=V2-2VBE
= 3 V- 0.7 V
= 2.3 V
DC emitter voltage, VE= 2.3 V
DC emitter current, IE is given by,
𝑉𝐸
𝐼𝐸 =
𝑅𝐸
2.3 𝑉
𝐼𝐸 = = 2.3 𝑚𝐴
1 𝐾Ω
DC Collector voltage, VC is determined as, VC = VCC - ICRC
VC=15 V - 2.3 X 2 KΩ since [IE = IC]
VC = 10.4 V
DC base current, IB is obtained as,
Using the relation IC = ß IB
IC 2.3 𝑚𝐴
IB = = = 0.023 𝑚𝐴
ß 100

32
 ii. DC voltages across the capacitors: From the above calculations, DC voltages across capacitors in the circuit is
obtained as,
DC voltage across capacitor, Cin is, V2 = 3 V
DC voltage across emitter capacitor, CE is , VE = 2.3 V
DC voltage across collector capacitor, CC is VC = 1.4 V
iii. AC Emitter Resistance: The ac emitter resistance, re’ is given by, [IE = 2.3 mA]
25 mV 25 mV
r′e = = = 10.9 Ω
IE 2.3 mA
iv. Voltage Gain(AV): The voltage gain AV of CE amplifier is defined by,
rc
AV =
r′e
Here, total ac collector resistance, rc is determined by, 𝑟𝑒 = 𝑅𝑐 ⃦ 𝑅𝐿
𝑅𝐶 𝑅𝐿 2𝑋1
𝑟𝑐 = = 10.9Ω = 0.667 𝐾Ω
𝑅𝐶 + 𝑅𝐿 2+1
Substituting rc value in AV, implies,
0.667 𝐾Ω
𝐴𝑉 =
10.9 Ω
Voltage gain, AV = 61.2
v. State of transistor: From the above calculation it can be determined that the transistor is in active state.
Since VC > VE

2. Determine the mid band gain, the upper 3 dB frequency fH of a CS amplifier fed with a signal source having an
internal resistance Rsig = 100 KΩ. The amplifier has RG = 4.7 MΩ, RD = RL = 15 KΩ gm = 1 mA/V, ro = 150
KΩ, Cgs = 1 pF and Cgd = 0.4 pF. (May/June2016)

𝑅𝐺
Solution: 𝐴𝑀 = 𝑔 𝑅′
𝑅𝐺 +𝑅𝑆𝑖𝑔 𝑚 𝐿
Where 𝑅𝐿′ = 𝑟0 ‖𝑅𝐷 ‖𝑅𝐿 = 150‖15‖15 = 7.14KΩ
𝑔𝑚 𝑅𝐿′ = 1 × 7.14 = 7.14𝑉/𝑉
4.7
Thus 𝐴𝑀 = − 4.7+0.1 × 7.14 = −7𝑉/𝑉
The equivalent capacitance Ceq is found as
𝐶𝑒𝑞 = (1 + 𝑔𝑚 𝑅𝐿′ )𝐶𝑔𝑑 = (1 + 7.14) × 0.4 = 3.26𝑝𝐹
The total input capacitance Cin can be now obtained as
𝐶𝑖𝑛 = 𝐶𝑔𝑑 + 𝐶𝑒𝑞 = 1 + 3.26 = 4.26 𝑝𝐹
The upper 3 dB frequency fH is found from
1 1
𝑓𝐻 = = = 382 𝑘𝐻𝑧
2𝜋𝐶𝑖𝑛 (𝑅𝑠𝑖𝑔 ‖𝑅𝐺 ) 2𝜋 × 4.26 × 1 (0.1‖4.7) × 106
−12

33
3. The MOSFET shown fig has the following parameter VT = 2V, 𝜷 = 𝟎. 𝟓 × 𝟏𝟎−𝟑, rd = 75KΩ. It is biased at
at ID = 1.9m A. (Nov/Dec2017)

a) Verify that the MOSFET is biased in its active region.

b) Find the input resistance.
c) Draw the small single equivalent circuit and find the voltage gain VL/VS.
Solution:
a) VDS = VDD – ID(RD + RS) = 18 – (1.9mA)(2.2 * 103 + 500) = 12.87V
22 ∗ 106
𝑉𝐺 = ( ) 18 = 5.74𝑉
47 ∗ 106 + 22 ∗ 106
Using equation 7.25 to find VGS, we have
VGS = 5.74-(1.9)(5) = 4.79V
|𝑉𝐺𝑆 − 𝑉𝑇 | = |4.79 − 2| = 2.79𝑉
Therefore condition 8.30 is satisfied;
12.87 = |𝑉𝐷𝑆 | > |𝑉𝐺𝑆 − 𝑉𝑇 | = 2.79
And we conclude that the MOSFET is biased in its active region.

b)
𝑟𝑖𝑛 = 𝑅1 ‖𝑅2 = (47𝑀Ω‖(22𝑀Ω) = 15𝑀Ω

c) From equation 8.31,

gm = 0.5 * 10-3(4.79 – 2) = 1.4 * 10-3 S
The small single equivalent circuit is shown in fig 8.33 from equation 8.33
𝑣𝐿 15 ∗ 106
=( ) ∗ (−1.4 ∗ 10−3 )[(75 ∗ 103 ‖(2.2 ∗ 13 ‖(100 ∗ 103 )]
𝑣𝑠 10 ∗ 103 + 15 ∗ 106
= (0.999)(-1.4*10-3)(2.09*103) = -2.92

34
4. A CC amplifier shown in below figure has VCC = 15V, RB = 75KΩ and RE = 910 Ω the 𝜷 of the silicon
transistors is 100 and the load resistor is 600 Ω find rin and AV. (Nov/Dec 2015)

Given:
VCC = 15V, RB = 75KΩ, RE = 910 Ω,𝛽 = 100, RL = 600 Ω
To Find: rin and AV
𝑉𝐶𝐶 −0.7 0.026
Formulae used 𝐼𝐵 = , 𝐼𝐸 = (1 + 𝛽)𝐼𝐵 , 𝑟𝐸 =
𝑅𝐵 +(𝛽+1)𝑅𝐸 𝐼𝐸
𝑟𝑖𝑛 (𝑠𝑡𝑎𝑔𝑒) = (𝛽 + 1)(𝑟𝑒 + 𝑟𝐿 )‖𝑅𝐵
𝑉𝐿 = 𝑅𝐸 ‖𝑅𝐿
𝑟𝑖𝑛 (𝑠𝑡𝑎𝑔𝑒) = (𝛽 + 1)(𝑟𝑒 + 𝑅𝐸 )
𝑟𝑜 (𝑠𝑡𝑎𝑔𝑒) = 𝑅𝐸 ‖𝑟𝑒 (𝑟𝑠 = 0)
𝑉𝐿 𝑅𝐸
𝐴𝑟 = = (𝑜𝑢𝑡𝑝𝑢𝑡 𝑜𝑝𝑒𝑛)
𝑉𝑆 𝑟𝐸 + 𝑅𝐸
Calculation:
𝑉𝐶𝐶 − 0.7 15 − 0.7 15 − 0.7 143
𝐼𝐵 = = = =
𝑅𝐵 + (𝛽 + 1)𝑅𝐸 75000 + (100 + 1)910 75000 + 101 ∗ 910 166910
= 8.5674 × 10−4 𝐴
𝐼𝐸 = (1 + 𝛽)𝐼𝐵 = (101) × 8.5674 × 10−4 = 0.08653𝐴
0.026 0.026
𝑟𝐸 = = = 0.300
𝐼𝐸 0.08653
𝑟𝑖𝑛 (𝑠𝑡𝑎𝑔𝑒) = (𝛽 + 1)(𝑟𝑒 + 𝑅𝐸 ) = (101) × (0.300 + 910) = 91940.3 𝑜ℎ𝑚𝑠
𝑉𝐿 𝑅𝐸 910
𝐴𝑉 = = = = 0.999
𝑉𝑆 𝑟𝐸 + 𝑅𝐸 910 + 0.300

35
5. Evaluate the AI, AV, Ri, Ro, Ais, Avs of a single stage CE amplifier with Rs=1 KΩ R1=22KΩ, R2=10KΩ,
Rc=2KΩ, RL=2KΩ, hfe=50,hie=1.1KΩ, hoe=25µA/V and hre=2.5X10-4
(Nov/Dec 2016)

Given
Rs=1 KΩ R1=22KΩ,R2=10KΩRc=2KΩ,RL=2KΩ,hfe=50,hie=1.1KΩ,hoe=25µA/V and hre=2.5X10-4.
i)Current gain
𝐴𝑖 = −ℎ𝑓𝑒 = −50
ii)Input impedance 𝑅𝑖 = ℎ𝑖𝑒 = 1.1 𝑘𝛺
𝑅𝑖 = ℎ𝑖𝑒 ⃦ 𝑅1 ⃦ 𝑅 2
= 1.1 × 103 ⃦ 22 × 103 ⃦ 10𝑘𝛺
22 × 10 × 106
= 1.1 × 103 ⃦ [ ]
32 × 103
220 × 103
= 1.1 × 103 ⃦ [ ]
32

= 1.1 ⃦ 6.87𝑘
6
1.1 × 6.87 × 10 7.56 × 106
= = = 0.947 × 103 = 947 𝛺
(1.1 + 6.87)103 7.975 × 103

𝒊𝒊𝒊)𝑽𝒐𝒍𝒕𝒂𝒈𝒆 𝒈𝒂𝒊𝒏
𝐴𝐼 𝑅𝐿 ′ −50 × (𝑅𝑐 ⃦𝑅𝐿 ) −50(2𝑘 ⃦ 2𝑘)
𝐴𝑣 = = = = −45.45
𝑅𝑖 𝑅𝑖 1.1𝑘
Output voltage
1
𝑅0 = =∞
𝑦0
𝑅0′ = 𝑅0 ⃦𝑅𝐿 ′ = ∞ ⃦ 2𝑘 ⃦ 2𝑘 = 1𝑘
Over all voltage gain
𝑉𝑖𝑛
𝐴𝑣𝑠 = 𝐴𝑉 ×
𝑉𝑠
𝑉𝑜 𝑉𝑜 𝑉𝑏
𝐴𝑣𝑠 = = ×
𝑉𝑠 𝑉𝑏 𝑉𝑠

𝑉𝑜 𝑉𝑏 𝑅1
𝑤ℎ𝑒𝑟𝑒 = 𝐴𝑣 𝑎𝑛𝑑 =
𝑉𝑏 𝑉𝑠 𝑅1 + 𝑅3

𝐴𝑣𝑅𝑖′ −45.45 × 947 −45.45 × 947

𝐴𝑣𝑠 = ′ = = = −22.106
𝑅𝑖 + 𝑅𝑠 947 + 1𝑘 1947
36
 Overall current gain
𝐼𝐿 𝐼𝐿 𝐼𝐶 𝐼𝑏
𝐴𝑖𝑠 == × ×
𝐼𝑆 𝐼𝐶 𝐼𝑏 𝐼𝑆
𝐼𝐿 𝑅𝑐 −2𝑘 −2𝑘
= = = = −0.5
𝐼𝐶 𝑅𝑐 + 𝑅𝐿 2𝑘 + 2𝑘 4𝑘
𝐼𝐶
= ℎ𝑓𝑒 = 50
𝐼𝑏
𝐼𝑏 𝑅𝐵 22 ⃦10 6.87𝑘 6.87
= = = = = 0.86
𝐼𝑆 𝑅𝐵 + 𝑅𝑖 22 ⃦10 + 1.1𝑘 6.87𝑘 + 1.1𝑘 7.97
𝐼
AI =𝐼𝐿
𝑆
= -0.5× 50 × 0.86
𝐴𝐼𝑆 = −21.54

6. Fig shows a common emitter amplifier. Determine the input resistance, ac load resistance, voltage gain
and output voltage?(May 2017)

Given:
𝑉𝐶𝐶 = 12 𝑉,𝑅𝐶 = 10 𝑘𝛺,𝑅𝛼 = 3 𝑘𝛺,𝛽 = 60, 𝑅1 = 100 𝑘𝛺,𝑅2 = 50 𝑘𝛺,𝑟𝐸 = 1 𝑘𝛺,𝑅𝐸1 = 2 𝑘𝛺,𝑅𝑆 =
100 𝛺,
𝑉𝑠 = 10 𝑚𝑉

Input resistance looking directly into the base.

𝑅2 50 × 103
𝑉𝑡ℎ = 𝑉𝐶𝐶 ( ) = 12 ( )
𝑅1 + 𝑅2 100 × 103 + 50 × 103
50 12
= 12 ( )= = 4𝑉
150 3
𝑅𝑡ℎ = 𝑅1 ⃦𝑅2
100 × 50 × 103 × 103 100 × 50 × 103
= 3 =
10 × 100 + 50 × 103 103 (150)
3 3
500 × 10 100 × 10
= = = 33.3 × 103 𝛺 = 33.3 𝑘𝛺
15 3
𝐸𝑚𝑖𝑡𝑡𝑒𝑟 𝑟𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒 (𝑅𝐸 )
37
 𝑅𝐸 = 𝑅𝐸1 + 𝑅𝐸 = 1𝑘𝛺 + 2𝑘𝛺 = 3𝑘𝛺
𝑉𝑡ℎ − 𝑉𝐵𝐸
𝐼𝐸 =
𝑅
𝑅𝐸 + 𝑡ℎ
𝛽
4 − 0.7
=
33.3 × 103
3 × 103 + 60
3.3
𝐼𝐸 = = 0.000928 = .92𝑚𝐴
3555.55

A.C resistance
25 25
𝑟𝑒1 = =
𝐼𝐸 (𝑚𝐴) 0.92
Input resistance
𝑅𝑖 = 𝛽(𝑟𝐸 + 𝑟𝑒1 ) = 27𝛺
= 60(1 × 103 + 27)
= 61620 𝛺
= 61.6 𝑘𝛺

Input resistance of the stage

𝑅𝑖𝑠 = (𝑅1 ⃦ 𝑅2 ) ⃦ [𝛽(𝑟𝐸 + 𝑟𝑒1 )]
33.33 × 61.6 × 103 × 103
=
33.33 × 103 + 61.6 × 103
2053.12 × 103
=
94.93
= 21.62 𝑘 𝛺
A.C load resistance
𝑟2 = 𝑅𝑐 ⃦ 𝑅𝐿

= 10𝑘 ⃦3𝑘
10 × 3 × 106 30
= = × 103 = 2.3 𝑘𝛺
13 × 103 13
𝑟𝐿 2307
𝐴𝑣 = = = 2.246
𝑟𝐸 + 𝛾𝑒1 1 × 103 + 27
Overall voltage gain
W.K.T the ratio of base to source voltage
𝑉𝑖𝑛 𝑅𝑖𝑆 21.62 × 103 21.62 × 103
= = = = 0.99
𝑉𝑠 𝑅𝑆 + 𝑅𝑖𝑆 100 + 21.62 × 103 21720
∴ 𝑜𝑣𝑒𝑟 𝑎𝑙𝑙 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑔𝑎𝑖𝑛
𝑉𝑖𝑛
𝐴𝑣𝑠 = 𝐴𝑉 × = 2.246 × 0.99 = 2.235
𝑉𝑠
Output voltage
𝑉𝑂 = 𝐴𝑉𝑆 × 𝑉𝑆 = 2.235 × 10 𝑚𝑉
𝑉𝑂 = 22.35 𝑚𝑉

38
7. An NPN common emitter amplifier circuit has the following parameters: hfe=50, hie=1KΩ and
Rc=3KΩ. Find the voltage gain of the amplifier. (April/May 2019)
𝐴𝐼 𝑅𝐿
𝐴𝑉 = ; 𝐴𝐼 = −ℎ𝑓𝑒 ; 𝑅𝑖 = ℎ𝑖𝑒 ; 𝑅𝐿 = 𝑅𝐶 ;
𝑅𝑖

−50 𝑋 3 𝑋 103
𝐴𝑉 = ; 𝐴𝐼 = −50; 𝑅𝑖 = 1𝐾; 𝑅𝐿 = 3𝐾;
1 𝑋 103

𝑨𝑽 = −𝟏𝟓𝟎

8. A common emitter amplifier has an input resistance 2.5 kΩ and voltage gain of 200.If the input signal
voltage is 5mV. Find the base current of the amplifier. (May 2017) (Nov/Dec 2017)
W.K.T
ib-base current, Ri=2.5 kΩ, Vs=5mV
𝑉
2.5X10-3 = 𝑠 = 5x10-3/𝑖𝑏 ∴ 𝑖𝑏 = 2 × 10−6 𝐴 = 2𝜇𝐴
𝑖𝑏

9. For a certain D-MOSFET, IDSS=10 mA and VGS(off)= -8 V. check if it is an n-channel or p-channel

device? Justify your answer. (Nov/Dec 2018)
Given that,
For a D-MOSFET,
Saturation currents, IDSS=10 Ma
Gate to source cut-off voltage, VGS (off)= -8V
Since the D-MOSFET has negative VGS (off). The device is n-channel D-MOSFET.

39
Additional Important question and answers:

1. Derive the expression for current gain, input impedance and voltage gain of a CE transistor Amplifier.
(Nov/Dec 2016) (Apr/May 2018)

The ac equivalent circuit can be obtained by replacing all the capacitors and voltage sources by a short circuit.

Characteristics of CE amplifier:
A. Without Emitter Resistor
(1) It has good voltage gain with phase inversion i.e., the output voltage is 180 ̊ out of phase with input.
(2) It also has good current gain, power gain and relatively high input and output impedance.

Fig. ac equivalent circuit of CE amplifier

Fig. h-parameter model of CE amplifier

Fig Approximate hybrid model of CE amplifier

40
Assume hre=0,
The input impedance: hie seen to be in series with hreV0.For CE circuit, hre is normally a very small quantity. So
that the voltage hreV0 fed back from the output to the input circuit is much smaller than the voltage drop across
hie.
Zi'= RB ‖hie where RB = R1|| R2
The output impedance: The output voltage variation have liitle
effect upon the input of CE circuit, only the output half of the
circuit need to be considered in determining the output
impedance.
1
Z0'= RC
ℎ𝑜𝑒

The voltage gain:AV=V0 / Vi

W.K.T V0 = -icRc Vi = ib hie
Where hre V0 is assumed short circuited.
ic = hfe ib
AV = -( hfe RC) / hie
Current Gain:
AI = I0 / Ii = ic / Ii
−𝑖𝑐 𝑖𝑏 𝑖𝑏 𝑖𝑏
= . = - hfe = RB / (hie + RB)
𝑖𝑏 𝐼𝑖 𝐼𝑖 𝐼𝑖
=- hfe RB / (hie + RB)

B. With emitter resistor:

A common emitter amplifier with emitter resistor Re provides feedback and voltage gain stabilized in a
CE amplifier But it reduces the gain.
To obtain h-parameter model of the circuit, we replace the transistor by its h-parameter model.

Fig. CE amplifier with Emitter resistor

Fig. AC equivalent circuit of CE amplifier with Emitter resistor

41
 Fig .h-parameter model of a CE amplifier with emitter resistor

Fig .Approximate Model

Assuming hre is very low, The input impedance

Zi' =𝑅𝐵 ║Zi
Zi =Vi / Ii =Vi / ib--------------------1
Vi =hie ib+ ie RE W.K.T (ie = ib+ic)
ie = ib+hfe ib = (1+hfe)ib-------------2

sub eq(2) in eq(1), Vi = ib ( hie +(1+hfe) RE)

Zi = Vi / ib = hie + (1+ hfe ) RE-----------3
Zi =𝑅𝐵 ║ Zi
=Rb ║ (hie +(1+hfe)RE)----------------4
Voltage Gain: Av = V0 / Vi------------------5
Vo = IL RC
= - ic Rcwhere(ic=hfe ib)
=-hfe ib Rc
Vi = Ii Zi
=ib (hie +(1+hfe) RE)------------------6
Sub eq(6) and eq(6) in eq(4)
AV= V0/ Vi= - hfe RC ib / (hie +(1+hfe) RE ) ib
= - hfe RC / hie (1+hfe) RE--------------------------7
Since (1+hfe)RE >> hieAv = - hfe Rc / (1+hfe)RE ---------------------------8

Since hfe>>1Av = - RC / RE -----------------------------9

Output impedance: Z0=RC-----------------10
Current gain:The current gain is defined as the ratio of output current to input current
42
 AI =I0/ Ii= I0 / ib . ib/ Ii
I0 = - i c
AI = - hfe ib / Ii---------------------11
using voltage divider rule, Ib / Ii = RB / RB + Zi
AI = - hfe RB / RB+Zi.---------------------12
Application:
It is used as voltage amplifier, among the three basic amplifier configuration CE amplifier most frequently used.

2. Derive the expression for current gain, input impedance and voltage gain of a CC transistor Amplifier.
This circuit is also known as emitter follower amplifier because its voltage gain is close to unity. Hence a change
in base voltage appears as an equal change across the load.
Characteristics of CC amplifier:
(1) CC amplifier provide current gain and power gain. but no voltage gain.
(2) It has high input impedance and very low output impedance.

Fig . Common collector amplifier

Fig . ac equivalent of CC amplifier

Fig .h-parameter model of a CC amplifier

The input impedance: Zi' =Zi ║𝑅𝐵 ---------------1

43
 Zi =Vi / ib
Vi =hie ib+ Ie RE-------2W.K.T ie = (1+hfe)ib

sub eq(2) in eq(1), Vi = ib( hie + (1+hfe) RE)

Zi = Vi / ib = hie + (1+ hfe ) RE-----------3
Zi'=𝑅𝐵 ║ Zi

Current gain: The current gain is defined as the ratio of output current to input current

AI =ie / Ii = Ie / ib . ib/ IiW.K.T ie =(1+hfe)ib

AI = - (1+hfe)ib / ib . ib/ Ii
AI = - (1+hfe).RB / RB+Zi.

Voltage Gain:Av = V0 / Vi------------------4

Vo = ie RE------------------5
Av = - ie RE / Vi
The input voltage Vi = ib Zi---------------6
Sub eq(3) in eq(6)
=ib (hie +(1+hfe) RE-----------7
AV = RE ie / (hie +(1+hfe) RE ) ibW.K.T ie = (1+hfe)ib
= - (1+hfe) RE / hie + (1+hfe) RE
= hie + (1+hfe) RE – hie / hie + (1+hfe) RE
ℎ𝑖𝑒
=1- --------------------8
ℎ𝑖𝑒 + (1+ℎ𝑓𝑒 ) 𝑅𝐸
ℎ𝑖𝑒
Since (1+hfe)RE >> hieand hfe >>1Av = 1- ---------------------------9
ℎ𝑓𝑒 𝑅𝐸
𝑆ℎ𝑜𝑟𝑡𝑐𝑖𝑟𝑐𝑖𝑡𝑐𝑢𝑟𝑟𝑒𝑛𝑡𝑡ℎ𝑟𝑜𝑢𝑔ℎ𝑜𝑢𝑡𝑝𝑢𝑡𝑡𝑒𝑟𝑚𝑖𝑛𝑎𝑙
Output impedance: Z0 =
𝑜𝑝𝑒𝑛 𝑐𝑖𝑟𝑐𝑢𝑖𝑡 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑏𝑒𝑡𝑤𝑒𝑒𝑛 𝑜𝑢𝑡𝑝𝑢𝑡 𝑡𝑒𝑟𝑚𝑖𝑛𝑎𝑙𝑠
Short circuit current through output terminalib = Vs / hie ║RB + RS--------------10

Open circuit voltage between output terminals = Vs

1+ℎ𝑓𝑒
Z0 = --------------------11
𝑅𝐸 ║ℎ𝑖𝑒 +𝑅𝑆
Application:
(1) The voltage gain of emitter follower as unity, thus it is used as buffer amplifier.
(2) It is used as impedance matching network.

44
3. Derive the expression for current gain, input impedance and voltage gain of a CB transistor Amplifier.
(May/June2016)
In this circuit only a fraction of output voltage is feedback to input thus hre is very small. Therefore hrbV0 can be
neglected when deriving CB gain and impedance.

Characteristics of CB amplifier:

(1) This CB circuit provides voltage gain and power gain but no current gain.
(2) It has high output impedance and very low input impedance thus it is unsuitable for most voltage amplification.

a. Input impedance: After neglecting hrbV0 , The Ze is given by,

Apply KVL , Vi = Iehib + IeRB – IeRB = Iehib +IeRB - IEhfbRB
IC = Iehfb=Ie [hib + RB – hfb RB]-------------------1
Ze = Vi / Ie = hib + RB(1 - hfb)---------------2
The actual impedance of the circuit is given by
Zi = Ze ║ Re----------------3

b. Output impedance: The output has very less impact on the input hence the output impedance can be taken as
Ze≅ 1 / hob
The actual output impedance is given by, Z0 = RC ║ZC≅ RC
RC is usually much smaller than 1/ hob, soothe circuit impedance is approximately equal to RC.
c. Voltage Gain: it is given by Av = V0 / Vi--------------------4
V0 = IC (RC ║RL) ------------5
Vi=Iehib +IeRB - IEhfbRB = Ie[hib + RB(1 - hfb)]
AV = IC (RC ║RL) / Ie[hib + RB(1 - hfb)]----------6
AV = hfb (RC ║RL) / hib + RB(1 - hfb)--------------7

d. Current gain: The transfer current gain of the device is given by hfc = IC / Ie-----------8
The signal current is divided between RE and Ze,and the collector current divides between RC and RL ,giving a lower
value of current gain.
IL = IC RE / RE + RL
= hfcIe RE / RE + RL but Ie=IS RB/ RB + Ze
Ai = IL / IS = hfcRERB / (RB + Ze)(RC + R:L)----------9

e. Power Gain:
The Power gain is given by APT = AV * hfb-------------10
Where Ai is significantly different from hfb Ap = AV * Ai------11

f. Application:
It is used for very high frequency voltage amplifier.

45
 EC8353-ELECTRON DEVICES AND CIRCUITS

UNIT-IV MULTISTAGE AMPLIFIERS AND DIFFERENTIAL AMPLIFIER

PART-A

BIMOS cascade amplifier, Differential amplifier

1. What is a differential amplifier?

An amplifier, which is designed to give the difference between two input signals, is called the differential
amplifier.

2. What is the function of a differential amplifier?

The function of a differential amplifier is to amplify the difference of two signal inputs,
i.e.,𝑉0 = 𝐴𝐷 (𝑉1 − 𝑉2 ), where AD is the differential gain.

3. What is the differential-mode voltage gain of a differential amplifier?

1
It is given by 𝐴𝑑 = (𝐴1 − 𝐴2 )
2
4. What are the ideal values of Ad and Acwith reference to the differential amplifier?
Ideally, Ac should be zero and Ad should be large, ideally infinite.

5. What are advantages of differential amplifier?

It has high gain and high CMRR.

6. List some applications of differential amplifiers?

Used in IC applications, AGC circuits and phase inverters.

Common mode and Difference mode analysis

7. Define differential mode signals of a differential amplifier. (Nov/Dec 2018)

The differential mode signal is the difference between two input voltages. i.e.,
Vd = V1 – V2
The differential mode input signal is zero when V1=V2

8. When two signals V1 and V2 are connected to the two inputs of a difference amplifier, define a
difference signal Vd and common-mode signal Vc
The difference signal Vd is defined as the difference of the two signal inputs,
i.e., Vd=V1–V2
The common-mode signal Vc is defined as the average of the two signals,
I.e., Vc = (V1+V2)
9. What is the common-mode gain AC in terms of A1and A2?
It is given by Ac = A1 + A2

10. Define CMRR what its ideal value How to improve it. (Nov/Dec2015), (May/ June2016)(May 2017)
The common-mode rejection ratio (CMRR) of a differential amplifier is defined as the ratio of the differential-
mode gain to common-mode gain.
|A |
CMRR = |Ad |
c

Ideal value of is Infinite.

The improve CMRR the following circuits are used
i) Current mirror circuit ii) Temperature compensation. iii) Differential amplifier with constant current bias.

11. Express CMRR in dB.

CMRR (dB)=20logAd–20logAc.

1
Single tuned amplifiers

12. What is meant by tuned amplifiers? (A/M 2010)

Tuned amplifiers are amplifiers that are designed to reject a certain range of frequencies below a lower cut off
frequency ωL and above a upper cut off frequency ωH and allows only a narrow band of frequencies.

13. Classify tuned amplifiers.

1. Single tuned amplifier.

2. Double tuned amplifier.
3. Synchronously tuned amplifier.
4. Stagger tuned amplifier.

14. What is the other name for tuned amplifier?

Tuned amplifiers used for amplifying narrow band of frequencies hence it is also known as “narrow band
amplifier” or “Band pass amplifier.

15. What is the application of tuned amplifiers?(N/D 2007)

The application of tuned amplifiers to obtain a desired frequency and rejecting all other frequency in
(i). Radio and T .V broadcasting as tuning circuit.
(ii). Wireless communication system.

16. What are the advantages of tuned circuit?

• High selectivity
• Smaller collector supply voltage
• Small power gain.

Neutralization methods

17. What is meant by neutralization? (N/D 2012)

It is the process by which feedback can be cancelled by introducing a current that is equal in magnitude but
180o out of phase with the feedback signal at the input of the active device. The two signals will cancel and the
effect of feedback will be eliminated. This technique is termed as neutralization.

18. What is the need for neutralization (Nov/Dec2015)

In turn RF amplifier at high frequency centered around a radio frequency the inter junction capacitance
between base and collector Cbc of the transistor becomes dominant i.e. its reactance become low enough to be
considered. As reactance of Cbc at RF is low enough it provides the feedback path from collector to base. If this
feedback is positive the circuit is converted to an unstable one generating its own oscillations and can stop
working as an amplifier. In order to prevent oscillations without redacting the stage gain neutralization is used
in tuned amplifiers.

19. State the merits of using push-pull configuration. (May 2018) (Apr/May 2018)
• Efficiency is high. (78.5%)
• Figure of merit is high.
• Distortion is less
• Ripple present in the output due to power supply is multiplied.
20. List the disadvantages of push-pull amplifier.
• Two identical transistors are needed.
• Centre taping is required in transformer.
• Transformers used are bulky and expensive.
• If the parameters of the two transistors differ, there will be unequal amplification of the two halves of
signal which introduces more distortion.

2
21. How do you bias class-A operation?

In class A mode of means, the output current flows throughout the entire period of input cycle and the Q-point is
chosen at the midpoint of A.C load line and biased.

22. Give two applications of class-C power amplifier.

• Used in radio and TV transmitters.

• Used to amplify the high frequency signals.
• Tuned amplifiers.

23. What is multistage amplifier?

Multistage cascading permits several single-stage amplifiers to be combined into one circuit. Multistage
cascading can produce an amplifier with large gain, high input resistance and low output resistance. The small-
signal behavior of a multistage amplifier can be modeled by cascading an appropriate number of small-signal
two-port amplifier models.

24. A multistage amplifier employs five stages each of which has a power gain of 30. What is the total gain of
the amplifier in dB. (Nov/Dec 2018)
Given that,
The power gain of each stage in a five-stage amplifier is,
AVn = 30, n = 1 to 5
Total gain, AV = ?
The overall gain, AV of an n-stage amplifier is given as,
AV = AV1 X AV2 X AV3 X ……AVn

Here, n = 5
AV = AV1 X AV2 X AV3 X AV4 X AV5
= 30 X 30 X 30 X 30 X 30
AV = 243 X 105
Total gain, AV = 243 X 105

AV = 147.71 dB

25. CMRR of an amplifier is 100dB, calculate common mode gain if the differential gain is 1000(Nov/Dec
2016)

CMRR=Ad/AC, 100=1000/Ac, Ac=10

26. Define conversion efficiency of power amplifier? (Nov/Dec 2016)

It is a measure of an active device in converting the d.c power of the supply into the ac power delivered to
load. It is also referred theoretical efficiency or collector circuit efficiency
• Mathematically, collector circuit efficiency,
a.c.power delivered to the load
𝜂𝑐 =
power supplied by the d.c.source to output circuit
27. A tuned circuit has a resonant frequency of 1600 KHz and a bandwidth of 10 KHz. What is the value of
its Q factor? (May 2017)
resonant frequency 1600
Q factor = bandwidth
= 10 = 160

28. What is thermal runaway? (Nov/Dec 2017)

Thermal runaway occurs in situations where an increase in temperature changes the conditions in a way that
causes a further increase in temperature, often leading to a destructive result. It is a kind of uncontrolled
positive feedback.

3
29. Compare the characteristics of CE, CB, CC amplifiers (May/June 2016) (Nov/Dec 2017)
30.
Common Collector
S.No Common Emitter Amplifier Common Base Amplifier
Amplifier

In this case emitter is In this case collector is

In this case base is common
1 common to both input and common to both input
to both input and output
output and output

2 1800 phase shift occurs No phase shift occurs No phase shift occurs

3 Input impedance: Low Very low Very high

4 Output impedance: High Very high Low

31. A multistage amplifier employs five stages each of which has a power gain of 30. What
is the total gain of the amplifier in dB? (Nov/Dec 2017)
Solution:
Absolute gain of each stage = 30 No. of stages = 5
Power gain of one stage in dB = 10 log 10 30 = 14.77
∴ Total power gain = 5 ×14.77 = 73.85 dB

32. What is cross over distortion? (Apr/May 2018)

Crossover distortion is the term given to a type of distortion that occurs in push-pull class AB or class B
amplifiers. It happens during the time that one side of the output stage shuts off, and the other turns on.

33. Determine the input impedance of a differential amplifier (emitter coupled) with R B=3.9 KΩ and ZB=2.4
KΩ. (April/May 2019)

𝑍𝑖 = 𝑅𝐵 ǁ 𝑍𝐵

𝑅𝐵 × 𝑍𝐵
𝑍𝑖 =
𝑅𝐵 + 𝑍𝐵

3.9 × 103 × 2.4 × 103

𝑍𝑖 =
3.9 × 103 + 2.4 × 103

The input impedance of a differential amplifier (emitter coupled), 𝒁𝒊 = 1.49 Ω

34. A single tuned amplifier provides a band width of 10KHz at a frequency of 1MHz. Find the circuit Q.
(April/May 2019)

𝑓𝑂 = 𝐵𝑊 × 𝑄𝑂

𝑓𝑂
𝑄𝑂 =
𝐵𝑊

1 × 106
𝑄𝑂 =
10 × 103

𝑄𝑂 = 100

4
 PART-B

BIMOS cascade amplifier, Differential amplifier

1. Explain the operation of cascade amplifier.

• The cascade amplifier consists of a common emitter amplifier stage in series with a common base
amplifier stage.
• It solves the low impedance problem of a common base circuit.
• It gives the high input impedance of a CE amplifier as well as good voltage gain and high
frequency response of CB circuit.
• For DC bias IC1= IE1, IE2 = IC1

• Ac equivalent circuit for cascade amplifier is drawn by shorting dc supply and capacitors.

• A simplified h parameter equivalent circuits for cascade amplifier is drawn by replacing

transistor with their equivalents

5
Analysis of second stage (CB)
a) Current gain (Ai2)

b) Input resistance (Ri2)

c) Voltage gain (Av2)

Analysis of first stage (CE)

a) Current gain (Ai1)
Ai1 = -hfe
b) Input resistance (Ri1)
Ri1 = hie
c) Voltage gain (Av1)

2. BIMOS cascade amplifier (or coupling amplifier):

❖ To get faithful amplification, amplifier should have desired voltage gain, current gain and it should
match its input impedance with the connected source impedance. Similarly, output impedance
must match with the load impedance.
❖ Normally, these requirements of the amplifier cannot be obtained in a single stage amplifier, which
is due to the limitation of the parameters of transistor or FET or whatever device used.
❖ Under these situations, more than one amplifier stages are cascaded such that input and output
stages provide impedance matching requirements with some amplification and remaining middle
stages provide most of the amplification.

Therefore, for making cascading following reasons,

❖ The amplification of a single stage amplifier is not sufficient.
❖ When input and output impedance is not of the correct magnitude, for a particular application
two or more amplifier stages are connected in cascaded fashion or coupling. This is known as
multistage amplifier.

Figure: Block diagram of cascade amplifier

6
From the above figure, 𝑉𝑖1 , 𝑉𝑖2 , 𝑉𝑖3the input of first, second and third stages and 𝑉𝑜1 , 𝑉𝑜2 , 𝑉𝑜3 are the output
𝑉
of the three stages. Therefore, 𝑉𝑜3 is the overall voltage gain of 3 stage amplifier which is given as follows:
𝑖1

𝑉𝑜3
𝐴𝑣 = …………… (1)
𝑉𝑖1

𝑉 𝑉 𝑉
= 𝑉𝑜3 .𝑉𝑖3 . 𝑉𝑖2 …………… (2)
𝑖3 𝑖2 𝑖1

From the figure, we know that,

𝑉𝑜1= 𝑉𝑖2; 𝑉𝑜2 = 𝑉𝑖3 ; put this into the above equation, we get
𝑉 𝑉 𝑉
𝐴𝑣 =𝑉𝑜3 .𝑉𝑜2 . 𝑉𝑜1 ……………. (3)
𝑖3 𝑖2 𝑖1

Already we know that,

𝑂𝑢𝑡𝑝𝑢𝑡 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑉
Voltage gain (A) = = 𝑉𝑜
𝐼𝑛𝑝𝑢𝑡 𝑣𝑜𝑙𝑡𝑎𝑔𝑒 𝑖

𝐴𝑣 =𝐴𝑣3 . 𝐴𝑣2 . 𝐴𝑣1 ………… (4)

Therefore, the voltage gain of multistage amplifier is the product of individual gains of the each stage.
Then the multistage amplifier is shown below.

Figure: Multistage amplifier

Voltage gain: The resultant voltage gain of the multistage amplifier is the product of the voltage gains of the various
stages or individual stages.

(i.e.,) 𝐴𝑣 == 𝐴𝑣1 . 𝐴𝑣2 . 𝐴𝑣3 . 𝐴𝑣4 . … … . 𝐴𝑣𝑛 … … … . . (5)

= Then, Voltage gain of 𝑛𝑡ℎ stage is as follows:

𝐴𝑖𝑛 𝑅𝑙𝑛
𝐴𝑣1 = 𝑅𝑖𝑛
……..…..(6)

Where, 𝑅𝑙𝑛 = Effective load resistance of 𝑛𝑡ℎ stage.

𝑅𝑖𝑛 = Input resistance / impedance of 1𝑠𝑡 stage.

Selection of cascading amplifier configuration:

From the above discussion, the multistage amplifier is divided into three parts:
i) Input stage
ii) Middle stage and
iii) Output stage.
❖ In the above, the input stage must be designed with input impedance matches with the source impedance.
❖ Similarly, the output stage designed must be the output impedance matches with the load impedance.
❖ Then, middle stage is designed with our desired voltage and current gain.
Anyhow, to select the cascading configuration, the following considerations are important since we normally
use these three configurations.
7
Common mode and Difference mode analysis

3. Draw the circuit diagram and explain the working of a differential amplifier using FET. Derive
the expression for differential mode gain and common mode gain.(May 2017)
• Normally, analysis in amplifier depends on both AC and DC analysis.
• In the above two, the d.c signals determines the operating values for the transistors and used as biasing.
• Similarly, a.c signals are used as input signals, which determine the output of the differential amplifier.
• The dual input, balanced output differential amplifier is also called Symmetrical Differential Amplifier.
❖ DC ANALYSIS:
• DC analysis means using D.c voltage as biasing voltage and keeping it constant (to obtain suitable
operating point).

❖ AC ANALYSIS:
• For performing AC analysis, we must apply AC input signals as an input. So, we can calculate the
following:
A. Differential mode gain (Ad).
B. Common mode gain (Ac).
C. Input resistance (Ri).
D. Output resistance (Ro).
The above can be obtained by using h-parameters.

A. Differential gain (Ad)

• To obtain the Differential mode gain, the two input signals must be different from each other.
• Here, we take the two a.c input signals as equal in magnitude but having 180ᵒ phase shift
between them.
V
• Then, the magnitude of each a.c input voltage VS1 and VS2is 2S .
• For the a.c purposes, emitter terminal can be grounded which is shown in figure below with
small signal analysis.

Figure (1): AC Equivalent for differential operation (half circuit concept)

• The circuit which can be analyzed by considering only one transistor is called Half
circuit concept of analysis.

Figure(2): Approximate hybrid model

8
 • For obtaining the differential mode gain (Ad) from the above hybrid model, we have to
apply the Kirchhoff’s voltage law in input side,
VS
= ib R S + ib hie ……..(1)
2

VS
= ib (R S + hie ) ……..(2)
2
VS
ib =2(R ……...(3)
S +hie )

• Similarly, applying the Kirchhoff’s voltage law to output loop, we get

Vo = - Ibhfe . RC ……….(4)
• Put the value of Ib in equation (4) from (3), we get,
−hfe VS R C
Vo = … … . . (5)
2(R S + hie )
V −h .R
• Then,Vo = 2(R fe+h C ) ………….(6)
S S ie

• Negative sign indicates that 1800 phase difference between input and output. If the input
signals are equal and are out of phase by 1800, we get
V V
• Differential mode signal Vd = V1 –V2 = ( 2S ) – (– 2S ) = VS …..(7)

Where, VSis differential input voltage.

Vo
• Differential voltage gain Ad = VS

hfe R C
Ad = … … … . (8)
2(R S + hie )
• When the output of differential amplifier is measured with reference to ground, it is called
unbalanced output.
• The output across the collectors of Q1 and Q2 to be perfectly matched then Ad for
balanced output is twice than that of Ad for unbalanced output. Therefore
hfe R C
Ad = … … … … … … . (9)
(R S + hie )

B. Common mode gain (AC)

• In common mode, the both transistor’s input magnitude and phases are also inphase with
each other.
• Let us assume that input signals are having the same magnitude VS and are in same
phase.
V1 +V2 VS +VS
• Common mode voltage VC = = = VS ………(10)
2 2
• If suppose, the output is expressed as, Vo = AC. VS ……(11)
V
• Common mode gain AC = Vo …….(12)
S

• In this mode, both the emitter current Ie1 = Ie2 = Ie of TQ1, TQ2 flows through RE in the
same direction, with same magnitude.

9
 • Hence, the total current flowing through RE is nearly 2Ie …..(13)

Figure(1): A.C. Equivalent Circuit for Common Mode Configuration

• Then the approximate hybrid model for the above circuit can be obtained and is used to
obtain the Ad.

Figure(2): Approximate Hybrid model

• As the current through RE is 2Ie , for simplicity of derivation, we have to assume the Ie
and effective emitter resistance as 2RE.
• Current through RC = Load current IL
• Effective emitter = 2 RE
• Current through emitter resistance = IL + Ib
• Current through hoe = (IL – hfe . Ib)
• Now, applying Kirchhoff’s voltage law to input
side,
Figure (3): Input side
-Ib RS + Ibhie+2R E (IL + Ib ) = - VS ……(14)
Ib RS-Ibhie−2R E (IL + Ib )= VS ………..(15)
While, Vo = - IL . RC …………(15a)
• Negative sign is due to the assumed direction of
current. Similarly apply KVL to output side.
−(IL −hfe Ib )
− 2R E (IL + Ib ) − IL R C = 0…. (16)
hoe
−IL hfe Ib
+ − 2IL R E − 2Ib R E − IL R C = 0…(17)
hoe hoe
h 1
Ib [h fe − 2R E ] = IL [ h + 2R E + R C ] ……… (18)
oe oe

Figure (4): Output side

10
 • Multiplying both sides by hoe , then
Ib [hfe − 2R E hoe ] = IL [ 1 + hoe (2R E + R C )] ………… (19)
IL [hfe − 2R E hoe ]
= … … … . . (20)
Ib [ 1 + hoe (2R E + R C )]
IL [ 1+hoe (2RE +RC )]
Ib = [hfe −2RE hoe ]
…………..(21)

• Putting this Ib in equation (15),

IL [1 + hoe (2R E + R C )][R S + hie + 2R E ] + 2R E
VS =
[hfe − 2R E hoe ]
VS [1 + hoe (2R E + R C )][R S + hie + 2R E ] + 2R E
= … (22)
IL [hfe − 2R E hoe ]
• Then, find LCM and adjusting the terms,
VS 2R E (1 + hfe ) + R S (1 + 2R E hoe ) + hie (1 + 2R E hoe ) + hoe R C (2R E + R S + hoe )
=
IL [hfe − 2R E hoe ]
VS 2R E (1 + hfe ) + (R S + hie )(1 + 2R E hoe ) + hoe R C (2R E + R S + hoe )
= … . (23)
IL [hfe − 2R E hoe ]
Actually hoe R C ≪ 1. Neglecting the terms,
VS 2R E (1 + hfe ) + (R S + hie )(1 + 2R E hoe )
= … . . (24)
IL [hfe − 2R E hoe ]
VS . [hfe − 2R E hoe ]
IL = … . . (25)
2R E (1 + hfe ) + (R S + hie )(1 + 2R E hoe )
Putting this IL in equation (15a),
Vo = - IL . RC
−VS .[hfe −2RE hoe ]RC
Vo = 2R … … . (26)
E (1+hfe )+(RS + hie )(1+2RE hoe )

Hence the common mode gain can be written as,

Vo [2R E hoe − hfe ]R C
AC = = … … . (27)
VS 2R E (1 + hfe ) + (R S + hie )(1 + 2R E hoe )
In practice, hoe is neglected, because the expression for AC can be further modified as,
−hfe R C
AC = … . . (28)
R S + hie + 2R E (1 + hfe )
The above expression is same whether the output is balanced or unbalanced.

COMMON MODE REJECTION RATIO (CMRR):

Ad
CMRR = | |
AC
From equation (8) and (28),
hfe RC
2(RS +hie )
CMRR = | hfe RC |……(29)
(RS +hie +2RE (1+hfe )

11
 (R S + hie + 2R E (1 + hfe )
CMRR = | | … (30)
2(R S + hie )
This is CMRR for dual input balanced output differential amplifier circuit.
For balanced case,
(R S + hie + 2R E (1 + hfe )
CMRR = | |
(R S + hie )
For unbalanced case,
(R S + hie + 2R E (1 + hfe )
CMRR = | |
2(R S + hie )
C. Input Impedance (Ri):
Ri is defined as the equivalent resistance existing between any one of the input and the ground
when other input terminal is grounded.
𝑉𝑆
𝑅𝑖 =
𝐼𝑏
Put the 𝑉𝑆 and 𝐼𝑏 from the above discussion, Ri = 2(RS + hie).

For one transistor and input pair, the resistance is RS + hie.

Hence for dual input circuit, the total input resistance is 2(RS + hie), as the 2 circuits are
perfectly matched.
This input resistance is not dependent on whether output is balanced or unbalanced.
D) OUTPUT IMPEDANCE RO:
• It is defined as the equivalent resistance between one of the output terminals with
respect to ground.
• The resistance between output terminal with respect to ground is RC.
RO = RC

Changes to be made for FET is

BJT FET
Rc Rd
1
re=𝑔
𝑚
𝑉 𝑅𝑑
𝐴𝑑 =𝑉 0 = 𝑉 = 𝑔𝑚𝑑 𝑅𝑑
𝑖𝑛 𝑔𝑚𝑑

12
4. Draw a differential amplifier and its ac equivalent circuit. (OR) Explain the operation of basic
emitter coupled differential amplifier (or) Explain the function of differential amplifier with neat
circuit. (A/M 2010) (M/J 2012) (OR) Explain the common mode and differential mode operation of
the differential amplifier (May/June2016 Nov/Dec-2017, May-2018) (OR)
Explain the working of a single ended input differential amplifier. (Nov/Dec 2018)

❖ DIFFERENTIAL AMPLIFIER BASIC BLOCK DIAGRAM:

• The differential amplifier amplifies the difference between two applied input signals Vin1 and Vin2
(voltage signals). Hence, it is called as Difference amplifier.

•
Fig: block diagram of differential amplifier
• In an ideal amplifier, the output voltage Vo is proportional to the difference between the two input
signals. Therefore we can write,
Vo α ( Vin1- Vin2 ) …………………..(1)
❖ DIFFERENTIAL GAIN Ad:
• From the above equation, we can write the differential gain Ad is [ Generally gain is nothing but the
output parameter (may be voltage, current, etc.) to input parameter].
• Therefore, Vo = Ad ( Vin1 – Vin2 ) …………………(2)
Where Ad = Differential gain constant
• This Ad is thegain with which differential amplifier amplifies the difference between two input signal
is called Differential gain.
• The difference between the two inputs (Vin1῀ Vin2) is generally called difference voltage and denoted
as Vd.
• output foreThere voltage is Vo = Ad . Vd ……………(3)
• Therefore the differential gain can be expressed as,
𝑉𝑜
Ad = …………………(4)
𝑉𝑑

❖ COMMON MODE GAIN Ac : If we apply two input voltages which are equal in all the respect to the
differential amplifier i.e., V1 = V2 then, ideally the output voltage Vo is (V1῀ V2) .Ad , must be zero.
• In this mode the applied input signals, phase and frequency must be in same.

13
 • But the output voltage of the practical differential amplifier not only depends on the difference voltage
but also depends on the average common level of the two inputs.
• Such an average level of the two input signal is called common mode signal which is denoted as Vc.
𝑉1+ 𝑉2
Vc = .........................(5)
2

• In practical, the differential amplifier produces the output voltage proportional to each common mode
signal. The gain which it amplifies the common mode signal to produce the output is called common
mode gain of the differential amplifier denoted as Ac.
𝑉𝑜
Ac = …………………….(6)
𝑉𝑐

• So that total output of any differential amplifier can be expressed as,

Vo = Ad .Vd + Ac .Vc ………………………(7)

❖ COMMON MODE REJECTION RATIO:

• In differential amplifier, if both transistors input the same, then that differential amplifier is called as
common mode differential amplifier.
• In common mode operation, the output is zero.
• But due to many disturbance in signals, noise signals appear as a common input signal to both the input
terminals of the differential amplifier.
• Such a common signal should be rejected by the differential amplifier(CMRR).
• Thus, the ability of a differential amplifier to reject a common mode signal is expressed by a ratio called
common mode rejection ratio.
• CMRR is defined as the ratio of the differential mode gain (Ad) to common mode voltage gain (Ac).
| 𝐴𝑑 |
CMRR = =ρ ………………..(8)
|𝐴𝑐 |

• In ideal case the CMRR is infinite, because the common mode gain is nearly or exactly zero. But in
practical, it is not infinite.
• But ρ is very large one, since Ad is very large and Ac is very small. The CMRR can be expressed in dB
also.
| 𝐴𝑑 |
CMRR in dB = 20 log dB …………..(9)
|𝐴𝑐 |

• The total output voltage is,

Vo = Ad .Vd + Ac .Vc ……………………(10)
Where, Vo = Total output voltage of differential amplifier,
Ad = Differential mode gain of differential amplifier,

14
 Ac = Common mode gain of differential amplifier,
Vd = Differential mode voltage.
• From equation (10), Vo can be written as,
Ac .𝑉
Vo = Ad .Vd[ 1+Ad . 𝑉𝑐 ] ………………..(11)
𝑑

1 𝑉𝑐
Vo = Ad .Vd[ 1+ 𝐴𝑑 . ]…………………(12)
𝑉𝑑
𝐴𝑐

1 𝑉𝑐
Vo = Ad .Vd[ 1+𝐶𝑀𝑅𝑅 . ] ……………..(13)
𝑉𝑑

• Therefore, from the above equation, the CMRR is practically very large, though both Vc and Vc
components are present.
• The output is proportional to the difference in signal only. Then the common mode component is greatly
rejected.

❖ EMITTER COUPLED DIFFERENTIAL AMPLIFIER:

• The transistorized differential amplifier is an emitter and emitter follower circuit. So this is called as
Emitter coupled differential amplifier.

Figure(1): Emitter biased circuit

• Figure(1) shows the emitter coupled biased circuit. The transistor TQ1 and TQ2used in the figure are
identical in characteristics and also having exactly matched characteristics.
• Then the two collector resistances RC1 and RC2 are equal while the two emitter resistances RE1 and RE2
are also equal.
Therefore RC1 = RC2 and RE1= RE2
• In this the magnitude of VCC and -VEE are also same. Therefore the differential amplifier can be obtained
by using such two emitter biased circuits.
• This emitter biased circuit can be obtained by connecting the E1 of TQ1 with E2 of TQ2.
• Because of this connection the RE1 is parallel with RE2.
15
 • The applied input Vs1 is connected with base of TQ1 and Vs2 input is connected with the base of TQ2.
• Both input voltages in Base is with respect to ground. Then its balanced output is taken in between the
respective collector terminals of both transistors (TQ1 and TQ2).
• This amplifier is called Emitter coupled Differential Amplifier. In this circuit, the two collector
resistanceRC used are also same.
• Then the dual input differential balanced output differential amplifier is shown below. Because, none of
the output terminal is grounded, the output is taken between two output terminals.
• So it is called as Balanced Differential Amplifier and it is shown in figure (2).

Figure (2): Balanced differential amplifier

• For studying the operation of differential amplifier, the following modes are used. (i) Differential
mode, and (ii) Common mode.
i) Differential mode operation:
• In this mode, both inputs are different in either magnitude or phase like 180ᵒ phase. This opposite phase
can be obtained from the Center tap Transformer.
• That is assume that the sine wave on the base of TQ1 is positive going while on the base of TQ2 is negative
going.
• With a positive going signal on the base of TQ1, if amplified, a negative going signal develops and appears
on the collector of TQ1.
• Due to positive going signal, current through RE also decrease and hence a positive going current wave is
developed across RE.

16
• Due to negative going signal on the base of TQ2, an amplified positive going signal develops on the
collector of TQ2 and anegative going signal develops across RE, because of emitter follower action of
TQ2.
• So. The signal voltage across RE due to effect of TQ1 and TQ2 are equal in magnitude and 180ᵒ out of
phase due to method pair of transistors.
• Hence these two signals cancel each other and there is no signal across the emitter resistance.
• Hence there is no AC signal current flowing
through the emitter resistance. Hence RE in this
case does not introduce negative feedback.

• While Vo is the output taken across collector of TQ1

and collector ofTQ2, the two outputs on collector C1
and C2 are equal in magnitude but opposite in
polarity.
• And Vo is the difference between these two signals.
Hence, the different output Vo is twice as large as the
signal voltage from collector to ground.

Figure (3): Differential mode

COMMON MODE OPERATION:
• In common mode the signals applied to the base of the both transistor TQ1 and TQ2 are in same phase,
frequency and also in magnitude.

Figure (4): common mode

• In phase signal voltages at the bases of TQ1 and TQ2 causes in phase signal voltages to appear across RE which add
together.
• Hence RE causes a signal current and provides negative feedback.
• This feedback reduces the common mode gain of differential amplifier.

17
5. Explain the analysis of Differential amplifier. With neat sketch explain the BJT differential
amplifier with active load and derive for Ad, Ac, and CMRR How CMRR improved (Nov/Dec
2015)(Nov/Dec 2016,May-2018) (OR)
Deduce the expression for Emitter currents in a differential amplifier under large signal operation.
(April/May 2019)

• Normally, analysis in amplifier depends on both AC and DC analysis.

• In the above two, the d.c signals determines the operating values for the transistors and used as biasing.
• Similarly, a.c signals are used as input signals, which determine the output of the differential amplifier.
• The dual input, balanced output differential amplifier is also called Symmetrical Differential Amplifier.

❖ DC ANALYSIS:
• DC analysis means using D.c voltage as biasing voltage and keeping it constant (to obtain suitable
operating point).
• For obtaining DC analysis, we must obtain operating point values i.e., ICQ and VCQ for the transistors
used.
• In DC analysis, the supply voltage d.c is taken as biasing voltage and the applied input a.c signals of both
Vs1 and Vs2 are to be zero.

Figure (1): DC Equivalent circuit

18
To obtain DC analysis following assumptions are to be taken:

1) Assuming RS1 = RS2 (source resistances of both sides) and is simply denoted by RS.
2) The transistor used TQ1 and TQ2 both are matched in their ideal identical characteristics.
3) Emitter resistances connected in both RE1 and RE2 must be the same.
i.e., RE1 = RE2 = RE
RE1 .RE2
Hence RE = RE1|| RE2 = [RE1 +RE2 ]

The collector resistances of both transistors also must be in same value.

i.e., RC1 = RC2 = RC
The magnitude of | VCC| = | VEE | are measured with respect to ground.
• Because of the above identical characteristics of both transistors, there is no necessity for finding out
the operating point of each transistors.
• So, simply finding out the operating point to one is enough ( ICQ and VCEQ ).
• For finding out the ICQ and VCE, the DC analysis diagram is needed.

Figure(2): DC analysis diagram

−IB R S − VBE − 2IE R E = −VEE ………… (1)

−IB R S − VBE − 2IE R E + VEE = 0 ……... (2)
But, IC = βIB and IC ≈ IE .……. (3)
IC IE
• According to equation (3), IB = = …………(4)
β β

• Putting the value of equation (4) in (2),we get,

I
− βE R S − VBE − 2IE R E + VEE = 0 ………… (5)
R
−IE [ βS + 2R E ] + VEE − VBE = 0 …………. (6)
R
IE [ βS + 2R E ] = VEE − VBE …..……. (7)
VEE −VBE
IE = R …………(8)
[ S + 2RE ]
β

RS
In practice, << 2R E ..……….(9)
β

19
 VEE −VBE
IE = …………. (10)
2RE

• From the above equation (1), we can observe the following points.
i. R E (Emitter resistance) determines the emitter circuit of TQ1 and TQ2 for the known value
of VEE .
ii. Then, the collector resistance (RL) is independent of current that flows through Emitter
terminals of TQ1 and TQ2.
The collector voltage, VC = VCC – IC RC ……….(11)
• Neglecting the drop across RS, we can obtain the emitter voltage of TQ1 as approximately equal to –
VBE.
• Then, VCE = VC – VE = (VCC – IC RC) - VBE …………(12)
VCE = VCC +VBE −IC RC
• Hence, IE = IC = ICQ while VCE = VCEQ for given values of VCC and VEE.
• Therefore operating point (Q) can be obtained from equation (10) and (12).

❖ AC ANALYSIS:(Nov/Dec 2016)
• For performing AC analysis, we must apply AC input signals as an input. So, we can calculate the
following:
E. Differential mode gain (Ad).
F. Common mode gain (Ac).
G. Input resistance (Ri).
H. Output resistance (Ro).
The above can be obtained by using h-parameters.
D. Differential gain (Ad)
• To obtain the Differential mode gain, the two input signals must be different from each other.
• Here, we take the two a.c input signals as equal in magnitude but having 180ᵒ phase shift between them.
VS
• Then, the magnitude of each a.c input voltage VS1 and VS2is .
2

• For the a.c purposes, emitter terminal can be grounded which is shown in figure below with small signal
analysis.

20
Figure (1): AC Equivalent for differential operation (half circuit concept)
• The circuit which can be analyzed by considering only one transistor is called Half circuit concept of
analysis.

Figure(2): Approximate hybrid model

• For obtaining the differential mode gain (Ad) from the above hybrid model, we have to apply the
Kirchhoff’s voltage law in input side,
VS
= ib R S + ib hie ……..(1)
2

VS
= ib (R S + hie ) ……..(2)
2
VS
ib =2(R ……...(3)
S +hie )

• Similarly, applying the Kirchhoff’s voltage law to output loop, we get

Vo = - Ibhfe . RC ……….(4)
• Put the value of Ib in equation (4) from (3), we get,
−hfe VS R C
Vo = … … . . (5)
2(R S + hie )
V −h .R
• Then,Vo = 2(R fe+h C ) ………….(6)
S S ie

• Negative sign indicates that 1800 phase difference between input and output. If the input signals are equal
and are out of phase by 1800, we get
21
 V V
• Differential mode signal Vd = V1 –V2 = ( 2S ) – (– 2S ) = VS …..(7)

Where, VSis differential input voltage.

Vo
• Differential voltage gain Ad = VS

hfe R C
Ad = … … … . (8)
2(R S + hie )
• When the output of differential amplifier is measured with reference to ground, it is called unbalanced
output.
• The output across the collectors of Q1 and Q2 to be perfectly matched then Ad for balanced output is twice
than that of Ad for unbalanced output. Therefore
hfe R C
Ad = … … … … … … . (9)
(R S + hie )
E. Common mode gain (AC)
• In common mode, the both transistor’s input magnitude and phases are also inphase with each other.
• Let us assume that input signals are having the same magnitude VS and are in same phase.
V1 +V2 VS +VS
• Common mode voltage VC = = = VS ………(10)
2 2

• If suppose, the output is expressed as, Vo = AC. VS ……(11)

V
• Common mode gain AC = Vo …….(12)
S

• In this mode, both the emitter current Ie1 = Ie2 = Ie of TQ1, TQ2 flows through RE in the same direction,
with same magnitude.
• Hence, the total current flowing through RE is nearly 2Ie …..(13)

Figure(1): A.C. Equivalent Circuit for Common Mode Configuration

• Then the approximate hybrid model for the above circuit can be obtained and is used to obtain the Ad.

22
 Figure(2): Approximate Hybrid model
• As the current through RE is 2Ie , for simplicity of derivation, we have to assume the Ie and effective
emitter resistance as 2RE.
• Current through RC = Load current IL
• Effective emitter = 2 RE
• Current through emitter resistance = IL + Ib
• Current through hoe = (IL – hfe . Ib)
• Now, applying Kirchhoff’s voltage law to input side,

Figure (3): Input side

-Ib RS + Ibhie+2R E (IL + Ib ) = - VS ……(14)
Ib RS-Ibhie−2R E (IL + Ib )= VS ………..(15)
While, Vo = - IL . RC …………(15a)
• Negative sign is due to the assumed direction of current. Similarly apply KVL to output
side.

Figure (4): Output side

−(IL −hfe Ib )
− 2R E (IL + Ib ) − IL R C = 0…. (16)
hoe
−IL hfe Ib
+ − 2IL R E − 2Ib R E − IL R C = 0…(17)
hoe hoe
h 1
Ib [h fe − 2R E ] = IL [ h + 2R E + R C ] ……… (18)
oe oe

• Multiplying both sides by hoe , then

Ib [hfe − 2R E hoe ] = IL [ 1 + hoe (2R E + R C )] ………… (19)
23
 IL [hfe − 2R E hoe ]
= … … … . . (20)
Ib [ 1 + hoe (2R E + R C )]
IL [ 1+hoe (2RE +RC )]
Ib = [hfe −2RE hoe ]
…………..(21)

• Putting this Ib in equation (15),

IL [1 + hoe (2R E + R C )][R S + hie + 2R E ] + 2R E
VS =
[hfe − 2R E hoe ]
VS [1 + hoe (2R E + R C )][R S + hie + 2R E ] + 2R E
= … (22)
IL [hfe − 2R E hoe ]
• Then, find LCM and adjusting the terms,
VS 2R E (1 + hfe ) + R S (1 + 2R E hoe ) + hie (1 + 2R E hoe ) + hoe R C (2R E + R S + hoe )
=
IL [hfe − 2R E hoe ]
VS 2R E (1 + hfe ) + (R S + hie )(1 + 2R E hoe ) + hoe R C (2R E + R S + hoe )
= … . (23)
IL [hfe − 2R E hoe ]
• Actually hoe R C ≪ 1. Neglecting the terms,
VS 2R E (1 + hfe ) + (R S + hie )(1 + 2R E hoe )
= … . . (24)
IL [hfe − 2R E hoe ]
VS . [hfe − 2R E hoe ]
IL = … . . (25)
2R E (1 + hfe ) + (R S + hie )(1 + 2R E hoe )
• Putting this IL in equation (15a),
Vo = - IL . RC
−VS .[hfe −2RE hoe ]RC
Vo = 2R (1+h
… … . (26)
E fe )+(RS + hie )(1+2RE hoe )

• Hence the common mode gain can be written as,

Vo [2R E hoe − hfe ]R C
AC = = … … . (27)
VS 2R E (1 + hfe ) + (R S + hie )(1 + 2R E hoe )
• In practice, hoe is neglected, because the expression for AC can be further modified as,
−hfe R C
AC = … . . (28)
R S + hie + 2R E (1 + hfe )
• The above expression is same whether the output is balanced or unbalanced.

COMMON MODE REJECTION RATIO (CMRR):

A
• CMRR = |Ad|
C

• From equation (8) and (28),

hfe RC
2(RS +hie )
CMRR = | hfe RC |……(29)
(RS +hie +2RE (1+hfe )

24
 (R S + hie + 2R E (1 + hfe )
CMRR = | | … (30)
2(R S + hie )
• This is CMRR for dual input balanced output differential amplifier circuit.

• For balanced case,

(R S + hie + 2R E (1 + hfe )
CMRR = | |
(R S + hie )
• or unbalanced case,
(R S + hie + 2R E (1 + hfe )
CMRR = | |
2(R S + hie )
C. Input Impedance (Ri):
• Ri is defined as the equivalent resistance existing between any one of the input and the ground when
other input terminal is grounded.
𝑉𝑆
𝑅𝑖 =
𝐼𝑏
• Put the 𝑉𝑆 and 𝐼𝑏 from the above discussion, Ri = 2(RS + hie).

• For one transistor and input pair, the resistance is RS + hie.

• Hence for dual input circuit, the total input resistance is 2(RS + hie), as the 2 circuits are perfectly
matched.
• This input resistance is not dependent on whether output is balanced or unbalanced.
D) OUTPUT IMPEDANCE RO:
• It is defined as the equivalent resistance between one of the output terminals with respect to ground.
• The resistance between output terminal with respect to ground is RC.
R O = RC

25
FET input stages
6. Explain the FET input stages.
❖ FET parameters:
• The following are the parameters of FET as an amplifier.
1. The transcondutance ‘𝑔𝑚 ’
2. The dynamic resistance ‘𝑟𝑑 ’ and
3. The amplification factor µ.
• Transcondutance:
✓ It is defined as the ratio of change in drain current to the change in gate source voltage at a constant
drain source voltage.
𝛥𝐼𝐷
𝑔𝑚 = / 𝛥𝑉𝐷𝑆 = Constant
𝛥𝑉𝐺𝑆

✓ It is expressed in mill amperes per volt or micro mhos. It is sometimes referred to as the common
source forward trans admittance.
• Dynamic Drain Resistance or output Resistance:
✓ The drain resistance is defined as the ratio of change in drain source voltage 𝑉𝐷𝑆 to the change in drain
current 𝐼𝐷 at a constant gate source voltage.
𝛥𝑉𝐷𝑆
𝑟𝑑 = / 𝛥𝑉𝐺𝑆
𝛥𝐼𝐷

✓ The reciprocal of drain resistance is the drain conductance, it is called sometimes as common source
output conductance.
• Amplification factor:
✓ Amplification factor is defined as the ratio of change in drain source voltage to the change in gate
source voltage at a constant drain current.
𝛥𝑉
µ = 𝛥𝑉𝐷𝑆 / 𝛥𝐼𝐷
𝐺𝑆

• Relation between FET parameters:

𝛥𝑉
✓ We know that µ = 𝛥𝑉𝐷𝑆
𝐺𝑆
✓ Multiplying the numerator and the denominator on the R.H.S by 𝛥𝐼𝐷 , We have
𝛥𝑉 𝛥𝐼 𝑉𝐷𝑆 𝐼
µ = 𝛥𝑉𝐷𝑆 x 𝛥𝐼𝐷 = x 𝑉 𝐷 = 𝑔𝑚 x 𝑟𝑑
𝐺𝑆 𝐷 𝐼𝐷 𝐺𝑆

✓ Therefore µ = 𝑔𝑚 x 𝑟𝑑 is the relation between the parameters of a FET.

• FET configurations:
✓ There are three types of configurations in the FET amplifier, they are:
• Common source configuration
• Common drain configuration
• Common gate configuration
✓ A FET can be connected in any one of the three configurations. The common drain circuit also called
source follower circuit.

26
Single tuned amplifiers

7. Draw the circuit diagram of a single tuned amplifier and obtained expression for its gain ,resonant
and cut off frequency (May/June 2016), (Nov/Dec2015)
(OR)
Illustrate the behavior of a MOSFET based amplifier circuit tuned load. Also deduce expression for
voltage gain at Centre frequency, Q and bandwidth. (April/May 2019)

SINGLE TUNED CAPACITIVE COUPLED TUNED AMPLIFIER

• Tuned amplifiers are amplifiers that are designed to reject a certain range of frequencies below a lower
cut off frequency ωL and above a upper cut off frequency ωH and allows only a narrow band of frequencies.

• The output across the tuned circuit is coupled to the next stage through the coupling capacitor. The
tuned circuit is formed by L and C resonates at the frequency of operation.

Here Ci and Ceq represent input and output circuits capacitance respectively. They can be given as
27
Ci = Cbe + Cbc (1-A) where A is the voltage gain of the amplifier
Ceq = Cbe( ( A-1) / A)+C where C is the tuned circuit capacitance
The gce is represented as the output resistance of current of generator gmVbe
gce = (1 / rce) = hce – gm*hce = hce = (1/R0)
The admittance of the inductor along with resistor R is given by
1
𝑌=
𝑅 + 𝑗𝜔𝐿
Multiplying numerator and denominator by 𝑅 + 𝑗𝜔𝐿we get

𝑅 − 𝑗𝜔𝐿 𝑅 𝑗𝜔𝐿 𝑅 𝑗𝜔2 𝐿 1 1

𝑌= 2 = − = − = +
𝑅 + 𝜔 2 𝐿2 𝑅 2 + 𝜔 2 𝐿2 𝑅 2 + 𝜔 2 𝐿2 𝑅 2 + 𝜔 2 𝐿2 𝜔(𝑅 2 + 𝜔 2 𝐿2 ) 𝑅𝑃 𝑗𝜔𝐿𝑃
𝑅 2 +𝜔 2 𝐿2 𝑅 2 +𝜔2 𝐿2
Where 𝑅𝑃 = , 𝑎𝑛𝑑𝐿𝑃 =
𝑅 𝜔2𝐿
The LP and RP are in shunt quality factor of the coil at resonance is given by
Qo = WoL/ R
𝑅 2 + 𝜔2 𝐿2
𝐿𝑃 =
𝜔2𝐿
2
Dividing numerator and denominator terms by𝜔 𝐿,
𝑅 2⁄
𝐿𝑃 = 𝜔2𝐿 + 𝐿
1
𝐿𝑃≈𝐿
Hence, The output circuit of the amplifier can be modified as

Taking R1 as the parallel combination of R0, RP and Ri i.e.

1 1 1 1
= + +
𝑅𝑡 𝑅0 𝑅𝑃 𝑅𝑖
The output circuit can be modified as shown in fig.
Susceptance of inductance L C′ capacitance C
𝑸𝒆 =
Conductance shunt resistance R t

Where Z is the impedance of C, L and Rtinparallel. The admittance Y = (1/Z) is given by

28
 1 1 1 1 𝑅𝑡
𝑌= = + + 𝑗𝜔𝐶 = [1 + + 𝑗𝜔𝐶𝑅𝑡 ]
𝑍 𝑅𝑡 𝑗𝜔𝐿 𝑅𝑡 𝑗𝜔𝐿

Multiplying numerator and denominator by 𝜔0

1 𝑅𝑡 𝜔0 𝑗𝜔𝜔0 𝐶𝑅𝑡
𝑌= [1 + + ]
𝑅𝑡 𝑗𝜔𝐿𝜔0 𝜔0

𝑅𝑡
= 𝜔0 𝐶𝑅𝑡 = 𝑄𝑒
𝐿𝜔0
𝜔 𝜔
1 + 𝑗𝑄𝑒 [𝜔 − 𝜔0 ]
0
𝑌=
𝑅𝑡

1 𝑅𝑡
𝑍= =
𝑌 1 + 𝑗𝑄 [ 𝜔 − 𝜔0 ]
𝑒 𝜔 𝜔
0

Let 𝛿 the fractional frequency variation.

𝜔 − 𝜔0 𝜔 𝜔
𝛿= = −1= = 1+𝛿
𝜔0 𝜔0 𝜔0

𝑅𝑡 𝑅𝑡
𝑍= =
1 1 + 𝛿 2 + 2𝛿 − 1
1 + 𝑗𝑄𝑒 [(1 + 𝛿) − ( )] 1 + 𝑗𝑄𝑒 [ ]
1+𝛿 1+𝛿

𝑅𝑡
𝑍=
𝛿
+1
1 + 𝑗2𝑄𝑒 𝛿 [2 ]
1+𝛿

Frequency close to resonance 𝜔0 , 𝛿 << 1

𝑅𝑡
𝑍=
1 + 𝑗2𝑄𝑒 𝛿

At resonance 𝜔 = 𝜔0 , 𝛿 = 0

𝑍 = 𝑅𝑡 = 𝑅0 𝑝𝑎𝑟𝑎𝑙𝑙𝑒𝑙 𝑅𝑃 𝑃𝑎𝑟𝑎𝑙𝑙𝑒𝑙 𝑅

𝜔0𝐿2 𝜔0 𝐿
𝑅𝑃 = =
𝑅 𝜔0 𝐶𝑅
𝑟𝑏′𝑒
𝑉𝑏′𝑒 = 𝑉𝑖
𝑟𝑏𝑏′ + 𝑟𝑏′𝑒
𝑟𝑏 ′ 𝑒
𝑉0 = −𝑔𝑚 𝑉𝑏′ 𝑒 𝑍 = −𝑔𝑚 (𝑉𝑖 )𝑍
𝑟𝑏𝑏′ + 𝑟𝑏′ 𝑒

Voltage gain with out considering the source resistance is given by

29
 𝑉0 𝑟𝑏 ′ 𝑒
𝐴𝑣 = = −𝑔𝑚 ( )𝑍
𝑉𝑖 𝑟𝑏𝑏′ + 𝑟𝑏′ 𝑒

𝑟𝑏 ′ 𝑒 𝑅𝑡
𝐴𝑣 = −𝑔𝑚 ( )∗
𝑟𝑏𝑏′ + 𝑟𝑏′ 𝑒 1 + 𝑗2𝑄𝑒 𝛿
𝑟𝑏 ′ 𝑒
𝐴𝑣 (𝑎𝑡 𝑟𝑒𝑠𝑜𝑛𝑎𝑛𝑐𝑒) = −𝑔𝑚 ( ) ∗ 𝑅𝑡
𝑟𝑏𝑏′ + 𝑟𝑏′ 𝑒

𝐴𝑣 1
| |=
𝐴𝑣 (𝑎𝑡 𝑟𝑒𝑠𝑜𝑛𝑎𝑛𝑐𝑒) √1 + (2𝛿𝑄𝑒 )2

1
2𝛿 =
𝑄𝑒

1
∆𝜔 = 𝑟𝑎𝑑/𝑠𝑒𝑐
𝑅𝑡 𝐶
𝐴𝑣
Gain plotted against 𝛿
𝐴𝑣 (𝑎𝑡 𝑟𝑒𝑠𝑜𝑛𝑎𝑛𝑐𝑒)

30
Gain and frequency response

8. Draw the frequency response of an ideal and a practical tuned amplifier and discuss their
characteristics. (Nov/Dec 2018)
The amplifier that amplifies a particular frequency and rejects other frequencies are termed as tuned
amplifiers.

Basically the tuned amplifier amplify the signal within a narrow frequency band that is centered about a
frequency f0. The signal between the lower and higher cut-off frequencies is amplified. The resonant
frequency of an ideal tuned circuit is expressed as,
1 1
𝑓0 = 2𝜋√𝐿𝐶 (or) 𝜔0 = [since ω0 = 2πf0]
√𝐿𝐶

Figures 2(a), 2(b) illustrates the ideal response and actual response curve of a tuned amplifier circuit
respectively.

From the figure 2(b), it is observed that at higher and lower cut-off frequencies, the curve decreases and is
maximum at resonant frequency (f0).

The behavior of tuned circuit at various frequencies is,

1. At frequencies above resonant frequency, the circuit behaves as capacitive load due to which the
current leads the applied voltage.
2. At frequencies below resonant frequency, the circuit behaves as inductive load due to which the
current lags behind the applied voltage.
3. At resonant frequency, the circuit behaves as resistive load since the inductive and capacitive effects
are nullified.
31
9. Explain briefly about gain and frequency response of single-tuned amplifier.
➢ The voltage gain of an amplifier depends upon current gain (β), input resistance (Ri) and effective or
a.c load resistance.
➢ The voltage gain is given by the relation,
𝑟
Av = β x 𝑅𝐿
𝑖
➢ The a.c load resistance of a parallel resonant circuit ( i.e., tuned circuit) is given by the relation,
L
RL = Zp = CR

Where, L = value of inductance,

C = value of capacitance, and

R = value of effective resistance of the inductor.

➢ Voltage gain of a voltage amplifier is given by the relation,

L

Av = β x CR
𝑅𝑖
L
➢ We know that the value of the quantity CR (changes above or below the resonant called impedance of
the tuned circuit) is very high at the resonant frequency and it decreases as the frequency changes
above or below the resonant frequency.
➢ Therefore voltage gain of a tuned amplifier is very high at the resonant frequency and it decreases as
the frequency changes above or below the resonant frequency.
➢ The above facts are shown in the form of a voltage gain versus frequency plot shown in figure below.

Figure: Frequency response curve

➢ Such a plot is called Frequency response curve of a tuned voltage amplifier.
➢ The bandwidth (BW) of an amplifier is equal to the frequency difference between the point A and B
on either side of the resonant frequency, where the value of voltage gain drops to 1/√2 of its maximum
value of resonance.
➢ Thus bandwidth,

32
 𝑓𝑜
BW = Δf = f2 – f1 = 𝑄𝑜

Where 𝑄𝑜 is the quality factor (or Q-factor) of the tuned circuit.

Neutralization methods

10. Describe any one method of neutralization used in tuned amplifier?

Briefly explain Hazel line neutralization used in tuned amplifiers for stabilization (May/June
2016)(Nov/Dec 2016,May-2018)

STABILITY OF TUNED AMPLIFIER

Stability of tuned amplifier is achieved by neutralization
i). Hezeltine neutralization ii). Neutrodyne neutralization

❖ In a tuned RF amplifier the transistor are used at the frequency near to their unity gain bandwidth. To
amplify the narrow band of high frequencies.
❖ At this frequency inter-junction capacitor b/w base and collector of transistor (Cbc)of transistor
becomes dominant
❖ As a reactance of Cbc at Rf is low and its provide feedback path from a collector to base.
❖ If some feedback signal reaches the input from output in a positive manner with proper phase shift
then the circuit is unstable, generating its own oscillation.
Amplifier, it was necessary to reduce stage gain to a level that ensures the circuit stability

. This can be achieved in several ways

i) favoring the stability factor of the tuned circuits

ii) loose coupling b/w stages
iii) Increase looser element into the element.

❖ To achieve stability the professor Hazettile introduced a circuit in which the troublesome effects of the
cbc was neutralized by introducing a signal coupled through the Cbc.

HAZELTINE NEUTRALIZATION:-
❖ This is the neutralization technique employed in tuned RF amplifier to maintain stability .
33
 ❖ The undesired effect of collector to base capacitance of the transistor is neutralized by introducing a
signal which cancels the signal coupled through the collector to base capacitance
❖ This is achieved by a small variable capacitance (CN)is connected from the bottom of coil to the base
of the transistor .It introduce a signal to the base of the transistor such that it cancels out the signal fed
to the base by Cbc
❖ By properly adjusted Cn exactly neutralized achived.
❖ Modified version of Hazeltine neutralization called neutron dyneneutralization.

NEUTRODYNE NEUTRALIZATION:-

❖ In a neutrodyne neutralization technique, Cn is connected to the centre trapped to the secondary coil.
❖ Hence it is connected with Vcc which ensures that it is insensitivity to any variation is supply voltage
Vcc .Hence provided higher neutralization for the tuned amplifier.
❖ In principle, the circuit functions are the same manner as the hazeltine neutralizing capacitor does not
have the supply voltage across it.

Power amplifiers –Types (Qualitative analysis).

11. Write a short notes on Power amplifier.(Nov/Dec 2017)

• A power amplifier is an amplifier, which is capable to providing a large amount of power to the load
such as loudspeaker, or motor etc.

34
 • It is essential in almost all electronic systems, where a large amount of power is required to be supplied
to the load.
• The power amplifier, is used as a last stage in a electronic system. For example, a public address system
(PAS) consists of a microphone, a multistage amplifier, a power amplifier and a loudspeaker.
• The microphone converts the sound waves into electrical signal, which is of very low voltage (usually of
few millivolts).
• This signal is insufficient to drive the loudspeaker. Therefore this signal is first raised to a sufficiently
high value (a few volts) by passing it through a multistage small-signal (or voltage) amplifier.
• This signal is then used to drive the power amplifier, because it is incapable of delivering a large amount
of power to the loudspeakers.
• A power amplifier is more commonly known as audio amplifier. The audio amplifiers are used in public
address system, tape recorders, stereo systems, television receivers, radio receivers, broadcast
transmitters etc.
• It will be interesting to know that a power amplifier dies not actually amplify the power. As a matter of
fact, it takes power from the d.c. power supply connected to the output circuit and converts it into useful
a.c. signal power.
• The power is fed to the load. The type of a.c. power developed, at the output of a power amplifier, is
controlled by the input signal.
• Thus we can say that actually a power amplifier is a d.c. to a.c. power converter, whose action is
controlled by the input signal.
• The power amplifiers, are also known as large signal amplifiers.
• The term ‘large signal’ for the power amplifiers arises because these amplifiers use a large part of their
a.c. load line for operation.
• It is in contrast to the small signal amplifiers, which use only 10% of their a.c. load line for operation.
The small signal amplifiers are commonly known as voltage amplifiers.

12. Explain in detail the various types of power amplifier. (OR) Explain with circuit diagram class B
power amplifier and derive for its efficiency (Nov/Dec2015)(May 2017)(Nov/Dec-2017)
i. Class-A amplifier:
• A class-A amplifier is one in which the operating point and the input signal are such that the
current in the output circuit, flows at all times.
• A class-A amplifier operates essentially over a linear portion of its characteristics.
• In class-A operation, the transistor stays in the active region throughout the a.c cycle.
• The point and the input signal are such as to make the output current flows for 360°.
• Voltage gain: The voltage gain for a class-A amplifier may be obtained in the same way as the
small-signal amplifier. It is given by the relation,
𝑟
𝐴𝑣 = 𝑟𝐿
𝑒
𝑟𝐿 = A.C. load resistance whose value is equal to the parallel combination of collector
resistance ( 𝑅𝑐 ) and load resistance ( 𝑅𝐿 ).

𝑟𝑒 = A.C. emitter diode resistance.

35
• Current gain: the current gain of a transistor is the ratio of a.c. collector current ( 𝑖𝑐 ) to the a.c.
base current ( 𝑖𝑏 ).
𝑖𝑐
𝐴𝑖 = =β
𝑖𝑏
• Power gain: The a.c. input power to the base of transistor,
𝑃𝑖𝑛 = 𝑉𝑖𝑛 . 𝑖𝑏

And the a.c. output power from the collector.

𝑃𝑜 = − 𝑉𝑜 . 𝑖𝑐
• The negative sign in the above equation indicates that the phase of input signal is reversed at the
output.
𝑃𝑜 −𝑉𝑜 .𝑖𝑐 𝑉𝑜 𝑖𝑐
Power gain, 𝐴𝑝 = = =− x
𝑃𝑖𝑛 𝑉𝑖𝑛 . 𝑖𝑏 𝑉𝑖𝑛 𝑖𝑏
𝑟
= − 𝐴𝑣 . 𝐴𝑖 = − 𝑟𝐿 x β
𝑒
Where 𝐴𝑣 = voltage gain, and
𝐴𝑖 = current gain.
• The overall efficiency or circuit efficiency of the amplifier circuit is defined as the ratio of a.c.
power delivered to the load to the total power supplied by the d.c. source.
• Mathematically, the overall efficiency,
a.c.power delivered to the load 𝑉𝐶𝐸𝑄. 𝐼𝐶𝑄
𝜂𝑜 = =
Total power supplied by the d.c. source 2𝑉𝐶𝐶. 𝐼𝐶𝑄

• Maximum value of overall efficiency,

𝑉 𝐼
𝜂𝑜(𝑚𝑎𝑥) = 2( 𝑉𝐶𝐸𝑄. 𝐼𝐶𝑄 ) = 0.25 = 25%
𝐶𝐸𝑄. 𝐶𝑄

• The collector efficiency of the amplifier circuit is defined as the ratio of a.c. power delivered to
the load, to the power supplied by thed.c. source to the transistor.
• Mathematically, collector circuit efficiency,
a.c.power delivered to the load
𝜂𝑐 = power supplied by the d.c.source to the transistor

• Maximum value of collector efficiency,

𝑉 𝐼
𝜂𝑐(𝑚𝑎𝑥) = 2( 𝑉𝐶𝐸𝑄. 𝐼𝐶𝑄 ) = 0.5 = 50%
𝐶𝐸𝑄. 𝐶𝑄

36
 Figure: classification of amplifiers based on the biasing condition

ii. Class-B amplifier:

• A class-B amplifier is one in which the operating point is at an extreme end of its characteristics, so
that the quiescent power is very small.
• Hence either the quiescent current or the quiescent voltage is approximately one half a cycle.
• In class-B operation, the transistor stays in the active region only for half the cycle. The Q-point is
fixed at the cut-off point of the characteristics.
• The output current flows for 180°.
• D.C. input power: the input power comes from the d.c. source (i.e., the 𝑉𝐶𝐶 supply) and is given by
the relation,
𝑃𝑖𝑛(𝑑𝑐) = 𝑉𝐶𝐶 . 𝐼𝑑𝑐

Where 𝐼𝑑𝑐 is the average value of current drawn from the 𝑉𝐶𝐶 supply.

• D.C. power loss in load resistor: Its value is given by the relation,

PRL(dc) = I2dc . RL

• A.C. output power in load resistor: Its value is given by the relation,

37
𝑃𝑜(𝑎𝑐) = I2 .RL = V2 / RL

Where I = the r.m.s. value of a.c. output current,

V = Ther.m.s. value of a.c. output voltage, and

VP= The peak value of a.c. output voltage.

• Power dissipated within the resistor: Its value is given by the relation,

Pc(dc) = Pin(dc) - PRL(dc) - 𝑃𝑜(𝑎𝑐)

𝑃𝑜(𝑎𝑐) 𝑃𝑜
• Overall efficiency: 𝜂𝑜 = =
𝑃𝑖𝑛(𝑑𝑐) 𝑉𝐶𝐶 . 𝐼𝑑𝑐

• Maximum value of overall efficiency,

1
𝑃𝑜(𝑎𝑐) 𝑉𝐶𝑃 . 𝐼𝐶𝑃
𝜂𝑜 = = 4𝑉 = 0.785=78.5%
𝑃𝑖𝑛(𝑑𝑐) 𝐶𝐶 . 𝐼𝑑𝑐

iii. Class-AB amplifier:

• A class-AB amplifier is one operating point between class A and class B.
• Hence the output signal is zero for part but less than one-half of an input sinusoidal signal cycle.
• The output current flows for more than 180° but less than 360°.
• a.c. power delivered to the load resistor,
𝑉𝑃 𝐼𝑃 𝑉𝑃. 𝐼𝑃
𝑃𝑜(𝑎𝑐) = 𝑉𝐶 . 𝐼𝐶 =( ) .( )=
√2 √2 2
• And total power dissipation of the two transistors,
𝑉𝑃. 𝐼𝑃
2 𝑃𝐶(𝑑𝑐) = 𝑃𝑖𝑛(𝑑𝑐) − 𝑃𝑜(𝑎𝑐) = 𝑉𝐶 . 𝐼𝐶 − 2
2 𝐼𝑃 𝑉𝑃. 𝐼𝑃
= 𝑉𝐶𝐶 . −
𝜋 2
𝑉𝐶𝐶 𝑉𝑃
= 2 𝐼𝑃 ( − )
𝜋 4
• Overall efficiency,
𝑉𝑃. 𝐼𝑃
𝑃𝑜(𝑎𝑐) 2 π 𝑉𝑃 𝑉𝑃
𝜂𝑜 = = 2𝐼 =4 . = 0.785
𝑃𝑖𝑛(𝑑𝑐) 𝑉𝐶𝐶 . 𝑃 𝑉𝐶𝐶 𝑉𝐶𝐶
𝜋

• For the largest possible output signal, the peak value of the output voltage is equal to the 𝑉𝐶𝐶 supply
(i.e., 𝑉𝑃 = 𝑉𝐶𝐶 ). In the case, the overall efficiency is maximum, and its value,

𝜂𝑜(𝑚𝑎𝑥) = 0.785 = 78.5%

• The value of collector efficiency is equal to the overall efficiency, whose maximum value is also
78.5%.

iv. Class-C amplifier:

• A class-C amplifier is one in which the operating point is chosen so that the output current (or
voltage) is zero for more than one-half of an input sinusoidal signal cycle.
• In class-C amplifier, the Q-point is fixed beyond the extreme end of the characteristics. The output
current remains zero for more than half cycle.
38
 • The unturned audio or video voltage amplifier with a resistive load is operated as small signal
amplifier under class-A operation.
• class-B amplifiers are mostly used for power amplification in push-pull arrangement.
• class-AB and class-B operation are used with unturned power amplifiers, whereas class-C operation
is used with tuned radio frequency amplifiers.

Additional Questions:

Explain briefly about push-pull amplifier

❖ Introduction:
• This means one in on and another one is off.
• It needs same type of transistors( i.e., NPN or PNP ).
• Also it needs two transformers in both input and output sides.
• One is input transformer and other is called output transformer.
• Input is applied to input driver transformer’s primary winding.
• Both transformers (input and output) is centre tapped one.
• Both are NPN means voltage VCC is positive.
• Both are PNP means voltage VCC is negative.

❖ Basic principle of operation:

Figure: Basic operation diagram

• During the positive half cycle of the applied input Q1 is only under ON condition. The positive half
cycle is across the load.
• Similarly, During the Negative half cycle of the applied input Q2 is only under ON condition. So the
Negative half cycle is across the load.

❖ Push-pull class-B amplifier:

39
 Figure: Push-pull amplifier- class-B
• In the above circuit, both transistors is of NPN type.
• If both are PNP, the supply voltage must be –VCC. but basic diagram is same.
• Input driver transfer driver circuit drives the circuit, then the input signal is applied to the primary of the driver
transformer.
• The centre tap on the secondary of the driver transformer is grounded. The centre tap on the primary of the
output transformer is connected to the supply voltage +VCC.
• Whenever the input signal is under positive half cycle, when point A is positive with respect to B, then the
transistor Q1 is in the active region. But Q2 is under in OFF condition now.So the load gets this positive voltage
drop output across it.
• Then, point B is positive with respect to A under negative half cycle. So, Q1 is in the OFF condition.so the load
gets voltage in negative across it due to negative voltage. This is shown in the waveform.
• For the output transformer, the number of turns of each half of the primary is N1. But in the secondary, it is N2.
• Hence, the total number of turns in primary side of output transformer is 2N1.
• Then turns ratio is 2N1 : N2.
• D.C operation:
✓ The Q-point is adjusted on the X-axis such that, VCEQ = VCC and ICEQ is zero. The coordinates of the Q-point
are (VCC,0). There is no d.c base bias voltage.
• D.C power input:
✓ Each transistor output is in the form of half rectified waveform. Hence, if Im is the peak value of the output
𝐼𝑚
current of each transistor, the dc or AV value is , due to half rectified waveform.
𝜋
✓ Then, two currents drawn by the two transistors, form the A.C supply are in the same direction.
✓ Therefore, the total D.C or average current drawn from the A.C supply is algebraic sum of the
individual average current drawn by each transistor,
𝐼𝑚 𝐼𝑚 2𝐼𝑚
Idc = + = …………..(1)
𝜋 𝜋 𝜋
✓ The total d.c power input is given by,
Pdc = VCC * Idc ……………(2)
2
Pdc = 𝜋VCC .Im …………..(3)

40
 Figure: Waveform output

• A.C operation:
✓ When A.C signal is applied to the input driver transformer, for positive half cycle Q1 transistor
is under ON condition. Then, its current flow path is shown in the following diagram.

Figure: current path

✓ From the above figure, when Q1 conducts, lower half of the primary of the input transformer
does not carry any current. Hence. Only N1number of turns carry the current.
✓ While, when Q2conducts , upper half of the primary does not carry any current. Therefore
again only N1 number of turns carry the current.
✓ Hence, the reflection on the primary can be written as,
𝑅 𝑁2
RL’ = n.n𝐿 ……..(4)and n = ……..(5)
𝑁1
✓ Note that the step down turns ratio is 2N1 : N2 but while calculating the reflected load, the ratio
n becomes N2 : N1.
✓ So each transistor shares equal load which is the reflected load RL’.

41
 −1
✓ The slope of the a.c load line is , while the d.c load line istheverticalline passing through the
RL’
Q on the X-axis. The load lines are shown below.

Figure: load lines for push-pull class B amplifier

✓ The slope of the a.c load line (magnitude of slope) can be represented in terms of Vm and Im,
1 𝐼
= 𝑉𝑚 ………..(6)
RL’ 𝑚
𝑉𝑚
R L’ = ………(7)
𝐼𝑚

Here, Vm = peak value of the collector circuit

• A.C power output:

✓ As Im and Vm are the peak values of the output current and the output voltage respectively.
Then
𝑉𝑚 𝐼𝑚
Vrms = …..(8) andIrms = ……(9)
√2 √2
The power output is, Pac = Vrms .Irms
= Irms .RL’ .Irms
= Irms2 .RL’ …………….(10)
= Vrms2/ RL’
• Efficiency: The efficiency of class-B amplifier can be calculated as follows:
𝑃
%η = 𝑃𝑎𝑐 x 100 ………..(11)
𝑑𝑐
𝑉𝑚𝐼𝑚

= 2
2
* 100 ……(12)
𝑉 .𝐼
𝜋 𝐶𝐶 𝑚
𝜋 𝑉𝑚
=4 ∗ 100 ……..(13)
𝑉𝐶𝐶
• Maximum efficiency:
✓ As the peak value of the collector voltage Vm increases, the efficiency also increases.
✓ Then the maximum value of Vm is possible which is equal to VCC.
𝑃
%η max = 𝑃𝑎𝑐 * 100
𝑑𝑐
𝜋 𝑉𝑚
=4 ∗ 100 = 78.5%
𝑉𝐶𝐶

42
13. Evaluate the (1) operating point (2)differential gain(3)common mode gain(4)CMRR and (5)output
voltage if Vs1=70mV peak to peak at 1 Khz and Vs2=40 mV peak to peak at 1 Khz of dual input
balanced output differential amplitude hie=2.8 KΩ.(Nov/Dec 2016)

1. Operating point value are 𝐼𝐶𝑄 , 𝑉𝐶𝐸𝑄 . Apply KVL to input side.
−𝐼𝐵 𝑅𝑆 − 𝑉𝐵𝐸 − 2𝑅𝐸 𝐼𝐸 + 𝑉𝐸𝐸 = 0

−𝐼𝐸
𝑅 − 𝑉𝐵𝐸 − 2𝑅𝐸 𝐼𝐸 + 𝑉𝐸𝐸 = 0
𝛽 𝑆

𝑉𝐸𝐸 − 𝑉𝐵𝐸
𝐼𝐸 =
𝑅
2𝑅𝐸 + 𝑆
𝛽

𝛽 = ℎ𝑓𝑒 = 100

15 − 0.7
𝐼𝐸 = = 1.051 𝑚𝐴
100
2 × 6.8 × 103 + 100

𝐼𝐶 = 𝐼𝐸 = 1.051 𝑚𝐴

𝑉𝐶𝐸 = 𝑉𝐶𝐶 + 𝑉𝐵𝐸 − 𝐼𝐶 𝑅𝐶 = 15 + 0.7 − 1.051 × 10−3 × 4.7 × 103

∴ 𝑉𝐶𝐸𝑄 = 10.758 𝑉
ℎ 𝑅𝐶
Differential gain, 𝐴𝑑 = 𝑅 𝑓𝑒+ℎ
𝑠 𝑖𝑒

100 × 4.7 × 103

𝐴𝑑 = = 162.068
100 + 2.8 × 103
ℎ𝑓𝑒 𝑅𝑐
Common mode gain, 𝐴𝐶 = 2𝑅
𝐸 (1+ℎ𝑓𝑒 )+𝑅𝑠 +ℎ𝑖𝑒

100 × 4.7 × 103

𝐴𝐶 =
2 × 6.8 × 103 (1 + 100) + 100 + 2.8 × 103
43
 = 0.3414

𝐴𝑑 162.068
𝐶𝑀𝑅𝑅 = = = 474.652
𝐴𝑐 0.3414

∴ 𝐶𝑀𝑅𝑅 = 20 log(474.652) = 53.527 𝑑𝐵

Output voltage, 𝑉𝑜 = 𝐴𝑑 𝑉𝑑 + 𝐴𝑐 𝑉𝑐

𝑉𝑑 = 𝑉𝑠1 − 𝑉𝑠2 = 70 − 40 = 30 𝑚𝑉 (𝑃 − 𝑃)

𝑉𝑠1 + 𝑉𝑠2 70 + 40
𝑉𝑐 = = = 55 𝑚𝑉 (𝑃 − 𝑃)
2 2
𝑉𝑜 = 162.068 × 30 × 10−3 + 55 × 10−3 × 0.3414

= 4.86204 + 0.0187

= 4.88 𝑉 (𝑃𝑒𝑎𝑘 − 𝑃𝑒𝑎𝑘)

14. A parallel resonant circuit has a capacitor of 250 pF in one branch and inductance of 1.2 mH and a
resistance of 10Ω in parallel branch. Find (1). Resonant frequency (2). Impedance of the circuit at
resonance (3). Q-factor of the circuit. (Nov/Dec 2018)
Solution:
i. Resonant frequency of the parallel tuned circuit is defined as,
1 1 𝑅2
𝑓𝑟 = √ −
2𝜋 𝐿𝐶 𝐿2

1 1 10 𝑋 10
𝑓𝑟 = √ −
2𝜋 1.25 𝑋 10−3 𝑋 250 𝑋 10−12 (1.25 𝑋 10−3 )2
1
𝑓𝑟 = 2𝜋 𝑋 178836.493 = 284.7 X 103 Hz

fr= 284.7 KHz

ii. Impedance of the circuit, Zr is given by,
𝐿 1.25 𝑋 10−3
𝑍𝑟 = =
𝑅𝐶 250 𝑋 10−12 𝑋 10
Zr = 500000

Zr = 500 KΩ

iii. Q-factor of the circuit is defined as,

2𝜋𝑓𝑟 𝐿 2𝜋 𝑋 284.7 𝑋 103 𝑋 1.25 𝑋 10−3 2236.02
𝑄= = = = 223.6
𝑅 10 10
Q = 223.6

44
15. Compare voltage and power amplifiers. (Nov/Dec 2018)

Voltage Amplifier Power Amplifier

1. The amplitude of input A.C signal is small 1. The amplitude of A.C signal is large.

The collector current is very high (greater

2. The collector current is low (about 1 mA) 2.
than 100 mA)
3. RC coupling is used. 3. Transformer coupling is used
4. The A.C power output is low 4. The A.C power output is high
5. Heat dissipation is less 5. Heat dissipation is high
6. The size of power transistor is small 6. The size of power transistor is large
7. Current gain is low 7. Current gain is high
8. Output impedance is high 8. Output impedance is low

16. Explain the self-biasing of a JFET. (Nov/Dec 2018)

• Self-bias is the most common type of JFET bias. Recall that a JFET must be operated such that the gate
source junction is always reverse-biased.
• The condition requires a negative VGS for an n-channel JFET and a positive VGS for p-channel JFET. This
can be achieved using the self-bias arrangement shown in Fig.1
• The gate resistor, RG, does not affect the bias because it has essentially no voltage drop across it; and
therefore the gate remains at 0 V.
• RG is necessary only to isolate an A.C. signal from ground in amplifier applications.
• The voltage drop across resistor, RS makes gate source junction reverse biased.

Fig 1: self-bias circuit for JFET

Step 1: Obtain expression for VGS
• For the n-channel FET in Fig. 1(a), IS produces a voltage drop across RS and makes the source positive with respect to
ground. Since IS = ID and VG = 0, then VS = IS RS = ID RS. The gate to source voltage is,
VGS = VG – VS = 0 – ID RS = - ID RS
• For the p-channel FET in Fig. 1(b), IS produces a voltage drop across RS and makes the source negative with respect to
ground. Since IS = ID and VG = 0, then VS = - ISRS = -IDRS the gate to source voltage is
VGS = VG – VS = 0 – (-IDRS) = + IDRS
45
 • In the following D.C. analysis, the n-channel JFET shown in Fig. 1(a) is used to for illustration.
• For D.C. analysis we can replace coupling capacitors by open circuits and we can also replace the resistor R G by a short
circuit equivalent, since IG = 0. This is illustrated in Fig.2.

Fig 2: Simplified self-bias circuit for dc analysis

Step 2: Calculate IDQ

𝑉𝐺𝑆 2
𝐼𝐷 = 𝐼𝐷𝑆𝑆 [1 − ]
𝑉𝑃

Substituting value of VGS in above equation we get,

−𝐼𝐷 𝑅𝑆 2 𝐼𝐷 𝑅𝑆 2
𝐼𝐷 = 𝐼𝐷𝑆𝑆 [1 − ] = 𝐼𝐷𝑆𝑆 [1 + ]
𝑉𝑃 𝑉𝑃

Step 3: Calculate VDS

Applying KVL to the output circuit we get,

𝑉𝑆 + 𝑉𝐷𝑆 + 𝐼𝐷 𝑅𝐷 − 𝑉𝐷𝐷 = 0

𝑉𝐷𝑆 = 𝑉𝐷𝐷 − 𝑉𝑆 − 𝐼𝐷 𝑅𝐷 = 𝑉𝐷𝐷 − 𝐼𝐷 𝑅𝑆 − 𝐼𝐷 𝑅𝐷 = 𝑉𝐷𝐷 − 𝐼𝐷 (𝑅𝑆 + 𝑅𝐷 )

46
 EC8353-ELECTRON DEVICES AND CIRCUITS

UNIT-V FEEDBACK AMPLIFIERS AND OSCILLATORS

PART-A
FEEDBACK AMPLIFIERS

1. Define feedback and feedback factor. Define Positive feedback and Negative feedback.

Feedback: The process of injecting a fraction of the output voltage of an amplifier into the input so that it becomes a
part of the input is known as feedback.

Feedback Factor: Feedback factor is defined as the ratio of feedback signal (Voltage/Current) to the amplifier output
which is given as input to the feedback network. Hence, it is also called as feedback ratio and is denoted by β.
𝑉
i.e., 𝛽 = 𝑉𝑓 ; 𝑉𝑓 − 𝐹𝑒𝑒𝑑𝑏𝑎𝑐𝑘 𝑉𝑜𝑙𝑡𝑎𝑔𝑒 𝑉𝑂 − 𝐴𝑚𝑝𝑙𝑖𝑓𝑖𝑒𝑟 𝑂𝑢𝑡𝑝𝑢𝑡 𝑉𝑜𝑙𝑡𝑎𝑔𝑒
𝑜

Positive feedback: If the feedback voltage is in-phase to the input from the source, i.e., feedback signal in-phase with
the original input signal. It is called positive feedback.

Negative feedback: If the feedback voltage is opposite (out of phase) to the input from the source, i.e., feedback signal
opposes the original input signal. It is called negative or degenerative feedback.

Advantages of negative feedback

2. Mention/List the advantages of negative feedback circuits. (Nov/Dec2015), (May/June2016)

➢ In negative feedback amplifiers, the voltage gain of the amplifier remains stable.
➢ High input resistance of a voltage amplifier can be made larger
➢ Low output resistance of a voltage amplified can be lowered
➢ Frequency response improves
➢ Significant improvement in the linearity of operation
➢ The transfer gain of the amplifier with feedback can be stabilized against variation in the h parameters.

3. Write the disadvantages of negative feedback in amplifier circuits and how it can be overcome? (April/May 2015)
The main disadvantage of using negative or degenerative feedback in amplifier is Reduction in Gain.
The required Gain can be attained by increasing the number of amplifier stages

4. What are the effects of a negative feedback?

a) Reduces noise
b) Reduces distortion
c) Reduces gain
d) Increases band width
e) The gain becomes stabilized with respect to changes in the amplifier active device parameters like hfe.
f) The non-linear distortion is reduced there by increasing the signal handling capacity or the dynamic range of the
amplifier.

5. What is the condition required for satisfactory operation of a negative feedback amplifier? (April/May 2019)
The open-loop voltage gain must be much greater than the required closed-loop gain.
𝐴𝑣
Overall Voltage Gain with -ve feedback (Closed-loop Gain), 𝐴𝑣𝑓 = 1+𝛽𝐴
𝑣
𝐴𝑣
𝐴𝑣𝑓 = {𝑆𝑖𝑛𝑐𝑒, 𝛽𝐴𝑣 ≫ 1}
𝛽𝐴𝑣
1
Therefore, 𝐴𝑣𝑓 = 𝛽
{Where 𝐴𝑣 is the voltage gain without a feedback and β is the feedback factor is due to negative feedback the gain is reduced
by factor 1 + 𝛽𝐴𝑣 }
6. With negative feedback the bandwidth of the amplifier increases- True/False?
True.
Bandwidth of amplifier with feedback is greater than bandwidth of amplifier without feedback.

Voltage / current, Series, Shunt feedback

7. Mention the four connections in Feedback.

a. Voltage series feedback.
b. Voltage shunts feedback.
c. Current series feedback.
d. Current shunt feedback.

8. Explain the voltage series feedback.

In this case, the feedback voltage is derived from the output voltage and fed in series with input signal. The input of the
amplifier and the feedback network are in series is also known as series parallel in parallel, hence this configuration is
also known as series parallel feedback network.

9. Explain the voltage shunt feedback.

The input of amplifier and the feedback network are in parallel and known as parallel –parallel feedback network.
This type of feedback to the ideal current to voltage converter, a circulating having very low input impedance and
very low output impedance.

10. Explain the current series feedback.

When the feedback voltage derived from the load current and is fed in series with the input signal, the feedback is said
to be current series feedback, the inputs of the amplifier and the feedback network are in series and the output are also
in series. This configuration is also called as series-series feedback configuration.

11. Explain the current shunt feedback.

When the feedback voltage is derived from the load current and a fed in parallel with the input signal, the feedback is
said to be current shunt feedback. Here in the inputs of the amplifier and the feedback network are in parallel and the
outputs are in series. This configuration is also known as parallel series feedback.

12. Which is the most commonly used feedback arrangement in cascaded amplifier and why? (Nov/Dec-2013-R13)
A voltage series feedback s commonly used in cascaded amplifiers. Since, it has high input impedance and low output
impedance that is needed for cascaded amplifiers.

Positive feedback (Oscillators)

13. What is Oscillator?
Oscillator is an electronic device which generates electrical oscillations (i.e., repeated waveforms) of required frequency.
It is used for converting DC energy into AC energy of the desired frequency.
{An oscillator is a circuit which generates an alternating voltage without any input signal. Instead of external input
signal, it uses feedback path through which it provides its own input signal.
It is used for converting DC energy into AC energy of the desired frequency.}

14. What are sustained Oscillations?

Electrical oscillations in which amplitude does not change with time are called sustained oscillations. It is called as un-
damped oscillations.

15. What is frequency of Oscillations?

The frequency at which circuit satisfies both the Barkhausen conditions i.e. |𝐴𝛽| = 1 and ∠𝐴𝛽 = 0° or 360°
simultaneously is called frequency of oscillations

16. Classify the various oscillators based on the output waveforms, circuit components, operating frequencies and
feedback used.
According to the nature of waveform generated.
1. Sinusoidal or Harmonic Oscillators
2. Non-sinusoidal or Relaxation oscillators
 Based on circuit components. (Nov/Dec 2017)
According to the frequency determining networks,
1. RC oscillators (Phase-shift Oscillator and Wien Bridge Oscillator)
2. LC oscillators (Hartley Oscillator and Colpitts Oscillator)
3. Crystal oscillators

According to the frequency of the Generated Signals

1. AFO (Audio Frequency Oscillators) – upto 20 KHz

2. RFO (Radio Frequency Oscillators) – 20 KHz to 30 MHz
3. VHFO (Very High Frequency Oscillators) - 30 MHz to 300 MHz
4. UHFO (Ultra High Frequency Oscillators) - 300 MHz to 3 GHz
5. MFO (Microwave Frequency Oscillators) – above 3 GHz

17. What are the types of sinusoidal oscillator? [or] Mention the different types of sinusoidal oscillator?
a) RC phase shift Oscillator.
b) Wein bridge Oscillator.
c) Hartley Oscillator
d) Colpitts Oscillator
e) Crystal Oscillator

18. Name two low frequency oscillators?

a) RC phase shift oscillator.
b) Wein bridge oscillator.

19. Name three high frequency oscillators?

The high frequency oscillators are
a) Hartley oscillator.
b) Colpitts oscillator.
c) Crystal oscillator

Condition for oscillations

20. Write the conditions for a Oscillator. (OR)

State. Barkhausen criterion (Barkhausen condition) for sustained oscillations. (Nov/Dec-2012,2011,09),
(May/June2016) (Nov/Dec-2016) (May 2017)
The Barkhausen criterion for obtaining sustained oscillations,
1. The feedback voltage must be in-phase with the input, i.e., total phase-shift around the closed-loop must be 0° or
360°, and
2. Magnitude of the loop gain must be unity i.e., |𝐴𝛽| = 1
Where, A – Open loop Gain of the system & β – Feedback ratio.

Phase Shift and Wien bridge oscillator (RC oscillators)

21. Why an RC phase shift oscillator is called so?

An RC network products 180o phase shift. Hence it is called RC phase shift oscillator.

22. List the advantages of phase shift oscillator. (May/June-2012)

• The phase shift oscillator does not required conductance or transformers.
• It is suitable for the low frequency range i.e., from a few hertz to several 100 kHz. The upper frequency is limited
because the impedance of RC network may become so small that it loads the amplifier heavily.

23. Write the disadvantages of Phase shift oscillator.

1. It is necessary to change the C or R in all the three RC networks simultaneously for changing the frequency of
oscillations. This is practically difficult.
2. It is not suitable for high frequencies.
24. Which oscillator uses both positive and negative feedback?
Wien bridge oscillator.

Hartley and Colpitts oscillators. (LC oscillators)

25. Distinguish between LC and RC oscillator.

LC Oscillator RC Oscillator

It operates at high frequencies It operates at low frequencies

It is suitable for RF only It is suitable for AF only
The frequency is constant.
Frequency is variable
It is known as fixed frequency oscillator.

26. Write the main drawback of LC oscillators.

1. The frequency stability is not very good.
2. They are too bulky and expensive and cannot be used to generate low frequencies.

27. What is the advantage of a colpitts oscillator compared to a phase shift oscillator? (Nov/Dec 2015)
ii) The advantage of colpitts oscillator is the frequency of oscillation is very high.
iii) We can vary the frequency of oscillation.

Crystal oscillators.

28. What is piezo electric effect? (May/June-2013)

The piezo electric crystal exhibits a property, that is, if a mechanical stress is applied across one face, an electrical potential is
developed across the opposite face. The inverse is also true. This phenomenon is called piezo-electric effect.

29. Why Quartz crystal is commonly used in crystal oscillator?

Quartz crystals are generally used in crystal oscillator because of their great mechanical strength, simplicity of manufacture and
abeyance to the piezo electric effect accurately.

30. What are the advantages of crystal oscillators? (NOV/DEC 2012)

The advantages of crystal oscillators are
a) Excellent frequency stability.
b) High frequency of operation
c) Automatic amplitude control.
d) It is suitable for only low power circuits
e) Large amplitude of vibrations may crack the crystal.
f) It large in frequency is only possible replacing the crystal with another one by different frequency.

31. An oscillator operating at 1 MHz has a stability of 1 in 10 4. What will be the minimum value of frequency generated?
(April/May 2019)
The typical frequency stability of oscillators that do not use CRYSTAL is about 1 in 104.
The minimum value of frequency generated might be 100KHz or lower than 1MHz for the oscillator
operating at 1MHz.
{If the crystal is used, the frequency stability can be improved to better than 1 in 106, which gives a ±1 Hz
variation in the output of a 1 MHz oscillator.}

32. How does an oscillator differ from an amplifier? (or) Differentiate oscillator & amplifier. [Nov/Dec 2013] [Nov/Dec 2016]

S.No. Oscillators Amplifiers

1 They are self-generating circuits. They are not self-generating circuits.
They generate waveforms like sine, square and triangular They need a signal at the input and they just increase
waveforms of their own without having input signal. the level of the input waveform.
2 It has infinite gain It has finite gain
3 Oscillator uses positive feedback. Amplifier uses negative feedback.
33. Compare RC Phase-Shift Oscillators and Wien Bridge Oscillator.

34. Classification of Oscillators

 PART-B
Advantages of negative feedback & positive feedback

1. What is meant by feedback? What are the types of feedback and effects of negative feedback?
(May/June-2012) (Nov/Dec 2017)

Negative feedback
If β is negative, the voltage feedback subtracts from the input yielding a lower output and reduced voltage
gain. Hence this feedback is known as negative feedback.

Positive feedback
If the phase of the voltage feedback is such as to increase the input, then β is positive and the result is
positive feedback.

Increase Stability:
The voltage gain due to a negative feedback is given by

𝐴𝑣
𝐴𝑣𝑓 = … … … … … . . (1)
1+𝛽𝐴𝑣

Where 𝐴𝑣 is the voltage gain without a feedback and β is the feedback factor is due to negative feedback
the gain is reduced by factor 1 + 𝛽𝐴𝑣

𝐴𝑣 1
If 𝛽𝐴𝑣 >> 1 then 𝐴𝑣𝑓 = =
𝛽𝐴𝑣 𝛽
Hence the gain of the amplifier with feedback has been stabilized against such problems as ageing of a transistor or
a transistor being re-placed by a transistor with a different value of β.

Sensitivity of transfer gain:

The fractional change in amplification with feedback divided by the fractional change without feedback is
called the sensitivity of the transfer gain

𝑑𝐴𝑣𝑓 (1+𝛽𝐴𝑣 )−𝐴𝑣 𝛽 1

From equ 1 = (1+𝛽𝐴𝑣 ).2
= (1+𝛽𝐴 2
𝑑𝐴𝑣 𝑣 ).

𝑑𝐴𝑣𝑓 1
= ((1+𝛽𝐴 2
𝑑𝐴𝑣 𝑣) )

𝑑𝐴
𝑑𝐴𝑣𝑓 = (1+𝛽𝐴𝑣 2
𝑣)

Dividing both side by 𝐴𝑣𝑓

𝑑𝐴𝑣𝑓 𝑑𝐴𝑣
= ((1+𝛽𝐴 2
𝐴𝑣𝑓 𝑣 ) ).𝐴𝑣𝑓
 𝐴𝑣
Instead of 𝐴𝑣𝑓 𝑠𝑢𝑏 in above equation
1+𝛽𝐴𝑣

𝑑𝐴𝑣𝑓 𝑑𝐴𝑣
= 𝐴𝑣
𝐴𝑣𝑓 ((1+𝛽𝐴𝑣 )2 ).( )
1+𝛽𝐴𝑣

𝑑𝐴𝑣
=
𝐴𝑣 (1+𝛽𝐴𝑣 )

Taking absolute value of the resultant equation we get

𝑑𝐴𝑣𝑓 1 𝑑𝐴𝑣
= |1+𝛽𝐴 | | | … … … … … . .3
𝐴𝑣𝑓 𝑣 𝐴𝑣

𝑑𝐴𝑣𝑓
| |
𝐴𝑣𝑓 1
Sensitivity= 𝑑𝐴 = |1+𝛽𝐴 | … … … … … . .4
| 𝑣| 𝑣
𝐴𝑣

The densitivity is reciprocal of sensitivity. Hence

𝐷 = 1 + 𝐴𝑣 β … … … … … … . .5
Frequency distortion
From equ 1 we find that for a negative feedback amplifier having 𝐴𝑣 β>> 1 the gain withfeedback is
𝐴𝑣𝑓 =1/β. If the feedback network does not contain any reactive elements the gain is not function of frequency.

Reduction in noise
There are many sources of noise is an amplifier. If the noise present at the output is N and the amplifier
gain is A. then the noise present in the amplifier with negative feedback is

𝑁
N1 = 1+𝛽𝐴 .
𝑣

Reduction in distortion
Let us assume that the distortion in the absence of feedback is D. Because the effect of feedback the
distortion present at the input is equal to

𝐷
𝐷𝑓 = 1+𝛽𝐴
𝑣

Bandwidth
If the bandwidth of an amplifier without feedback is given by

Bwf=BW(1+β𝐴𝑣 )

In curve a source the frequency response of an amplifier without feedback when a negative feedback is
introduced the gain of the amplifier decreases.
 Frequency response of an amplifier with and without feedback

Obtain curve C. from fig we can observe that there is decrease in the lower cutoff frequency and increase in upper
cutoff frequency hence the bandwidth increases. Therefore β increases Bandwidth also increases Loop Gain
A loop gain is used to describe the product of voltage gain 𝐴𝑣 and feedback factor β. The amount of
feedback introduced into an amplifier may be expressed in decibels according to the following definition.
F=feedback in db
𝐴𝑣𝑓
= 20 log
𝐴𝑣
1
= 20 log
1 + 𝛽𝐴𝑣

2. Advantages of Negative feedback in amplifiers. (Nov/Dec 2018)

The advantages of negative feedback in amplifiers are listed as follows.
1. The negative feedback amplifiers, the voltage gain of an amplifier remains stable.
2. It reduces the non-linear distortion produced in large signal amplifiers.
3. It improves the frequency response of the amplifier.
4. It increases the stability of the circuit.
5. Negative feedback increases the input impedance and decreases the output impedance of the amplifier.
6. It decreases the noise voltage in the amplifier.
7. Negative feedback amplifier is less sensitive to variations in amplifier parameters.
8. It increases the amplifier bandwidth.
9. The input and output impedances of feedback amplifier can be adjusted to desired value.
10. It has less phase, amplitude and frequency distortion.
11. Amplifier with negative feedback operates linearly.
12. Operating point of amplifier can be stabilized.
3. With proper mathematical derivation, proven that bandwidth increases in a negative feedback amplifier.
(April/May 2019)

The negative feedback increases amplifier bandwidth which can be proven mathematically as
below
TYPES OF NEGATIVE FEEDBACK AMPLIFIER

4. Explain the various types of feedback amplifier (May 2017)

(OR)
With a neat block diagram, explain the operation of Current Shunt Feedback Amplifier.
(OR)
Determine Rif, Rof, Av, Avf for the following feedback amplifier
A. Voltage series feedback amplifier (Series-Shunt feedback amplifier) (Nov/Dec 2016)
(May 2017)
B. Current Series Feedback Amplifier (Shunt-Series feedback amplifier)
C. Current Shunt Feedback Amplifier (Series-Series feedback amplifier) (May 2017)
D. Voltage Shunt Feedback Amplifier (Shunt-Shunt feedback amplifier)
(OR)
Discuss the effect of voltage series feedback and derive the expression for input resistance, output
resistance and voltage gain.
(OR)
Discuss about the following feedback configurations of amplifiers and obtain the feedback factor and
closed loop gain. (April/May 2018-R13)
A. Shunt-Shunt Feed Back
B. Series-Series Feed Back
C. Shunt-Series Feed Back
D. Series-Shunt Feed Back

Feedback amplifier, the output signal sampled may be either voltage or current and sampled signal can be
mixed either is series or in shunt with the input

The four types of amplifiers, they are

➢ Voltage series feedback amplifier (Series-Shunt feedback amplifier) (Nov/Dec 2016) (May 2017)
➢ Current Series Feedback Amplifier (Shunt-Series feedback amplifier)
➢ Current Shunt Feedback Amplifier (Series-Series feedback amplifier) (May 2017)
➢ Voltage Shunt Feedback Amplifier (Shunt-Shunt feedback amplifier)

(A) Voltage Series Amplifier:

With proper mathematical derivation, proven that output resistance reduces in a negative feedback
amplifier. Assume a series shunt feedback scheme. (April/May 2019)

• Ri – input resistance
• Rs – source resistance
• RL – load resistance
• RO – output resistance
• AV – voltage gain
• Ri >> RS then Vi = Vs
• RL >> Ro then Vo = AVVi = Av Vs
• Amplifier provides a voltage output proportional to the voltage input
• The proportionality factor does not depend on magnitudes of the source an load resistance
• Hence it is called voltage amplifier

Feedback Topology

Input resistance

Step 1: equivalent circuit

Step 2: obtain expression for VS

Applying KVL to the input side we get,
V S – Ii – V f = 0 ⸫ Vs = Ii Ri + Vf = Ii Ri + βVo
⸫ Vf = βVo

Step 3: obtain expression for Vo in terms of Ii

The output voltage Vo is given as
𝐴𝑉 𝑉𝑖 𝑅𝐿 𝐴𝑣 𝑅𝐿
𝑉𝑜 = = 𝐴𝑉 𝑉𝑖 𝑤ℎ𝑒𝑟𝑒, 𝐴𝑣 =
𝑅𝑂 + 𝑅𝐿 𝑅𝑜 + 𝑅𝐿
Vo = Av Ii Ri ⸫ Vi = Ii Ri
 Step 4: obtain expression for Rif
Substituting value of V0 from above equation we get
VS = Ii Ri + βAv Ii Ri ⸫ Rif = Vs / Ii = Ri + βAv Ri
Rif = Ri (1+βAv)

Output Resistance
Step 1: Equivalent circuit

Step 2: obtain expression for I in terms of V

Applying KVL to the output side we get
𝑉−𝐴𝑉 𝑉𝑖
Av Vi + IR0 –V = 0 ⸫𝐼=
𝑅0

The input voltage is given as

Vi = - Vf = -βV ⸫Vs = 0
Substituting the Vi from above equation we get
𝑉 + 𝐴𝑣 𝛽𝑉 𝑉(1 + 𝛽𝐴𝑉 )
𝐼= =
𝑅0 𝑅0
Step 3: obtain expression for Rof
𝑉 𝑅𝑜
𝑅𝑜𝑓 = 𝑅𝑜𝑓 =
𝐼 (1 + 𝛽𝐴𝑣 )

Step 4: obtain expression for Rof’

𝑅𝑂
𝑅𝑂𝑓 𝑋 𝑅𝐿 ( ) 𝑋 𝑅𝐿
’ 1+𝛽𝐴𝑉
R of = Rof || RL = = 𝑅𝑂
𝑅𝑂𝑓 + 𝑅𝐿 + 𝑅𝐿
(1+𝛽𝐴𝑉 )

RO RL RO RL
= =
RO +RL (1+βAV ) RO +RL +βAV RL

Dividing numerator and denominator by (Ro + RL)

 𝑅𝑜 𝑅𝐿
′ 𝑅𝑜 + 𝑅𝐿 𝑅𝑜 𝑅𝐿 𝐴𝑣 𝑅𝐿
𝑅𝑜𝑓 = ⸫𝑅𝑜′ = 𝑎𝑛𝑑 𝐴𝑣 =
𝛽𝐴𝑣 𝑅𝐿 𝑅𝑜 + 𝑅𝐿 𝑅𝑜 + 𝑅𝐿
1+
𝑅𝑜 + 𝑅𝐿

′
𝑅𝑜′
𝑅𝑜𝑓 =
1 + 𝛽𝐴𝑣

(B)Current Series Amplifier:

• Ri – input resistance
• Rs – source resistance
• RL – load resistance
• RO – output resistance
• AI – current gain

• Rs >> Ri and Ii = Is
• Ro >> RL IL = AI Ii
• Amplifier provides a current output proportional to the current input
• The proportionality factor does not independent on source and load resistance
• Hence it is called current amplifier
Feedback Topology

Input Resistance
Step 1: equivalent circuit
 Step 2: obtain expression for VS
Applying KVL to the input side we get,
VS – Ii Ri – Vf = 0 ⸫ Vs = Ii Ri + Vf = Ii Ri + βIo
⸫ Vf = βIo

Step 3: obtain expression for Io in terms of Vi

The output current Io is given by

𝐺𝑚 𝑉𝑖 𝑅𝑜 𝐺𝑚 𝑅𝑜
𝐼𝑜 = = 𝐺𝑀 𝑉𝑖 where 𝐺𝑀 =
𝑅𝑜 +𝑅𝐿 𝑅𝑜 +𝑅𝐿

Step 4: obtain expression for Rif

Substituting value of Io from above equation

VS = Ii Ri + β GM Vi = Ii Ri + β GM Ii Ri {Since, Vi = Ii Ri}

Rif = Vs / Ii = Ri (1+ β GM)

Output Resistance

Step 1: equivalent circuit

Step 2: obtain expression for I in terms of V

Applying KVL to the output node we get

𝑉
𝐼= − 𝐺𝑚 𝑉𝑖
𝑅𝑜

The input voltage is given as Vi = -Vf = - β Io = β I ⸫ Io = - I

Substituting value of Vi from above equation we get

𝑉 𝑉
𝐼 = 𝑅 − 𝐺𝑚 β I = 𝐼 + 𝐺𝑚 βI = I(1 + 𝐺𝑚 β)
𝑜 𝑅𝑜
 Step 3: obtain expression for Rof

𝑉
𝑅𝑜𝑓 = = 𝑅𝑜 (1 + 𝐺𝑚 β)
𝐼

′
𝑅𝑜𝑓 𝑋 𝑅𝐿
𝑅𝑜𝑓 = 𝑅𝑜𝑓 ||𝑅𝐿 =
𝑅𝑜𝑓 + 𝑅𝐿

𝑅𝑜 (1 + β𝐺𝑚 )𝑅𝐿 𝑅𝑜 𝑅𝐿 (1 + β𝐺𝑚 )

= =
𝑅𝑜 (1 + β𝐺𝑚 ) + 𝑅𝐿 𝑅𝑜 + 𝑅𝐿 + β𝐺𝑚 𝑅𝑜

Dividing numerator and denominator by Ro + RL we get

𝑅𝐿 𝑅𝑜 (1 + β𝐺𝑚 )
𝑅𝑜 + 𝑅𝐿
𝑅𝑓𝑜 =
β𝐺𝑚 𝑅𝑜
1+𝑅 +
𝑜 𝑅𝐿

′
𝑅𝑜′ (1 + β𝐺𝑚 ) 𝑅𝑜 𝑅𝐿 𝐺𝑚 𝑅𝑜
𝑅𝑜𝑓 = ⸫𝑅𝑜′ = 𝑎𝑛𝑑 𝐺𝑀 =
1 + β𝐺𝑚 𝑅𝑜 + 𝑅𝐿 𝑅𝑜 + 𝑅𝐿

(C) Voltage Shunt Amplifier

• Ri << Rs and Ro << Rs’

• Since Ri << Rs’
• Ii = Is and Ro << RL ,
Vo = Rm Is
• Where Rm = Vo / Is is
the transfer or mutual
resistance

Feedback Topology
Input Resistance

Step 1: Equivalent Circuit

Step 2: obtain expression for Is

Applying KCL at input node we get

Is = Ii + If = Ii + β Vo ⸫ If = β Vo

Step 3: obtain expression for Rif

The output voltage Vo is given by

𝑅𝑚 𝐼𝑖 𝑅𝑜 𝑅𝑚 𝑅𝑜
𝑉𝑜 = = 𝑅𝑀 𝐼𝑖 where 𝑅𝑀 =
𝑅𝑜 +𝑅𝐿 𝑅𝑜 +𝑅𝐿

Step 4: obtain expression for Rif

Substituting value of Vo from above equation we get

Is = Ii + β RM Ii = Ii (1+ β RM)

The input resistance with feedback Rif is given by

𝑉𝑖 𝑉𝑖 𝑉𝑖
𝑅𝑖𝑓 = = ⸫ 𝑅𝑖 =
𝐼𝑠 𝐼𝑖 (1+β𝑅𝑀 ) 𝐼𝑖

𝑅𝑖
⸫ 𝑅𝑖𝑓 =
(1+β𝑅𝑀 )
Output Resistance

Step 1: Equivalent Circuit

Step 2: obtain expression for I in terms of V

Applying KVL to the output side we get

𝑉−𝑅𝑚 𝐼𝑖
Rm Ii + I Ro – V =0 ⸫𝐼=
𝑅𝑜

The input current is given as

Ii = - If = - β V

Substituting Ii in above equation we get

𝑉+𝑅𝑚 β V 𝑉(1+𝑅𝑚 β)
𝐼= =
𝑅𝑜 𝑅𝑜

Step 4: obtain expression for 𝑹′𝒐𝒇

𝑅𝑜 𝑋 𝑅𝐿
′
𝑅𝑜𝑓 𝑋 𝑅𝐿 1 + 𝑅𝑚 β 𝑅𝑜 𝑅𝐿
𝑅𝑜𝑓 = 𝑅𝑜𝑓 ||𝑅𝐿 = = =
𝑅𝑜𝑓 + 𝑅𝐿 𝑅𝑜 𝑅𝑜 + 𝑅𝐿 (1 + 𝑅𝑚 β)
+ 𝑅𝐿
1 + 𝑅𝑚 β

Dividing numerator and denominator by (Ro + RL) we get

𝑅𝑜 𝑅𝐿
′ 𝑅𝑜 + 𝑅𝐿
𝑅𝑓𝑜 =
β𝑅𝑚 𝑅𝐿
1+
𝑅𝑜 + 𝑅𝐿

′ 𝑅𝑜′ 𝑅𝐿 𝑋 𝑅𝑜𝑓 𝑅𝑚 𝑅𝐿
𝑅𝑓𝑜 = where 𝑅𝑜′ = 𝑎𝑛𝑑 𝑅𝑀 =
1+β𝑅𝑀 𝑅𝐿 +𝑅𝑜𝑓 (𝑅𝑜 +𝑅𝐿 )
(D) Current Shunt Amplifier:

• Ri << Rs and Ro <<

Rs’
• Since Ri << Rs’
• Ii = Is and Ro <<
RL , Vo = Rm Is
• Where Rm = Vo / Is
is the transfer or
mutual resistance
Feedback Topology

Input Resistance
Step 1: Equivalent Circuit

Step 2: obtain expression for Is

Applying KCL to the input node we get

Is = Ii + If = Ii + β Io ⸫ If = β Io

Step 3: obtain expression for Io in terms of Ii

𝐴𝑖 𝐼𝑖 𝑅𝑜 𝐴𝑖 𝑅𝑜
𝐼𝑜 = = 𝐴𝐼 𝐼𝑖 where 𝐴𝐼 =
𝑅𝑜 +𝑅𝐿 𝑅𝑜 +𝑅𝐿

Step 4: obtain expression for Rif

Substituting value of Io in above equation we get

Is = Ii + β AI Ii = Ii (1+ β AI)

The input resistance with feedback is given as

 𝑉𝑖 𝑉𝑖
𝑅𝑖𝑓 = =
𝐼𝑠 𝐼𝑖 (1 + β 𝐴I )

𝑅𝑖
𝑅𝑖𝑓 =
(1 + β𝐴𝐼 )

Output Resistance
Step 1: Equivalent Circuit

Step 2: obtain expression for I in terms of V

Applying KCL to the output node we get

𝑉
𝐼= − 𝐴𝑖 𝐼𝑖
𝑅𝑜

The input current is given as

Ii = - If = - β Io ⸫ Is = 0

Ii = β I ⸫ I = - Io

Substituting value of Ii in above equation we get

𝑉 𝑉
𝐼= − 𝐴𝑖 β I ⸫ = 𝐼 + 𝐴𝑖 β = I (1 + β𝐴𝑖 )
𝑅𝑜 𝑅𝑜

Step 3: obtain expression for Rof

′
𝑅𝑜𝑓 𝑋 𝑅𝐿
𝑅𝑜𝑓 = 𝑅𝑜𝑓 ||𝑅𝐿 =
𝑅𝑜𝑓 + 𝑅𝐿

𝑅𝑜 (1 + β𝐴𝑖 )𝑅𝐿 𝑅𝑜 𝑅𝐿 (1 + β𝐴𝑖 )

= ⸫ =
𝑅𝑜 (1 + β𝐴𝑖 ) + 𝑅𝐿 𝑅𝑜 + 𝑅𝐿 + β𝐴𝑖 𝑅𝑜

Dividing numerator and denominator by (Ro + RL) we get

 𝑅𝑜 𝑅𝐿 (1 + β𝐴𝑖 )
′ 𝑅𝑜 + 𝑅𝐿
𝑅𝑜𝑓 =
β𝐴𝑖 𝑅𝑜
1+
𝑅𝑜 + 𝑅𝐿

′
𝑅𝑜′ (1 + β𝐴𝑖 )
𝑅𝑜𝑓 =
(1 + β𝐴𝐼 )
𝑅𝑜 𝑅𝐿 𝐴𝑖 𝑅𝑜
𝑅𝑜′ = 𝑎𝑛𝑑 𝐴𝐼 =
𝑅𝑜 +𝑅𝐿 𝑅𝑜 +𝑅𝐿

OSCILLATORS:

5. Explain the construction and working of the following oscillators and derive the expression for
frequency of oscillation. Also, write about advantages and disadvantages.
A. Phase-Shift Oscillator (RC type Oscillator)
B. Wein Bridge Oscillator (RC type Oscillator)
C. Hartley Oscillator (LC type Oscillator)
D. Colpitts Oscillator (LC type Oscillator)
E. Crystal Oscillator

(A) RC Phase Shift Oscillator:

Explain the construction and working of RC Phase-Shift oscillator and derive the expression for frequency
of oscillation.

• It consists of an amplifier and feedback network consisting of resistors and capacitors.

• An amplifier can be BJT, FET or operational amplifier.

Analysis of RC circuit:
• In this circuit output is taken across resistor R.

1
• The capacitive reactance XC is given by 𝑋𝐶 = 2𝜋𝑓𝐶 Ω where f is frequency of the input.
• The total impedance of the circuit is,
1
𝑍 = 𝑅 − 𝑗𝑋𝐶 = 𝑅 − 𝑗 ( ) Ω
2𝜋𝑓𝐶
 = |𝑍| < −Ф0 Ω
• The current ‘I’ flowing in the circuit is,
𝑉𝑖 < 00 𝑉𝑖 < 00 𝑉𝑖
𝐼= = 0
= | | < +Ф0 𝐴
𝑍 |𝑍| < −Ф 𝑍

𝑋𝐶
|𝑍| =√𝑅 2 + 𝑋𝐶2 𝑎𝑛𝑑 Ф = tan−1
𝑅
• In this equation the current ‘I’ leads input voltage by angle Ф
• The output voltage is drop across R hence VO=VR=IR
• The output voltage is in phase with current hence it leads input voltage by angle Ф
• Thus, RC circuit introduces a phase shift Ф between input and output which depends on R, C and frequency f.

RC Feedback Network for phase shift oscillator:

• In RC phase shift oscillator, amplifier introduces a phase shift of 1800
• Thus, the feedback network must introduce a phase shift of 1800 to satisfy Barkhausen condition.
• The RC feedback network consists of three RC sections, with each RC section contributing 600 phase-shift.
• Hence in RC phase shift oscillator, the feedback network consists of three RC sections are shown in fig.
• In all the three sections, resistance values and capacitance values are same so that at a particular frequency,
each section produces precisely 600 phase-shift. This is the operating frequency of oscillator.

Transistorized RC phase shift oscillator:

• The RC phase shift oscillator uses BJT amplifier stage which is single stage amplifier in common emitter
configuration.
• A phase shift network has three RC sections
• The output of CE amplifier is connected as input to the RC phase shifting network
• The output of RC phase shifting network is connected as input to the amplifier
• Due to common emitter amplifier it introduces a phase shift of 1800 between its input and output
• The RC phase shift network contributes further 1800 phase shift so that phase shift around a loop is 3600
 • From the fig. neglecting R1 and R2 we can write hie= input impedance of amplifier stage
• Thus, to have all three resistance values in three RC section equal, resistance in the last section is selected
as R3 so that R3+hie=R
R3 + hie = R i.e R3 = R- hie ------------- eq. 1
• If R1 and R2 are not neglected then, R3 = R- [R1 || R2 || hie] ----- eq. 2
• When gain A of the amplifier stage and feedback factor β are adjusted to give |Aβ| = 1, then the circuit
works as an oscillator, satisfying both Barkhausen condition.

Derivation for frequency of oscillation:

• Replacing the transistor by its approximate h-parameter model, the equivalent circuit of RC
phase shift oscillator is shown in fig.

• It is known that R = hie + R3 and replace current source by equivalent voltage source.
𝑅𝐶
• The ratio of resistance RC to R is K. =𝐾
𝑅
• The modified equivalent circuit is shown below
• Applying KVL to the three loops
1
𝐼1 𝑅𝐶 − 𝐼 − 𝑅(𝐼1 − 𝐼2 ) − ℎ𝑓𝑒 𝐼𝑏 𝑅𝑐 = 0 𝑎𝑛𝑑 𝑢𝑠𝑒 𝑅𝐶 = 𝑘 𝑅
𝑗𝜔𝐶 1
1
⸫ 𝐼1 [𝑘𝑅 + 𝑅 + ] + 𝐼2 𝑅 = ℎ𝑓𝑒 𝐼𝑏 𝑘 𝑅 ------ eq. 3
𝑗𝜔𝐶
1 1
− 𝐼2 − 𝑅(𝐼2 − 𝐼1 ) − 𝑅(𝐼2 − 𝐼3 ) = 0 𝑖. 𝑒 𝐼1 𝑅 − 𝐼2 (2𝑅 + ) + 𝐼3 𝑅 = 0 ---- eq. 4
𝑗𝜔𝐶 𝑗𝜔𝐶
1 1
− 𝐼3 − 𝐼3 𝑅 − 𝑅(𝐼3 − 𝐼2 ) = 0 𝑖. 𝑒 𝐼2 𝑅 − 𝐼3 (2𝑅 + ) = 0 ---- eq. 5
𝑗𝜔𝐶 𝑗𝜔𝐶
• Using jω = s and Cramers’s rule
1
−(𝑘 + 1)𝑅 − +𝑅 0
𝑠𝐶
| 1 |
𝐷= 𝑅 −2𝑅 − 𝑅
| 𝑠𝐶 |
1
0 𝑅 −2𝑅 −
𝑠𝐶
• Solving the determinant, we get,
𝑠3 𝐶 3 𝑅 3 (3𝑘+1)+𝑠2 𝐶 2 𝑅 2 (4𝑘+6)+𝑠𝑅𝐶(5+𝑘)+1
𝐷 = −{ } ---- eq. 6
𝑠3 𝐶 3

• To find I3, find D3 as,

1
−(𝑘 + 1)𝑅 − 𝑅 ℎ𝑓𝑒 𝐼𝑏 𝑘𝑅
𝑠𝐶
𝐷3 = | 𝑅 −2𝑅 −
1
0 | = 𝑘𝑅3 ℎ𝑓𝑒 𝐼𝑏 ------ eq. 7
𝑠𝐶
0 𝑅 0

𝐷3 −𝑘𝑅 3 ℎ𝑓𝑒 𝐼𝑏 𝑠3 𝐶 3
𝐼3 = = ------- eq. 8
𝐷 𝑠3 𝐶 3 𝑅 3 (3𝑘+1)+𝑠2 𝐶 2 𝑅 2 (4𝑘+6)+𝑠𝑅𝐶(5+𝑘)+1

I3 = Output current of the feedback circuit

Ib = Input current of the amplifier
IC = hfe Ib = input current of the feedback circuit
 Output of the feedback circuit I3 I3
β = = =
Input to feedback circuit IC hfe Ib

Output of the amplifier I3

A= = = hfe
Input to the amplifier Ib
𝐼3 𝐼3
𝐴𝛽 = ℎ𝑓𝑒 𝑋 = ------- eq. 9
ℎ𝑓𝑒 𝐼𝑏 𝐼𝑏

From equation 8 and 9,

−𝑘𝑅 3 ℎ𝑓𝑒 𝑠 3 𝐶 3
𝐴𝛽 = − − − − − − 𝒆𝒒. 𝟏𝟎
𝑠 3 𝐶 3 𝑅 3 (3𝑘+1)+𝑠 2 𝐶 2 𝑅 2 (4𝑘+6)+𝑠𝑅𝐶(5+𝑘)+1

Using s = jω s2 = j2 ω2 = -ω2, s3 = j3 ω3 = -jω3 and separating the real and imaginary

part we get,

+𝑗𝜔3 𝑘𝑅3 𝐶 3 ℎ𝑓𝑒

𝐴𝛽 =
[1 − 4𝑘𝜔 2 𝐶 2 𝑅2 − 6𝜔 2 𝐶 2 𝑅2 ] − 𝑗𝜔[3𝑘𝜔 2 𝑅3 𝐶 3 + 𝜔 2 𝑅3 𝐶 3 − 5𝑅𝐶 − 𝑘𝑅𝐶

Dividing numerator and denominator by j ω3 R3 C3 and replacing -1/j = +j

𝑘ℎ𝑓𝑒
𝐴𝛽 =
1 4𝑘 6 5 𝑘
−𝑗 { − − } − {3𝑘 + 1 − − 2 2 2}
𝜔 3 𝑅3 𝐶 3 𝜔𝑅𝐶 𝜔𝑅𝐶 2
𝜔𝑅 𝐶 2 𝜔 𝑅 𝐶
Replacing 1/ωRC by α for simplicity
𝑘ℎ𝑓𝑒
𝐴𝛽 = [−3𝑘−1+5𝛼2 ------- eq. 11
+𝑘𝛼 2 ]−𝑗[𝛼 3 −4𝑘𝛼−6𝛼]

To satisfy Barkhausen criterion, <Aβ = 00 hence imaginary part of the denominator term
must be 0

⸫ α3 – 4kα - 6α = 0 i.e. α ( α2 – 4 k – 6 ) = 0

⸫ α2 = 4 k + 6 (α ≠ 0 ) i.e. 𝛼 = √4𝑘 + 6 ------ eq. 12

1 1
⸫ 1/ωRC = √4𝑘 + 6 i.e. 𝜔 = i.e. 𝑓 =
𝑅𝐶√4𝑘+6 2𝜋√4𝑘+6

This is the required frequency of oscillations.

Substituting 𝛼 = √4𝑘 + 6 in equation 11 we get,

𝑘ℎ𝑓𝑒 𝑘ℎ𝑓𝑒
𝐴𝛽 = = 2
−3𝑘 − 1 + (4𝑘 + 6)(5 + 𝑘) 4𝑘 + 23𝑘 + 29
 𝑘ℎ𝑓𝑒
But |𝐴𝛽| = 1 𝑖. 𝑒 | 2
|=1
4𝑘 +23𝑘+29

29
⸫ ℎ𝑓𝑒 = 4𝑘 + 23𝑘 +
𝑘

This is the required hfe for the oscillations.

Minimum value of hfe:

• For satisfying Aβ = 1, the expression for the value of hfe of the transistor used in RC phase
shift oscillator is given by,
29 𝑅𝐶
hfe ≥ 4 k +23 + where k =
𝑘 𝑅
• For minimum hfe, find k for minimum hfe from the expression
𝑑ℎ𝑓𝑒
𝑑𝑘
=0
𝑑 29 29 29
⸫ [4𝑘 + 23 + ] = 0 i.e. 4 − = 0 i.e. 𝑘 2 =
𝑑𝑘 𝑘 𝑘2 4
k = 2.6925 for minimum hfe
using in the expression of hfe,
29
hfe (min) = 4 X 2.6925 + 23 + = 44.54
2.6925
Thus for the circuit to oscillate, the transistor must be selected with hfe greater than 44.54
Advantages:

• The circuit is simple to design

• Can produce output over audio frequency range
• Produces sinusoidal output waveform
• It is fixed frequency oscillator

Disadvantages:

• To vary the frequency, values of R and C of all three sections are to be varied simultaneously which is
practically difficult. Hence frequency cannot be varied
• Frequency stability is poor due to changes in the values of various components due to effect temperature,
aging etc.
(B) WEIN BRIDGE OSCILLATOR: (RC Oscillator)
Explain the working of Wien Bridge Oscillator. Derive the expression for frequency of oscillation and
condition for maintenance of oscillation.
(OR)
Design an oscillator to operate at a frequency of 10 KHz which gives an extremely pure sine
wave output, good frequency stability and highly stabilized amplitude. Discuss the operation
of this oscillator as an audio signal generator.

Construction and operation - (Wien Bridge Oscillator Circuit)

✓ Two stage amplifiers (non-inverting) and feedback network are used in Wien Bridge Oscillator.
✓ Both amplifier and feedback network does not introduce any phase shift i.e. 0° phase-shift around the loop in Wien
Bridge Oscillator.
✓ R1 & C1 in series and R2 & C2 in parallel are frequency sensitive arms.
✓ The output of Amplifier is applied as input to Feedback Network (Vin) between 1 and 3.
✓ The output of Feedback Network (Vf) taken between 2 and 4 is given as input to amplifier.
✓ This Feedback Network is also known as Lead-Lag Network.
 Derive the expression for frequency of oscillation:

Analysis for frequency of oscillation:

1 1 + 𝑗𝜔𝑅1 𝐶1
𝑍1 = 𝑅1 + ⥤ 𝑍1 = (1)
𝑗𝜔𝐶1 𝑗𝜔𝐶1
1
1 𝑅2 × 𝑅2
𝑗𝜔𝐶2
𝑍2 = 𝑅2 ⃦ ⇒ 𝑍2 = 1
⇒ 𝑍2 = (2)
𝑗𝜔𝐶2 𝑅2 + 1 + 𝑗𝜔𝑅2 𝐶2
𝑗𝜔𝐶2
𝑉𝑓 𝑉𝑖𝑛
𝛽= (3) 𝐼= (4)
𝑉𝑖𝑛 𝑍1 + 𝑍2

Sub (6) in (3) 𝑉𝑓 = 𝐼 𝑍2 (5)

𝑍2 𝑆𝑢𝑏 (4)𝑖𝑛 (5) ⥤ 𝑉𝑓 =
𝑍2
𝑉 (6)
⥤ 𝛽= (7) 𝑍1 +𝑍2 𝑖𝑛
𝑍1 + 𝑍2

𝑆𝑢𝑏𝑠𝑡𝑖𝑡𝑢𝑡𝑒 (1) & (2) 𝑖𝑛 (7)

𝑅2
1 + 𝑗𝜔𝑅2 𝐶2
𝛽= (8)
1 + 𝑗𝜔𝑅1 𝐶1 𝑅2
+
𝑗𝜔𝐶1 1 + 𝑗𝜔𝑅2 𝐶2

Simplify the equation (8),

𝑗𝜔𝑅2 𝐶1
𝛽= (9)
(1 − 𝜔 2 𝑅1 𝑅2 𝐶1 𝐶2 ) + 𝑗𝜔(𝑅1 𝐶1 + 𝑅2 𝐶2 + 𝑅2 𝐶1 )

Rationalizing and Simplifying the equation (9),

𝜔2 𝑅2 𝐶1 (𝑅1 𝐶1 + 𝑅2 𝐶2 + 𝑅2 𝐶1 ) + 𝑗𝜔𝐶1 𝑅2 (1 − 𝜔2 𝑅1 𝑅2 𝐶1 𝐶2 )
𝛽= (10)
(1 − 𝜔 2 𝑅1 𝑅2 𝐶1 𝐶2 )2 + 𝜔 2 (𝑅1 𝐶1 + 𝑅2 𝐶2 + 𝑅2 𝐶1 )2

To have zero phase shift, imaginary part of above equation must be zero.

(1 − 𝜔2 𝑅1 𝑅2 𝐶1 𝐶2 ) = 0

𝜔 (𝜔2 𝑅1 𝑅2 𝐶1 𝐶2 ) = 0 but 𝜔 can not be zero. So,

1
𝜔2 𝑅1 𝑅2 𝐶1 𝐶2 = 0 ⇒ 𝜔2 =
𝑅1 𝑅2 𝐶1 𝐶2
 1
⇒𝜔= (11)
√𝑅1 𝑅2 𝐶1 𝐶2

𝟏
𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 𝑜𝑓 𝑊𝑖𝑒𝑛 𝐵𝑟𝑖𝑑𝑔𝑒 𝑂𝑠𝑐𝑖𝑙𝑙𝑎𝑡𝑜𝑟, 𝒇 = Hz (12)
𝟐𝝅√𝑹𝟏 𝑹𝟐 𝑪𝟏 𝑪𝟐

𝐼𝑛 𝑝𝑟𝑎𝑡𝑖𝑐𝑒, 𝑅1 = 𝑅2 = 𝑅 and 𝐶1 = 𝐶2 = 𝐶 hence,

𝟏
𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 𝑜𝑓 𝑊𝑖𝑒𝑛 𝐵𝑟𝑖𝑑𝑔𝑒 𝑂𝑠𝑐𝑖𝑙𝑙𝑎𝑡𝑜𝑟, 𝒇= 𝑯𝒛
𝟐𝝅 𝑹𝑪
Derive the condition for maintenance of oscillation:
1
Case (1): 𝐼𝑓 𝑅1 = 𝑅2 = 𝑅 and 𝐶1 = 𝐶2 = 𝐶 𝑡ℎ𝑒𝑛 𝑢se 𝜔 = 𝐻𝑧 in (10),
𝑅𝐶

we get the magnitude of the feedback network as,

3 3 𝟏 𝟏
𝜷= = = ⇒ 𝜷=
1 2 9 𝟑 𝟑
0+ (3𝑅𝐶)
𝑅2 𝐶 2
As |𝐴𝛽 | ≥ 1 ℎ𝑒𝑛𝑐𝑒 |𝐴| ≥ 3 𝑓𝑜𝑟 𝑊𝑖𝑒𝑛 𝐵𝑟𝑖𝑑𝑔𝑒 𝑂𝑠𝑐𝑖𝑙𝑙𝑎𝑡𝑜𝑟.

Thus, the gain of amplifier stage must be at least 3 to ensure sustained oscillations in Wien Bridge
Oscillator.
1
Case (2): If 𝑅1 ≠ 𝑅2 and 𝐶1 ≠ 𝐶2 then use 𝜔 = 𝑖𝑛 (10) 𝑡ℎ𝑒𝑛
√𝑅1 𝑅2 𝐶1 𝐶2

𝑹𝟐 𝑪𝟏 𝑹𝟏 𝑪𝟏 + 𝑹𝟐 𝑪𝟐 + 𝑹𝟐 𝑪𝟏 𝟐
𝜷= ⇒∴𝑨≥ {∵ |𝐴𝛽| ≥ 1}
𝑹𝟏 𝑪𝟏 + 𝑹𝟐 𝑪𝟐 + 𝑹𝟐 𝑪𝟏 𝑹𝟐 𝑪𝟏

LC OSCILLATORS:
Outline the LC tuned Oscillator and deduce expression for amplifier Gain, feedback Gain
and necessary condition for LC Oscillator in general.
 Analysis of Amplifier stage

Applying KVL,
𝐴𝑉 𝑉𝑖
𝐼=− and 𝑉𝑂 = 𝐼𝑍𝐿
𝑅𝑜 +𝑍𝐿

𝑽𝒐 𝑨𝑽 𝒁𝑳
𝑨= =−
𝑽𝒊 𝑹𝒐 + 𝒁𝑳

Ro – Output impedance of the amplifier stage. A – Gain of amplifier stage.

As, I=0 due to infinite input impedance, Z1 and Z3 appear in series and the
combination in parallel with Z2 as shown in figure.
Analysis of feedback stage
By voltage division in parallel circuit,
𝑉 𝑍
𝑉𝑓 = 𝑍 𝑜+𝑍1
1 3

𝑉𝑓 𝑍1
i.e. 𝛽 = =
𝑉𝑜 𝑍1 +𝑍3

But as feedback network introduces 180°

phase-shift, use negative sign
𝒁𝟏
𝜷=−
𝒁𝟏 + 𝒁𝟑
Types of LC Oscillators:

(C) Hartley Oscillator:

Explain the working of Hartley Oscillator. Derive the expression for frequency of oscillation and condition
for maintenance of oscillation.

Circuit diagram

Construction:
• The Hartley oscillator circuit using BJT as an active device.
• The resistances R1, R2 and RE are biasing resistors
• The RFC is radio frequency chock whose reactance value is very high and high frequency and can be
treated as open circuit. While for d.c operation, it is shorted hence does not cause problems for d.c
operation.
• Due to RFC, the isolation between a.c and d.c operation is achieved. The C1 and C2 are coupling capacitors
while CE is the emitter bypass capacitor. The CE amplifier provides phase shift of 1800.
• In the feedback circuit, as the centre of L1 and L2 is grounded, it provides additional phase shift of 1800.
This satisfies Barkhausen condition. In this oscillator, X1 = ωL1,
X2 = ωL2, X3 = -1/ωC
Analysis:

• For LC oscillator, X1+X2+X3=0

1
⸫ 𝜔𝐿1 + 𝜔𝐿2 − =0
𝜔𝐶

1
i.e 𝜔(𝐿1 + 𝐿2 ) =
𝜔𝑐

1 1
⸫ 𝜔= i.e 𝑓 =
√(𝐿1 + 𝐿2 )𝐶 2𝜋√(𝐿1 + 𝐿2 )𝐶

• The inductance L1+L2 is equivalent inductance denoted as Leq. To satisfy |Aβ| = 1, then hfe of
the BJT used must be L1/L2.
𝐿1
ℎ𝑓𝑒 =
𝐿2
• Practically L1 and L2 are wound on a single core and there exists a mutual inductance M
between them.
In this case, 𝐿𝑒𝑞 = 𝐿1 + 𝐿2 + 2𝑀
1 𝐿1 +𝑀
𝑓= and ℎ𝑓𝑒 =
2𝜋√𝐿𝑒𝑞 𝐶 𝐿2 +𝑀
• If capacitor C is kept variable, frequency can be varied over wide range.

Derivation of frequency of Oscillations

• The output current is collector current which is hfe Ib, where Ib is base current. Assuming coupling
capacitors shorted the capacitor C gets connected between collector and base.
• As emitter is grounded for a.c analysis, L1 is between emitter and base while L2 is between emitter and
collector.
• hie is the input impedance of the transistor. The output current is Ib while input current is hfe Ib. Convert
current source to voltage source.
𝑉𝑂 = ℎ𝑓𝑒 𝐼𝑏 𝑗𝑋𝐿2 = ℎ𝑓𝑒 𝐼𝑏 𝑗𝜔𝐿2

• Total current I is,

−𝑉𝑜
𝐼=
[𝑋𝐿2 + 𝑋𝐶 ] + [𝑋𝐿1 ||ℎ𝑖𝑒 ]
• Negative sign is because direction of I is opposite to the polarities of Vo
1 −𝜔2 𝐿2 𝐶 + 1
𝑋𝐿2 + 𝑋𝐶 = 𝑗𝜔𝐿2 + =
𝑗𝜔𝐶 𝑗𝜔𝐶
𝑗𝜔𝐿1 ℎ𝑖𝑒
𝑋𝐿1 ||ℎ𝑖𝑒 =
𝑗𝜔𝐿1 + ℎ𝑖𝑒
 −ℎ𝑓𝑒 𝐼𝑏 𝑗𝜔𝐿2
⸫𝐼 =
−𝜔 2 𝐿1 𝐶 + 1 𝑗𝜔𝐿1 ℎ𝑖𝑒
+
𝑗𝜔𝐶 𝑗𝜔𝐿1 + ℎ𝑖𝑒
• Using current division rule for parallel elements,
𝑗𝜔𝐿1
𝐼𝑏 = 𝐼 𝑋
𝑗𝜔𝐿1 + ℎ𝑖𝑒

−ℎ𝑓𝑒 𝐼𝑏 𝑗𝜔𝐿2 𝑗𝜔𝐿1

𝐼𝑏 = 𝑋
−𝜔 2 𝐿2 𝐶 + 1 𝑗𝜔𝐿1 ℎ𝑖𝑒 𝑗𝜔𝐿1 + ℎ𝑖𝑒
+
𝑗𝜔𝐶 𝑗𝜔𝐿1 + ℎ𝑖𝑒

𝑗𝜔3 ℎ𝑓𝑒 𝐶𝐿1 𝐿2

⸫1=
−𝑗𝜔3 𝐿1 𝐿2 𝐶ℎ𝑖𝑒 (𝐿1 +𝐿2 )+𝑗𝜔𝐿1 +ℎ𝑖𝑒

𝑗𝜔3 ℎ𝑓𝑒 𝐶𝐿1 𝐿2

⸫ 1 = [ℎ 2 𝐶ℎ 2𝐿
𝑖𝑒 −𝜔 𝑖𝑒 (𝐿1 +𝐿2 )]+𝑗𝜔𝐿1 (1−𝜔 2 𝐶)
• Rationalizing R.H.S of the above equation,

𝜔4 ℎ𝑓𝑒 𝐿21 𝐿2 𝐶(1 − 𝜔2 𝐿2 𝐶) + 𝑗𝜔3 ℎ𝑓𝑒 𝐿1 𝐿2 𝐶[ℎ𝑖𝑒 − 𝜔2 𝐶ℎ𝑖𝑒 (𝐿1 + 𝐿2 )]

1=
[ℎ𝑖𝑒 − 𝜔 2 𝐶ℎ𝑖𝑒 (𝐿1 + 𝐿2 )]2 + 𝜔 2 𝐿21 (1 − 𝜔 2 𝐿2 𝐶)2

• Imaginary part of R.H.S of above equation must be Zero

1
⸫ 1 − 𝜔3 𝐶(𝐿1 + 𝐿2 ) = 0 𝑖. 𝑒 𝜔 = (𝜔3 ℎ𝑓𝑒 ℎ𝑖𝑒 𝐿1 𝐿2 𝐶 ≠ 0)
√𝐶(𝐿1 +𝐿2 )

1 1
𝑓= =
2𝜋√𝐶(𝐿1 + 𝐿2 ) 2𝜋√𝐶𝐿𝑒𝑞
1
• Equating magnitude of both sides of the equation and using 𝜔 = 𝑤𝑒 𝑔𝑒𝑡
√𝐶(𝐿1 +𝐿2 )
𝐿1
ℎ𝑓𝑒 = ℎ𝑓𝑒 𝑟𝑒𝑞𝑢𝑖𝑟𝑒𝑑 𝑓𝑜𝑟 𝑜𝑠𝑐𝑖𝑙𝑙𝑎𝑡𝑖𝑜𝑛
𝐿2
• In practice, L1 and L2 may be wound on a single core so that there exists a mutual
inductance between them denoted as M.
• In such a case, the mutual inductance is considered while determining the equivalent
inductance Leq, Leq = L1+L2+2M
• If L1 and L2 are assisting each other, then sign of 2M is positive while if L1 and L2 are in
series opposition then sign of 2M is negative.
Advantage:
• The frequency can be easily varied by variable capacitor
• The output amplitude remains constant over the frequency range
• The feedback ratio of L1 and L2 remains constant
• It can be operated over wide range of frequency

Disadvantage:
• The output is rich in harmonics hence not suitable for pure sine wave requirement
• Poor frequency stability

Applications:
• Used as local oscillators in TV and radio receivers
• In function generators
• In radio frequency sources

(D) COLPITTS OSCILLATOR:

Explain the working of Colpitts Oscillator. Derive the expression for frequency of oscillation and condition
for maintenance of oscillation.
(OR)
With a neat circuit diagram deduce the necessary condition for oscillations and expression for oscillation
frequency in the case of Colpitts Oscillator.

Construction:

• It uses two capacitive resistances and one inductive reactance in its feedback network.
• The amplifier stage uses BJT in common emitter configuration providing 180o phase shift. The resistance
R1, R2 and RE are the biasing resistors.
• The RFC is radio frequency choke providing insulation between AC and DC operations. The CC1 and CC2
are coupling capacitors. In the feedback circuit, as the center C1 and C2 are grounded, it provides additional
phase shift of 1800, satisfying Barkhausen angle condition.
 −1 −1
• In this oscillator 𝑋1 = 𝑋2 = 𝑋3 = 𝜔𝐿
𝜔𝐶1 𝜔𝐶2
• For LC oscillator, X1+X2+X3=0
1 1 1 1 1
⸫ − − + 𝜔𝐿 = 0 i.e 𝜔𝐿 = [ + ]
𝜔𝐶1 𝜔𝐶2 𝜔 𝐶1 𝐶2
1 𝐶1 𝐶2
⸫𝜔2 = 𝐶 𝐶 where = 𝐶𝑒𝑞
𝐿[ 1 2 ] 𝐶1 +𝐶2
𝐶1 +𝐶2
1 1 𝐶1 𝐶2
⸫ 𝜔= i.e 𝑓 = 𝑎𝑛𝑑 𝐶𝑒𝑞 =
√𝐿𝐶𝑒𝑞 2𝜋√𝐿𝐶𝑒𝑞 𝐶1 +𝐶2

• To satisfy magnitude condition of Barkhausen criterion, the h fe of BJT used is given by

𝐶2
ℎ𝑓𝑒 =
𝐶1

Derivation of Frequency of oscillations

• The equivalent circuit and simplified equivalent circuit.

−𝑗ℎ𝑓𝑒 𝐼𝑏 1 𝑗
𝑉0 = ℎ𝑓𝑒 𝐼𝑏 𝑋𝐶2 = ….. 𝑋𝐶2 = =−
𝜔𝐶2 𝑗𝜔𝐶2 𝜔𝐶2

• The total current drawn I is,

−𝑉0
𝐼=
[𝑋𝐶2 + 𝑋𝐿 ] + [𝑋𝐶1 ||ℎ𝑖𝑒 ]
−𝑗 −𝑗(1 − 𝜔2 𝐿𝐶2 )
𝑋𝐶2 + 𝑋𝐿 = + 𝑗𝜔𝐿 =
𝜔𝐶2 𝜔𝐶2
𝑗
− 𝑋 ℎ𝑖𝑒 −𝑗ℎ𝑖𝑒
𝜔𝐶1
𝑋𝐶1 ||ℎ𝑖𝑒 = =
𝑗
− + ℎ𝑖𝑒 −𝑗 + 𝜔𝐶1 ℎ𝑖𝑒
𝜔𝐶1
𝑗ℎ𝑓𝑒 𝐼𝑏
− [−
𝜔𝐶2 ]
𝐼=
−𝑗(1 − 𝜔 2 𝐿𝐶2 ) −𝑗ℎ𝑖𝑒
−
𝜔𝐶2 −𝑗 + 𝜔𝐶1 ℎ𝑖𝑒
• Using current division rule for parallel elements
 −𝑗
𝜔𝐶1 −𝑗𝐼
𝐼𝑏 = 𝐼 𝑋 =
−𝑗
+ ℎ𝑖𝑒 −𝑗 + 𝜔𝐶1 ℎ𝑖𝑒
𝜔𝐶1
𝑗ℎ𝑓𝑒 𝐼𝑏
𝜔𝐶2 1
𝐼𝑏 = −𝑗 [ ] [ ]
−𝑗(1 − 𝜔 2 𝐿𝐶2 ) −𝑗ℎ𝑖𝑒 −𝑗 + 𝜔𝐶1 ℎ𝑖𝑒
𝜔𝐶2 −𝑗 + 𝜔𝐶1 ℎ𝑖𝑒
−ℎ𝑓𝑒
1 = (1−𝜔2 𝐿𝐶 2 𝐿𝐶 𝐶 ] -------------- 1
2 )+𝑗𝜔ℎ𝑖𝑒 [𝐶1 +𝐶2 −𝜔 1 2

• To have imaginary part of above equation zero

𝐶1 +𝐶2 1
C1+C2-ω2LC1C2 = 0 i.e 𝜔2 = = 𝐶 𝐶
𝐿𝐶1 𝐶2 𝐿[ 1 2 ]
𝐶1 +𝐶2

1 1 𝐶1 𝐶2
𝜔= 𝑎𝑛𝑑 𝑓 = 𝑤ℎ𝑒𝑟𝑒 𝐶𝑒𝑞 =
√𝐿𝐶𝑒𝑞 2𝜋√𝐿𝐶𝑒𝑞 𝐶1 + 𝐶2

• Substituting ω in equation 1 and equating magnitudes of both sides

𝐶2
ℎ𝑓𝑒 =
𝐶1
Advantages:
• Pure output waveform
• Good stability at high frequency
• Improved performance at high frequency
• Wide range of frequency
• Simple construction
•
Disadvantages:
• Difficult to adjust the feedback
• Poor isolation
Applications:
• Its main application is high frequency function generators.
 (E) CRYSTAL OSCILLATOR:
Describe and explain the operation of the crystal oscillator.
(OR)
Can you use Piezo-Electric effect for electric oscillators? If so, explain a
component with such characteristics. Also draw a circuit for the same.
• The crystals are either naturally occurring or synthetically manufactured, exhibiting the piezoelectric effect
• The piezoelectric effect means under the influence of mechanical pressure, the voltage gets generated
across the opposite faces of the crystal
• If the mechanical force is applied in such a way to force the crystal to vibrate the a.c voltage gets generated
across it.
• Every crystal has its own resonating frequency depending on its cut. So under the influence of the
mechanical vibrations, the crystal generates an electrical signal of very constant frequency
• The crystal has a greater stability in holding the constant frequency. The crystal oscillators are preferred
when greater frequency stability is stability
• Quartz is a compromise between the piezoelectric activity of Rochelle salt and the strength of the
tourmaline.
• Quartz is inexpensive and easily available in nature hence very commonly used in the crystal oscillators.

Constructional Details:

• The natural shape of quartz is a hexagonal prism. But for its practical use, it is cut to the rectangular slab.
This slab is then mounted between the two metal plates.

• The metal plates are called holding plates, as they hold the crystal slab in between them.

A.C. Equivalent circuit:

CM – Mounting Capacitance (due to two metal plates
separated by dielectric like crystal slab).
R – Resistance (internal friction loss during vibration)
L – Inductance (indication of inertia of mass of crystal)
C – Capacitor (stiffness during vibrating)

• RLC forms a resonating circuit. The expression for the resonating frequency fr is,
1 𝑄2
𝑓𝑟 = 2𝜋√𝐿𝐶 √1+𝑄2 where Q = Quality factor of crystal

𝜔𝐿
𝑄=
𝑅
 𝑄2
• The Q factor of the crystal is very high, typically 20,000. Value of Q up to 106 also can be achieved. Hence √1+𝑄2
1
factor approaches to unity and we get the resonating frequency as 𝑓𝑟 = 2𝜋
√𝐿𝐶
• The crystal frequency is in fact inversely proportional to the thickness of the crystal.
1
• f α 𝑡 where t = Thickness
• So to have very frequencies, thickness of the crystal should be very small
• The crystal has two resonating frequencies, series resonant frequency and parallel resonant frequency.

Applications
• Watches
• Communication transmitters and receivers

Series and Parallel resonance:

• Series Resonance frequency

1
𝑓𝑠 =
2𝜋√𝐿𝐶

• Parallel Resonance frequency

1
𝑓𝑃 =
2𝜋√𝐿𝐶𝑒𝑞
•
• If we neglect the resistance R, the impedance of the crystal is a reactance jX which depends on the frequency as,

𝑗 𝜔2 − 𝜔𝑠2 Where, ωs = Series resonant

𝑗𝑋 = − frequency
𝜔𝐶𝑀 𝜔 2 − 𝜔𝑝2
ωp = Parallel resonant frequency

• Reactance against frequency is shown in fig.

Crystal Stability:

i. Temperature stability
ii. Long term stability
iii. Short term stability

Types of Crystal Oscillator:

1. Pierce Crystal Oscillator:
2. Miller Crystal Oscillator:

Pierce Crystal Oscillator: Miller Crystal Oscillator:

 Comparison between Crystal and LC Oscillator:

Solved Problems
1. In a Hartley oscillator, if L1=0.2mH, L2=0.3mH and C=0.003µF. Calculate the frequency of oscillations.
[MAY 2012]
Given: L1=0.2mH, L2=0.3mH, C=0.003µF
To find frequency of oscillations f=1/(2π√[(L1+L2) C)] by substituting f=129.949KHz

2. In a RC phase shift oscillator if R1=R2=R3=200KΩ and C1=C2=C3=100PF. Find the frequency of

oscillation? (Apr/May 2018)
Solution:
The frequency of an RC phase shift oscillator is given by
1 1
Fo = Fo = 2𝜋×200×103×100×10−12 ×√6 Fo = 3.248KHZ
2𝜋𝑅𝐶√6

3. In a phase shift oscillator, R1=R2=R3=1 MΩ and C1=C2=C3=68 pF. At what frequency does the circuit
oscillate. (Nov/Dec 2018)
Given that,
For a phase shift oscillator, Resistance, R1 = R2 = R3 = 1 MΩ; Capacitor, C1 = C2 = C3 = 68 pF
Frequency, f = ?
1
Frequency of phase shift oscillator is given by, 𝑓 = 2𝜋𝑅𝐶√6
1 frequency, f = 955.9 Hz
Substituting corresponding values in above equation ,𝑓 = 2𝜋 𝑋 1𝑋106 𝑋 68 𝑋 = 955.9 𝐻𝑧
√6
4. A wien bridge oscillator is used for operation at 10KHz. If the value of the resistor R is 100Kohms, what
is the value of C required?
Solution:
Given: F = 10KHZ, R = 100KΩ, C= ?
The frequency of oscillation is
1 1 1
F =2𝜋𝑅𝐶 C = 2𝜋𝑅𝐹 C= 2𝜋×100×103×10×103

C = 1.591× 𝟏𝟎−𝟏𝟎 F

5. An amplifier has a c urrent gain of 240 and input impedance of 15 k Ω without feedback. If negative
current feedback (mi = 0.015) is applied, what will be the input impedance of the amplifier? (Nov/Dec
2017)

6. Design a Wien bridge oscillator circuit to oscillate at a frequency of 20KHz. (Nov/Dec2015)

Solution:
1
f= f = 20 kHz, Let C = 0.01𝜇𝐹
2𝜋𝑅𝑐
1 1 1
f= , 𝑅= = = 80ohms.
2𝜋𝑅𝑐 2𝜋𝑓𝐶 2×𝜋×20000×0.01×10−6

7. A 1 mH inductor is available. Find the capacitor values of a colpitt’s oscillator so that f=1 MHz and
feedback fraction=0.25 (Nov/Dec 2018)
Solution:
Given that,
For a Colpitts oscillator,
Inductance, L = 1 mH
Resonant frequency, f0 = 1 MHz
Feedback factor, β = 0.25
The resonant frequency of Colpitts oscillator is given by,
1
𝑓0 = − − − −(1)
2𝜋√𝐿𝐶𝑒𝑞
𝐶 𝐶
Where,𝐶𝑒𝑞 = 𝐶 1+𝐶2
1 2
From equation (1),
1
𝐶𝑒𝑞 = 2 2 − − − −(2)
4𝜋 𝑓0 𝐿
𝐶1
Given feedback factor, 𝛽 = = 0.25
𝐶2
C2 = 4C1
Substituting the given specifications in equation (2)
 1
𝐶𝑒𝑞 =
4𝜋 2 (106 )2 𝑋 10−3
𝐶1 𝐶2
= 2.533 𝑋 10−11
𝐶1 + 𝐶2
4𝐶12
= 2.53 𝑋 10−11
5𝐶1
C1 = 3.166 X 10-11 = 31.66 pF

From C2 = 4C1,
C2 = 4 X (3.166 X 10-11)

C2 = 126.65 pF

8. The overall gain of a multistage amplifier is 140. When negative voltage feedback is applied the gain is
reduced to 17.5 find the fraction of the output that is feedback to the input. (Nov/Dec 2018)
Given that,
For a multistage feedback amplifier,
Overall gain, AV = 140
Feedback gain, Avf = 17.5
Feedback fraction, β = ?
Voltage gain of negative feedback amplifier is defined as,
𝐴𝑣 40
𝐴𝑣𝑓 = 17.5 =
1 + 𝐴𝑣 𝛽 1 + 140𝛽
17.5 + 2450 β = 140
1
𝛽 = 20 = 0.05
β = 0.05

9. In colpitts oscillator C1 = 1nF and C2 = 100nF. If the frequency of oscillation is 1 kHz find the value of
inductor. Also find the minimum gain required for obtaining sustained oscillations. (May / Jun 2016)
Given data:

C1 = 1nF, C2 = 100nF, Frequency of oscillation f = 100 kHz.

Formulae used:

1 𝐶1+𝐶2 𝐶1
𝑓 = 2𝑛 √𝐿1𝐶1𝐶2 , 𝐴𝑉 = 𝐶2

𝐶1+𝐶2 101×10−6
Frequency of oscillations 𝐿 = 4𝑛2 𝑓2𝐶1𝐶2 = 4𝑛2 ×(10×1000)2×100×10−12
𝑟

101×106 101
= 4𝑛2 ×(100000)2 = 3.99 × 10−5 = 25.634 × 10−5 𝐻 = 256.34𝜇𝐹

𝐶1 1
𝐴𝑉 > = = 0.01𝑛𝐹
𝐶2 100
10. Design a RC phase Shift Oscillator to generate 5KHz sine wave with 20 V peak to Peak amplitude.
Assume hfe=𝜷 = 𝟏𝟓𝟎, 𝑪 = 𝟏. 𝟓𝒏𝑭, hre=1.2KΩ(Nov.Dec 2016)
1 1 1
𝑓= ; 5 × 103 = −9 𝑅=
2𝜋𝑅𝑐√6 2𝜋×1.5×10 √6×𝑅 2𝜋×1.5×10 ×√6×5×103
−9

𝑅 = 8.67 𝑘 𝛺
11. In Colpitts Oscillator, the desired frequency is 500 KHz. Find the value of L. Assume C= 1000pF.
(Apr/May 2018)

12. When negative voltage feedback is applied to an amplifier of gain 100, the overall gain falls to 50.
Calculate the fraction of the output voltage fedback. If this fraction is maintained, calculate the value of
the amplifier gain required if the overall stage gain is to be 75. (Nov/Dec 2017)
13. In Colpitts oscillator, C1 = C2 =C and L=100 X 10-6 H. The frequency of oscillation is 500 KHz.
Determine the value of C. (Apr/May 2018)

14. An amplifier in required with a voltage gain of 100 which does not vary by more that 1%. If it is to use
negative feedback with a basic amplifier the voltage gain of which vary by 20%, find the minimum
voltage gain required and the feedback factor. (Nov/Dec 2018)
Solution:
Closed loop voltage gain of amplifier, Af is defined as,
𝐴𝑚
𝐴𝑓 = − − − − − (1)
1 + 𝐴𝑚 𝛽
𝐴𝑚
100 =
1 + 𝐴𝑚 𝛽
𝐴𝑚 = 100 + 100 𝐴𝑚 𝛽 − − − − − (2)
Since, feedback voltage gain, Af does not vary more than 1% and amplifier gain varies by 20% equation (1) can
be written as,
0.8 𝐴𝑚
99 =
1 + 0.8 𝐴𝑚 𝛽
0.8 𝐴𝑚 = 99 + 79.2 𝐴𝑚 𝛽 − − − − − (3)
Multiplying equation (1) with 0.792 or both sides,
0.792 𝐴𝑀 = 79.2 + 79.2 𝐴𝑚 𝛽 − − − − − (4)
Subtracting equation (3) and (4),
19.8
0.008 Am = 19.8; 𝐴𝑚 = Am = 2475
0.008
Substituting Am in equation (2),
2475 = 100 + 100 X 2475 X β
2475 − 100
𝛽= β = 0.0096
2475 𝑋 100

⸫ Feedback factor, β = 0.0096 and minimum voltage gain Am = 2475 V.

-------------------------------------------------------------------------------------------------------------------------------------------------
 Additional Important Questions:

6. Discuss the effect for the following negative feedback amplifiers and derive the expression for input
resistance, output resistance and voltage gain for common emitter amplifier.
A. VOLTAGE SERIES FEEDBACK
B. VOLTAGE SHUNTFEEDBACK
C. CURRENT SERIES FEEDBACK
D. CURRENT SHUNT FEEDBACK

(A) VOLTAGE SERIES FEEDBACK

Draw circuit of CE amplifier with Voltage Series feedback and obtain the expression for feedback ratio, voltage
gain, input and output resistances.

Input is the feedback network is parallel with output of amplifier

shunt connection to reduce output resistance 𝑅𝑜 series connection at
the input increase the input resistance.

𝑉𝑓
𝑉𝑜𝑙𝑡𝑎𝑔𝑒 𝑓𝑒𝑒𝑑𝑏𝑎𝑐𝑘 𝑓𝑎𝑐𝑡𝑜𝑟 𝛽 =
𝑉𝑜

Gain
𝑉
Amplifier Gain 𝐴𝑣 = 𝑉𝑜
𝑖

𝑉𝑜 = 𝐴𝑣 𝑉𝑖 − − − (1)

Feedback is connected 𝑉𝑠 = 𝑉𝑖 + 𝑉𝑓 ; 𝑉𝑖 = 𝑉𝑠 − 𝑉𝑓

Now 𝑉𝑠 = 𝑉𝑖 + 𝛽 𝑉𝑜 = 𝑉𝑖 + 𝛽𝐴𝑣 𝑉𝑖

𝑉𝑠 = 𝑉𝑖 (1 + 𝐴 𝛽) − − − (2)

𝑉𝑖 = 𝑉𝑠 − 𝑉𝑓 & 𝑉𝑖 = 𝐼𝑖 𝑅𝑖

∴ 𝑉𝑠 = 𝑉𝑖 + 𝑉𝑓 = 𝐼𝑖 𝑅𝑖 + 𝐴 𝛽 𝑉𝑖

= 𝐼𝑖 𝑅𝑖 + 𝐴 𝛽 𝑅𝑖 𝐼𝑖

𝑉𝑠 = 𝑅𝑖 𝐼𝑖 (1 + 𝐴 𝛽)
𝑉𝑖 𝐼𝑖 𝑅𝑖 (1+𝐴 𝛽)
Now, Input Impedance 𝑍𝑖𝑓 = 𝐼𝑖
= 𝐼𝑖

𝑉𝑖
= (1 + 𝐴 𝛽)
𝐼𝑖

𝑍𝑖𝑓 = 𝑍𝑖 (1 + 𝐴 𝛽)

Output impedance, 𝑉𝑜 = 𝑅𝑜 𝐼𝑜 + 𝐴𝑉𝑖 , 𝑉𝑖 = 𝑉𝑠 − 𝑉𝑃

𝑉𝑠 = 0

𝑉𝑖 = −𝑉𝑃 = 𝛽𝑉𝑜
 ∴ 𝑉𝑜 = 𝐼𝑜 𝑅𝑜 − 𝐴 𝛽𝑉𝑜

𝑉𝑜 + 𝐴 𝛽𝑉𝑜 = 𝐼𝑜 𝑅𝑜

𝑉𝑜 (1 + 𝐴 𝛽) = 𝐼𝑜 𝑅𝑜

𝑉𝑜 𝑅𝑜
=
𝐼𝑜 1 + 𝐴 𝛽

𝑅𝑜
𝑍𝑜 =
1+𝐴𝛽

𝑅𝑜 → 𝑜𝑢𝑡𝑝𝑢𝑡 𝑟𝑒𝑠𝑖𝑠𝑡𝑎𝑛𝑐𝑒 𝑜𝑓 𝑎𝑚𝑝𝑙𝑖𝑓𝑖𝑒𝑟 𝑤𝑖𝑡ℎ𝑜𝑢𝑡 𝑓𝑒𝑒𝑑𝑏𝑎𝑐𝑘.

𝐼𝑒 𝐼𝑏 + 𝐼𝑐
𝐴𝑖 = = = 1 + ℎ𝑓𝑒
𝐼𝑏 𝐼𝑏

𝑅𝑖 = ℎ𝑖𝑒 + (1 + ℎ𝑓𝑒 )𝑅𝐸

𝐴𝐶 𝑅𝐿 (1+ℎ𝑓𝑒 )𝑅𝐿 ℎ𝑖𝑒

𝐴𝑉 = = =1−
𝑅𝑖 ℎ𝑖𝑒 +(1+ℎ𝑓𝑒 )𝑅𝐿 𝑅𝑖

ℎ𝑖𝑒 + 𝑅𝑠
𝑅𝑜 =
1 + ℎ𝑓𝑒

𝑅𝑜𝑓 = 𝑅𝑜 ⃦ 𝑅𝑐

(B) VOLTAGE SHUNT FEEDBACK AMPLIFIER

Draw circuit of CE amplifier with Voltage Shunt feedback and obtain the expression for feedback ratio, voltage
gain, input and output resistances. (April / May 2015 -R13)

Trans resistance Amplifier

Connection Diagram:

𝑉𝑜 𝑉𝑜
𝐺𝑎𝑖𝑛 ∶ 𝐴𝐹 = =
𝐼𝑠 𝐼𝑖

𝐼𝑠 = 𝐼𝑖 + 𝐼𝑓

= 𝐼𝑖 + 𝛽 𝑉𝑜

𝐼𝑠 = 𝐼𝑖 + 𝐴 𝛽𝐼𝑖 = 𝐼𝑖 (1 + 𝐴𝛽)
𝑉𝑜 𝐴𝐼
𝑖 𝐴
𝐴𝐹 = 𝐼𝑠
= 𝐼 (1+𝐴𝛽) = 1+𝐴𝛽 𝑤𝑖𝑡ℎ𝑜𝑢𝑡 𝑓𝑒𝑒𝑑𝑏𝑎𝑐𝑘.
𝑖

∴ The gain of the amplifier without feedback is reduced by a factor of (1 + 𝐴𝛽)

𝐼𝑛𝑝𝑢𝑡 𝐼𝑚𝑝𝑒𝑑𝑎𝑛𝑐𝑒:
𝑉𝑖 𝑉 𝑉 𝑉 𝑉
𝑍𝑖 = 𝐼𝑠
; 𝑍𝑖 = 𝐼 +𝐼𝑖 ; 𝑖
𝑍𝑖 = 𝐼 +𝛽𝑉 ; 𝑖
𝑍𝑖 = 𝐼 +𝐴𝛽𝐼 ; 𝑖
𝑍𝑖 = 𝐼 (1+𝐴𝛽) ;
𝑖 𝑓 𝑖 𝑜 𝑖 𝑖 𝑖

𝑖 𝑍
𝑍𝑖 = (1+𝐴𝛽)

Input impedance is reduced by the factor (1 + 𝐴𝛽) for both series, shunt feedback connection.

Output Impedance

𝑉𝑜 = 𝑅𝑜 𝐼𝑜 − 𝐴 𝐼𝑖 𝐼𝑖 = 𝐼𝑆 − 𝐼𝐹 , 𝐼𝑓 𝐼𝑠 𝑡𝑟𝑎𝑛𝑠𝑓𝑒𝑟𝑟𝑒𝑑 𝑡𝑜 𝑜𝑢𝑡𝑝𝑢𝑡 𝑠𝑖𝑑𝑒 𝐼𝑠 = 0

= 𝑅𝑜 𝐼𝑜 − 𝐴 𝐼𝐹 ∴ 𝐼𝑖 = −𝐼𝐹

𝑉𝑜 + 𝐴𝛽 𝑉𝑜 = 𝑅𝑜 𝐼𝑜 𝑉𝑜 (1 + 𝐴𝛽) = 𝑅𝑜 𝐼𝑜
𝑉𝑜 𝑅𝑜 𝑉𝑜 𝑜 𝑅
𝐼𝑜
= 1+𝐴𝛽 𝑍𝑜 = 𝐼𝑜
= 1+𝐴𝛽

(C) CURRENT SHUNT FEEDBACK AMPLIFIER

Draw circuit of CE amplifier with Current Shunt feedback and obtain the expression for feedback ratio, voltage
gain, input and output resistances. (April / May 2015 -R13)

Connection Diagram

𝑉𝑜
𝐴𝑚𝑝𝑙𝑖𝑓𝑖𝑒𝑟 𝐺𝑎𝑖𝑛, 𝐴 = 𝐼𝑆 = 𝐼𝑖 + 𝐼𝐹
𝐼𝑖
𝐼𝐹
𝐹𝑒𝑒𝑑𝑏𝑎𝑐𝑘 𝑓𝑎𝑐𝑡𝑜𝑟 𝛽 = 𝐼𝐹 = 𝛽𝐼𝑜
𝐼𝑜

𝐼𝑜 = 𝐴𝐼𝑖

Gain of the Amplifier

𝐼𝑜 𝐴𝐼 𝐴𝐼 𝐴𝐼
𝐴𝐹 = 𝐼𝑠
= 𝐼 +𝐼𝑖 = 𝐼 +𝛽𝐼
𝑖
= 𝐼 +𝛽 𝑖𝐴𝐼
𝑖 𝐹 𝑖 𝑜 𝑖 𝑖

𝐴
𝐴𝐹 =
1 + 𝛽𝐴
Input Impedance:

𝐼𝑠 = 𝐼𝑖 + 𝐼𝐹

𝑉𝑖 𝑉𝑖 𝑉𝑖 𝐴𝛽𝑉𝑖 𝑉𝑖
𝐼𝑠 = + 𝛽𝐼𝑜 ; 𝐼𝑠 = + 𝐴𝛽𝐼𝑖 ; 𝐼𝑠 = + ; 𝐼𝑠 = (1 + 𝐴𝛽)
𝑅𝑖 𝑅𝑖 𝑅𝑖 𝑅𝑖 𝑅𝑖

Input resistance of amplifier with feedback 𝑅𝑖𝑓

𝑉𝑖 𝑅𝑖
𝑅𝑖𝑓 = 𝐼𝑠
= 1+𝐴𝛽

Output Impedance:

𝐼𝑠 = 𝐼𝑖 + 𝐼𝐹 𝐼𝑖 = 𝐼𝑠 − 𝐼𝐹

𝐼𝑠 = 0, Source transferred to output side to calculate the output impedance.

𝑉𝑜
𝐼𝑜 = 𝐴 𝐼𝑖 +
𝑅𝑜

𝑉𝑜
= (1 + 𝐴𝛽)
𝑅𝑜

𝑉𝑜
𝑅𝐹 = = 𝑅𝑜 (1 + 𝐴𝛽)
𝑅𝑜

Thus, output impedance increased by (1 + 𝐴𝛽)

(D) CURRENT SERIES FEEDBACK AMPLIFIER

Draw circuit of CE amplifier with Current Series feedback and obtain the expression for feedback ratio, voltage
gain, input and output resistances. (April / May 2015 -R13)

Transconductance Amplifier:

𝐼𝑜 𝐼𝑜
𝐺𝑎𝑖𝑛 = =
𝑉𝑜 𝑉𝑖 + 𝑉𝐹
 𝐴 𝑉𝑖 𝐴 𝑉𝑖
= ⥤
𝑉𝑖 + 𝛽𝐼𝑜 𝑉𝑖 + 𝐴𝛽𝑉𝑖

𝐴 𝑉𝑖 𝐴
𝐴𝐹 = =
𝑉𝑖 (1 + 𝐴𝛽) 1 + 𝐴𝛽

Equivalent Circuit

Input Impedance:

𝑉𝑠 = 𝐼𝑖 𝑅𝑖 + 𝑉𝐹

= 𝐼𝑖 𝑅𝑖 + 𝛽𝐼𝑜

= 𝐼𝑖 𝑅𝑖 + 𝐴𝛽𝑉𝑖

= 𝐼𝑖 𝑅𝑖 + 𝐴𝛽𝐼𝑖 𝑅𝑖

= 𝐼𝑖 𝑅𝑖 (1 + 𝐴𝛽)

𝑉𝑠
𝑍𝑖 = = 𝑅𝑖 (1 + 𝐴𝛽)
𝐼𝑖

∴ 𝐼𝑛𝑝𝑢𝑡 𝑖𝑚𝑝𝑒𝑑𝑎𝑛𝑐𝑒 𝑖𝑛𝑐𝑟𝑒𝑎𝑠𝑒𝑑 𝑏𝑦 𝑓𝑎𝑐𝑡𝑜𝑟(1 + 𝐴𝛽)

Output Impedance:

𝑉𝑠 = 0

𝑉𝑠 = 𝑉𝑖 + 𝑉𝐹

𝑉𝑖 + 𝑉𝐹 = 0; 𝑉𝑖 = −𝑉𝐹

𝑉𝑜 𝑉𝑜
𝐼𝑜 = 𝐴𝑉𝑖 + = −𝐴𝑉𝑖 +
𝑍𝑜 𝑍𝑜

𝑉𝑜
= −𝐴 𝛽𝐼𝑜 +
𝑍𝑜
𝑉 𝑉
𝐼𝑜 + 𝐴 𝛽𝐼𝑜 = 𝑍𝑜 ; 𝐼𝑜 (1 + 𝐴𝛽) = 𝑍𝑜
𝑜 𝑜

𝑉𝑜
𝑍𝑂𝐹 = = 𝑍𝑜 (1 + 𝐴𝛽)
𝐼𝑜

The output impedance is increased by factor (1 + 𝐴𝛽)

7. Sketch the circuit diagram of a two-stage capacitor coupled BJT amplifier that uses series voltage negative
feedback. Briefly explain hoe the feedback operates (Nov/Dec 2015)
It is a shunt or nodal sampling and series mixing. Also cascading means two or more amplifier are connected in series
using coupling capacitor or coupling elements. This is shown in fig.

Above fig shows cascaded voltage series amplifier. This analysis

of cascaded amplifiers is as follows.

Step 1:

RF and RE1 acts as feedback. The,

i) ß network is directly taken from V0. Therefore, it is called voltage sampled.

ii) Also 𝛽network is not directly connected to base hence it is not shunt mixing and therefore it is series feedback.

Therefore, the voltage series feedback X0, XS, Xi, Xf are voltages. Then its analysis is as followings.

𝐒𝐭𝐞𝐩 𝟐 ∶
𝑉𝑓
𝛽= 𝑉0

𝑉0
𝑊ℎ𝑒𝑟𝑒𝑉𝑓 = (𝑅 ) 𝑅𝐸1
𝑓 +𝑅𝐸1

𝑉
0 )𝑅
(𝑅 +𝑅 𝐸1
𝑓 𝐸1
𝐴𝑙𝑠𝑜, 𝛽 =
𝑉0

𝑅𝐸1
∴𝛽=𝑅
𝑓 +𝑅𝐸1

𝐒𝐭𝐞𝐩 𝟑 ∶ 𝐷𝑟𝑎𝑤𝑖𝑛𝑔𝑏𝑎𝑠𝑖𝑐𝑎𝑚𝑝𝑙𝑖𝑓𝑖𝑒𝑟.=

(𝑖)𝐹𝑜𝑟𝑡ℎ𝑒𝑖𝑛𝑝𝑢𝑡𝑐𝑖𝑟𝑐𝑢𝑖𝑡𝑔𝑜𝑡𝑜𝑜𝑢𝑡𝑝𝑢𝑡𝑎𝑛𝑑𝑝𝑢𝑡𝑋0 = 0; 𝑖. 𝑒. , 𝑉0 = 0

(𝑖𝑖)𝐹𝑜𝑟𝑜𝑢𝑡𝑝𝑢𝑡𝑐𝑖𝑟𝑐𝑢𝑖𝑡𝑔𝑜𝑡𝑜𝑖𝑛𝑝𝑢𝑡𝑎𝑛𝑑𝑝𝑢𝑡𝐼𝑖 = 0

𝐴𝑛𝑦ℎ𝑜𝑤, 𝑅𝐸 = 𝑅𝐸1 ⃦ 𝑅𝑓 (𝑜𝑟)

𝑅𝐸1 𝑅𝑓
𝑅𝐸 =
𝑅𝐸1 + 𝑅𝑓
 𝐴𝑙𝑠𝑜, 𝑅𝐿2 = 𝑅𝐶2 ⃦ (𝑅𝑓 + 𝑅𝐸1 )

𝑅𝐶2 × (𝑅𝑓 + 𝑅𝐸1 )

𝑅𝐿2 =
𝑅𝐶2 + 𝑅𝑓 + 𝑅𝐸1

This is the basic amplifier equivalent circuit is as in figure 3.40

Here, the first stage is common emitter connection with feedback resistor 𝑅𝑓 𝑎𝑛𝑑𝑅𝐸1 is also called𝒈𝒍𝒐𝒃𝒂𝒍𝒇𝒆𝒆𝒅𝒃𝒂𝒄𝒌.

𝑆𝑡𝑒𝑝 4 ∶ 𝐴𝑛𝑎𝑙𝑦𝑠𝑖𝑠𝑔𝑖𝑣𝑒𝑠𝑡ℎ𝑒𝑓𝑜𝑙𝑙𝑜𝑤𝑖𝑛𝑔𝑟𝑒𝑠𝑢𝑙𝑡𝑠𝑖𝑛𝑠ℎ𝑜𝑟𝑡,

𝑖. 𝑒. , D = 1 + AV β

AV AV
AVf = or
D (1 + AV β)

R if = R i × DorR i (1 + AV β)

R0 R0
R 0f = or
D (1 + AV β)

From the above analysis voltage gain with feedback 𝐴𝑉𝐹 and output resistance 𝑅0𝑓 is reduced by (1 + 𝐴𝛽) times, and input
resistance (𝑅𝑖𝑓 ) with feedback is increased by ( 1 + 𝐴𝛽) times.