NAME: IBEKWE SAMSON IFEANYI

REG. NO: 2017/241386

QUESTION: Write everything you know on interrupt

INTERRUPT
In digital computers, an interrupt is an input signal to the processor indicating an event that
needs immediate attention. An interrupt signal alerts the processor and serves as a request for the
processor to interrupt the currently executing code, so that the event can be processed in a timely
manner. If the request is accepted, the processor responds by suspending its current activities,
saving its state, and executing a function called an interrupt handler (or an interrupt service
routine, ISR) to deal with the event. This interruption is temporary, and, unless the interrupt
indicates a fatal error, the processor resumes normal activities after the interrupt handler finishes.
Interrupts are commonly used by hardware devices to indicate electronic or physical state
changes that require attention. Interrupts are also commonly used to implement computer
multitasking, especially in real-time computing. Systems that use interrupts in these ways are
said to be interrupt-driven.

HISTORY
Hardware interrupts were introduced as an optimization, eliminating unproductive waiting time
in polling loops, waiting for external events. The first system to use this approach was
the DYSEAC, completed in 1954, although earlier systems provided error trap functions.[13]
The UNIVAC 1103 computer is generally credited with the earliest use of interrupts in 1953.
[14]
 Earlier, on the UNIVAC I (1951) "Arithmetic overflow either triggered the execution a two-
instruction fix-up routine at address 0, or, at the programmer's option, caused the computer to
stop." The IBM 650 (1954) incorporated the first occurrence of interrupt masking. The National
Bureau of Standards DYSEAC (1954) was the first to use interrupts for I/O. The IBM 704 was
the first to use interrupts for debugging, with a "transfer trap", which could invoke a special
routine when a branch instruction was encountered. The MIT Lincoln Laboratory TX-2 system
(1957) was the first to provide multiple levels of priority interrupts.

TYPES
Interrupt signals may be issued in response to hardware or software events. These are classified
as hardware interrupts or software interrupts, respectively. For any particular processor, the
number of hardware interrupts is limited by the number of interrupt request (IRQ) signals to the
processor, whereas the number of software interrupts is determined by the processor's instruction
set design.

Hardware interrupts
A hardware interrupt request (IRQ) is an electronic signal issued by a hardware device which is
external to the processor, to communicate that that the device needs attention from the operating
system (OS)[3] or, if there is no OS, from the "bare-metal" program running on the CPU. Such
external devices may be part of the computer (e.g., disk controller) or they may be
external peripherals. For example, pressing a keyboard key or moving the mouse triggers
hardware interrupts that cause the processor to read the keystroke or mouse position.
Unlike software interrupts, hardware interrupts can arrive asynchronously with respect to the
processor clock, and at any time during instruction execution. Consequently, all hardware
interrupt signals are conditioned by synchronizing them to the processor clock, and acted upon
only at instruction execution boundaries. In many systems, each device is associated with a
particular IRQ signal. This makes it possible to quickly determine which hardware device is
requesting service, and to expedite servicing of that device.

Software interrupts
A software interrupt is requested by the processor itself upon executing particular instructions or
when certain conditions are met. Every software interrupt signal is associated with a particular
interrupt handler. A software interrupt may be intentionally caused by executing a
special instruction which, by design, invokes an interrupt when executed. Such instructions
function similarly to subroutine calls and are used for a variety of purposes, such as requesting
operating system services and interacting with device drivers (e.g., to read or write storage
media).
Software interrupts may also be unexpectedly triggered by program execution errors. These
interrupts typically are called traps or exceptions. For example, a divide-by-zero exception will
be "thrown" (a software interrupt is requested) if the processor executes a divide instruction with
divisor equal to zero. Typically, the operating system will catch and handle this exception.
TRIGGERING METHODS
Each interrupt signal input is designed to be triggered by either a logic signal level or a particular
signal edge (level transition). Level-sensitive inputs continuously request processor service so
long as a particular (high or low) logic level is applied to the input. Edge-sensitive inputs react to
signal edges: a particular (rising or falling) edge will cause a service request to be latched; the
processor resets the latch when the interrupt handler executes.

Level – triggered
A level-triggered interrupt is requested by holding the interrupt signal at its particular (high or
low) active logic level. A device invokes a level-triggered interrupt by driving the signal to and
holding it at the active level. It negates the signal when the processor commands it to do so,
typically after the device has been serviced. The processor samples the interrupt input signal
during each instruction cycle. The processor will recognize the interrupt request if the signal is
asserted when sampling occurs. Level-triggered inputs allow multiple devices to share a common
interrupt signal via wired-OR connections. The processor polls to determine which devices are
requesting service. After servicing a device, the processor may again poll and, if necessary,
service other devices before exiting the ISR.

Edge – triggered
An edge-triggered interrupt is an interrupt signaled by a level transition on the interrupt line,
either a falling edge (high to low) or a rising edge (low to high). A device wishing to signal an
interrupt drives a pulse onto the line and then releases the line to its inactive state. If the pulse is
too short to be detected by polled I/O then special hardware may be required to detect it.

PROCESSOR RESPONSE
The processor samples the interrupt trigger signal during each instruction cycle, and will respond
to the trigger only if the signal is asserted when sampling occurs. Regardless of the triggering
method, the processor will begin interrupt processing at the next instruction boundary following
a detected trigger, thus ensuring:
 The Program Counter (PC) is saved in a known place.
 All instructions before the one pointed to by the PC have fully executed.
 No instruction beyond the one pointed to by the PC has been executed, or any such
instructions are undone before handling the interrupt.
 The execution state of the instruction pointed to by the PC is known.
SYSTEM IMPLEMENTATION
Interrupts may be implemented in hardware as a distinct component with control lines, or they
may be integrated into the memory subsystem.
If implemented in hardware as a distinct component, an interrupt controller circuit such as the
IBM PC's Programmable Interrupt Controller (PIC) may be connected between the interrupting
device and the processor's interrupt pin to multiplex several sources of interrupt onto the one or
two CPU lines typically available. If implemented as part of the memory controller, interrupts
are mapped into the system's memory address space.

Hybrid
Some systems use a hybrid of level-triggered and edge-triggered signaling. The hardware not
only looks for an edge, but it also verifies that the interrupt signal stays active for a certain period
of time.
A common use of a hybrid interrupt is for the NMI (non-maskable interrupt) input. Because
NMIs generally signal major – or even catastrophic – system events, a good implementation of
this signal tries to ensure that the interrupt is valid by verifying that it remains active for a period
of time. This 2-step approach helps to eliminate false interrupts from affecting the system.

Messaged – signaled
A message-signaled interrupt does not use a physical interrupt line. Instead, a device signals its
request for service by sending a short message over some communications medium, typically
a computer bus. The message might be of a type reserved for interrupts, or it might be of some
pre-existing type such as a memory write.
Message-signaled interrupts behave very much like edge-triggered interrupts, in that the interrupt
is a momentary signal rather than a continuous condition. Interrupt-handling software treats the
two in much the same manner. Typically, multiple pending message-signaled interrupts with the
same message (the same virtual interrupt line) are allowed to merge, just as closely spaced edge-
triggered interrupts can merge.
Message-signaled interrupt vectors can be shared, to the extent that the underlying
communication medium can be shared. No additional effort is required.
Because the identity of the interrupt is indicated by a pattern of data bits, not requiring a separate
physical conductor, many more distinct interrupts can be efficiently handled. This reduces the
need for sharing. Interrupt messages can also be passed over a serial bus, not requiring any
additional lines. PCI Express, a serial computer bus, uses message-signaled
interrupts exclusively.

Doorbell
In a push button analogy applied to computer systems, the term doorbell or doorbell interrupt is
often used to describe a mechanism whereby a software system can signal or notify a computer
hardware device that there is some work to be done. Typically, the software system will place
data in some well-known and mutually agreed upon memory location(s), and "ring the doorbell"
by writing to a different memory location. This different memory location is often called the
doorbell region, and there may even be multiple doorbells serving different purposes in this
region. It is this act of writing to the doorbell region of memory that "rings the bell" and notifies
the hardware device that the data are ready and waiting. The hardware device would now know
that the data are valid and can be acted upon. It would typically write the data to a hard disk
drive, or send them over a network, or encrypt them, etc.
The term doorbell interrupt is usually a misnomer. It is similar to an interrupt, because it causes
some work to be done by the device; however, the doorbell region is sometimes implemented as
a polled region, sometimes the doorbell region writes through to physical device registers, and
sometimes the doorbell region is hardwired directly to physical device registers. When either
writing through or directly to physical device registers, this may cause a real interrupt to occur at
the device's central processor unit (CPU), if it has one.
Doorbell interrupts can be compared to Message Signaled Interrupts, as they have some
similarities.

PERFORMANCE
Interrupts provide low overhead and good latency at low load, but degrade significantly at high
interrupt rate unless care is taken to prevent several pathologies. The phenomenon where the
overall system performance is severely hindered by excessive amounts of processing time spent
handling interrupts is called an interrupt storm.
There are various forms of live locks, when the system spends all of its time processing
interrupts to the exclusion of other required tasks. Under extreme conditions, a large number of
interrupts (like very high network traffic) may completely stall the system. To avoid such
problems, an operating system must schedule network interrupt handling as carefully as it
schedules process execution.[6]
With multi-core processors, additional performance improvements in interrupt handling can be
achieved through receive-side scaling (RSS) when multiqueue NICs are used. Such NICs
provide multiple receive queues associated to separate interrupts; by routing each of those
interrupts to different cores, processing of the interrupt requests triggered by the network traffic
received by a single NIC can be distributed among multiple cores. Distribution of the interrupts
among cores can be performed automatically by the operating system, or the routing of interrupts
(usually referred to as IRQ affinity) can be manually configured.
A purely software-based implementation of the receiving traffic distribution, known as receive
packet steering (RPS), distributes received traffic among cores later in the data path, as part of
the interrupt handler functionality. Advantages of RPS over RSS include no requirements for
specific hardware, more advanced traffic distribution filters, and reduced rate of interrupts
produced by a NIC. As a downside, RPS increases the rate of inter-processor
interrupts (IPIs). Receive flow steering (RFS) takes the software-based approach further by
accounting for application locality; further performance improvements are achieved by
processing interrupt requests by the same cores on which particular network packets will be
consumed by the targeted application.

TYPICAL USES
Interrupts are commonly used to service hardware timers, transfer data to and from storage (e.g.,
disk I/O) and communication interfaces (e.g., UART, Ethernet), handle keyboard and mouse
events, and to respond to any other time-sensitive events as required by the application system.
Non-maskable interrupts are typically used to respond to high-priority requests such as watchdog
timer timeouts, power-down signals and traps.
Hardware timers are often used to generate periodic interrupts. In some applications, such
interrupts are counted by the interrupt handler to keep track of absolute or elapsed time, or used
by the OS task scheduler to manage execution of running processes, or both. Periodic interrupts
are also commonly used to invoke sampling from input devices such as analog-to-digital
converters, incremental encoder interfaces, and GPIO inputs, and to program output devices such
as digital-to-analog converters, motor controllers, and GPIO outputs.
A disk interrupt signals the completion of a data transfer from or to the disk peripheral; this may
cause a process to run which is waiting to read or write. A power-off interrupt predicts imminent
loss of power, allowing the computer to perform an orderly shut-down while there still remains
enough power to do so. Keyboard interrupts typically cause keystrokes to be buffered so as to
implement typeahead.
Interrupts are sometimes used to emulate instructions which are unimplemented on some
computers in a product family.[11] For example floating point instructions may be implemented in
hardware on some systems and emulated on lower-cost systems. In the latter case, execution of
an unimplemented floating point instruction will cause an "illegal instruction" exception
interrupt. The interrupt handler will implement the floating point function in software and then
return to the interrupted program as if the hardware-implemented instruction had been executed.
[12]
 This provides application software portability across the entire line.
Interrupts are similar to signals, the difference being that signals are used for inter-process
communication (IPC), mediated by the kernel (possibly via system calls) and handled by
processes, while interrupts are mediated by the processor and handled by the kernel. The kernel
may pass an interrupt as a signal to the process that caused it (typical examples
are SIGSEGV, SIGBUS, SIGILL and SIGFPE).

REFERENCES
1.  Jonathan Corbet; Alessandro Rubini; Greg Kroah-Hartman (2005). "Linux Device Drivers,
Third Edition, Chapter 10. Interrupt Handling" (PDF). O'Reilly Media. p. 269.
Retrieved December 25, 2014. Then it's just a matter of cleaning up, running software
interrupts, and getting back to regular work. The "regular work" may well have changed as a
result of an interrupt (the handler could  wake_up  a process, for example), so the last thing that
happens on return from an interrupt is a possible rescheduling of the processor.
2. ^ Rosenthal, Scott (May 1995). "Basics of Interrupts". Archived from the originalon 2016-04-26.
Retrieved 2010-11-11.
3. ^ "Hardware interrupts". Retrieved 2014-02-09.
4. ^ Bai, Ying (2017). Microcontroller Engineering with MSP432: Fundamentals and Applications.
CRC Press. p. 21. ISBN 978-1-4987-7298-3. LCCN 2016020120. In Cortex-M4 system, the
interrupts and exceptions have the following properties: ... Generally, a single bit in a mask
register is used to mask (disable) or unmask (enable) certain interrupt/exceptions to occur
5. ^ Jump up to:a b Li, Qing; Yao, Caroline (2003). Real-Time Concepts for Embedded Systems.
CRC Press. p. 163. ISBN 1482280825.
6. ^ "Eliminating receive livelock in an interrupt-driven kernel". doi:10.1145/263326.263335.
Retrieved 2010-11-11.
7. ^ Jump up to:a b Tom Herbert; Willem de Bruijn (May 9,
2014). "Documentation/networking/scaling.txt". Linux kernel documentation. kernel.org.
Retrieved November 16, 2014.
8. ^ "Intel 82574 Gigabit Ethernet Controller Family Datasheet" (PDF). Intel. June 2014. p. 1.
Retrieved November 16, 2014.
9. ^ Jonathan Corbet (November 17, 2009). "Receive packet steering". LWN.net.
Retrieved November 16, 2014.
10. ^ Jake Edge (April 7, 2010). "Receive flow steering". LWN.net. Retrieved November 16, 2014.
11. ^ Thusoo, Shalesh; et al. "Patent US 5632028 A". Google Patents. Retrieved Aug 13, 2017.
12. ^ Altera Corporation (2009). Nios II Processor Reference (PDF). p. 4. Retrieved Aug 13, 2017.
13. ^ Codd, Edgar F. "Multiprogramming". Advances in Computers. 3: 82.
14. ^ Bell, C. Gordon; Newell, Allen (1971). Computer structures: readings and examples. McGraw-
Hill. p. 46. ISBN 9780070043572. Retrieved Feb 18, 2019.
15. ^ Smotherman, Mark. "Interrupts". Retrieved Feb 18, 2019.