Bachelor Thesis: Analysis and Design of A 900MHz Doherty Power Amplifier

Analysis and design of a 900 MHz Doherty Power Amplier
by Nam Tran Pham in Partial Fulllment of the Requirements for the Degree of Bachelor of Engineering at the Konstanz University of Applied Sciences Faculty of Electrical and Information Technology August 14, 2011
Thesis Supervisors: Prof. Dr. Christoph Schick
Abstract
In the late 1930s Radio became the dominant mass media in industrial nations and with it there was a demand for higher power levels in broadcasting. At that time most of the RF power ampliers had very low eciency, which increased the expense for operating a broadcast station in power consumption and cooling system. In September 1936 William H. Doherty introduced a new method to increase the eciency of power ampliers, this technique was able to increase the eciency up to nearly 80%, later it was widely used in mediumand high-power RF ampliers. Nearly 60 years later energy-eciency becomes more and more important, especially in new wireless transmitters such as cellular telephones, in which battery life is one of the key features of the device, the Doherty power amplier architecture has become the amplier of choice. There have been many improvements since the rst publication of the Doherty amplier; this thesis, however, only introduces the basic ideal of Doherty architecture. The basic functionality will be discussed and nally a Doherty amplier is implemented at 900 MHz, both in simulation and hardware.
Acknowledgements
I wish to express my sincere gratitude and appreciation to my advisor, Prof. Dr. Christoph Schick, for introducing me to this challenging and interesting topic. I have signicantly beneted from his broad range of expertise. I would also like to thank to my committee members for all of the time they spent to review my thesis and their helpful comments. Special thanks to Prof. Edmund Zhringer for his advices on working with transistor at high frequency. a My gratefulness is directed to all the technical engineers at faculty of Electrical and Information Technology, HTWG Konstanz and to all my friends, who supported me during the research for this thesis. Finally, I am grateful and indebted to the continuous love, understanding and supporting from my family. Love you all.
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Declaration
I declare that this thesis was composed by myself, that the work contained herein is my own except where explicitly stated otherwise in the text, and that this work has not been submitted for any other degree or professional qualication except as specied.
Konstanz, August 14, 2011

Nam Tran Pham
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Contents
Table of contents List of gures List of tables Abbreviation 1. Introduction 1.1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2. Thesis organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2. Doherty Amplier Architecture 2.1. Power Amplier Classes . . . . . . . . . . . . . 2.2. Doherty Load Modulation . . . . . . . . . . . . 2.3. Analysis of the Doherty Amplier Architecture 2.3.1. Classical Doherty Amplier . . . . . . . 2.3.2. Low-Power Operation . . . . . . . . . . 2.3.3. Peak-Power Operation . . . . . . . . . . 2.3.4. Medium-Power Operation . . . . . . . . 2.3.5. Summary of Operation . . . . . . . . . . 3. Design with analytic method 3.1. Design Parameters . . . 3.2. Input and output design 3.2.1. Input design . . 3.2.2. Output design . 3.3. Carry Amplier design . 3.4. Peak Amplier design . 3.5. Design review . . . . . . iv vi ix x 1 1 2 3 3 5 8 8 10 11 12 13 15 15 19 19 23 25 26 27 31 31 33 34 36 36 40 44 44 44 46
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4. Design with Load-Pull technique 4.1. Quality factor Q . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2. Power Amplier design with Load-Pull Technique . . . . . . . . . . . 4.3. Design parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4. Amplier design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.4.1. Carry amplier V4 . . . . . . . . . . . . . . . . . . . . . . . . 4.4.2. Carry amplier V5, Peak amplier V4 and Doherty amplier 4.5. Performance review . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.1. DC current behavior . . . . . . . . . . . . . . . . . . . . . . . 4.5.2. Carry amplier . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5.3. Peak amplier . . . . . . . . . . . . . . . . . . . . . . . . . .
iv
Contents
4.5.4. Doherty amplier . . . . . . . . . . . . . . . . . . . . . . . . . 5. Conclusions and Recommendations 5.1. Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2. Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . A. Load pull simulation results B. Schematics and layouts C. Data sheet Bibliography 48 52 52 53 54 59 65 69
List of Figures
2.1. Ideal class B amplier circuit . . . . . . . . . . . . . . . . . . . . . . 3 2.2. Conduction angles for a class A, B or C amplier . . . . . . . . . . . 4 2.3. Collector current and voltage with power dissipation . . . . . . . . . 5 2.4. Transistor amplier in common emitter circuit . . . . . . . . . . . . 6 2.5. Active load-pull concept . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.6. Doherty amplier architecture . . . . . . . . . . . . . . . . . . . . . . 7 2.7. Output voltage and current of classical Doherty amplier[6] . . . . . 8 2.8. Eciency of classical Doherty amplier[6] . . . . . . . . . . . . . . . 9 2.9. Comparision of real Doherty amplier with class A and AB amplier[20] 10 2.10. Doherty amplier architecture . . . . . . . . . . . . . . . . . . . . . . 10 2.11. Ideal eciency of Doherty amplier vs. output power[5] . . . . . . . 14 3.1. Simplied transistor circuit . . . . . . . . . . . . . . . . . . . . . . . 3.2. Collector current and voltage of class B transistor . . . . . . . . . . . 3.3. Peak value of collector voltage at 50mW output . . . . . . . . . . . . 3.4. Fundamental and peak value of collector current at 50mW output . 3.5. Collector voltage at 25mW output . . . . . . . . . . . . . . . . . . . 3.6. Current through load and collector at 25mW output . . . . . . . . . 3.7. Doherty amplier architecture . . . . . . . . . . . . . . . . . . . . . . 3.8. Hybrid divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9. Wilkinson coupler . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10. Input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11. Return loss and Insertion loss of the input circuit . . . . . . . . . . . 3.12. Phase delay and isolation of the input circuit . . . . . . . . . . . . . 3.13. Output circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.14. Phase of output signal . . . . . . . . . . . . . . . . . . . . . . . . . . 3.15. Insertion loss and Isolation from P1 and P2 . . . . . . . . . . . . . . 3.16. Collector current of AT42086 with Vcc = 2.7V . . . . . . . . . . . . 3.17. Carry-Amplier circuit simulation . . . . . . . . . . . . . . . . . . . 3.18. Peak-Amplier simulation circuit . . . . . . . . . . . . . . . . . . . . 3.19. Doherty Amplier Simulation . . . . . . . . . . . . . . . . . . . . . . 3.20. Collector eciency of the simulation circuit . . . . . . . . . . . . . . 3.21. Carry- and Peak-Transistor at transition point Pin = 3dBm . . . . . 3.22. Carry- and Peak-Transistor at max input power Pin = 6dBm . . . . 3.23. Summary of collector current and voltage in simulation (line - carry, dashed - peak), peak value of the fundamental frequency . . . . . . . 3.24. Waveform of collector current at the Carry- and Peak-Transistor . . 3.25. PAE and Gain of Doherty amplier . . . . . . . . . . . . . . . . . . . 3.26. Output power, PAE, Gain versus input power [10] . . . . . . . . . . 4.1. Capacitor and inductor model at radio-frequency . . . . . . . . . . . 15 16 17 17 18 18 19 20 21 21 22 22 23 24 24 25 26 26 27 27 28 28 29 29 29 30 31
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List of Figures
Insertion loss of capacitor [Murata-Data sheet] . . . . . . . . . . . . Measurement the 220nF capacitor . . . . . . . . . . . . . . . . . . . Block diagram of a load-pull system[19] . . . . . . . . . . . . . . . . Results of load-pull technique . . . . . . . . . . . . . . . . . . . . . . Measurement results from test device Carry-V4B, measurement 1 . . Measurement results from test device Carry-V4B, measurement 2 . . Schematic of input matching for carry V4 . . . . . . . . . . . . . . . Comparison between software simulation and hardware measurement of the carry input matching network V4 , Simulation-Line, HardwareSymbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.10. Layout and S-Parameter simulation result of the carry input matching network V4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.11. Schematic of the output matching network for carry amplier V4D . 4.12. Layout and S-Parameter simulation of the carry output matching network V4D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.13. Stability factor of the carry amplier V4 . . . . . . . . . . . . . . . . 4.14. Schematic of the input network for the carry amplier V5 . . . . . . 4.15. Layout and S-Parameter simulation results of the input network for the carry amplier V5 . . . . . . . . . . . . . . . . . . . . . . . . . . 4.16. Schematic of the output network for the carry amplier V5 . . . . . 4.17. Layout and S-Parameter simulation results of the output network for the carry amplier V5 . . . . . . . . . . . . . . . . . . . . . . . . . . 4.18. Schematic of the input network for the peak amplier V4 . . . . . . 4.19. Layout and S-Parameter simulation results of the input network for the peak amplier V4 . . . . . . . . . . . . . . . . . . . . . . . . . . 4.20. Schematic of the output network for the peak amplier V4 . . . . . 4.21. Layout and S-Parameter simulation results of the output network for the peak amplier V4 . . . . . . . . . . . . . . . . . . . . . . . . . . 4.22. Collector current versus base voltage of AT42086, with 2.7V Vcc supply 4.23. Measurement setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.24. Measurement results from test device Carry-V4B . . . . . . . . . . . 4.25. Measurement results from test device Carry-V5A with 5V supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.26. Measurement results from test device Carry-V5A with dierent supply voltages, Pin = 3dBm . . . . . . . . . . . . . . . . . . . . . . . . 4.27. Measurement results from test device Carry-V5A with dierent supply voltages, Pin = 6dBm . . . . . . . . . . . . . . . . . . . . . . . . 4.28. Measurement results from test device Peak-V4 with dierent bias voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.29. Measurement results of Doherty amplier V1B . . . . . . . . . . . . 4.30. Measurement results of Doherty amplier V1B . . . . . . . . . . . . 4.31. Measurement results of Doherty amplier V2B . . . . . . . . . . . . 4.32. Measurement results of Doherty amplier V2B . . . . . . . . . . . . 4.33. Measurement results of Doherty amplier V2B . . . . . . . . . . . . A.1. A.2. A.3. A.4. Load pull contour with 0.7V bias and 2.7 V supply . Source and Load impedance with 0.7V bias and 2.7V Load pull contour with 0.3V bias and 2.7V supply . Source and Load impedance with 0.3V bias and 2.7V . . . . . supply . . . . . supply . . . . . . . . . . . . . . . . 4.2. 4.3. 4.4. 4.5. 4.6. 4.7. 4.8. 4.9. 32 32 33 34 35 35 37
37 38 38 39 39 40 41 41 42 42 42 43 43 44 44 45 45 45 46 47 49 49 50 50 51 54 54 55 55
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List of Figures
A.5. Load pull contour with 0.7V bias and 5V supply . A.6. Source and Load impedance with 0.7V bias and 5V A.7. Load pull contour with 0.3V bias and 5V supply . A.8. Source and Load impedance with 0.3V bias and 5V A.9. Load pull contour with 0.5V bias and 5V supply . A.10.Source and Load impedance with 0.5V bias and 5V B.1. B.2. B.3. B.4. B.5. B.6. . . . . . supply . . . . . supply . . . . . supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 56 57 57 58 58 60 61 62 63 64 64
Carry amplier schematic with 0.7V bias and 2.7V supply, V4B . Carry amplier schematic with 0.7V bias and 2.7V supply, V4D . Carry amplier schematic with 0.7V bias and 5V supply, V5A . . Peak amplier schematic with 0.5V bias and 5V supply, V4 . . . Layout of the Doherty amplier V1B . . . . . . . . . . . . . . . . Layout of the Doherty amplier V2B . . . . . . . . . . . . . . . .
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List of Tables
2.1. Summary of class A, AB, B and C amplier . . . . . . . . . . . . . . 4.1. Summary of source and load impedance for design . . . . . . . . . . 5 36
ix
Abbreviation
ADS . . . . . . . . . . . . . . . . . . . . . . BJT . . . . . . . . . . . . . . . . . . . . . . CAD . . . . . . . . . . . . . . . . . . . . . CAE . . . . . . . . . . . . . . . . . . . . . CDMA . . . . . . . . . . . . . . . . . . . DUT . . . . . . . . . . . . . . . . . . . . . ESR . . . . . . . . . . . . . . . . . . . . . . FET . . . . . . . . . . . . . . . . . . . . . . HBT . . . . . . . . . . . . . . . . . . . . . HTN . . . . . . . . . . . . . . . . . . . . . LSSP . . . . . . . . . . . . . . . . . . . . . PA . . . . . . . . . . . . . . . . . . . . . . . PAE . . . . . . . . . . . . . . . . . . . . . . PCB . . . . . . . . . . . . . . . . . . . . . PEP . . . . . . . . . . . . . . . . . . . . . . PSK . . . . . . . . . . . . . . . . . . . . . . QAM . . . . . . . . . . . . . . . . . . . . . RF . . . . . . . . . . . . . . . . . . . . . . . RFC . . . . . . . . . . . . . . . . . . . . . Advanced Design System Bipolar Junction Transistor Computer Aided Design Computer-Aided Engineering Code Division Multiple Access Device Under Test Equivalent Series Resistance Field Eect Transistor Heterojunction Bipolar Transistor Harmonic Termination Network Large-Signal S-Parameter Power Amplier Power Added Eciency Printed Circuit Board Peak Envelope Power Phase Shift Key Quadrature Amplitude Modulation Radio Frequency Radio Frequency Choke
1. Introduction
1.1. Introduction
For the last decade the phenomenal growth of wireless communications has made remarkable impacts on the modern life. It began with the radio in the late 1930s and nowadays billions of people use mobile cellular phones everyday with the massive coverage around the world, which requires a signal with higher power level as well as high dynamic range. In order to communicate with the base station and among each other, every mobile device needs a RF power amplier, which is a circuit for converting DC supply power into a signicant amount of RF output power. In case of cellular telephone, the DC supply comes from the battery and the time it takes to discharge the battery while on call is an important metric to the success of a phone. Hence, there is an increasing demand for highly ecient RF power amplier to meet the growing need for power saving, compact and low cost solutions. RF power amplier with high eciency is able to extend the battery life and produce less heat, which means smaller heat sinks, this allows the cellular phone to have smaller size. Likewise for cellular base stations, high eciency power amplier is the key to save operation supply power, lower the cooling system cost and reduce thermal stress on active devices. The instantaneous eciency for the most power ampliers is at its highest at its peak envelope power and decreases as output power decreases. In modern digital communication for maximum spectrum eciency the modulation techniques like Phase Shift Key (PSK) or Quadrature Amplitude Modulation (QAM) are used in modulated signals such as W-CDMA. This results in a very large peak to average ratios of between 6 dB and 13 dB in the output power of signal [3], it means the power amplier are often operated in low eciency area. There are many methods to increase the eciency of power amplier for large range of output power like the Kahn Envelope Elimination and Restoration method [16] or the Chireix-outphasing transmitter [8], but they require a complicated circuitry. The Doherty amplier is the best candidate, as a relatively simple eciency enhancement technique. The rst goal in this thesis is to analyze the functionality and performance of the classical Doherty amplier architecture. The second one is to design, manufacture and evaluate a classical Doherty amplier, which is capable of deliver 20 dBm maximum output power at 900 MHz.
CHAPTER 1. INTRODUCTION
1.2. Thesis organization

The thesis is organized as follows: Chapter 1 is a short introduction on the topic of power amplier and the need for high eciency amplier. The main objects of this thesis are given at the end of the chapter. Chapter 2 starts with a brief review of the classes of power ampliers and their maximum available eciencies. This is followed by the principle of Dohertys solution to increase the eciency of the power amplier. At the end is the review of the ideal Doherty power amplier. This chapter provides the support theory for the power amplier design process. Chapter 3 explains in detail the design and implementation of a Doherty power amplier using the analytic method or load-line technique. A discussion on the advantages and disadvantages of this design is given at the end of the chapter. Chapter 4 discusses the new approach on design of a Doherty amplier with load-pull technique. The problem with the implementation from simulation into hardware using the lumped component is explained at the begin of the chapter. This is followed by the introduction of the load-pull technique, after that the detail of using of using load-pull technique in designing Doherty amplier is given. At the end a short review of the performance and measurement results is provided. Finally the conclusions of this thesis and recommendations for further work are given in Chapter 5.
2. Doherty Amplier Architecture

2.1. Power Amplier Classes
Before going to the functionality of Doherty architecture, a short review of class A, B and C power ampliers and the collector eciency of a PA1 is in order. The class of a PA is dened by its conduction angle, which is dened as the portion of each RF2 sine wave the transistor is on. The simplied circuit in Figure 2.1 shows an example for PA class B: the input drive current I is assumed to be sinusoidal, the collector current maintains a sinusoidal shape when the transistor is on and conducts no current when it is o, all the harmonic currents are assumed to be shorted to ground by the ideal parallel resonant circuit at VCC . The resulting current I1 is sinusoidal and creates a sinusoidal voltage waveform as it terminates in the load resistance RL . The class B amplier is dened as having a conduction angle of = , which means that the transistor conducts for half of the RF cycle. The bias voltage VP C is congured for class B operation so that the base-emitter junction remains forward biased for half of the RF cycle. Class A amplier has a conduction angle of = 2, it requires the bias voltage
Figure 2.1.: Ideal class B amplier circuit

VP C to be suciently high to maintain forward base current throughout the RF cycle. Class C operation is dened as having any conduction angle less than and ampliers with conduction angle between and 2 are referred to as class AB. Figure 2.2 shows resulting collector current IC with dierent amplier class. Collector eciency is dened as the ratio of the to load delivered RF power to the consumed DC power from collector voltage supply, as show in (2.1), where If 1
1 2
Power Amplier Radio Frequency
CHAPTER 2. DOHERTY AMPLIFIER ARCHITECTURE
Figure 2.2.: Conduction angles for a class A, B or C amplier

is the magnitude of the fundamental component of the collector current waveform: = Pout PDC,coll 2 If 1 RL (If 1 / 2)2 RL = = IDC,coll Vcc 2IDC,coll Vcc (2.1)
A class B amplier example is used to demonstrate the calculation of eciency, because of its ease of analysis and its application in Doherty architecture. Figure 2.3 displays the collector waveform current and voltage of a class B transistor (assuming all harmonic currents are terminated that the voltage at the load is a sinusoidal wave), the drawn line shows the transistor in saturation mode3 , the dashed line shows the transistor out of saturation mode. The eciency is directly related to the DC power dissipated in the transistor. Since the collector current IC is zero for half the conduction cycle, the instantaneous power dissipation in the transistor happens only during the lower half cycle of the voltage swing, where the product of IC and VC is non-zero. This area is shown in Figure 2.3 as a hashed area under the curve, and as the voltage swing is reduced, the area under the curve goes up, therefore the eciency of transistor is reduced. The current waveform of a class B transistor is a half sine wave, its DC and fundamental values If 1 from the Fourier Series are: IDC = IP eak (2.2)
IP eak If 1 = 2 Substituting these into (2.1) gives If 1 IP eak RL 4 IP eak Vcc VL = 4 Vcc =
3
(2.3)
(2.4) (2.5)
Saturation: The condition, in which the minimum value of voltage swing at the collector equals the minimum voltage of P-N junction or in ideal condition 0V
Figure 2.3.: Collector current and voltage with power dissipation

which VL = If 1 RL is a magnitude of voltage swing at the load.At saturation, VL = Vcc and = /4 = 78.5%, therefore the maxinum eciency of class B transistor is 78.5%. Table 2.1 shows the summary of dierent transistor classes versus conduction angles and ideal collector eciencies.
Amplier class Class A Class AB Class B Class C
Conduction angle = 2 < < 2 = <
Ideal collector eciency 50% 50% to 78.5% 78.5% 78.5% to 100%
Table 2.1.: Summary of class A, AB, B and C amplier
2.2. Doherty Load Modulation

Figure 2.4 displays a transistor in common emitter circuit, the LC resonator at collector terminates all DC and harmonic frequency. UL is denoted as magnitude of voltage swing at the load and when the transistor is in saturation-mode UL reaches its maximum value. The basic idea of the load modulation is: an amplier capable of delivering P1 to load R1 at its saturation UL = UL,max (high eciency), if the load R1 can be reduced to R2 with R2 = R1 (0 < < 1), where is a ratio between R1 and R2 , and the amplier still remains in saturation mode, then the
Figure 2.4.: Transistor amplier in common emitter circuit

amplier can deliver more output power at the same UL,max and consequently the same eciency. This can be derived as follow: 2 UL,max 1 P1 = 2 R1 P2 = 2 UL,max 1 P1 = > P1 2 R2 (2.6)
(2.7)
To achieve this condition Doherty introduced the second current source into the circuit of amplier, where current from the second transistor (or tube) is used to modify the load seen by the rst device. This technique is called the active loadpull concept[14], which is shown in Figure 2.5. Assume that I1 and I2 combine in-phase at RL , the relation between the impedances R1 , R2 and currents I1 , I2 is shown as follows: I1 + I2 R1 = RL (2.8) I1 R2 = RL I1 + I2 I2 (2.9)
By using this eect, the current from one transistor can be used to manipulate the load resistance seen by the other. But the active load-pull concept illustrated in Figure 2.5 moves the load impedance seen by Q1 in the wrong way, as the current I2 increases so increases the impedance R1 . So Doherty used an impedance inverter network at the output of the rst transistor to reverse the active load-pull eect, this provides a reducing of R1 as I2 increases. If this reducing R1 is coupled with a rising RF drive to Q1 , the saturation mode at Q1 is still assured, consequently the eciency remains at maximum. The impedance inverter in Figure 2.6 is realized by using a quarter wavelength line with characteristic impedance of ZIN V , the governing equation for the impedance inverters is: 2 R1 R1,T = ZIN V (2.10)
Figure 2.5.: Active load-pull concept
Figure 2.6.: Doherty amplier architecture

P1 is denoted as the output power delivered from Transistor T1 into the transmission line and P1,T is the power out of the transmission line. Assuming a lossless transmission line, the current I1 at transistors side can be calculated as: P1 = P1,T
2 I1,ef f R1 = 2 VL,ef f
(2.11) (2.12) (2.13)
R1,T
2 2 I1,ef f R1 R1,T = VL,ef f
Using (2.10) I1,ef f = and the current I1,T at loads side is:
2 I1,T,ef f R1,T = 2 V1,ef f
VL,ef f IIN V
(2.14)
R1
(2.15) (2.16) (2.17)
2 2 I1,T,ef f R1,T R1 = V1,ef f V1,ef f I1,T,ef f = ZIN V

Note from (2.14) and (2.17) that the voltage on one side of the inverter is proportional to the current on the other side, but voltages are not directly related. This property allows V1 to remain xed at saturation while VL is varied. The impedance inverter at the output of transistor T1 introduces a 90o phase lag in the output current from T1 , therefore the RF input of T2 must also be delayed by 90o for I2 and I1,T to combine in phase. This can be achieved with a second impedance inverter at the input of transistor T2 , in Figure 2.6 a second quarter wavelength transmission line is used.
2.3. Analysis of the Doherty Amplier Architecture

2.3.1. Classical Doherty Amplier
Doherty chose both transistors to deliver half the power to the load at full output power: PT 1,max PT 2,max 1 = = (2.18) PL,max PL,max 2 this establishes a relation between R1,T , R2 and RL at full power as follows:
2 VL,max
R1,T,max
2 VL,max
R2,max
1 VL,max 2 RL
(2.19) (2.20)
R1,T,max = R2,max = 2 RL
The characteristic impedance of the impedance inverter is also chosen to be 2 times the load impedance ZIN V = 2 RL (2.21) These decisions result a region of high eciency from full power to 6dB below full power. Doherty summarized the voltage and current relationships for the two devices in Figure 2.7 and the eciency of the amplier in Figure 2.8. In the following paragraph, the term tube is used, because at the time, when Do-
Figure 2.7.: Output voltage and current of classical Doherty amplier[6]

herty rst introduced this technique, most of the power amplier were vacuum tube
Figure 2.8.: Eciency of classical Doherty amplier[6]

amplier. Figure 2.9 shows the comparison of collector eciency between classical Doherty amplier and class A, B ampliers [20]. Noted that the comparison is made with real components and a research [9] has conrmed the second peak in eciency at the transition point, the Dohertys curve of eciency in Figure 2.8 doesnt show the second peak at 6 dB under full power, therefore not fully satisfying the relationship of voltage and current in Figure 2.7. Note that tube 1 maintains constant RF plate voltage after transition point, which is dened as the point where tube 2 begins to conduct current. Both RF current curves are linear functions, but since the tube 2 turns on much later than tube 1 and ends up at the same value, the collector currents slopes are dierent. This is one of the main problem during the design of Doherty Amplier, Doherty solved this problem by using a class C amplier, which turns later on and has higher slope than the class B amplier. The ratio between R1 and R2 in Section 2.2 also designates the operation of the Doherty amplier,which can be divided into 3 main areas, the next sub-sections are dedicated to review the working progress of Doherty amplier in these areas: Low-Power area: 0 < VL < Vcc Medium-Power area: Vcc < VL < Vcc Peak-Power area: VL = Vcc . From this point on all the given AC values are peak values of the fundamental frequency and transistor T1 is referred as Carry-Transistor, transistor T2 as PeakTransistor.
Figure 2.9.: Comparision of real Doherty amplier with class A and AB amplier[20]
2.3.2. Low-Power Operation

At low input power levels, the Peak-Transistor is o (I2 = 0) and Carry-Transistor operates as a linear current source, the impedance R1,T according to (2.8) is R1,T = RL Using (2.10) gives the impedance R1 seen by the Carry-Transistor R1 (I2 = 0) = (2RL )2 ZIN V 2 = = 4RL R1,T RL (2.23) (2.22)
Assuming that the quarter wavelength transmission line is lossless, the voltage trans-
10

formation produced by the coupler is given by
2 VL V12 = 2 R1,T 2 R1 2 V1 R1 2 = R VL 1,T
(2.24) (2.25) (2.26)
V1 = VL
1 R1 =2= R1,T
The Carry-Transistor enters the saturation mode when V1 = Vcc , therefore the saturation of Carry-Transistor occours at VL = Vcc . The RF-Output current delivered by the Carry-Transistor is derived as follows I1,T VL I1 V 1 = 2 2 VL I1 = = I1,T V1 I1 = I1,T = for I1,T = IL (2.27) (2.28) VL R1,T (2.29)
For an ideal B class transistor and relationships from (2.2) and (2.3) the DC-current is calculated as 2 VL (2.30) Idc = R1,T hence, the eciency of the amplier is: PAC = = PDC =
2 VL 2R1,T 2 VL R1,T Vcc
(2.31) (2.32)
VL 4 Vcc
When the Carry-Transistor reaches saturation and the Peak-Transistor remains cuto VL = Vcc , the resultant eciency is = /4 = 78.53%. This is the rst peak of collector eciency at 6 dB under maximum output power or 3 dB under maximum input power as shown in Figure 2.9.
2.3.3. Peak-Power Operation

In this area sucient input power is provided to allow the Peak-Transistor to become saturated, collector voltages of the Carry-Transistor and the Peak-Transistor both swing from 0 < VCE < 2Vcc . According to (2.18) the currents from the Carry- and the Peak-Transistor are equal I1 = I2 = IL . Using the relation from (2.8) and (2.9) the impedances R1,T and R2 are given as follows R1,T = R2 = 2 RL (see Figure 2.10) (2.33)
Since the characteristic impedance of the impedance inverter ZIN V = 2RL , no transformation will occur, therefore the load impedance seen by the Carry-Transistor is
11

also R1 = R1,T = 2RL . Normally reducing load impedance tends to reduce the magnitude of voltage oscillation, but in this case with the rising input power the CarryTransistor is able to deliver more output current, allowing the Carry-Transistor to remain saturated during the load modulation process. The Peak-Transistor has the same supply voltage Vcc like the Carry-Transistor, sees the same load impedance at collector and delivers the same amount of output current, resulting the PeakTransistor is also saturated and has the maximum eciency. This is the second peak of eciency at full output and input power. The DC-Current from both transistor is given 2 VL Idc = Idc,1 + Idc,2 = (2.34) RL The resultant eciency =
2 VL 2RL 2 VL RL
(2.35)
is the same as the rst peak eciency in an ideal class B transistor. The collector voltage of the Carry-Transistor is saturated, the same at the rst peak eciency, while the load impedance seen at the collector node is reduced to a half, as the result the output power of Carry-Transistor at second peak eciency is two times its output power at the rst peak eciency. This accomplishes the goal of using load modulation, described at the beginning of section 2.2. The Carry- and the Peak-Transistor now deliver two times more output power than the maximum output power of the Carry-Transistor in low power region, hence, the sum of output power at peak power region is four times more than at low power, this explains the 6 dB distance between two peaks of the collector eciency versus the output power as mentioned in Section 2.3.1. And because the Peak-Transistor has the maximum eciency of a B class amplier, it appears that the biasing point of the Peak-Transistor is shifted from class C to class B, as shown in Figure 3.24(b) the Peak-Transistor at maximum output power has the same conduct angle = like the Carry-Transistor in Figure 3.24(a).
2.3.4. Medium-Power Operation

At medium power levels, the Carry-Transistor is kept at verge of saturation and the Peak-Transistor operates as a linear current source. As displayed in Figure 2.7 the current I1,T is constant in the medium-power area, in spite of the rising current of I1 , this can be proven by using the relation from (2.17) I1,T = V1 ZIN V = Vcc Vcc = ZIN V RL (2.36)
From (2.36), the RF current from Peak-Transistor to produce an output voltage VL is VL Vcc I2 = IL I1,T = (2.37) RL Using (2.14), (2.17) and (2.36) the output current I1 of the Carry-Transistor is I1 = VL I1,T VL = V1 RL for V1 = Vcc (saturated) (2.38)
12

For an ideal class B transistor, the total DC-input current is: IDC = 2 (1 + )VL Vcc RL (2.39)
2.3.5. Summary of Operation

In the low-power region, the input power is insucient to overcome the PeakTransistor bias, hence the Peak-Transistor remains cut-o. The Carry-Transistor sees a constant load transformed by the quarter wavelength and operates as a normal class-B amplier. The eciency of the system in this region is given low = VL 4 Vcc for 0 < VL < Vcc (2.40)
As the input power increases over the transition point, dened by VL = Vcc , the Carry-Transistor saturates and the Peak-Transistor begins to become active. The load R1 seen by Carry-Transistor is reduced by the additional current I2 , the Carry-Transistor remains in saturation and acts as a voltage source, since the output voltage V1 saturates, it operates at peak eciency but delivers an increasing amount of power. The eciency in medium-power region is composited of collector eciency from Carry- and Peak-Transistor, depending on which side is contributing more power at each point. Because the Peak-Transistor doesnt have the benet of loadmodulation like Carry-Transistor, its eciency is like a normal class-B amplier mid = VL /Vcc 4 (1 Vcc /VL ) + 1 for Vcc < VL < Vcc (2.41)
At PEP4 output, both transistors see 2RL loads and deliver half of system output power. The eciency is the same as class B amplier. peak = 4 for VL = Vcc (2.42)
Figure 2.11 shows the comparison of eciency between Doherty amplier with dierent values and class-B Amplier. The value of = 0.25 is a modern approach with Doherty amplier, called extended Doherty amplier, where the rst peak eciency is 12 dB below full power, therefore the region of high eciency is larger. But the dip in eciency with = 0.25 is also deeper, because the eciency of the Peak-Transistor in area near transition point is quite low. There are several researches ( [10],[21],[8],...) to reduce the dip in eciency with = 0.25.
Peak Envelope Power
13
Figure 2.11.: Ideal eciency of Doherty amplier vs. output power[5]
14
3. Design with analytic method

3.1. Design Parameters
Figure 3.1.: Simplied transistor circuit

Figure 3.1 shows a simplied common collector circuit for transistor with an RFC1 at the supply voltage. Figure 3.2 shows the resulting collector current and collector voltage of a class B transistor, the harmonic frequency is shorted to ground by an LC resonant circuit. The requirement in this thesis is to design a Doherty amplier with BJTs2 capable of delivering a power of 20 dBm or 100 mW at full output power.The design is based on the classical Doherty (section 2.3.1), therefore at peak output power each transistor delivers half of the output power 17 dBm or 50 mW. From (2.6) the amplitude of the voltage swing at the collector node as a function of output power Pf 1 and load impedance seen by collector RL is: VL = 2 Pf 1 RL (3.1)
which is shown in Figure 3.3 for an output power P = 50 mW, also the fundamental frequency If 1 is calculated as VL If 1 = (3.2) RL
1 2
Radio Frequency Choke Bipolar Junction Transistor
15
CHAPTER 3. DESIGN WITH ANALYTIC METHOD
Figure 3.2.: Collector current and voltage of class B transistor

using (2.3) the peak value Ipeak of collector current is Ipeak = 2 If 1 (3.3)
The load impedance is chosen to be 50, because the resulting voltage and collector current are in the limit range of the AT42086 BJT, and the 50 load impedance at full output power allows the design of Carry- and Peak-Transistor to be directly and individually tested with a spectrum analyzer without using any impedance converter network. Because at saturation the collector voltage is not zero, the saturation voltage for BJT normaly ranges from 0.3V to 0.5V , therefore the supply voltage is Vcc = VL + VCE,sat 2.3 + 0.4 2.7V (3.4)
the value of VL is acquired from Figure 3.3 for an 50 impedance, also Figure 3.4 displays the peak values of the fundamental and maximal currents at the collector node for 50 mW output power. As for the low-power region, where Carry-Transistor delivers half of the output power compared to its output at full output power and Peak-Transistor remains cut-o, the output power is Pout,low = 25 mW, the CarryTransistor sees a load impedance two times larger than in the peak-power region R1,low = 100 (section 2.3.2). The resulting collector current and voltage is shown in Figures 3.5, 3.6.
16
Figure 3.3.: Peak value of collector voltage at 50mW output
Figure 3.4.: Fundamental and peak value of collector current at 50mW output
17
Figure 3.5.: Collector voltage at 25mW output
Figure 3.6.: Current through load and collector at 25mW output
18

The concept circuit of Doherty amplier in Figure 2.6 is repeated in Figure 3.7 for convenience. Summary of design parameters:
Supply voltage: Vcc = 2.7V At full output power: R1 = R2 = 50. As derived in section 2.3.3, the load impedance RL = 25. The characteristic impedance of the impedance inverter ZIN V = 50. At low-power region: R1,low = 100. The bipolar-transistor AT-42086 from Avago-Technologies is used in the prototype design, because its high output power at high frequency (20dBm at 2GHz - Data sheet) and its available simulator model for CAE3 program. Agilents Advanced Design System(ADS) is used to simulate and to rene the prototype design. The FR4 substrate with 1 mm thickness, 35m copper thickness, double side and = 4.3 was used.
3.2. Input and output design

3.2.1. Input design
Requirements for designing the input circuit are:
Computer-aided engineering
19

The input power is to be equally divided between Carry- and Peak-Transistor. The output ports should be isolated from the other to prevent cross-talk. The output at port 3 is 90o phase lag compared to port 2.
Figure 3.8.: Hybrid divider

Normally a hybrid-divider (Figure 3.8) can be used to fulll these requirements, but a hybrid-divider requires a large physical space and is not exible with respect to layout design. In this thesis the input is designed using the combination of a Wilkinson-divider and a microstrip line at the output of the Wilkinson-divider to create the phase-oset between the two output-ports of the input circuit, because the output signals of Wilkinson-coupler are in-phase. The benet of using a microstrip line for phase-delay is, the length of the microstrip line can be simply adjusted to have dierent phase-oset other than 90o without any chance in power divide ratio between two transistors, because two transistor with dierent biasing are expected to have dierent phase-delay and regarding the inuences of matching circuit at base and collector node of the transistors on phase-oset. The prototype is designed to work in a 50-enviroment, so the ports P1 , P2 , P3 of the Wilkinson-coupler will see a Z0 = 50 impedance. The characteristic impedance of each arm of the coupler is Zarm = 2 Z0 70.71 (3.5) and the coupler resistor between two arms is Zcoupler = 2 Z0 = 100 (3.6)
The Wilkison-coupler is designed using microstrip line for convenient PCB4 implementation, and at 900MHz the quarter wavelength is short enough for small PCB
4
Printed Circuit Board
20
Figure 3.9.: Wilkinson coupler

layout. Using the mircostrip line calculation tool from ADS the parameters of the Wilkinson-couplers arm are W idth 1mm Length 47.8mm A 50 quarter wavelength transmission line is used to insert the 90o phase lag between the output P2 and P3 while maintaining the matching condition for all ports. The design of the input circuit is shown in Figure 3.10 There are dierences
Figure 3.10.: Input circuit

of the insertion loss between ports P2 and P3 as shown in Figure 3.11(b) due to the
21
(a) Return loss
(b) Insertion loss
Figure 3.11.: Return loss and Insertion loss of the input circuit
(a) Phase delay
(b) Isolation between outputs
Figure 3.12.: Phase delay and isolation of the input circuit

dierent length of transmission lines and this also causes degradation in return loss (Figure 3.11(a)), but the dierence is negligible. Figure 3.12 displays the resulting phase-oset between the two output ports of the input circuit. The 90o phase-lag between port P2 and P3 is temporary, because the phase delay of the Carry- and Peak-Transistor with dierent biasing is expected to be dierent, the length of the transmission line can be later adjusted for the optimal phase delay, which required for the outputs of the Carry- and Peak-Transistor to combine in-phase later. There is also a research on uneven power divider [12], in which the Peak-Transistor receives more input power than the Carry-Transistor to achieve the same output power. This can be useful, if the both transistor are the same type and it is dicult for the PeakTransistor to have the same maximal output current like the Carry-Transistor.
22
3.2.2. Output design

As mentioned in the summary of the design paramters (section 3.1) the load impedance is RL = 25, for the convenience of directly using a spectrum analyzer for measurement the output signal later, an impedance converter transformation is used to convert the 50 terminal impedance of the spectrum analyzer to 25 load impedance. The impedance converter is a quarter wavelength mircostrip line, its characteristic impedance is: Zoutput = RL Rterminal = 25 50 35.35 (3.7) Hence, the physical parameters of the mircostrip line at 900MHz are: W idth = 3.27mm Length = 45.12mm The output circuit (Figure 3.13) consists of two parts: A 35 quarter wavelength microstrip line to transform the 50 terminal load to the 25-load. A 50 quarter wavelength microstrip line acting as an impedance inverter between the output of the Carry-Transistor and the 25 load.
Figure 3.13.: Output circuit

The disadvantage of this design is, there is lack of isolation between Port P1 and Port P2 (Figure 3.15(b)), this may cause undesired talk over between P1 and P2 . There is also dierence in insertion loss from P1 to P3 and from P2 to P3 because of the dierent length of transmission line. Figure 3.14 shows the 90o phase-oset between the signal from P1 to P3 and the signal from P2 to P3 .
23
Figure 3.14.: Phase of output signal
(a) Insertion loss
(b) Isolation between input P1 and P2
Figure 3.15.: Insertion loss and Isolation from P1 and P2
24
3.3. Carry Amplier design

Before the design of Carry amplier begins, a simulation is made to determine the characteristic of the transistor AT42086. This information is used to design the bias network for the Carry-transistor. As mention in section 2.3.1 the Carry-transistor needs to be biased in class B mode, therefore from gure 3.16 the bias voltage to set to UBias,B = 0.7V. To improve the stability behavior of the transistor, a voltage
Figure 3.16.: Collector current of AT42086 with Vcc = 2.7V

feed-back circuit is deployed between the collector and the base node of the Carrytransistor, this will act as a controlled feed-back path between the collector and base node and the coupling resistance will suppress the unwanted inuence from the collector node to the base node . The value of impedance in feed-back circuit is selected based on simulation experiment with the stability factor calculation function from ADS, goals are to achieve unconditionally stable and to maintain high-gain at 900 MHz. The schematic of the Carry-Amplier is shown in Figure 3.17,at the base node a matching network is used for matching purpose. This matching network is designed by using the LSSP5 function from ADS. A 50 quarter wavelength at the collector output terminates the harmonic frequencies to ground. The components in the simulation of the carry amplier shown in Figure 3.17 are ideal components, with innite quality factor. From simulation result the carry amplier has 14 dB gain at 900 MHz, therefore the output reaches the transition point 14 dBm with 0 dBm input power.
Large Signal S-Parameter simulation
25
Figure 3.17.: Carry-Amplier circuit simulation
3.4. Peak Amplier design

The design of Peak-amplier is highly dependent on the operating point of the Carryamplier, in this case the bias voltage of the Peak-amplier must be low enough so that at the transition point, 14 dBm output power, the Peak-transistor is in cut-o mode, but still high enough for the peak-transistor to achieve the same output power like the carry-transistor at max output power. Because at 900 MHz the AT-42086 is almost at its limit in the gain factor, and as discussed in section 2.3.1 the slope of the collector current from the peak-transistor is higher than the one from the carry-transistor, therefore a stabilization circuit for the Peak-transistor is removed as a trade-o for power gain. This decision can be accepted at this point, because the Peak-Transistor is biased very low, only conducts for short time. The input
Figure 3.18.: Peak-Amplier simulation circuit

matching for Peak-Amplier is based on LSSP-Simulation, and used to improve the power gain. The bias voltage of the Peak-Transistor is set to be 0.3V
26
3.5. Design review

Figure 3.19 shows the nal stage of the Doherty amplier in simulation. The simulation circuits of Carry- and Peak-Amplier are combined with the input and output circuit. Figure 3.20 shows the resulting collector eciency of the simulation circuit.
Figure 3.19.: Doherty Amplier Simulation

As expected the rst maximum eciency is reached at Pin = 3 dBm or Pout = 14 dBm and the second maximum by Pin = 6 dBm or Pout = 20 dBm. The maximum eciency is only about 50%, lower than the expected eciency of 78.52% in Section 2.3, because of the saturated voltage VCE the collector voltage does not swing from 0 to 2Vcc and due to the mis-matched at output of the transistor the output power can not fully delivery to load. Although the rst maximum drifts to near Pout = 15 dBm in Figure 3.20(b), this can be explained by the performance of Carry- and Peak-Transistor at transition point Pin = 3 dBm in Figure 3.21. At Pin = 3 dBm the Carry-Transistor is almost at its saturation and the voltage at load is relatively high as well as the collector voltage of Peak-Transistor, because of Miller-eect[17] between the collector node and the base not, the base voltage of Peak-Transistor is shifted higher and the PeakTransistor begins to conduct sooner than expected.
(a)
(b)
Figure 3.20.: Collector eciency of the simulation circuit 27
(a) Carry-Transistor
(b) Peak-Transistor
Figure 3.21.: Carry- and Peak-Transistor at transition point Pin = 3dBm
(b) Peak-Transistor
Figure 3.22.: Carry- and Peak-Transistor at max input power Pin = 6dBm
At Pin = 6 dBm both transistors are in saturation as expected (Figure 3.22) and the output power is Pout = 20 dBm, the amplier reaches its maximum eciency. Figure 3.23 shows the summary performance of voltage and current in Carry- and Peak-Transistor dependent on Pin . There is a dip in collector voltage of the CarryTransistor due to the non-linear slope of Peak-Transistors collector voltage. At high input power level the bias of Peak-Transistor is shifted from class C to class B, this explains the waveform of collector current in Figure 3.24(b), therefore the maximum eciency of Doherty amplier is equal the maximum eciency of class B amplier as predicted in Section 2.3.3. Figure3.25(b) illustrates the gain factor of the Doherty amplier in simulation, the gain factor has a non-linear progress in comparison with the result from [10], which displays in Figure 3.26, this result is caused because of the small collector current of the transistor, the collector current at its maximum value according to Figure 3.16, is still in the non-linear area. In order to improve the linearity the collector current must be large enough to overcome the non-linear area, in this case it is not recommended from the data sheet, because the maximum limit collector current of the AT42086 transistor is only 80 mA. The research in [22] is dedicated to improving the linearity of the Doherty Amplier using Heterojunction Bipolar Transistor(HBT), which is a improvement of BJT for high frequency and high power application.
28
(a) Collector voltage
(b) Collector current
Figure 3.23.: Summary of collector current and voltage in simulation (line carry, dashed - peak), peak value of the fundamental frequency
(b) Peak-Transistor
Figure 3.24.: Waveform of collector current at the Carry- and Peak-Transistor
(a) PAE
(b) Gain
Figure 3.25.: PAE and Gain of Doherty amplier
29
Figure 3.26.: Output power, PAE, Gain versus input power [10]
The design in this section is quite easy to understand and straightforward, but this also has some disadvantages: Using the S-Paramter simulation is not particularly useful for designing high power amplier. The performance of the design depends heavily on the accuracy of each discrete components. Realization with discrete components and microstrip lines can be a major challenge, because of the physical form of the components. The mircostrip lines between the discrete components are not taken in to account in the simulation, and may cause undesired eects on the performance. The calculation of load impedance only concerns the resistive impedance, while at high frequency the imagine part of load impedance also has great inuent on performance of the transistor. The HF-bypass capacitors have a value of 100 pF and at 900 MHz it is quite dicult to acquire a capacitor, which has this capacitance. The typical limit value for capacitor at this frequency is 10 pF. The quarter wavelength microstrip line lter at collector output can only lter the even harmonic frequency and its eect reduces with the increasing frequency because of the inaccuracy of circuit fabrication.
30
4. Design with Load-Pull technique

4.1. Quality factor Q
Quality factor is dened as the ratio of the stored energy and the average dissipated power multiplied by the frequency. Q = 0 Estored Eloss (4.1)
Noted 0 is the resonant frequency of a resonant circuit.Regarding a parallel conguration with a resistor, a capacitor and an inductor in parallel, the equation for the Q is shown R R Qp = = = 0 RC (4.2) 0 L L/C and the Q factor for the conguration of RLC in series is Qs = L/C R (4.3)
The Q Factor is very important at RF, where all the parasitic elements of package and environment have a signicant inuence on performance of the circuit. In Figure 4.1 is models of capacitor and inductor at RF. The ESR denotes the resistive impedance of parasitic element. Each capacitor and inductor has a self-resonant frequency, where capacitor becomes inductor and inductor becomes capacitor because of the parasitic capacitor and inductor. Figure 4.2 illustrates the insertion loss of capacitor depend on frequency, this leads to problem with choosing a usable
(a) Capacitor RF model
(b) Inductor RF model
Figure 4.1.: Capacitor and inductor model at radio-frequency 31
CHAPTER 4. DESIGN WITH LOAD-PULL TECHNIQUE
Figure 4.2.: Insertion loss of capacitor [Murata-Data sheet]

capacitor for the design in chapter 2, the lowest peak of insertion loss denotes the self-resonant frequency of capacitor. In Figure is a measurement result of a 220 nF capacitor, the result shows that at 900 MHz the capacitor is already a inductor.
Figure 4.3.: Measurement the 220nF capacitor
32
4.2. Power Amplier design with Load-Pull Technique

For designing power amplier, using the conjugated complex impedance with SParameter simulation to achieve low noise and maximal power is not so useful, because the S-Parameter simulation only shows the small-signal response of amplier in a 50 environment as a function of frequency and bias point. Due to non-ideal eects, including transistor parasitics, nite RF choke inductance and bias networks, classical design with S-Parameter can not predict well for realistic large-signal operation of RF PA device. Design-key to achieve the maximal output power with power amplier is to present a optimum source and loadimpedance to the transistor amplier. Load-pull analysis is a method for characterizing nonlinear behavior of high-power transistor under large signal, this information is used to determine the optimum source and loadimpedance for the desired performance. The load-pull technique is essentially, a process of varying the impedance seen by
Figure 4.4.: Block diagram of a load-pull system[19]

the output of an active device to other than 50 in order to measure performance parameters. The data are plotted on a Smith chart as contours, which directly helps nding out the optimal load impedance, normally the decision is based on trade-o between the output power and PAE1 , where the PAE is calculated as: P AE = Pout Pin PDC (4.4)
In Figure 4.4 is a simplied diagram of a load-pull system. The power transistor is placed at DUT2 , the bias voltage and supply voltage are set up as a desired working condition. A pair of tuner at input and output are used to vary the input
1 2
Power Added Eciency Device Under Test
33

and output impedance. The accuracy of load-pull measurement is highly depended on the tuner, for high repeatability measurement data a precision tuner is needed. The active transistors performance data will be acquired while the tuner varies its impedances, the entire process is controlled by a computer. The real hardware loadpull measurement is highly recommended for designing high frequency high power amplier, which requires high reliable data, although this method is high cost and requires large amount of time. There is a alternative for hardware load-pull measurement, in this thesis the virtual impedance tuner embedded in the circuit simulator of Agilents ADS3 is used, while the Load-Pull Simulation in ADS does not calculate the collector eciency, the PAE can be used to determine the desired collector eciency. This load-pull simulation utilizes the fast computation power of EDA, but it depends on the accuracy and availability of large-signal transistor model. This is a biggest disadvantage of virtual load-pull measurement, because most of the semiconductor manufacturer only provides the small-signal transistor model, and the large-signal model is not so accuracy. With the load-pull method, the goal for design is concentrated on maximal output power, therefore the input and output matching maybe poor, because it is intentionally mismatched in order to achieve maximal RF power generation. The results from the Load-Pull simulation are the impedance of source ZS and the impedance of load ZL (Figure 4.5), which are needed to be presented at the base and the collector nodes of the transistor to achieve the desired output power and PAE.
Figure 4.5.: Results of load-pull technique
4.3. Design parameters

The Doherty amplier design in this section is aimed to have the rst peak of collector eciency at 0 dBm input power and the second peak at 3 dBm input power like in the design with analytic method. Therefore, the bias voltage for the carry transistor remains the same 0.7V as in the previous chapter, as well as the supply voltage of 2.7 V. The result from load pull simulation in Figure A.1 shows that the carry transistor can deliver 17.89 dBm maximal output power and have the PAE of 50.2%
3
Advanced Design System
34
(a) Collector eciency
(b) Pout , Gain
Figure 4.6.: Measurement results from test device Carry-V4B, measurement 1
(b) Pout , Gain
Figure 4.7.: Measurement results from test device Carry-V4B, measurement 2

at 3 dBm input power. At the maximal output power of the Doherty amplier the carry transistor only needs to deliver 17 dBm output power at 3 dBm input power (Section 3.1), therefore the load impedance can be moved to further outside of the middle of the output power contour toward the center of the PAE contour. Figure A.2 shows the pair of source and load impedances, which are needed to present at the base and collector nodes of the transistor, is: ZS,B,V 4 = 10.50 j6.6[] ZL,B,V 4 = 66.398 + j10.26[] Figure 4.6 shows that with ZS,B,V 4 and ZL,B,V 4 the carry amplier can not able to deliver 17 dBm output power with 3 dBm input power and the collector eciency is only about 35%. The supply voltage was varied to determine the new working condition for the amplier. The new 5 V supply voltage was chosen, because of its high eciency 30% and relatively high output power about 15 dBm. Figure A.5 displays the load pull simulation results with the new supply voltage, from Figure A.6 the new pair of source and load impedance for the carry amplier is: ZS,B,V 5 = 7.96 j5.63[] ZL,B,V 5 = 108.46 + j55.464[] The design for the peak amplier is made before the measurement on the test device Carry-V4B and because of the time limit the design for the peak amplier is not
35

optimized for the new supply voltage. The result in Figure A.3 shows with 0.3 V bias and 2.7 V supply voltage the peak transistor only deliver maximum -12.38 dBm output power with PAE of 37.97% at 3 dBm input power. The decision of source and load impedance is made based on the best possible combination of output power and PAE, therefore the chosen pair of source and load impedances is: ZS,C,V 4 = 6.97 j69.01[] ZL,C,V 4 = 96.3 + j60.186[] The measurement experiments show that, the peak transistor can work with this conguration but only with higher bias and supply voltages. Table 4.1 shows the summary of the source and load impedances, which are used to design the amplier, the values of bias and supply voltages are the ones, which are used in the load pull simulation.
Device Carry-V4 Carry-V5 Peak-V4
ZS [] 10.50 -j6.6 7.96-j5.63 6.97-j69.01
ZL [] 66.398+j10.26 108.46+j55.46 96.3+j60.186
Bias, sim[V] 0.7 0.7 0.3
Supply, sim[V] 2.7 5 2.7
Table 4.1.: Summary of source and load impedance for design
4.4. Amplier design

4.4.1. Carry amplier V4
To start with the design of the input matching network, the source impedance ZS,B,V 4 = (10.50 j6.6) is conjugated, i.e. ZS,B,V 4 = (10.50 + j6.6). Using the function SmithChart from ADS, the matching network is designed to trans form a 50 to ZS,B,V 4 . A DC-Block capacitor is integrated into the input matching network, with the visual advantage of the SmithChart the value of the DC-Block capacitor can be chosen, so that the variance of the capacitor value only has minimum aection on the accuracy of the matching network, in this case the value of the capacitor can range from 6 F to 9 F without causing any sucient degradation on the matching network. The biasing network can also be a part of the input network, this can be useful in some circumstances. Using the function LineCal from ADS the input matching network is synthesized into a circuit, which shown in Figure 4.8. Later a physical layout of the input matching network is made (Figure 4.10(a)), there are some dierences in the actually physical size of the elements in comparison with the ideal strip line model. The results in Figure 4.10(b) is from the simulation with the physical layout. A small input matching network is made to compare the accuracy of this design method with the actually hardware, the results in Figure 4.9 conrm the precision of the design process. The design of the output matching network for the carry amplier follows the same procedure like the input matching network, the conjugated load impedance
36
Figure 4.8.: Schematic of input matching for carry V4
Figure 4.9.: Comparison between software simulation and hardware measurement of the carry input matching network V4 , Simulation-Line, Hardware-Symbol
ZL,B,V 4 = (66.398 j10.26) is used to design the output matching network, excepted that at the output network a lter for the harmonic frequencies is needed. The lter for the harmonic frequencies can be a part of the matching network or implemented separated as a Harmonic Termination Network(HTN), such network was used in the research [4] to achieve the optimum lter for the harmonic frequencies. Because the lack of time and to simplify the design process only a simple lter with quarter wavelength is used. Figure 4.11 shows the schematic of the output matching network, in Figure 4.12(a) is the physical layout of the matching network, and in Figure 4.12(b) is the S-Parameter simulation result. Even though the lter network is quite simple, its result is good enough to lter the second and third harmonic frequencies. One of the aspect, which was not taken into account with the load pull simulation, is stability factor of the amplier. Figure 4.13(a) displays the result of stability factor calculation using the function StabFact from ADS, there is a major problem with the stability in the low frequency region, the early prototype of the Carry amplier V4 also conrms this problem during the test measurement. Normally the open loop design of amplier should not cause any problem with the stability factor, but in this case the Miller capacitor between the collector and the base and the parasitic elements of the transistor package cause the unwanted feed-back from the collector to the base. In the low frequency region the reactance of the 7 F DC-Block capacitor in the input and output network is too high, therefore the low frequency wave component can not be terminated to ground. To solve this problem a 470 nF and a
37
(a) Layout
(b) Simulation results
Figure 4.10.: Layout and S-Parameter simulation result of the carry input matching network V4
Figure 4.11.: Schematic of the output matching network for carry amplier V4D
1 nF are implemented into the input and output network, also the bias and supply network are enhanced with large capacitors to create a short-cut to ground for the low frequency wave. At high frequency region most of the new added capacitors have already lost the property of capacitor, therefore there is no unwanted eect on the accuracy of the matching networks. Figure 4.13(b) shows the improvement of the stability factor after stabilization procedure, the stability factor is now above 1 for all frequencies. The nal design for the carry amplier V4D is shown in Figure B.2.
38
(a) Layout
Figure 4.12.: Layout and S-Parameter simulation of the carry output matching network V4D
(a) Before stabilization
(b) After stabilization
Figure 4.13.: Stability factor of the carry amplier V4
39
4.4.2. Carry amplier V5, Peak amplier V4 and Doherty amplier

The designs of the carry amplier V5 and the peak amplier V4 follow the same procedure as one of the carry amplier V4, but because of the time limit the output network of the peak amplier V4 does not have any improvement on lter characteristic. Note that the improvements on the stability property of the amplier for the carry amplier V5 and the peak amplier V4 are taken over from the design of the carry amplier V4. In Figures 4.14 and 4.16 are the schematics of the input and output networks
Figure 4.14.: Schematic of the input network for the carry amplier V5
for the carry amplier V5, their physical layout and S-Parameter simulations results are shown in Figure 4.15 and 4.17, respectively. The complete design for the carry amplier V5 is shown in Figure B.3. Figure 4.18 shows the schematic of the input network for the peak amplier V4, while the schematic of the output network is shown in Figure 4.20. The physical layouts and S-Parameter simulation results of the peak ampliers input and output networks are illustrated in Figure 4.19 and Figure 4.21, in the order as mentioned. The nal design of the peak amplier V4 is displayed in Figure B.4. The designs of the carry amplier V4 and the peak amplier V4 are combined using the input and output network of the Doherty amplier (Section 3.2) to form the Doherty amplier V1B, while the design of the Doherty amplier V2B is created using the designs of the carry amplier V5 and the peak amplier V4. The physical layouts of the Doherty amplier V1B and V2B are shown in Figure B.5, B.6, respectively. Because the inaccuracy of the AT42086s CAD model for high power signal, the performance of the designs can not be evaluated based on the simulation results, therefore both of these two designs are fabricated for hardware measurement and analysis.
40
(a) Layout
Figure 4.15.: Layout and S-Parameter simulation results of the input network for the carry amplier V5
Figure 4.16.: Schematic of the output network for the carry amplier V5
41
(a) Layout
Figure 4.17.: Layout and S-Parameter simulation results of the output network for the carry amplier V5
Figure 4.18.: Schematic of the input network for the peak amplier V4
(a) Layout
Figure 4.19.: Layout and S-Parameter simulation results of the input network for the peak amplier V4 42
Figure 4.20.: Schematic of the output network for the peak amplier V4
(a) Layout
Figure 4.21.: Layout and S-Parameter simulation results of the output network for the peak amplier V4
43
4.5. Performance review

4.5.1. DC current behavior
Figure 4.22.: Collector current versus base voltage of AT42086, with 2.7V Vcc supply
A small test circuit is made to test the accuracy of the available CAD model of the AT42086 transistor. Figure 4.22 shows that the slopes of both collector currents are the same, but the real AT42086 has the lower knee base voltage than the one from CAE model, hence, the real AT42086 oers better linearity character than the CAD model, this property is conrmed through all the measurements with hardware.
4.5.2. Carry amplier
Figure 4.23.: Measurement setup

The measurement setup is shown in Figure 4.23, the spectrum analyzer has a 50 input impedance. For convenient reason the measurement results of the carry amplier V4 are plotted again in Figure 4.24. Figures 4.25(a) and 4.26(a) show, that the carry amplier V5A reaches its maximum eciency at Pin = 3 dBm and 5 V supply voltage as expected, but the output power is only 14dBm (Figure 4.25(b)), lower than the output power of 15.5 dBm shown in Figure 4.7(b). The comparison between the linearity of the carry amplier V4 and the carry amplier V5 in Figure 4.24(b) and Figure 4.25(b) shows that the version V4 has better linear property than the version V5. All the results of the collector eciency measurements indicate, that
44
(b) Pout , Gain
Figure 4.24.: Measurement results from test device Carry-V4B
(b) Pout , Gain
Figure 4.25.: Measurement results from test device Carry-V5A with 5V supply voltage
(b) Pout , Gain
Figure 4.26.: Measurement results from test device Carry-V5A with dierent supply voltages, Pin = 3dBm
45
(b) Pout , Gain
Figure 4.27.: Measurement results from test device Carry-V5A with dierent supply voltages, Pin = 6dBm
the transistor AT42086 in class B conguration only has the maximum collector eciency about 32%. According to the results shown in Figure 4.27, to achieve the 17 dBm output power the input power must be increased to 6 dBm and the supply voltage to 7.5 V.
4.5.3. Peak amplier

The peak amplier is designed to have its maximum collector eciency at Pin = 3 dBm, therefore as shown in Figure 4.28 the bias voltage and the supply voltage are chosen to be 0.5 V and 5 V, respectively. Also the measurement results show that the maximum collector eciency of the peak amplier V4 is about 45%.
46
(a)
(b)
(c)
Figure 4.28.: Measurement results from test device Peak-V4 with dierent bias voltages
47
4.5.4. Doherty amplier

Note that after the input network of the Doherty amplier each amplier only receives the half of the input power, therefore if the amplier is design to reach its maximum output power at 3 dBm in Section 4.4 then the actually input power of the Doherty amplier must be at least 6 dBm. All the collector current values, which are measured, are DC-current values, but because of the relationship between the DC current and the AC current shown in (2.2) and (2.3) these values are still valid for the analysis. The collector eciencies in Figure 4.29 and Figure 4.30 have two peaks of eciency with dierent values, the distance between the two peaks is exactly the same as predicted in Section 2.3.5, 3 dBm versus Pin and 6 dBm versus Pout , and the second peak of eciency is not occurred at Pout = 20 dBm. With the reducing bias for the peak amplier, the rst peak of eciency is increased, but the linearity and the second peak eciency of the amplier is reduced, also the carry ampliers collector current is able to reach a higher value. Figure 4.29(d) and Figure 4.30(d) show, there is a dip in the course of the carry ampliers collector current, when the peak amplier begins to conduct. Figure 4.31(a) and 4.32(a) show, that the Doherty amplier at Pin = 3 dBm has already reached its rst peak eciency, which is too soon, this explains the low values of the ampliers collector eciency. This may be caused by the high bias of the peak amplier, from Figure 4.31(d) and Figure 4.32(d) the peak amplier begins to conduct before the carry ampliers collector current reaches its maximum values, unlike the behaviors of the collector current of the Doherty amplier V1B in Figure 4.29(d) and 4.30(d). With the reduced bias voltage for the peak amplier, the collector eciency is able to reach the maximum value of 25% (Figure 4.33), but the development of the collector currents still does not have the characteristic of a Doherty amplier. Overall the DC values of V2B ampliers collector current are too high in comparison with the DC values of the V1B ampliers collector currents. The version V2B has a lower gain factor than the gain factor of the version 1B, but the gain factors of both ampliers V1B and V2B are still lower than expected, therefore the input power level must be higher in oder to reach the maximum output power level of 20 dBm. It appears that at high power level the transistor has reached the compression, because of the drop in the gain factor. Compared the performance of the version V1B and V2B shows that the version V1B has a better controlled performance as calculated and a higher collector eciency.
48
(a)
(b)
(c)
(d)
Figure 4.29.: Measurement results of Doherty amplier V1B
(a)
(b)
(c)
(d)
Figure 4.30.: Measurement results of Doherty amplier V1B 49
(a)
(b)
(c)
(d)
(a)
(b)
(c)
(d)
Figure 4.32.: Measurement results of Doherty amplier V2B 50
(a)
(b)
(c)
(d)
51
5. Conclusions and Recommendations

5.1. Conclusions
The objective of this thesis is to investigate the operation of the classical Doherty amplier and the development of a 900 MHz Doherty amplier, which is capable of delivering 20 dBm at its peak eciency. The functionality and support theory of the Doherty amplier are rst analyzed in Chapter 2. Analysis and design equation based on the classical assumption are given. In Chapter 3 a design with the available CAD model is given using the analytic method. This design delivers a deeper understanding of the functionality of a transistor with dierent bias conguration and the usage of the matching network in achieve matched condition between source and input of the amplier for maximum output power. The relation between stability factor and gain shows a typical problem with the design of amplier, in the case of the carry amplier a compromise was made to achieve a stability working behavior of the amplier while ensure the high output power. A S-Parameter simulation is used to determine the eect of the matching network on phase response of the amplier, this information was used to design the input network for the Doherty amplier, to make sure that at the load impedance the signal from the carry and peak amplier combine in-phase for the maximum output power. The problems with the leakage between the carry and peak amplier as well as the nite saturated voltage VCE and their inuent on the resulting collector eciency of the amplier are shown in the simulation result. The simulation design has a maximum collector eciency above 50% and delivers 20 dBm output power with 6.5 dBm input power. The diculty with the realization of simulation into hardware and the inaccuracy of S-Parameter simulation for high power signal have led to a new approach on the amplier design in Chapter4. Amplier design with load pull technique is one of the widely used methods in design a high power amplier. It is used to determine the optimum working condition, in which the amplier has its maximum output power with the optimum eciency. Using the load pull technique on the amplier device results in not only the real impedance part but also the imagine reactance part of the source and load impedance, which is very important in high power and high frequency power amplier. With the advance of knowing the exact impedances, which are needed to be presented to the transistor, the matching network can be designed to eliminate the unwanted inuence of components tolerance while including some extra useful attributes like lter characteristic, but the design process requires more time inten-
52
CHAPTER 5. CONCLUSIONS AND RECOMMENDATIONS

sity. In this thesis a load pull procedure is made based on simulation, therefore the reliability of the results depends on the accuracy of the CAD model. As a result, two designs of Doherty amplier are built and evaluated. The evaluation results show that the amplier is capable of delivering 20 dBm at maximum output power and has a fairly Doherty-like characteristic, but with some problems in linearity and gain factor.
5.2. Recommendations
One of the reasons, which results bad performance and diculty during the design process is caused by the choice of transistor. In the modern RF high power amplier most of the transistor use the HBT or FET technology because of their ability to work with high power and high frequency conditions ([21],[11],[12],[10],...), therefore the further work should focus on using these new technologies. Although working with the load pull technique based on simulation can reduce the time intensity of the design, it requires an accurate CAD model, which should be able to characterize the behavior of the transistor with high power signal. If it is possible, a hardware load pull measurement on real hardware is recommended. There are some necessary tests, which are needed to be carried out, in order to fully understand the property of the designed Doherty amplier like the two-tone test for 3dB-interception point or the IMD3 test for the intermodulation distortion from the third harmonic frequency. If the further work is based on the same transistor, then a research on optimizing the performance of the amplier based on the measurement results is advised.
53
A. Load pull simulation results
Figure A.1.: Load pull contour with 0.7V bias and 2.7 V supply
Figure A.2.: Source and Load impedance with 0.7V bias and 2.7V supply
54
APPENDIX A. LOAD PULL SIMULATION RESULTS
Figure A.3.: Load pull contour with 0.3V bias and 2.7V supply
Figure A.4.: Source and Load impedance with 0.3V bias and 2.7V supply
55
Figure A.5.: Load pull contour with 0.7V bias and 5V supply
Figure A.6.: Source and Load impedance with 0.7V bias and 5V supply
56
57
58
B. Schematics and layouts
59
APPENDIX B. SCHEMATICS AND LAYOUTS
Figure B.1.: Carry amplier schematic with 0.7V bias and 2.7V supply, V4B
60
Figure B.2.: Carry amplier schematic with 0.7V bias and 2.7V supply, V4D
61
Figure B.3.: Carry amplier schematic with 0.7V bias and 5V supply, V5A
62
Figure B.4.: Peak amplier schematic with 0.5V bias and 5V supply, V4
63
Figure B.5.: Layout of the Doherty amplier V1B
Figure B.6.: Layout of the Doherty amplier V2B
64
C. Data sheet
65
AT-42086 Up to 6 GHz Medium Power Silicon Bipolar Transistor Data Sheet
Description
Avagos AT-42086 is a general purpose NPN bipolar transistor that offers excellent high frequency performance. The AT-42086 is housed in a low cost surface mount .085" diameter plastic package. The 4 micron emitter-to-emitter pitch enables this transistor to be used in many different functions. The 20 emitter finger interdigitated geometry yields a medium sized transistor with impedances that are easy to match for low noise and medium power applications. Applications include use in wireless systems as an LNA, gain stage, buffer, oscillator, and mixer. An optimum noise match near 50 up to 1 GHz, makes this device easy to use as a low noise amplifier. The AT-42086 bipolar transistor is fabricated using Avagos 10 GHz fT Self-Aligned-Transistor (SAT) process. The die is nitride passivated for surface protection. Excellent device uniformity, performance and reliability are produced by the use of ion-implantation, self-alignment techniques, and gold metalization in the fabrication of this device.
Features
High Output Power: 20.5 dBm Typical P1 dB at 2.0 GHz High Gain at 1 dB Compression: 13.5 dB Typical G1 dB at 2.0 GHz Low Noise Figure: 1.9 dB Typical NFO at 2.0 GHz High Gain-Bandwidth Product: 8.0 GHz Typical fT Surface Mount Plastic Package Tape-and-Reel Packaging Option Available Lead-free Option Available
86 Plastic Package
Pin Connections
EMITTER 4
420
BASE 1
COLLECTOR 3
2 EMITTER
AT-42086 Absolute Maximum Ratings

Symbol
VEBO VCBO VCEO IC PT Tj TSTG
Parameter
Emitter-Base Voltage Collector-Base Voltage Collector-Emitter Voltage Collector Current Power Dissipation [2,3] Junction Temperature Storage Temperature
Units
V V V mA mW C C
Absolute Maximum[1]
1.5 20 12 80 500 150 -65 to 150
Thermal Resistance [2]: jc = 140C/W

Notes: 1. Permanent damage may occur if any of these limits are exceeded. 2. TCASE = 25C. 3. Derate at 7.1 mW/C for TC > 80C.
Electrical Specifications, TA = 25C

Symbol
|S 21E| 2
Parameters and Test Conditions

Insertion Power Gain; VCE = 8 V, IC = 35 mA f = 1.0 GHz f = 2.0 GHz f = 4.0 GHz f = 2.0 GHz f= 4.0 GHz f = 2.0 GHz f = 4.0 GHz f = 2.0 GHz f = 4.0 GHz f = 2.0 GHz f = 4.0 GHz
Units
dB
Min.
15.0
Typ.
16.5 10.5 4.5 20.5 20.0 13.5 9.0 1.9 3.5 13.0 9.0 8.0
Max.
P1 dB G1 dB NFO GA fT hFE ICBO IEBO CCB Note:
Power Output @ 1 dB Gain Compression VCE = 8 V, IC = 35 mA 1 dB Compressed Gain; VCE = 8 V, IC = 35 mA Optimum Noise Figure: VCE = 8 V, IC = 10 mA Gain @ NFO; VCE = 8 V, IC = 10 mA Gain Bandwidth Product: VCE = 8 V, IC = 35 mA Forward Current Transfer Ratio; VCE = 8 V, IC = 35 mA Collector Cutoff Current; VCB = 8 V Emitter Cutoff Current; VEB = 1 V Collector Base Capacitance[1]: VCB = 8 V, f = 1 MHz
dBm dB dB dB GHz A A pF 30
150
270 0.2 2.0
0.32
1. For this test, the emitter is grounded.
AT-42086 Typical Performance, TA = 25C

24 P1 dB (dBm)
2.0 GHz
20
1.0 GHz
40 35 30
MSG
20
4.0 GHz
16 |S21E|2 GAIN (dB)

P1dB
2.0 GHz
GAIN (dB)
16
12
25 20 15
|S21E|2 4.0 GHz MAG
2.0 GHz
12 G1 dB (dB)
G1dB
10 5
4.0 GHz
4 0 10 20 30 IC (mA) 40 50
0 0 10 20 30 IC (mA) 40 50
0 0.1 0.3 0.5 1.0 3.0 6.0 FREQUENCY (GHz)
Figure 1. Output Power and 1 dB Compressed Gain vs. Collector Current and Frequency. VCE = 8 V.
Figure 2. Insertion Power Gain vs. Collector Current and Frequency. VCE = 8 V.
Figure 3. Insertion Power Gain, Maximum Available Gain and Maximum Stable Gain vs. Frequency. VCE = 8 V, IC = 35 mA.
24 21 18 15 GAIN (dB) 12 9 6 3 0 0.5

NFO GA
4 3 2 1 1.0 2.0 3.0 0 4.0 5.0 NFO (dB)
FREQUENCY (GHz)
Figure 4. Noise Figure and Associated Gain vs. Frequency. VCE = 8 V, IC = 10 mA.
Bibliography
[1] K. F. Brand. The Experimental Design and Characterization of Doherty Power Ampliers. Masters thesis, Stellenbosch University, 2006. [2] Bumman Kim, Jangheon Kim, Ildu Kim, and Jeonghyeon Cha. The doherty power amplier. IEEE mircowave magazine, October 2006. [3] Charles J.Meyer, Booton Electronics. Measuring the peak-to-average power of digitally modulated signals, April 1993. [Online; accessed August-2011]. [4] X. Cui. Ecient Radio Frequency Power Ampliers for Wireless Communications. PhD thesis, The Ohio State University, 2007. [5] Darren W. Ferwalt. A Base Control Doherty Power Amplier Design for Improved Eciency in GSM Handsets. Masters thesis, Oregon State University, 2004. [6] W. Doherty. A new high eciency power amplier for modulated waves. Proceedings of the Institute of Radio Engineers, 24(9):1163 1182, sept. 1936. [7] N. Dubuc, C. Duvanaud, and P. Bouysse. Analysis of the doherty technique and application to a 900mhz power amplier. In Microwave Conference, 2002. 32nd European, pages 1 3, sept. 2002. [8] F.H. Raab, P.M. Asbeck, S.C. Cripps, P.B. Kenington, Z.B. Popovic, N. Pothecary, J.F. Sevic and N.O. Sokal. Power ampliers and transmitter for RF and microwave. IEEE Trans. Microwave Theory and Tech, 50, March 2002. [9] Frederick H. Raab. Eciency of doherty RF power-amplier systems. IEEE, 33(3), September 1987. [10] M. Iwamoto, A. Williams, P.-F. Chen, A. Metzger, C. Wang, L. Larson, and P. Asbeck. An extended doherty amplier with high eciency over a wide power range. In Microwave Symposium Digest, 2001 IEEE MTT-S International, volume 2, pages 931 934 vol.2, 2001. [11] B. Kim, J. Kim, I. Kim, J. Cha, and S. Hong. Microwave doherty power amplier for high eciency and linearity. In Integrated Nonlinear Microwave and Millimeter-Wave Circuits, 2006 International Workshop on, pages 22 25, jan. 2006.
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Bibliography
[12] A. Z. Markos. Eciency Enhancement of Linear GaN RF power Amplier Using the Doherty Technique. PhD thesis, University Kassel, November 2008. [13] Robert J. McMorrow, David M. Upton and Peter R. Maloney. The Microwave Doherty Amplier. Microwave Symposium Digest, , IEEE MTT-S International, 3, September 1994. [14] S.C. Cripps. RF Power Amplier for Wireless Communications. MA: Artech House, 1999. [15] C. Tongchoi, M. Chongcheawchamnan, and A. Worapishet. Lumped element based doherty power amplier topology in cmos process. In Circuits and Systems, 2003. ISCAS 03. Proceedings of the 2003 International Symposium on, volume 1, pages I445 I448 vol.1, may 2003. [16] M. Vasic, O. Garcia, J. Oliver, P. Alou, D. Diaz, J. Cobos, A. Gimeno, J. Pardo, C. Benavente, and F. Ortega. High eciency power amplier for high frequency radio transmitters. In Applied Power Electronics Conference and Exposition (APEC), 2010 Twenty-Fifth Annual IEEE, pages 729 736, feb. 2010. [17] Wikipedia. Miller eect wikipedia, the free encyclopedia, 2011. [Online; accessed 3-August-2011]. [18] www.microwaves101.com. Eciency of Microwave Devices, October 2009. [Online; accessed August-2011]. [19] www.microwaves101.com. Load Pull for Power Devices, July 2011. [Online; accessed August-2011]. [20] X. Q. Chen, Y. C. Guo and X. W. Shi. A High Eciency and Gain Doherty Amplier for Wireless Mobile Base Stations. Microwave Journal, 51(4):102, April 2008. [21] Y. Yang, J. Cha, B. Shin, and B. Kim. A fully matched n-way doherty amplier with optimized linearity. Microwave Theory and Techniques, IEEE Transactions on, 51(3):986 993, mar 2003. [22] Y. Zhao, A. Metzger, P. Zampardi, M. Iwamoto, and P. Asbeck. Linearity improvement of hbt-based doherty power ampliers based on a simple analytical model. In Microwave Symposium Digest, 2006. IEEE MTT-S International, pages 877 880, june 2006.
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Bachelor Thesis: Analysis and Design of A 900MHz Doherty Power Amplifier

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Bachelor Thesis: Analysis and Design of A 900MHz Doherty Power Amplifier

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Analysis and design of a 900 MHz Doherty Power Amplier

Thesis Supervisors: Prof. Dr. Christoph Schick

Konstanz, August 14, 2011

1.2. Thesis organization

2. Doherty Amplier Architecture

Figure 2.1.: Ideal class B amplier circuit

Power Amplier Radio Frequency

CHAPTER 2. DOHERTY AMPLIFIER ARCHITECTURE

Figure 2.2.: Conduction angles for a class A, B or C amplier

CHAPTER 2. DOHERTY AMPLIFIER ARCHITECTURE

Figure 2.3.: Collector current and voltage with power dissipation

Amplier class Class A Class AB Class B Class C

Conduction angle = 2 < < 2 = <

Ideal collector eciency 50% 50% to 78.5% 78.5% 78.5% to 100%

Table 2.1.: Summary of class A, AB, B and C amplier

2.2. Doherty Load Modulation

CHAPTER 2. DOHERTY AMPLIFIER ARCHITECTURE

Figure 2.4.: Transistor amplier in common emitter circuit

CHAPTER 2. DOHERTY AMPLIFIER ARCHITECTURE

Figure 2.5.: Active load-pull concept

Figure 2.6.: Doherty amplier architecture

(2.11) (2.12) (2.13)

2 2 I1,ef f R1 R1,T = VL,ef f

(2.15) (2.16) (2.17)

2 2 I1,T,ef f R1,T R1 = V1,ef f V1,ef f I1,T,ef f = ZIN V

CHAPTER 2. DOHERTY AMPLIFIER ARCHITECTURE

2.3. Analysis of the Doherty Amplier Architecture

Figure 2.7.: Output voltage and current of classical Doherty amplier[6]

CHAPTER 2. DOHERTY AMPLIFIER ARCHITECTURE

Figure 2.8.: Eciency of classical Doherty amplier[6]

CHAPTER 2. DOHERTY AMPLIFIER ARCHITECTURE

2.3.2. Low-Power Operation

Figure 2.10.: Doherty amplier architecture

CHAPTER 2. DOHERTY AMPLIFIER ARCHITECTURE

(2.24) (2.25) (2.26)

2.3.3. Peak-Power Operation

CHAPTER 2. DOHERTY AMPLIFIER ARCHITECTURE

2.3.4. Medium-Power Operation

CHAPTER 2. DOHERTY AMPLIFIER ARCHITECTURE

2.3.5. Summary of Operation

Peak Envelope Power

CHAPTER 2. DOHERTY AMPLIFIER ARCHITECTURE

Figure 2.11.: Ideal eciency of Doherty amplier vs. output power[5]

3. Design with analytic method

Figure 3.1.: Simplied transistor circuit

Radio Frequency Choke Bipolar Junction Transistor

CHAPTER 3. DESIGN WITH ANALYTIC METHOD

Figure 3.2.: Collector current and voltage of class B transistor

CHAPTER 3. DESIGN WITH ANALYTIC METHOD

Figure 3.3.: Peak value of collector voltage at 50mW output

CHAPTER 3. DESIGN WITH ANALYTIC METHOD

Figure 3.5.: Collector voltage at 25mW output

Figure 3.6.: Current through load and collector at 25mW output

CHAPTER 3. DESIGN WITH ANALYTIC METHOD

Figure 3.7.: Doherty amplier architecture

3.2. Input and output design

CHAPTER 3. DESIGN WITH ANALYTIC METHOD

Figure 3.8.: Hybrid divider

Printed Circuit Board