CH32V003DS0 en
CH32V003DS0 en
V1.0
Overview
CH32V003 series is an industrial-grade general-purpose microcontroller designed based on QingKe RISC-V2A
core, which supports 48MHz system main frequency in the product function. The series features wide voltage,
single line debug, low-power consumption and ultra-small package. It provides commonly used peripheral
functions, built-in 1 group of DMA controller, 1 group of 10-bit analog-to-digital conversion ADC, 1 group of
op-amp comparator, multiple timers, standard communication interfaces such as USART, I2C, SPI, etc. The rated
operating voltage of the product is 3.3V or 5V, and the operating temperature range is -40℃~85℃ industrial-
grade.
Features
l Core: l 1 group of OPAs and comparators: connected
- QingKe 32-bit RISC-V core, RV32EC with ADC and TIM2
instruction set l 1 group of 10-bit ADC
- Fast programmable interrupt controller + - Analog input range: 0~VDD
hardware interrupt stack - 8 external signals + 2 internal signals
- Support 2-level interrupt nesting - Support external delayed triggering
- Support system main frequency 48MHz l Multiple timers
l Memory: - 1 16-bit advanced-control timers, with dead
- 2KB volatile data storage area SRAM zone control and emergency brake; can offer
- 16KB program memory CodeFlash PWM complementary output for motor control
- 1920B BootLoader - 1 16-bit general-purpose timers, provide
- 64B non-volatile system configuration input capture/output comparison/PWM/pulse
memory counting/incremental encoder input
- 64B user-defined memory - 2 watchdog timers (independent watchdog
l Power management and low-power and window watchdog)
consumption: - SysTick: 32-bit counter
- System power supply VDD: 3.3V or 5V l Communication interfaces:
- Low-power mode: Sleep, Standby - 1 USART interfaces
l Clock & Reset - 1 I²C interfaces
- Built-in factory-trimmed 24MHz RC - 1 SPI interfaces
oscillator l GPIO port
- Built-in 128KHz RC oscillator - 3 groups of GPIO ports, 18 I/O ports
- High-speed external 4~25MHz oscillator - Mapping 1 external interrupt
- Power on/down reset, programmable voltage l Security features: 64-bit unique ID
detector l Debug mode: serial single-wire debug
l 1 group of 1-channel general-purpose DMA interface
controllers l Package: SOP, TSSOP or QFN
- 7 channels, support ring buffer
- Support TIMx/ADC /USART/I2C/SPI
General- Advanced- General- System ADC
Flash Pin Package
Model SRAM purpose control purpose Watchdog Clock Channel SPI I2C USART
memory No. Form
I/O timer timer Source No.
CH32V003F4P6 TSSOP20
16K 2K 20 18 1 1 2 3 8 1 1 1
CH32V003F4U6 QFN20
CH32V003A4M6 16K 2K 16 14 1 1 2 3 6 1 1 1 SOP16
CH32V003J4M6 16K 2K 8 6 1 1 2 3 6 1 1 1 SOP8
CH32V003 Datasheet http://wch.cn
Chapter 1 Specification
Memory
DMA 7 Channels
System Bus
Reset &
SYSCLK
MUX & DIV
MUX
SRAM
HSI-RC
AHBCLK *2
OSC_IN
HSE
OSC_OUT
WWDG
GPIO
IWDG_CLK LSI-RC
IWDG PWR_CLK
EXTI
AHB Fmax = 50MHz
PWR
EXTEN
I2C SCL, SDA
AIN0~AIN7
ETR、ETR2 ADC
AFIO
Amplify
V1.0 1
CH32V003 Datasheet http://wch.cn
Reserved
0x5005 0400
Reserved
0x4002 3C00
EXTEND
0x4002 3800
Reserved
0x4002 2400
Flash Interface
0x4002 2000
Reserved
0x4002 1400
RCC
0x4002 1000
Reserved
0x4002 0400
DMA
0x4002 0000
Reserved
0x4001 3C00
USART
0x4001 3800
Reserved
0x4001 3400
SPI
0x4001 3000
TIM1
0x4001 2C00
Reserved
0x4001 2800
ADC
0x4001 2400
0xFFFF FFFFF Reserved
0x4001 1800 Port D
0x4001 1400 Port C
0x1FFF FFFF Reserved 0x4001 1000
Reserved Reserved
0x4001 0C00
0x1FFF F840 Port A
Option Bytes 0x4001 0800
0x1FFF F800 0xE010 0000 EXTI
Core Private 0x4001 0400
Vendor Bytes Peripherals AFIO
0x1FFF F7C0 0x4001 0000
Reserved 0xE000 0000
0x1FFF F780 Reserved
0x4000 7400
System FLASH PWR
(BOOT_1920B) 0x4000 7000
Reserved
0x1FFF F000
Reserved
Reserved
0x4000 5800
Peripherals I2C
0x0800 4000 0x4000 5400
0x4000 0000
Reserved
Code FLASH Reserved
0x4000 3400
16KB 0x2000 0800 IWDG
2KB SRAM 0x4000 3000
0x2000 0000 WWDG
0x0800 0000 0x4000 2C00
Aliased to Flash or
system memory
depending on FLASH
Reserved
software
configuration
0x0000 0000 0x0000 0000 0x4000 0400
4G线性地址空间 TIM2
0x4000 0000
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CH32V003 Datasheet http://wch.cn
V1.0 3
CH32V003 Datasheet http://wch.cn
to gpio(internal,to time)
128kHz IWDGCLK
LSI RC to independent watchdog
RCC_CFGR0
SW
OSC_IN 4~25MHz *2
PLLSRC
OSC_OUT HSE OSC
SYSCLK
/3 to Flash(time base)
SW
24MHz
HSI RC HSI
CSS
MCO[1:0] to Flash(register)
AHB prescaler
/1,/2.../256
HSI FCLK core free running clock
MCO
HSE
PLLCLK to Core System Timer
/8
HCLK
to SRAM/DMA
48MHz max
peripheral clock enable
to AHB peripherals
peripheral clock enable
to TIM2
to TIM1
peripheral clock enable
/2,/4,/6,/8,/12,/1 ADCPRE
to ADC
6…,/64,/96,/128
to IWDG
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CH32V003 Datasheet http://wch.cn
In addition, the system is equipped with a programmable voltage monitor (PVD), which needs to be turned
on by software to compare the voltage of VDD power supply with the set threshold VPVD.Turn on the
corresponding edge interrupt of PVD, and you can receive interrupt notification when VDD drops to the PVD
threshold or rises to the PVD threshold. Refer to Chapter 4 for the values of VPOR/PDR and VPVD.
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CH32V003 Datasheet http://wch.cn
l Sleep mode
In Sleep mode, only the CPU clock is stopped, but all peripheral clocks are powered normally and the
peripherals are in a working state. This mode is the shallowest low-power mode, but it is the fastest mode to
wake up the system.
Exit condition: any interrupt or wake-up event.
l Standby mode
The PDDS and SLEEPDEEP bits are set, and the WFI/WFE instruction is executed to enter. The power
supply of the kernel part is turned off, and the RC oscillator of HSI and the HSE crystal oscillator are also
turned off, and the lowest power consumption can be achieved in this mode.
Exit conditions: any external interrupt/event (EXTI signal), external reset signal on NRST, IWDG reset,
where EXTI signal includes one of 18 external I/O ports, output of PVD, AWU auto-wakeup.
The main peripherals used by DMA include: general-purpose/advanced-control/basic timers TIMx, DAC,
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CH32V003 Datasheet http://wch.cn
Note: DMA and CPU access the system SRAM after arbitration by the arbiter.
l Advanced-control timer
The advanced-control timer is a 16-bit auto-loading up/down counter with a 16-bit programmable prescaler.
In addition to the complete general-purpose timer function, it can be regarded as a three-phase PWM
generator distributed to 6 channels, with a complementary PWM output function with dead zone insertion,
allowing the timer to be updated after a specified number of counter cycles to repeat counting cycle, braking
function, etc. Many functions of the advanced-control timer are the same as the general timer, and the internal
structure is also the same. Therefore, the advanced-control timer can cooperate with other TIM timers
through the timer link function to provide synchronization or event link functions.
l General-purpose timer
The general-purpose timer is a 16-bit or 32-bit auto-loading up/down counter with a programmable 16-bit
prescaler and 4 independent channels. Each channel supports input capture, output comparison, and PWM
generation and single pulse mode output. It can also work with advanced-control timers through the timer
link function to provide synchronization or event link functions. In Debug mode, the counter can be frozen
while the PWM outputs are disabled, thereby cutting off the switches controlled by these outputs. Any
general-purpose timer can be used to generate PWM output. Each timer has an independent DMA request
mechanism. These timers can also process signals from incremental encoders, as well as digital outputs from
1 to 3 Hall sensors.
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CH32V003 Datasheet http://wch.cn
l Independent watchdog
The independent watchdog is a configurable 12-bit down counter that supports 7 frequency division factors.
The clock is provided by an internal independent 128 KHz RC oscillator (LSI); because the LSI is
independent of the main clock, it can run in Stop and Standby modes. IWDG is outside the main program and
can work completely independently. Therefore, it is used to reset the entire system when a problem occurs, or
as a free timer to provide timeout management for the application. It can be configured as software or
hardware to start the watchdog through the option byte. In Debug mode, the counter can be frozen.
l Window Watchdog
The window watchdog is a 7-bit down counter and can be set to free-running. It can be used to reset the entire
system when a problem occurs. It is driven by the main clock and has an early warning interrupt function; in
Debug mode, the counter can be frozen.
l SysTick Timer
This is a 32-bit optional increment or decrement counter that comes with the core controller. It is used to
generate SYSTICK anomalies (exception number: 15). It can be dedicated to the real-time operating system
(RTOS) to provide a "heartbeat" tick for the system, or it can be used as a standard 32-bit counter. It has an
automatic reload function and a programmable clock source.
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CH32V003 Datasheet http://wch.cn
The I/O pins in the system is provided by VDD. Changing the VDD power supply will change the high
value of the I/O pin output level to adapt to the external communication interface level. Please refer to
the pin description for specific pins.
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CH32V003 Datasheet http://wch.cn
1 20
PD4/A7/UCK/T2CH1ETR/OPO/T1CH4ETR_ PD3/A4/T2CH2/AETR/UCTS/T1CH4_
2 19
PD5/A5/UTX/T2CH4_/URX_ PD2/A3/T1CH1/T2CH3_/T1CH2N_
3 18
PD6/A6/URX/T2CH3_/UTX_ PD1/SWIO/AETR2/T1CH3N/SCL_/URX_
4 17
PD7/NRST/T2CH4/OPP1/UCK_ PC7/MISO/T1CH2_/T2CH2_/URTS_
5 16
PA1/OSCI/A1/T1CH2/OPN0 PC6/MOSI/T1CH1CH3N_/UCTS_/SDA_
6 15
PA2/OSCO/A0/T1CH2N/OPP0/AETR2_ PC5/SCK/T1ETR/T2CH1ETR_/SCL_/UCK_/T1CH3_
7 14
VSS PC4/A2/T1CH4/MCO/T1CH1CH2N_
8 13
PD0/T1CH1N/OPN1/SDA_/UTX_ PC3/T1CH3/T1CH1N_/UCTS_
9 12
VDD PC2/SCL/URTS/T1BKIN/AETR_/T2CH2_/T1ETR_
10 11
PC0/T2CH3/UTX_/NSS_/T1CH3_ PC1/SDA/NSS/T2CH4_/T2CH1ETR_/T1BKIN_/URX_
CH32V003F4U6
20
19
18
17
16
PD6/A6/URX
PD5/A5/UTX
PD6/T2CH3_/UTX_
PD5/T2CH4_/URX_
PD4/OPO/T1CH4ETR_
PD2/A3/T1CH1/T2CH3_
PD2/T1CH2N_
PD4/A7/UCK/T2CH1ETR
PD3/A4/T2CH2/AETR
PD3/UCTS/T1CH4_
0
VSS
1 PD7/NRST/T2CH4 PD1/SWIO/AETR2 15
PD7/OPP1/UCK_ PD1/T1CH3N/SCL_/URX_
2 PA1/OSCI/A1 PC7/MISO/T1CH2_ 14
PA1/T1CH2/OPN0 PC7/T2CH2_/URTS_
3 PA2/OSCO/A0/T1CH2N PC6/MOSI/T1CH1CH3N_ 13
PA2/OPP0/AETR2_ PC6/UCTS_/SDA_
PC1/T2CH1ETR_/T1BKIN_/URX_
4 PC5/SCK/T1ETR/T2CH1ETR_ 12
VSS
PC5/SCL_/UCK_/T1CH3_
PC2/AETR_/T2CH2_/T1ETR_
5 PD0/T1CH1N/OPN1 PC4/A2/T1CH4/MCO 11
PC2/SCL/URTS/T1BKIN
PD0/SDA_/UTX_ PC4/T1CH1CH2N_
PC1/SDA/NSS/T2CH4_
PC3/T1CH3/T1CH1N_
PC0/NSS_/T1CH3_
PC0/T2CH3/UTX_
PC3/UCTS_
VDD
8
6
10
CH32V003A4M6
1 16
PC1/SDA/NSS/T2CH4_/T2CH1ETR_/T1BKIN_/URX_ PC0/T2CH3/UTX_/NSS_/T1CH3_
2 15
PC2/SCL/URTS/T1BKIN/AETR_/T2CH2_/T1ETR_ VDD
3 14
PC3/T1CH3/T1CH1N_/UCTS_ VSS
4 13
PC4/A2/T1CH4/MCO/T1CH1CH2N_ PA2/OSCO/A0/T1CH2N/OPP0/AETR2_
5 12
PC6/MOSI/T1CH1CH3N_/UCTS_/SDA_ PA1/OSCI/A1/T1CH2/OPN0
6 11
PC7/MISO/T1CH2_/T2CH2_/URTS_ PD7/NRST/T2CH4/OPP1/UCK_
7 10
PD1/SWIO/AETR2/T1CH3N/SCL_/URX_ PD6/A6/URX/T2CH3_/UTX_
8 9
PD4/A7/UCK/T2CH1ETR/OPO/T1CH4ETR_ PD5/A5/UTX/T2CH4_/URX_
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CH32V003 Datasheet http://wch.cn
CH32V003J4M6
PD4/A7/UCK/T2CH1ETR/OPO/T1CH4ETR_
1 PD6/A6/URX/T2CH3_/UTX_ PD5/A5/UTX/T2CH4_/URX_ 8
PA1/OSCI/A1/T1CH2/OPN0 PD1/SWIO/AETR2/T1CH3N/SCL_/URX_
2 7
VSS PC4/A2/T1CH4/MCO/T1CH1CH2N_
3 PC2/SCL/URTS/T1BKIN 6
PA2/OSCO/A0/T1CH2N/OPP0/AETR2_
PC2/AETR_/T2CH2_/T1ETR_
4 5
VDD PC1/SDA/NSS/T2CH4_/T2CH1ETR_/T1BKIN_/URX_
QFN20
SOP16
I/O structure
SOP8
- - 0 - VSS P VSS - -
UCK/T2CH1ETR/A7/
8 1 18 8 PD4 I/O PD4 TICH4ETR_(1)
OPO
9 2 19 8 PD5 I/O PD5 UTX/A5 T2CH4_/URX_
10 3 20 1 PD6 I/O PD6 URX/A6 T2CH3_/UTX_
11 4 1 - PD7 I/O PD7 NRST/T2CH4/OPP1 UCK_
12 5 2 1 PA1 I/O PA1 T1CH2/A1/OPN0 OSCI
13 6 3 3 PA2 I/O PA2 TICH2N/A0/OPP0 OSCO/AETR2_
14 7 4 2 VSS P VSS - -
- 8 5 - PD0 I/O PD0 TICH1N/OPN1 SDA_/UTX_
15 9 6 4 VDD P VDD - -
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CH32V003 Datasheet http://wch.cn
All minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage
and clock frequency. Typical values are based on normal temperature (25℃) and VDD = 3.3V or 5V environment,
which are given only as design guidelines.
The data based on comprehensive evaluation, design simulation or technology characteristics are not tested in
production. On the basis of comprehensive evaluation, the minimum and maximum values refer to sample tests.
Unless otherwise specified that is tested, the characteristic parameters are guaranteed by comprehensive evaluation
or design.
VDD
2.7-5.5V
0.1uF VSS
V1.0 14
CH32V003 Datasheet http://wch.cn
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CH32V003 Datasheet http://wch.cn
VDD
Electric current
measurement
Table 3-6-1 Typical current consumption in Run mode, data processing code runs from the internal Flash
(VDD=3.3V)
Typ.
Symbol Parameter Condition All peripherals All peripherals Unit
enabled disabled(2)
IDD(1) Supply External clock FHCLK = 48MHz 6.96 4.67 mA
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CH32V003 Datasheet http://wch.cn
Table 3-6-2 Typical current consumption in Run mode, data processing code runs from the internal Flash
(VDD=5V)
Typ.
Symbol Parameter Condition All peripherals All peripherals Unit
enabled disabled(2)
FHCLK = 48MHz 8.02 5.77
FHCLK = 24MHz 6.21 5.17
External clock FHCLK = 16MHz 5.64 4.85
FHCLK = 8MHz 3.61 3.22
Supply FHCLK = 750KHz 1.93 1.89
(1)
IDD current in Runs on the FHCLK = 48MHz 7.67 5.27 mA
Run mode high-speed internal FHCLK = 24MHz 5.77 4.60
RC oscillator (HSI). FHCLK = 16MHz 5.28 4.48
Uses AHB prescaler FHCLK = 8MHz 3.24 2.84
to reduce the
FHCLK = 750KHz 1.54 1.50
frequency.
Note: 1. The above are measured parameters.
Table 3-7-1 Typical current consumption in Sleep mode, data processing code runs from internal Flash or
SRAM(VDD=3.3V)
Typ.
Symbol Parameter Condition All peripherals All peripherals Unit
enabled disabled(2)
Supply FHCLK = 48MHz 5.07 2.66
current in FHCLK = 24MHz 3.05 1.86
Sleep mode External clock FHCLK = 16MHz 2.64 1.84
(In this case, FHCLK = 8MHz 1.83 1.43
IDD(1) mA
peripheral FHCLK = 750KHz 1.28 1.24
power supply Runs on the FHCLK = 48MHz 4.31 1.88
and clock are high-speed internal FHCLK = 24MHz 2.24 1.05
maintained) RC oscillator FHCLK = 16MHz 1.84 1.04
V1.0 17
CH32V003 Datasheet http://wch.cn
Table 3-7-2 Typical current consumption in Sleep mode, data processing code runs from internal Flash or
SRAM(VDD=5V)
Typ.
Symbol Parameter Condition All peripherals All peripherals Unit
enabled disabled(2)
FHCLK = 48MHz 5.29 2.91
FHCLK = 24MHz 3.28 2.08
Supply
External clock FHCLK = 16MHz 2.87 2.07
current in
FHCLK = 8MHz 2.06 1.66
Sleep mode
FHCLK = 750KHz 1.50 1.47
(1)
(In this case,
IDD Runs on the FHCLK = 48MHz 4.39 1.95 mA
peripheral
high-speed internal FHCLK = 24MHz 2.31 1.13
power supply
RC oscillator FHCLK = 16MHz 1.92 1.11
and clock are
(HSI). Uses AHB FHCLK = 8MHz 1.10 0.70
maintained)
prescaler to reduce
FHCLK = 750KHz 0.54 0.50
the frequency.
Note: 1. The above are measured parameters.
V1.0 18
CH32V003 Datasheet http://wch.cn
OSC_OUT
OSC_IN
24MHz
Crystal
Oscillator
OSC_OUT
CL2
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VDD
RPU
NRST
0.1μF
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CH32V003 Datasheet http://wch.cn
tSCK tr(SCK)
tf(SCK)
SCK Output
CPHA=0
CPOL=0
CPHA=0
CPOL=1
tw(SCKH)
tw(SCKL)
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
th(MI)
tsu(MI)
MISO Input Input highest bit Input 6-1位 Input lowest bit
tV(MO) th(MO)
MOSI Output Output highest bit Output 6-1位 Output lowest bit
th(NSS)
tSCK tr(SCK)
tf(SCK)
SCK Input tsu(NSS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO) tV(SO)
th(SO)
tdis(SO)
MISO Output Output highest bit Output 6-1位 Output lowest bit
tsu(SI) th(SI)
MOSI Input Input highest bit Input 6-1位 Input lowest bit
V1.0 24
CH32V003 Datasheet http://wch.cn
th(NSS)
tSCK tr(SCK)
tf(SCK)
SCK Input tsu(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
MOSI Input Input highest bit Input 6-1位 Input lowest bit
V1.0 25
CH32V003 Datasheet http://wch.cn
VDD=3 to 5.5V 1 4
fADC ADC clock frequency MHz
VDD=4.5 to 5.5V 1 6
VAIN Conversion voltage range VSS VDD V
Internal sample and hold 3
CADC pF
capacitor
fADC=4 MHz 285
fS Sampling rate KHz
fADC=6 MHz 430
fADC=4 MHz 0.75
ts Sampling time us
fADC=6 MHz 0.5
tSTAB Power-on time 7 us
fADC=4 MHz 3.5 us
Total conversion time
tCONV fADC=6 MHz 2.33 us
(including sampling time)
14 1/fADC
Note: Above parameters are guaranteed by design.
Cp represents the parasitic capacitance on the PCB and the pad (about 5pF), which may be related to the
quality of the pad and PCB layout. A larger Cp value will reduce the conversion accuracy, the solution is to
reduce the fADC value.
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VDD
VDD
0.1uF
VSS
V1.0 27
CH32V003 Datasheet http://wch.cn
RLOAD=4kΩ, input 0 5
RLOAD=4kΩ,@1KHz 83
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CH32V003 Datasheet http://wch.cn
Packages
Part No. Package Body size Lead pitch Description Packing type
Thin-and-small 20-pin
CH32V003F4P6 TSSOP20 4.4*6.5mm 0.65mm Plastic tube
chip
CH32V003F4U6 QFN20 3.0*3.0mm 0.4mm Quad no-lead 20-pin Tray
V1.0 29
CH32V003 Datasheet http://wch.cn
Note: All dimensions are in millimeters. The pin center spacing values are nominal values, with no error.
Other than that, the dimensional error is not greater than the greater of ±0.2mm or 10%.
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Product type
0 = QingKe V2 core
1 = M3/ QingKe V3A core, clock speed @72M
2 = M3/ QingKe V4B_C core, clock speed @144M
3 = QingKe V4F floating-point core, clock speed @144M
Device subfamily
03 = General-purpose
05 = Connectivity (USB high-speed, SDIO, dual CAN)
07 = Interconnectivity (USB high-speed, dual CAN, Ethernet, DVP, SDIO, FSMC)
08 = Wireless (BLE5.3, CAN, USB, Ethernet)
Pin count
J = 8 pins A = 16 pins F = 20 pins
G = 28 pins K = 32 pins T = 36 pins
C = 48 pins R = 64 pins W = 68 pins
V = 100 pins Z = 144 pins
Package
T = LQFP
U = QFN R = QSOP
P = TSSOP M = SOP
Temperature range
6 = -40℃~85℃ (industrial-grade)
7 = -40℃~105℃ (automotive-grade 2)
3 = -40℃~125℃ (automotive-grade 1)
D = -40℃~150℃ (automotive-grade 0)
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