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Reliability of fine pitch halogen-free organic substrates for green electronics

Conference Paper  in  Proceedings - Electronic Components and Technology Conference · May 2011

DOI: 10.1109/ECTC.2011.5898793

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 Reliability of Fine Pitch Halogen-Free Organic Substrates for Green Electronics

Koushik Ramachandran1, Fuhan Liu1, Nitesh Kumbhat1, Mark Wilson2, Venky Sundaram1, and Rao Tummala1
1
3D Systems Packaging Research Center, Georgia Institute of Technology
813 Ferst Drive, Atlanta, GA 30332
2
Dow Epoxy Research and Development, The Dow Chemical Company
2301 N. Brazosport Blvd., Freeport, TX 77541

One of the most important reliability concerns with

Abstract
surface fine-line wiring in a packaging substrate is the loss of
European Union’s Regulation on halogens and lead-based
surface insulation resistance (SIR). SIR is the electrical
solders has lead to the development of new class of high Tg
resistance between two conductors separated by the dielectric.
halogen-free polymer-glass laminates for package substrates.
SIR loss is driven by the formation of conductive dendrites.
At the same time, Moore’s law and 3D ICs have accelerated
Dendrites form under the presence of certain accelerating
the demand for high I/O density. These fine pitch
factors such as humidity, temperature, voltage among other
requirements in new substrates can affect reliability in terms
factors. Several testing standards are available to determine
of loss of surface insulation resistance (SIR) and formation of
the SIR of materials. Since SIR is affected by the presence of
conductive anodic filament (CAF) leading to electrical
ionic impurities in the substrate, SIR test has been used to
failures. Therefore newly developed materials are required to
determine whether the materials used in an assembly are
have excellent resistance to electrochemical migration and
likely to produce unacceptable leakage current levels, or
high thermal stability for lead-free assembly. This study
shorts due to copper migration in the presence of ions,
focuses on experimental reliability study of novel halogen-
moisture, and an electrical potential [5, 6].
free substrates under accelerated conditions. This study
consists of 1) SIR test with 50 µm line width/spacing, 2) CAF Plated Through-Package-Vias (TPVs) in package
test of through-vias of 100 µm diameter with pitch of 250 µm substrates, on the other hand suffer from the formation of
and 500 µm, 3) through-via reliability and, 4) Pb-free flip- conductive anodic filament (CAF). CAF is a sub-surface
chip package reliability with halogen-free substrates. The phenomenon that involves the migration of copper ions
halogen-free substrate used in this work was observed to have resulting in sudden loss of electrical resistance. This typically
high resistance to surface migration at 50 µm line-width/ occurs in two steps. The first step involves the degradation of
spacing. However, CAF failures were observed even at 250 the polymer-glass interface and the second step involves the
µm pitch indicating that failures due to CAF at fine pitch are a transport of ions along this interface that results in an
serious reliability concern. The substrates did not show any electrical insulation failure [6, 7]. It has been reported that
failures in through-vias and flip-chip interconnections under both the CAF and SIR of organic laminate materials are
thermal cycling indicating good reliability for halogen-free affected by the presence of humidity, temperature and voltage
and Pb-free applications. [5-7]. The decreasing copper line-width and spacing and pitch
of TPVs significantly increase the risks of these types of
Introduction failures during operation. While most of the previous studies
The German dioxin law in 1994 shifted the trend to using have been carried out on halogenated materials for printed
halogen-free materials for electronics. Since then, several wiring boards, limited research data is available on halogen-
industries have adopted the standards of halogen-free free packaging substrates. This study aims to investigate
materials for printed wiring boards in electronics. Halogen- reliability issues in halogen-free materials to enable “green
free materials have been reported to be environmentally safe electronics”.
during recycling and are considered to be superior compared The other focus of this study is to investigate the flip-chip
to halogenated materials [1]. Also, the RoHS restrictions on interconnection reliability of the novel halogen-free substrates
lead-based solders have necessitated the development of with Pb-free interconnection. In the recent years, flip-chip
halogen-free substrate materials that also have high thermal packaging has had a great impact because of its ability to
stability and heat resistance for Pb-free assembly [2]. With the meet the needs of high speed microprocessors and high
introduction of new class of materials that satisfy the RoHS frequency ASICs. Organic laminates are very popular for flip-
requirements, there are potential reliability concerns in fine- chip packaging because of their ability to achieve high density
pitch wiring, TPVs and Pb-free interconnections for high- using sequential build-up and micro-via technologies. The
density flip-chip packaging. introduction of new class of halogen-free organic materials
As industries adopt the halogen-free material standards in poses challenges in terms of requiring high thermal stability
electronic packaging, phosphorus-based flame retardants are and interconnection reliability [8]. Thermal cycling tests have
predicted to be the largest growing share of flame retardant been used in this study to investigate the reliability of Pb-free
market. Organic phosphorus-based flame retardants are interconnections and through-vias in halogen-free substrates.
considered to be less harmful and do not form toxic gases Halogen-free substrate
because the flame retardation mechanism is achieved through A high performance Bismaleimide-Triazine (BT)-epoxy
formation of char [3]. blend has been selected in this study. This BT-epoxy

978-1-61284-498-5/11/$26.00 ©2011 IEEE 2015 2011 Electronic Components and Technology Conference
formulation utilizes resins and ingredients developed by Dow The TV design and fabricated test structure on halogen-free
Epoxy R&D. The resin system incorporates halogen free substrate are shown in figure 1.
flame retardant onto the polymer backbone, thereby reducing
the need for particulate flame retardants. This approach
enables a higher decomposition temperature (Td) of above 50µm
350oC and a glass transition temperature (Tg) above 200oC. 50µm

The high Tg and high Td offers superior high temperature

properties, also enabling the required thermal stability for Pb- 10 mm

free assembly process. + ‐

Several versions of prepreg were prepared utilizing 1080 (a) (b)
and 7628 glass. Both filled and unfilled versions of the high Figure 1. a) Schematic of SIR Test coupon with 50 µm line/spacing
performance BT-Epoxy system were prepared. The filled copper traces based on IPC-TM-650 test standard, and b) Fabricated
versions incorporated 43% by weight of amorphous silica to SIR test coupon with 50 µm line/spacing.
adjust the thermomechanical properties of the cured
laminates, specifically the coefficient of thermal expansion The test coupons consist of electrodes of alternating
and modulus. Double sided copper clad laminates were polarity. Substrates with comb patterns of 50 μm line-width
pressed under vacuum using a 12 μm copper foil and two to and space test patterns were investigated for SIR. Before the
four sheets of prepreg to achieve the desired thickness. The SIR test, the coupons were subjected to preconditioning.
stacks were placed into a Tetrahedron press to fabricate the Preconditioning involved 24 hour bake at 125OC , followed
12” by 12” core stock. The profile consisted of a ramp to 220 by accelerated MSL-3 (60OC , 60%RH, and 40 hours) and
°C followed by an isotherm at 220 °C for 90 minutes. The three times reflow at peak temperature of 260OC consistent
pressure ranged from 50 to 200 psi. The pressed laminates with Pb-free assembly standards.
were then analyzed for key properties of interest which are SIR test was carried out at 85OC and 85% RH at 100V DC
outlined in Table 1 below. for 1000 hours in a temperature-humidity chamber. A 1
Table 1. Halogen-free substrate properties MOhm resistor was connected in series with the test coupon.
This prevents damage to the test circuit caused by excessive
Filled on Filled on
current in the case of dendritic shorting. Resistance drop to
Laminate Properties
1080 7628 1MOhm is recorded as the failure event where electrical
Tg 3 (DSC, 20 °C/min ramp, °C) 205 205 shorting occurs between two electrodes. Five test coupons
Td (TGA, 5% loss, °C) 381 395 were subjected to this test.
Thickness (TMA, mm) 0.48 0.91
Conductive Anodic Filament (CAF) Test
Copper Peel (lb force / inch width, 35 μm foil) 6.5 6.8
Moisture Uptake (%) 1.18 0.55
Test coupons were fabricated based on IPC-B-24
Solder Dip, 288 °C, 20 sec (% pass) 100 100
standards with 5 rows of 42 TPVs in each test coupon. A
CTE (TMA, <Tg ppm/°C) 18 29 schematic of the test coupon design based on IPC standards is
CTE (TMA, >Tg ppm/°C) 132 136 shown in figure 2.
T-288 (minutes) 26 21 250µm
UL-94 (2 and 4 ply) V0 V0

100µm
Substrate fabrication
The test coupons for SIR and CAF were fabricated using + ‐
a subtractive etching process. The substrates used for CAF
Figure 2. Schematic of CAF test coupon with 100 µm through-
and SIR studies were of 400 µm thickness. For CAF tests,
package-vias with a pitch of 250 µm adopted from IPC-TM-650 test
TPVs with diameter of 100 µm were mechanically drilled in standards.
the substrate at Innovative Circuits Inc. The spindle speed
used for drilling the TPVs was 150,000 rpm. After via-
Five test coupons each with 250 µm and 500 µm pitch
drilling, the test coupons for CAF were fabricated by first
respectively were subjected to CAF test. The test coupons
subjecting the substrates to electroless plating followed by
were subjected to preconditioning prior to CAF test. This test
electrolytic plating. The plated substrates were then subjected
coupon design results in a total of 168 TPV-TPV in-line
to subtractive etching process to fabricate test coupons. A
failure sites. An optical image of the surface and SEM image
detailed description of the test structures used for both the
of 100 μm TPVs with a pitch of 250 µm is shown in figure 3.
SIR and CAF tests are given in the following section.
Surface Insulation Resistance (SIR) Test
SIR test was carried out on substrates with inter-digitated
comb patterns in accordance to IPC-TM-650 test standards.

2016
 150 µm

Potential
CAF failure
site

(a) (b)
Figure 3. a) Optical image of surface of CAF test coupon, and b) (a) (b)
SEM image of cross-section of 100 μm TPVs with 250 μm pitch Figure 5. a) Test vehicle design for 4 metal layer flip-chip package,
showing potential CAF failure site. and b) fabricated flip-chip package used for reliability studies.

Similar to SIR test, CAF test was carried out in a Assembly of flip-chip packages was done using a Finetech
temperature-humidity environmental chamber at 85OC and Fineplacer© Lambda assembly tool with an alignment
85% RH at 100V DC for 1000 hours. A 1MOhm resistor is accuracy of +/-1μm. The peak temperature was 260OC. Alpha
connected in series with the test coupon even in this case. metals NR-200 no-clean flux was used for assembly. A
Electrical resistance was recorded periodically and the failed standard fast-flow underfill (Henkel UF8826) was used for
samples were analyzed for identifying the formation of sub- underfilling.
surface filaments. The flip-chip packages were subjected to preconditioning
before thermal cycling test with the same conditions as
Flip-chip interconnection and through-via reliability mentioned earlier. Five 4-metal layer packages were subjected
to Thermal Cycling Test (TCT) under the following
A four- metal layer package (1-2-1) using 800 µm thick
condition: 125OC to -55OC, cycle time 30 min, and 15 min
halogen-free laminate core and ABF build-up was used for
dwell time at each extreme temperature as described in
investigating flip-chip reliability as shown in figure 4.
JEDEC JESD22-A104 condition B. The resistances of all
daisy chains were monitored at room temperature and an open
Silicon Die circuit was used as the failure criteria. Electrical resistance
underfill Pb‐free solder was recorded during thermal cycling and SAM images were
recorded every 100 cycles to investigate delamination induced
Halogen‐free core failures using Sonoscan C-SAM equipment.
ABF build‐up Through-via and blind-via reliability were also
Figure 4. 1-2-1 Flip-chip test structure design. investigated on the halogen-free substrates using a daisy chain
structure. The through-via diameter was 200 μm and the
The diameters of TPVs and blind-vias used in this test blind-via diameter was 100 μm. The daisy chain structures
vehicle were 200 µm and 100 µm respectively. The TPVs in consisted of 300 TPVs and 600 blind-vias. The cross-section
were formed by mechanical drilling. These vias were plated schematic of the test structure is shown in figure 6. The test
with copper and patterned with a subtractive etching process. coupons consisting of via daisy chain structures were
ABF build-up films were laminated on both sides, followed subjected to TCT to investigate via reliability in the halogen-
by semi additive plating (SAP) process to fabricate the 1-2-1 free organic substrates.
build-up substrate. Taiyo AUS5 PSR 4000 was used as the ABF build‐up Blind‐via
solder mask because of its low moisture absorption and good
crack resistance properties. A 10 x 10 mm die (Pac-Tech
FA572) with 200 µm and 400 µm pitch lead-free solder
bumps was used. The solder bump metallurgy consists of Sn,
Ag and Cu (SAC 405). Electroless Nickel, Electroless
Palladium and Immersion Gold (ENEPIG) was chosen as the TPV Halogen‐free core
surface finish as it has been shown to be a robust surface Figure 6. Schematic of daisy chain test structure used for TPV and
finish for lead-free solder applications as compared to blind-via reliability.
Electroless Nickel and Immersion Gold (ENIG) [10].
The four-metal layer test structure consists of 22 daisy Results and Discussions
chain interconnection structures. Two of the daisy chains had
a pitch of 200 µm and the rest of the daisy chains had a pitch Surface Insulation Resistance
of 400 µm. The test vehicle was designed such that each daisy The test coupons used in this study consisted of inter-
chain structure was connected to four blind-vias and two digitated comb patterns with 50 µm line/space. After 1000
TPVs. Some of the TPVs on the core were placed below the hours of testing, the test coupons were removed and dried at
area of the die. The test vehicle design and an assembled flip- 125 OC. Resistance measurements was made at 100V DC
chip package are shown in figure 5. again after this step. Figure 7 shows the SIR plotted against
time up to 1000 hours with the final data point showing the
resistance recovery after drying. During in-situ testing, there

2017
were intermittent drops in resistance observed in some of the resistance characteristics of this halogen-free substrate can be
test coupons, possibly due to moisture condensation between attributed to the absence of halogens that drive
the electrodes. The electrical resistance measurements after electrochemical migration in the substrate.
drying showed that most of the resistance value recovered
after drying. This indicated that the resistance drop was Conductive Anodic Filament
possibly related to moisture absorption and not due to the Five test coupons, each of 100 µm diameter TPVs with
formation of dendrites. The applied DC bias of 100V results 250 µm and 500 µm pitch, were subjected to CAF test as
in an electric field of 2 x 106 V/m (E = V/d) between the mentioned before. During CAF test, the test coupons were
copper electrodes. Electrochemical migration of copper has removed from the chamber, dried at 125OC to remove
been shown to be a strong function of the electric field [5]. moisture before resistance measurements were made at 100V
However, there were no failures resulting from DC. This ensured that any resistance drops related to moisture
electrochemical migration in the substrates. condensation was avoided. Figure 9 and figure 10 show the
resistance changes plotted against time for 250 μm and 500
1.00E+12 μm pitch respectively. From resistance measurements, it was
seen that there were two CAF failures in test coupon with
OPEN
1.00E+11
TPVs of 250 μm pitch. One CAF failure occurred within 100
1.00E+10
hours of test and the other failure was observed after 600
1.00E+09 hours of test. The TPVs with 500 μm pitch did not show any
failures due to formation of CAF.
SIR  (ohms)

1.00E+08
Cu line/space: 50/50 µm
1.00E+07 85OC, 85 %RH, 100V DC 1.00E+12
OPEN

1.00E+06 1.00E+11

1.00E+05 1.00E+10

Resistance (ohms)
1.00E+09
1.00E+04
1.00E+08
1.00E+03
0 200 400 600 800 1000 1200 1.00E+07
Time  (hours)
1.00E+06
Figure 7. Surface insulation resistance (ohms) vs. time (hours) of 50
μm comb patterns. The final data point shows the recovery of SIR 1.00E+05
TPV dia/Pitch: 100/250 µm
85OC, 85 %RH, 100V DC
after drying. 1.00E+04

1.00E+03

It was observed that the resistance of one test coupon did

0 200 400 600 800 1000

Time  (hours)
not recover completely after the SIR test. This test coupon
was inspected under an optical microscope and dendrites were Figure 9. Resistance (ohms) vs. time (hours) for 100 µm TPV with
250 µm pitch.
found in some areas as shown in figure 8. The formation of
dendrites decreased the resistance to more than 1 order of 1.00E+13
magnitude however it was found to be less than the failure OPEN
1.00E+12
criteria (108 ohms). The possible reason for the formation of
1.00E+11
dendrites in localized region is due to ionic contamination
Resistance (ohms)

1.00E+10
during processing. This needs to be confirmed through
chemical analysis. 1.00E+09

1.00E+08

1.00E+07
TPV dia/Pitch: 100/500 µm
1.00E+06
85OC, 85 %RH, 100V DC
1.00E+05

1.00E+04

1.00E+03
0 200 400 600 800 1000

Time (hours)
Figure 10. Resistance (ohms) vs. time (hours) for 100 µm TPV with
Figure 8. Dendrites observed in a SIR test coupon. 500 µm pitch.

Previously reported literature on SIR indicates that the An optical image of the surface of test coupons that
effects of various processing parameters and presence of revealed CAF formation is shown in figure 11. CAF
halogens such as chlorine and bromine have an adverse effect formation was confirmed by cross-sectioning the test coupon.
on insulation resistance of halogenated FR4 [5-7]. Halogens The formation of CAF resulted in excessive current flowing
such as chlorine and bromine can accelerate electrochemical between the two vias. This, in turn carbonized the resin (seen
migration of copper. The substrates used in this study are as dark areas in both the surface and cross-section images).
halogen-free consisting of low levels of chlorine. The Welsher et al. have reported that electrochemical corrosion
substrates do not contain any bromine. The surface insulation

2018
step is an inverse function of the electric field (V/d) as well as 2

a function of temperature and humidity [11]. The applied DC 22 daisy chain interconnections

bias of 100V results in an electric field of 6.7 x 106 V/m and (Pitch: 200 µm and 400 µm)

2.5 x 106 V/m between the through-vias for 150 µm and 400
1.5

Normalized resistance
µm wall-wall spacing respectively. This indicates that the
decrease in wall-wall spacing is a serious reliability concern 1

for substrates with fine pitch TPVs.

0.5

0
0 200 400 600 800 1000 1200 1400 1600 1800 2000
No. of thermal cycles

Figure 12. Normalized resistance vs. no. of thermal cycles up to

2000 cycles for one representative 4-metal layer (1-2-1) flip-chip
package with 22 daisy chain interconnections.
(a) (b)
Figure 11. a) Optical image of surface of test coupon that showed
A cross-section of the flip-chip package with Pb-free
CAF failure, and b) Cross-section of vias where CAF failure was
observed. interconnection after 2000 thermal cycles is shown in figure
13.
Previous studies on CAF formation have shown that there
are several factors that influence the formation of conductive
anodic filament. Some of the factors include properties of
substrate material, conductor configuration and spacing,
voltage gradient, thermal excursion and humidity effect [7].
Rudra et al. [9] have studied and compared formation of CAF
in epoxy-glass laminate (FR-4), Bismaleimide-Triazine (BT)
and cyanate ester (CE). BT was shown to have the highest Figure 13. Cross-section of 4-metal layer flip-chip package using
resistance to CAF formation because of its low moisture halogen-free substrate after 2000 thermal cycles.
absorption properties. Formation of CAF has been shown to
increase with decrease in spacing between the conductors [8]. SAM images were also recorded every 100 cycles during
Rudra et al. [9] have shown that for 500 μm spacing in FR4, TCT. The SAM image representative of one package before
the time to failure was 190 hrs at 85% RH. The halogen-free cycling and after 2000 cycles is shown in figure 14. No
substrates used in this study did not show any failures in thermal cycling induced delamination was observed in these
through-vias with 400 μm spacing up to 1000 hours. Thus packages. The results indicate that the halogen-free substrates
these substrates have better electrochemical migration have shown good reliability under thermal cycling with Pb-
resistance because of its higher thermal stability and low free solder metallurgy.
moisture absorption properties compared to halogenated FR-4
boards. However, CAF formation at fine pitch needs further
investigation.
Thermal Cycling Test
Five flip-chip packages were subjected to 2000 thermal
cycles. The normalized resistance change is plotted in figure
12 up to 2000 cycles. The normalized resistance change of
one representative flip-chip package is plotted against the
number of thermal cycles in figure 12. As seen from figure (a) (b)
12, the resistance change was less than 2% for the 22 daisy Figure 14. C-SAM images of test package (a) After assembly, and
chains up to 2000 cycles. The observed resistance change is (b) after 2000 cycles of thermal cycling.
well within the failure criteria for TCT.
The flip-chip packages were also cross-sectioned to The normalized resistance of 10 daisy chains is plotted
confirm that there were no thermal cycling induced failures of against the number of cycles in figure 15 up to 2000 cycles.
interconnections after 2000 cycles. Each daisy chain consisted of 30 through-vias and 60 blind-
vias. As seen from the plot, the resistance change of the
through-vias up to 2000 cycles is less than 5% of the initial
resistance values, indicating excellent TPV reliability under
thermal cycling.

2019
 (TU Dresden) for their assistance in substrate fabrication and
2
10 daisy chain nets
testing.
TPV dia/pitch: 200/450 µm
Blind‐via dia/pitch: 100/400 µm References
1. T. Suzuki, “Trend of halogen free printed wiring board
Normalized resistance

materials,” of Second International Symposium on

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Pecht, “Are you ready for lead-free electronics?,” IEEE
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1500 2000
3. A. B. Morgan, and C. A. Wilkie, “Flame retardant
Figure 15. Normalized resistance vs. no. of thermal cycles for TPV polymer nanocomposites: Introduction to flame
and blind-via reliability test structure for 10 daisy chain structures. retardancy and polymer flammability,” Wiley-
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Acknowledgments 18th Annual Proceedings, 1980, pp. 235–237.
The authors would like to thank The Dow Chemical
Company for supporting this research. The authors would
also like to thank Lameck Banda (Dow Chemical), Baik-Woo
Lee, Srikrishna Sitaraman, Dibyajat Mishra, Hunter Chan,
Jason Bishop (GT PRC), Christian Ullman and Daniel Pahner

2020

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