STEP TOWARDS SUCCESS AKASH’S Guru Gobind Singh Indra Prastha University Series SOLVED PAPERS, | (PREVIOUS VEAR SSTION PAPERS) [B.Tech] THIRD SEMESTER Digital Logic and Computer Design (ECC-207)SYLLABUS DIGITAL LOGIC AND COMPUTER DESIGN PAPER CODE : ECC-207 Instructions for paper setter: 1. There should be 9 questions in the tert 2. The first (1st) question should be com) question should be objective, single line answers 0 total 15 marks. 3. Apart from question 1 which is compulsory, rest of the paper shall consist of 4 units { as per the syllabus. Every unit shall have two questions covering the corresponding weit of the syllabus. However, the student shall be asked to attempt only one of the two questions in the unit. Individual questions may contain upto sub-parts / sub-questions. Each Unit shall have a marks weightage of 1 UNIT-I Boolean Algebra and Combinational Logic: Review of number systems » signed, unsigned, fixed point, floating point numbers, Binary Codes, Boolean algebra — basic postulates, theorems, Simplification of Boolean function using ‘Karnaugh map and Quine-MeCluskey method ~ Implementations of combinational logic functions using gates, Adders, Subtractors, Magnitude comparator, encoder and decoders, multiplexers, soit converters, parity generator/checker, implementation of combinational circuits using multiplexers. 1m end examinations question paper. pulsory and cover the entire syllabus. This 1r short answer type question of UNIT -II Sequential Circuits: General model of sequential circuits, Flip-flops, latches, level triggering, edge triggering, master slave configuration, concept of state diagram, state Eine, state reduction procedures, Design of synchronous sequential circuits, up/down era modulus counters, shift registers, Ring counter, Johnson counter, timing diagram, aeval adder, sequence detector, Programmable Logic Array (PLA), Programmable ‘Array Logic (PAL), Memory Unit, Random Access Memory UNIT - II Basic Computer organization: Stored Program, Organization, Computer | registers, bus system, instruction set completeness, instruction cycle, Register Transfer Language, Arithmetic, Logic and Shift Micro-operations, Instruction Codes, Design of a simple computer, Design of Arithmetic Logic unit, shifter, Design of a simple hardwired control unit, Programming the basic computer, Machine language instructions, assembly language, Microprogrammed control, Horizontal and Vertical Microprogramming, Central Processing Unit, instruction sets and formats, addressing modes, data paths, RISC and CISC characteristics. UNIT -IV Computer Arithmetic, addition, subtraction, multiplication and division algorithms, put Organization, Modes of data transfer, Interrupt cycle, direct memory Input-Output processor, Memory Organization, Memory Hierarchy, Associative | Cache Memory, Internal and external Memory, Virtual Memory.FROM ACADEMIC SESSION [2022-23] THIRD SEMESTER [B.TECH] al s * ‘This method is suitable for pr DIGITAL LOGIC AND COMPUTER DESIGN (ECC-207) nepe are followed for simplification of Bool UNIT-I of variables. = AB+CD+ EFG+.. nt of a sum is equal to the product of the complements, ‘Demorgan's second theorem42021 ‘Third Semester, Digital Logic and Computer Design ‘Table: Truth table for Demorgan’s second theorem 8 0 1 0 ofi] o lolol o Lo ‘This law can be extended to any number of variables or combinations of variables. For example. k ApBrCsD-. = ABCD. ‘ABSCD+EFG+.. = AB CD EFG-.. Q.3. Draw the logic diagram of 3-bit parity generator and respective truth table. (2014) pit of a ‘0’ or a ‘1's attached to the data bits such that total no. of 1's 8 bit can be attached to the ; Q7. Find essential 8 prime implicant in the given equation: F (WXY,Z) = Em (0,2y4,5,6,7,8,10,13.15) (Ww, X, ¥, Z) = Em (0, 2 4,5, 6, 7,8, 10, 13, 15) ‘encoder is a combinational logic cireuits. It is ‘and‘n’ output lines. An encoder accepts (2015) ‘representing a digit such as a decimal/octal digit and converts‘Third Semester, Digital Logic and Computer Design (ioe i ae expeal in. if both ae I's or beth 4 Where x, = 1 only if the pair of bits em are 0's. For the equality condition to exist. all « ‘an AND operation of all vanables (A=B) = 134 ‘The binary variable (A = B) is equal to 1 only fal pairs of git of thee cae mamewas 82021 Third Semester, Digital Logic and Computer Design ee" sai Q.13. Implement the followis i er \¢ following multiple output combinational logic circus oat ‘sing a 3-0-8 line Decoder? Sak sicigsiacn fer ae () Fy = 2m (0,1,2,6) Gi) F, = 5m (2,4,6) Gil) F, = 220(0,1,5,6) Pe AL Ans. Given that : @ F, = &m(0,1,2,6) i) F, = imi2, 4,6) , : cans / ® a8 eit ah Siar oe re (i) Excess 3 = ae) Gi) Octal = 1: ing 4:1 multiplexer and 63! 6:1 multiplexer using Q.18. Design an ‘Ans. 8:1 MUX using 4:1 MUX10-2021 i ‘Third Semester, Digital Logic and Computer Design Q.20. Simplify th Boolean function us Ar Cl nyeis Gia i ion using K-map: 2016) LP. University-[B.Tech}-Akash Books 2021-11 +8, 7, 11, 15) + 2d (0, 2, 5) Ans. . 5 K-map forthe given fancin i 18 ‘ye gp [EB o5] ob 2 ae at 0048 lf ie) feta Tet 7am {ence THs 01 Aa| 1 [fs 1 1 4 lie is] 1 1 1188 «qs hea n|__10 1028 | 1 : T a] ol] In . Cs “ Y = AB0+ACD+ Ac + ABC g ; Q24. Desoribe the circuit and operation of single Dit magnitude comparator. (2016) ‘Ans. One bit magnitude comparator is @ combination logic circuit which compares ‘the two inputs in the binary code and gives three outputs ‘Truth Table of 1-bit comparator i een Input Comparator Outputs A B AB A=B AB i“ = 0 o 1 oO o a o o 1 ea o 1 o o 1 0 1 o (A> B) = AB (A=B) = AB+AB-AOB AB) = AB A ®2021-13 's complement method? Outputs 1 (2017) a (11101100), -+ 2's complement of addition of ~ 10 and ~10 in 2's complement form, Q.26. FIA, B,C, D) =1(0, 1,2,5,7, 8,9, 10, 14, 16). Find all the prime: )=3(0, 1,2,5,7 im ‘essential prime implicants and minimal SOP expression. eon 10 Ans. ‘pit number X and Y. X consists of XX, and Y consists of with three outputs Z,, Z, and Z, sucl (2017) (ii) Z, = Lwhen X=¥ iii) Z, = 1 when X>¥14-202} i 1 ‘Third Semester, Digital Logic and Computer Design Ans. Truth table for 2 - Bit Magnitude comparator. Outputs | resvivsen | xm vive) [xv LP. University-1B.Tech}-Akash Books 2021-15 Q.30. Why is the ASCII code « 7 bit code? (G2 symbols) and some 1 ym It is used extensively for printers and terminals that interface with small computer systems. Q31. What are the two basic form of the Boolean expression name them? (2017) expression are: oduct Of Sum (POS) ‘Ans. Two basic form of the B (@) Sum Of Product (SOP) Q82. Realize EX-OR gate using minimum number of NAND gate only, 2017) fe 2, = XRVFo + EXT Yo + MXN MO KK i A oer) a . Fi {> Output =AeB Q.38. Simplify the given Boolean expression and implement it with NOR eon gate circuit only F = AB + ABD + ABD + ACD + ABC Ans. ACB s0000+c00e+c000- ©4400+-000400c0 @000-c00++004~~ B +e-0-0-0-0-0-0-0 F = AB+ ABD+ ABD~ ACD ~ ABC B= a+B0+ACD the essential prime implicants? jor rectangle made up of the bunch of adjacent mit b of these subcubes is called a prime implicants “L which cannot be covered by any other PI is called an essent the following function using K-map 2017) ,2, 6,8, 9, 10) 5, 7,9, 12) + 400, 1,6)Third Semester, Digital Logic and ( F, = AcD« BCD + ABD F,= AB + BCD + AD + BCD Q.35. Obtain the decimal equivalent of the given hexadecimal number (2017) Ams (ABP), = 3x 16's 10» 16" + 2x 16 + 15 = 16% = 48+10+ Z- zg 2 58 + 0.125 + 0.058 = (58.183), 36, oe eee (2017) ode ended ha18-2021 ‘Third Semester, Digital Logic and Computer Design ‘Table truth table common cathode 7-segment display. Din BCD input 7 Segment Beem oD ° oe. Oe o 1 oo 8 7 2 LT 3 Go Ty 4 ot 0 5 oo 6 tO 1 ee 1 8 O- 04-0 9 Ok Onna ‘The unused BCD codes are 1010, condition {or these corresponding cells, Kemap Simplification Fora oo orn b=B+t5+co e=B+e+0 LP. University-{B Tech}-Akash Books 2021-19 ot eo wo So on oo Logic diagram: Fig. shows the logic diagram of BCD to 7-segment display decoder/ driver. LtEe ‘Third Semester, Digital Logic and Computer Design Realize the = half adder circuit using minimum umber of NAND, Ans, “> a1, cla ties By. LP. University-{B.Tech|~Akash Books 2021-21 = X¥+ z+ v2 = X¥+%2+¥2 = (X+¥)(x+2Z).(F+z)2021-23 (2018) 1 D)\A+B+O+ By output logic 1 of 2-bit venever 2-bit input A is greater than 2-bit24-2021 ‘Third Semester, Digital Logic and Computer Design Bray code converter; rerter a tional Circuit is deni re ae va = pe oo yert binary to Gray code. ‘The lope bape output code of code converter is. Gray code. ec a ‘Truth Table le of-HEE TEE EEF 5 -[-[-[- LP. University-{B-Tech}-Akash Books K-Map Simplification Expression For Gy ny 6 pa 10/8 Pt fo 6,06 +DC= co We get the simplified boolean expression for the code converter of Binary of Binary to Gray code G,= BA+BA=BOA G, = CB+€B-coB G, = De+Bc-c@D 9, =D B 1 ag the above expression we can construct the binary to gray code converter asfol \ se Fig.) Logic Diagram 8 ‘Ao Binary code, 2 & 6, Gy Bray code Pig. Logic circuit for binary to gray code converter : Q.A48, Implement the logic expression using 4:1 MUX, F = Im (1, 3, 5 7) P = tm(1,3,5,7) ni26-2021 ‘Third Semester, Digital Logic and Computer Design Raw a Dain s— A) even Paty Sonemaeay | © y cf (lobe > SJ sansa tee] p> Even panty Fig. Even Parity generator Error in the data can be detected using XOR gates. Bin: prea ene Binary data may be corrupted zeae At the receiving side, the parity bit will be used to check. errors and then the additional bit will be truncated before processing the data. (2018) LP. University-1B Tech}-Akash Books 2021-27 UNIT-II Q.1. Explain various types of isters? Ans. Shift Register: A registe FFs used to store binary data. In shift into and shifted out register, FFs are connected together ‘data may be shifted into an‘ A chift register. Thus shifting may be in serial form or parallel form. types of shift register. (2018) wot a ct ar TET ie RESIS nate Q2. Explain the process of state reduction and stage assignment ero ewens cogent crost oo accep aoe sTwo states are said to be redundant every possible set of inputs ‘the same outputs and the same next states. When two states are equivalent one of them can be removed ‘without altering input output relationship, Let us consider the state diagram as shown in Fig. The states are denoted by letter symbols ‘Step 1: Finding the state tabl First the given state diag: of state diagram. Present state ‘the given state diagram. - ‘averted into state table. Fig. shows the examplethe most significant bits in ax LLP. University-{B TechI-Akash Books 021-29 ya tepain varios operations performed i RaMand ROM. Mentegsy data and control signals in RAM and ROM? «aoid) "has. The basic memory operation follows the given functses vic Held the data coming from Ube memory during « read operation 5. Explain the features ofedge-trignered flip-flop. Draw the logic diagram of D-type positive edge-triguered fip-op? (2018) age Triggered D Flip Flop: Thi from low to high to I ‘during the positive transition or megat ‘equivalent circuit (called as edge det ‘The shorter pulse (spike) width at the clock input of « chance of the output being synchronized to the flip flop fives less chance for the SET and RESET inputs to cha30-2021 ‘Third Semester, Digital Logic and Computer Design p= Poni Es wig Neqaive Ege Tageing Fig. (4) Logic symbol of positive and negative edge triggered of D flip flop. When D = 0, and the edge detector senses a positive edge at the CLK input, the output of the lower AND gate steers a low going pulse to the RESET input of flip flop, thus storing a 0 at Q. When D = 1, the upper AND gate is enabled. The edge detector sends a high going pulse to the upper steering gate, which transmits a low going SET pulse to the output of flip flop. The action stores a 1 at Q. ‘Table 1: Truth table of edge positive triggered D flip flop CLK D & t 0 0 1 1 1 Q6. Compare the design features of synchronous and Asynchronous Counters. Give an illustration for each. (2014) ‘Ans. Asynchronous Counter: To design an asynchronous counter, the number of flip-flops required depends on the number of states. The maximum number of state ofa counter is 2%, where m is the number of flip-flops in the counter. If we have two flip- flops, the maximum possible number of output states of the counter is 2" ie., 4. In this case, all the flip-flops are not clocked simultaneously. Example of 3-bit asynchronous up counter is shown below. 2 » Ol eens rms of flip-flop outputs as the input LP. University-1BTechl-Akash Books 2021-31 ify the k-maps and obtain the minimized expressions Connect he cireuit using flipflops and other gates corresponding. to the zed expressions synchronous counter is shown below. cu: Q.7.A sequential circuit with two D flip-flops A to and B, two inputs and yvone output zis specified by the following next-state and output equations: Ate) = xy exd Bit+1) = xB+xA 2=B ( Draw the logic diagram of the circuit. @ ; i) Derive the state table, @ Derive the state diagram. es) ‘The next state and output equation are as follows: Atte) = xyexA Bite) = xB+xA 2-8 (ord) 1elogie diagram is as follows:32-2021 ‘Third Semester, Digital Logic and Computer Design Gi) The state table is as follows: LP. University-{B.Techt-Akash Books peal T_tepate Next State Output x ® x Y a B = ° ° ° ° ° ° ° ° ° ° 1 1 ° ° ° ° 1 o ° ° ° ° ° 1 1 ° ° ° ° 1 ° ° ° 1 1 ° 1 ° 1 1 1 1 ° 1 1 ° ° ° 1 ° 1 1 1 ° ° 1 1 ° ° ° ° ° ° ‘ - ° 1 1 ° ° : ° 1 ° 1 1 ° 2 iP a 1 1 1 ° 1 1 ° ° ° 1 1 2 1 ° 1 1 1 1 : 1 1 ° 1 1 1 : 5 1 1 1 1 aa | ‘The state diagram is as follows: 20 own U ww on 8. Design a 4-bit axynchronous counter. (2015) ‘Ans. 4-bit asynchronous counter, counts 0000 i : woe titan to 1111, Le. 16 states; it is also called2021-35 -auash Books sat vagc and Computer Design eas sind Semester, iia LO P a a a a ae 14. What do you mean by the “as Cnen \ change? description about present staes net ste iar aa pas. iat able gives mpl pe tale of sequence CANT Tt and output of a sequent conaition of the Basie ip and ae Sve amt Now al oS nen s ToeSor Ri io crab el ve tee R Gh ° ° 2 x Q, ® 1 0 o Q ; ae : caput of aS ; F ; : Q.15. Show the characteristic equation for ‘the complement outp' it pas Tot sed senor chars a a ? sips top is G+ = 70+ K2- tee cae... oy “— ‘Ans. The characteristic table of Jk flip-flop is Que Cres ‘Ans. For the given state diagram, the state table is given below PS Input NS. 0 0 00 a o o 10 \ 10 0 10 U it n =<——==—— a Ou +1) = 70+ KO) ot a 16. Fxplain fourbit Bi-directional Register with the help of Multiplexers, 1 1 (2018) 0 1 u Ans. Pig shows a 4-bi lirect shift register This register can serially shaft n + 00 data right or left, we need one contro signal to perform the bidirectional data shaft Q13. What is the drawback of JK flip-flop? vt G, mit nsK pte, when J == 1 wtp ple, <4 open ee hapa when te pay es than the ple with ofthe ack. the output vill ts “tile iren Ondine drain ofthe clock ple ‘width, This because we eannot shift the ‘used to shift the data right si side. When the Right/left contr flip flop output of each bits is moved towards left side caneously The contrat signal RIGHTILERT i= side, When the Right/Left control imput is High ind the output of each flip lop is moved through to ‘applied, the data bits are shifted from left to right 14 G, are enable the clock pul96-2021 Third Semester, Digital Logic and Computer Design LP. Universi ity-[B Tech]-Akash Books 2021-37 Ta 205, Ty A&A Tait 0, 0:05 2a) ee 2,855, HO by airy 4 2 73 ; 2,4} i Q,a,} 1 Q,0,) x Se se aalx |x Natt s ant ffs x"]x" ool |) xix Ty = QQ Q17, Design a decade synchronous UP counter. Use T flip-flops 20, ae ao ae ce 0] x" | x" 2,0, Te= An + Op and T, = 1 Q.18. Explain Twisted Ring counter with the help of Timing Diagram. (2015) ter, the complement of the first flip-flop. This number of flip-flop. The 3, lo, , atl [ [’ E . ‘Truth Table CLK | Q, | Q, |: | Q | o jojojojojr 1 fifofojols afififofofr a fifafafofa afrfafrtrfo sfolifr}rfo 6 jofofijajo 7 lolojojijo s lojojolo|r38-2021 ‘Third Semester, Digital Logic and Computer Design Q19. Design a sequence detector that sequence should be Overlapping that will detect the sequence 1011 an Ans. Given sequence is 1011 (2015),2016) eS % 1" yuming two flip-flops to con: dotecter hae geal erage 0 construct the sequence detector creuit. The sequen We choose T flip flop Let A=00,B = 01,€=10,D=11 XAB = XA B)+ AB Y = sAB for sequence detector LP. University-{B:Tech}~Akash Books 2021-39 Q.20. Whatis race around condition? How can we overcome this condition? (2014),(2016),(2017) ‘Ans. Race Around Condition: It is important to note that in JK flip-flop, the output sta the input, and therefore change in the-output results in « change in the th t, as shown in Fig. (a) is applied, the output will interval At, where propagation delay of two level NAND gates t, = pulse width k= 1andQ= 1 after another At, output Q will become Nate back and forth between 0 and 1 in the duration tp of ‘of the clock pulse, the value of Q is ambiguous, This Fil te Fig. (@) Fig) ‘The race around condition can be avoided when t, < At as shown in Fig, (b). This condition can be obtained by 1. If, is reduced 2. Reduction of t, means, we ha ‘a pulse generator to produce less pulse width waveform, butis difficult to get such type of circuit. The value of At can be increased by in veries with feedback connection, which is again worthless tions for reducing race around condition (2016)40-2001 ‘Third Semester, Digital Logie and Computer Design 2021-41 (2016),(2017) . eo" outpu stage fip-op is connected tothe input of ° ° 2 2 | sho ae Desige an SR Flip Flop and explain how it works using truth table. ‘aa SR Flip Flop can be conv verted to D Flip Flop. Gaus ing NAND gate =0 D gates 3 and 4 “no” change” co42-2021 ‘Third Semester, Digital Logic and Computer Design Bot Progr ——] th AND and OR arrays are programmable, OR array is Bred and AND array is programmable. “a Costliest and m« PROMS, 1d more complex than PALs and | Cheaper and simpler AND array can be programmed to get desired minterms. Any Boolean function in SOP from van be implemented using PLA. AND array can be programmed to desired minterms “i ‘Any Boolean function in SOP from can bbe implemented using PAL. cigta Wives ‘AND yates on 6 LLP. University-{B.Tech|Akash Books 2021-43 Excitation table of RS flip flop Step 3: Conversion table ¢ Compute the flip flop inputs by using excitation table of RS flip flop [Given tip tow | PAL circuits (Programmable Array Logic) Q.26. Design a Delay Flip-Flop using S-R flip flop. Ans. Step. Given flip flop is RS ip flop Required flip flop is D flip op Block diagram {Rr al Fp top Given eonversion || —P” tip flop bd is 4 ‘Step 2. Truth table of D flip op 1p simplifieation flip flop inputs and present state are considered for K-map simplification Expronsion for R Expression for S oma no o ° 1 Sica . agals q =p ; at's r=6 S=0 ‘Step 5: The obtained expression are S = Dand R= 5Q.28. A sequential circuit has one input and one output and its state diagram is shown in Fig. (a). Design the sequential circuit using (i) D flip flop and (ii) JK flip flop. (2016) Ans. Mod-8 down asynchronou: inter :LP. University-{B.Tech|-Akash Books 2021-47 flop), we need the excitation table. input equation for flip flop and output equation are summarized as follows which we can develop excitation tabl ee eon ee D-A@BOx —Dy= ABRs ABy y= A+ AB Reequentialcireut using D ip-op is obtained by using above equations ax shown in Fig. (b). required circuit as shown, ‘Table (b) Excitation table table for D-fip flop fo, a] 2 (| On: a xo>nom = £ Fig, (b) Sequentia! logic diagram using D fip-fop. Q29. Explain JK flip-flop with the help of truth table, characteristic ‘equation and waveform. 2017) "Ans. JK flip Flop: It is used to remove the invalid condition of S-R Flip-Flop, The logic diagram and truth table is shown below. : Lo, cux The fip-Hop input function and the circuit output functions are obtained by usi K-map simplification. = "a a « +o aN 00 ° Q.30, Design a synchronous BCD counter with JK flip-flop. (2017) = ABs Be) + ABE + Be) * ‘Ans. ABCD counter is nothing but a mod-10 counter It has 10 states Considering s = Br+ He, then Bz+Br=z ‘ (0000 to 1001 }. It requires n = 4 flip flop. ‘Simplify the above equation i 29h, aaa 'Q, 0,0, , JK nee oooo ooor o* oo01 | oo10 oO» coro | oort o* oo11 | 0100 a» o1o0t ox 0110 o* oi o* 1000 o* toot 0 0000 a|AJ-K FLIP-FLOP thus obtained ‘Table 1 whichis redoced to Table the possible cersbinations of J and K input ofthe output have been considered. Fig. 1: An $-R FLIP-FLOP Converted into J-K FLIP-FLOP Table 1: Truth Table for Fig. 1 LP.U ‘Table 2: Truth {B Tech|~Akash Books le of J-K FLIP-FLOP 2021-61 at , | ee ee —s Danie aan a 4 SS SS : an ~ PROM EPROM gaan Sr = ‘Storage high Low storay . Q41. What is Johnson counter? (2018) — - Ans. Johnson Counter: Its av the complement of the output of first flip-flop. This counter have ‘umber of fip-flop. The logic cireui Q.43. Design a Mod-5 asynchronous counter using T-FF. 1 ofa shift rogister counter. In this counter, ‘Ans. MOD-5 Asynchronous counter using T-FF: A mod-5 counter has five stable flip-flop is connected back to the input of the 001, (00. when the fifty pulse is applied the counter temporily goes sounting cycles of length 2N, where N is the ly resets to 000 because of the feedback provided. ;nson counter is shown below. ), Rel for 101, and 110 and R = X for 111 a, a, a a R= QiQsQ, + QQ + QQ = Qs Gr Q + Wr = (HE + @) | | | ‘Aner | State R De 2, 9 >, a, 2, a, raat 7 @ a ° 0 0 0 ° a} I 1 one [ool co | Table of R 2 2 ial o oO cu 3 ° r rl oo | ova roamed 5 0 1 1 6 a ° ° 7 i 1 Le yt Q42, Distinguish between (i) SRAM and DRAM (ii) PROM and EPROM oe 2018) |SS ae : , Digital Logic and Computer Design Design a Pinpat 2output synchronous sequential circuie wy a : ‘an output z = 1, whenever any input sequence -11 a a = 7 : = vreaire The circuit resets to the intial state after output reaches 1, "1M [Present State Q,@,Q, |_Nest State QQ) =e ores opment | ase] a heneve i ee on 10 . ° o10 a ° 110 is : 000 a ‘ et on x ae 101 - ~ Exciting Table PS. a a cae 000 a oe x xo : ox 101 So = QrQe =F Make Shen 6 M| EE 10. Using this, following state table can be ob obtained.62-2021 ‘Third Semester, Digital Logie and Computer Design UNIT-HL Q.2. Represent the following conditional statement by two register transfer statements with control functi (2015) sequence of binary value: circular shift right, follow ike place when the following instructions LD addr & STA addr 20) rp] <— data > Se 4 B eo Cece Here oH conc “Hoo 1 1 1 o ° shift 0 ° 1 ° 1 ee Hore Shift 1 Q7. What are the various registers of 8085? Ans. 5085 Microprocessor has 6-bit registers: A.B,C,D.E.H.LF and two 16-bit registers PC and SP. These registers can be classified as 1. General Purpose Registers. 2 Temporary Registers: porary Data Registers ind Z Registers 8. Special Purpose Registers Flag Registers 4. Sixteen Bit Registers eae ory pointer store data in them. The efficient 0 store intermediate results ‘They are also called Programmer prefersusing 9's complement for (87-39). (2018) BCD Subtraction using 9's complement of (87-39) is 48 Jing diagram for fetch operation ? 6 bet acirens tras. The higher order 8 bits are tr bower order # buts are ranslerred to multiplexed A/D Q.10. The content of accumul: are B7H, add both contents. Ans of two Sum(a) = 1 4aH = Status of the flag r A aH Cer inning of this state, the RD’ signal goes low to enable te, the selected memory location is placed on D,-D, of the loxed bus are 93H and the contents of register C (2015) oF content = 99H and content of register C ~ BTH, then addition CY 07 06 5 04 03 2 bt oo (OTs te eae 9 ne 1 te 2: ee any ho ee ee foot 6 «nes after addition Flag Register D7 D6 D5 Ds DS D2 DI DO ae = 4. o o 0 ° i 2015, 2017) lementary operation performed with the data stored digital computers are classified inte four categories:- erations which transfer binary information from ene‘Third Semester, Digital Logic and Computer Design 65-2021 Here, P1,F2,F3 : Microoperation fields CD : Condition for Branching Br : Branch field AD: Address field Qs. microprogrammed control? (2015),(2016),(2018) ‘Ans. Micro programmed control: Micro programmed control is # control by using a memory called control (C8), programmed co be advantageous to CISC sophisticated control signals, there is Hard-wired control: signals by using appropriate fi register” and “control storage for the hardwired control. Not combinational logic circuit. We can assi to each address, which can be regarded as the This is a truth table. Status =— = tttttt tttttt [comer] re | (0) Microprogrammed contro! (6) Hardwied contol address field + instruction is stored at location 300 with its Quis. location $01. The address field has the value 400. A processor resist e contains the number 200. Evaluate the effective address if the addressing mode of jction is: “wo G) Direct (ii) Immediate (iii) Relative (iv) Register Indirect (v) Index “2018) Ri as the index register? ‘Ans. Location _ Contents 300 _ opcode; the instruction operation code 301 _ 400; address field of the above instruction 1a conta (a) Direct addressing: Direct addressing means that the address EP tore a the address of memory location the instruction is-supposed to work with operand “resides”). ae Explain the difference between hardwired control and 0 LP. University-IB.Tech]-Akash Books 2021-67 Effective address would therefore be 400 (o) Immediate addressing: Immediate addressing means that the address feld contains the operand itself. Biffecive address would therefore be 301. (@) Relative addressing: Relative addressing means that the address field contains offet to be added to the program counter to address a memory location of the addressing means that the ld in this case contains just address of an operand is in the regis ‘another operand. 5 index register: There are several possible se (there is an address field) it is co called ing the effective address .dding the contents of th fore be 400 + R1 = 400 + 200 = 600. 2. An address field that designated a memory address or a processor register. 3. A mode field that specifies the way the operand or the effective address is determined. Mode ‘Opeode ‘Address t lengths containing varying truction format of a computer st computers fall into one of Computers may have number of addresses. The num! depends on the internal orga: three types of CPU organization. (2) Single Accumulator organization ADD X AC @ AC + M [x] sneral Register Organization ADD R1, R2, R3R® R2 + RS tack Organization PUSH X ‘Three address Instruction: Computer with three addresses instruction format ‘an use each address field to specify either processor register are memory operand. ADD R1,A,B ALO@M ADDR2,C,D R2® MULX, R1,R2_ M [X| RI *R2 whet tdvantage of the three address formats is that it results in short program evaluating arithmetic expression. The disadvantage is that the binary-coded ‘structions require too many bits to specify three addresses. [B] X=(A+B)*(C+A)LL Ol——™=—[>>&ESX_ i <“<&se eat a 68-2021 Third Semester, Digital Logie and Computer Design ‘Two Address Instruction: Most common in commercial computers. Each a field can specify either register on a memory word. LP. University-{B:Techl-Akash Books 2021-69 MOV RA RI@MIAl Example: D,T, PC < AR, SC <-0. ADD RIB RI®R1+M [BI BSA: Branch and Save Return Address ae te’ “metig. x-C:eiecua) As the name lis the function o this Inatrton it allows the branching in the a ‘execution of instruction. By branching we mean e instructions can have sub ADD R2,D R2@R2+M (DI | routine or procedure. When this instruction is executed, it stores the address of the next instruction to be executed as PC (Program coun! Q.17. Draw the general register organization of basic computer, having MUL R1,R2 RI@RI* RZ MOU ELE... MPSS seven registers. Also show all connections with Arithmetic Logical Unit (ALU) One Address instruction: It used an implied accumulator (AC) rerisie! for & and control word? eat data manipulation. For multiplication/division, there is a need for a second registe roy LOAD A AC@MIAL (Clock ADD B AC®@AC + MIB] 4 STORET MIm@ac X= a memory operand, the intermediate {All operations are done between the AC register and a address of a temporary memory location required for storing LOAD C AC@M(C) ADD D AC@AC +M(D) ML OT AC@AC + M(T) STORE X M bJ® AC Zero - Address Instruction: A stack organized com) field for the instruction ADD and MUL. The PUSH & POP it fan address field to specify the operand that communicates wi of the stack) | PUSH A TOS®A PUSH B TOS®B TOS® (A+B) | ADD PUSH C PUSH D ADD MUL. pop X MIX} Q.16. Explain BUN (Branch unconditionally) and BSA (Branch and * | be necessary to write the result of multiplica etc) to main memory, perhaps only to for use in the next operation. Access to main memory is slower BUN instruction allows the program and modify the program.ESS —~"~SS—S=_—s—s&H=—sa(—_tette 70-2021 ‘Third Semester, Digital Logic and Computer Design le general purpose registers that Modern computer systems often have multiple gener rn computer eyed the term i no longer as common as it once was. However, -purpose processors still use a single accumulator for their work, in {Q.19. What is the role of implied mode in addressing mode? (2015),(2018) node: In this mode the operands are specised implicit the struction. For example, the instruetion “complement accumulator” is vestraction because the operand in the accumulator register if implied of an 6-track magnetic tape whose speed is 1600 bits/inch? (2018) Q.20. What is the transfer rate | 1s on a track x Rotation time 120 inches/second and densi ‘Ans. We Know, Transfer Rate = Number of Here, Number of Bytes on 1600 rate = 120 = 192000ms/track Q.21. How performance of instruction improved using pipelining? (2018) of | ‘Ans. Pipelining is a technique used to improve the tion throughput of a CPU | nt mi ructions into a series of small independent ‘certain part of the instruction. At a very ‘sie level, these stages can be broken down into: | « Fetch Unit Fetch an instruction from memory « Decode Unit Decode the instruction be executed | « Execute Unit Execute the instruction «s Write Unit Write the result back to register or memory vreructon [1 [| aia | teen 7 eee —— \Non-Pipelines = | =e tweneion [1 [2 fetcn code poe, Pipeined ete dock sf2{sjals portico On a non-pipelined CPU, when a instruction is being processed at 07 i stage, the other stages are at an idle state - which is very inefficient. If you ae LP. University-{B Tech]-Akash Books diagram, when the 1st instruction is being decoded, the Fetch, Execute and Write Units ofthe CPU are not being used and it takes 8 clock cycles to execute the 2 instructions (On the other hand, on a pipelined CPU, all the stages work in parall the ist instruction is being decoded by the Decoder Unit, the 2nd instruction is being fetched by the Fetch Unit. It only takes 5 clock cycles to execute 2 instructions on a pipelined CPU. Increasing the number of stages in the pipeline will not always result in an increase of the execution throughput. Q.22. Represent floating point in IEEE standard format for given No. 1,001010...0x2" and explain difference in Single precision and double precision numbers? (2015),(2019) Ans. 3 © al — ‘Sign of number 8 signed at Ostgilies + exponent in erga econ ‘gnifes-_excess-127 marissa representation Valve represented = (2) Single precision (000401000001010 Value represented = 1,001010..2"” (0) Example ofa single precision number 64 ie es © ™ 11-bit excoss-1023 coun mantssa racion Velue represented = 2 1.M 2 1023 SEEEEEEEE FFFFFFFFFFFFFFFFFFFFFFF o1 89 31 ‘The value V represented by the word may be determined as follows: ‘If B=256 and F is nonzero, then V=NaN (“Not a number”) 'E=255 and F is zero and S is 1, then V=-Infinity + IfE=255 and F is 0, then V-Infinity + If 0cB<255 then 2 ** (E-127) * (LF) where “LF” is intended to represent the binary number created by prefixing F with an implicit leading 1 and a binary point. * If E=0 and F is nonzero, then V=(-1)"*S * 2 ** (126) * (OF). These are “wnnormalized” values,} ‘Third S 1c and Comy } Semester, Digital Logic and Computer Design | LP. University-{B Tech}-Akash Books 2o21-73 0 and F is zero and S is 1, then V=0 ee eae Q24. Register A holds the S-bit binary value 11011001, Determine the B é "perand and the logic micro-operation to be performed in order to change the 72-2021 100000000 00000000000000000000000 = 0 Galue in A to: 2015) 190900060 90000000000000000000000 = -0 ce 91900000000000000000000 = Infinity - not nor | 25. What are the features of 8085 microprocessor? Explain mode of 8085. (203 ‘Aas. (1) 8085 microprocessor is an 8 bit microprocessor. ie it ean accept or provide Bbit data simultaneously. (2) 8085 microprocessor is a single chip, NMOS device implemented with 6206 transistors. (3) 8085 microprocessor requires a single +5V DC power supply ‘on chip clock generator, therefore there is no need srnal tuned wwo phase, 50% duty evel ke LC, RC or erystal Je, TTL clock. These clock Double Precision: Thy jock generator representation requires a GA bi ‘ney of 8085 microprocessor is 3MHz where as to 63, left to right | minimum clock frequency 1s 500 KHz. ©The first bit is the sign bit, 8, 1. Immediate Addressing Mode: - An immediate is transferred directly to the * the next eleven bits are the exponent bits, ‘F’, and register. (2 bits are the fraction 'F" ee VF FEF FFF PPP PFFPF PEP FF PFEFFER PEPE PPE JA 3000H (The content at the location 3000H is copied to the register A). data is transferred from the address pointed 25, An Wit reginter eon value after arithmetic (2015),2017) mverflow vecuuse « nogutive number chanel— eae” =— R2) else if (Q= 1) then (R1 < R3) | ae sequence pe cinan transfer, The select lines $1 and SO indicate which of four ‘register will have its contents transferred to the bus. In general, ‘system will multiplex k registers of bit each to produce a n-line common bus. ‘require n kx 1 multiplexers. The bus is connected to the inputs. ‘and will activate the load control of the selected register wh ready to transfer data Statement P: Re-R2,Q:R1< RS Q.56. Convert the decimal 61.5867 into its binary equivalent (2017) ‘Ans. Conversion steps: 1. Divide the number by 2. 2. Get the integer quotient for the next iteration. ‘Value actually stored in float: Error due to conversion: Binary Representation Hexadecimal Representation88-2021 ‘Third Semester, Digital Logic and Computer Design Q.58. Explain serial and parallel! bus arbitration in detail. 2017) there ure multiple masters, then multiple master decides ig data pattern. In case where master needs to Q.59. Explain instruction cycle(fetch) and (decode) in detail. Also a the working of computer registers used in ‘Ans. Each computer's CPU can have different cycles based on different instruction sets, but will be similar to the following cy 1. Fetch the instruction: The ne: that is currently stored in the program register (IR). At the end of the fetch oper: that will be read at the next eycle. 2. Decode the instruction: During this cycle rect) (iret or indir ion has an indirect data is and any required into data registers (Clo is clock pulses. If this {fetched from main memory to be processed and then pl Pulse: T,) Ifthe instruction is direct, nothing is don _, LP. University-(B Tech|-Akash Books 2021-89 (WO instruction or a Register instruction, the operation is performed (executed) at clock Pulse. 4. Execute the instruction: The control unit of the CPU passes the decoded information as a sequence of control signals to the relevant function units of the CPU to perform the actions required by the instruction such as reading values from registers, passing them to the ALU to perform mathematical or logic functions on them, and writing the result back to a register. If th olved, it sends a condition signal back to the CU. The result generated by the opera tored in the main memory, or sent toan output device. Based on the condition of back from the ALU, Program Counter may be updated to different address from which the next instruction wall be fetched,LP. University-B.Tech]-Akash Books 2021-91 62. Consider a hypothetical processor which supports expand opcode technique. A 32 bit instruction is place in 256MW memory. If there exist 10, one address instruction then how many zero-address instruction are possible. (2017) peas ‘Two address Upcode | Address! | Address] instructions nese _ us Register is wed fr storing the Results thos ary sccomelae Whea be CPU ‘will generate proce bt So See rdear em hol 156-250 = 6 combinations can be used for one address («in ee 3 sdéress. Also knows a8 form an cece ee aed ser ae sais" as a instructions ele peter ia wae to store datafnstroction 6x2 a ‘Maximum num ber of tion: transmitted too from a peripheral device scoH the es Fe the err feachine aay | Q.63. What are the advan: byte addressing mechanism over word are Toalbinstracns arerequredo which Sdrethestack opera ion is jes? (2017) ‘ . Eraluate X= (A+B)*(C+D) a r a ‘S a | er units called words, which would be PUSH B TOS Al Hs ‘ 08 + as met common computer m0 : ed | PUSH D Tos ce uae se co Tos + c+D a 70s < (C+ DIASB) Mx 2 ss | . POP me QSL. Consider the following program segment weed aoe on hypothetical machine instructors are: Inst 1, Inst2, Inst3, Inst, 5, Insts = tha 16-bit address space. The machine ies. The maximum memory size would Size(in words): 2,1,12,1,2,1 respectively. ee ‘Assume the word size ofthe instruction is $2 bit and the Program TA eg, sa loaded i wit i 1000 (Decim: into the memory with starting of 1 inten oe ‘What could be the value present in PC during the execution of 256 KB‘Third Semester, Digital Logie and Computer Design ly selective clear and masking operation on contents of registers (2018) Sear clears to 0 the bits in register A where there 92-2021 Content of A before Content of B (logic operand) (2018) the operand is found, in instruction cycle. (2018) Ans. Fetch the instruction: The n° ‘address that is currently stored in the program counter and stored int register. At the end ofthe fetch operation, the PC points to the next instruction that will be read at the next cycle. Decode the instruction: During this cycle the encoded instruction present in the instruction register is interpreted by the decoder. Sat sce choice. ‘Ans. Addressing modes are nothing but the different ways in which the location of aan operand can be specified in an instruction. The number ‘processor supports changes according to the instruction se 5 fare a few generic ones that are present in almost all processors and are thus of utmost importance. They are as follows: 1 Immediate mode ii, Register mode tit. Absolute mode iv. Indirect mode ¥ Index mode vi. Base with index ‘vii Base with index and offset ‘& Auto increment viii, Relative x Auto decrement LP. University-IB.Tech}~Akash Books 2021-98 this mode, the operand is specified in the instruction itself stion places the value 200 in the register RO Clearly Immediate ‘to specify the source operand. Figure 1 shows the above concept i.e. the operand is a part of the instruction Instruction ‘Operand Figure 1: Immediate mode of a register. We specify th case by specifying the name register. Regie: ction names Fig. 2 Register mode in a memory location; the address of the operand, jon, Global variables are represented using this is passed ex addressing mode. E.g. Move LOC, RO Here LOC corr the processor and placed in RO. Indirect mode: The effective address (E.A.) of the operands is the contents of ‘a register (see Figure 3(b)) or the memory location whose address appears in the instruction (see Figure 3(a)). The name of the register or the memory address is placed in parentheses to denote indirection or in other words that the contents are addresses of the operands. E.g. Add (R1), RO (this mode is often called as register indirect mode) Add (B), RO Fig 3aei be ina In either case it is called as Eg Move X (RO), RI Here, Contents at address —————— Instruction Base with index mode: The registers. The first register as be! : the base register. This mode provi ‘be changed. Base with index and offset mode: Bug. Move X (PC), RL Here, Contents at address register are automat effective address is fore is called the index ané ides more flexibility since tically incremented to R idaress RO+R1 are moved to R2. ‘The effective address is ‘case is often cal ‘onstant value in this ret operands, 2 for 16 bit operands and #9 on. Eg Add (R2) +, RO Here are the contents ‘Auto decrement mode: The effective address of the Before accessing the operand, register specified in the instruction register are automatically decrement of R2 are first used as an E.A. then they operand ed and then the value is (dress of the operand is calculated by adding a constant ‘shown in Figure 4. The address can irpose registers, X+RO are moved to RIX contains a constant value the sum of contents of two d the second register is called ‘both the components are accessed the sum of contents ied the offset LP. University-{B-Tech}-Akash Books 2021-965 Eg Add -(R2), RO Here are the contents of R2 are first decremented and then used as an E.A for the ‘operand which is added to the contents of RO. The auto increment addressing mode and the auto decrement addressing mode are widely used for the implementation of data operations in brief? (2016),(2018),(2019) ‘Ans. Micro-operations perform basic operations on data stored in one or more registers, including transferring data between registers or between registers and ff the central processing unit (CPU), and performing arithmetic or con registers. The micro-operations in computers are classified into operations in data ‘Arithmetic Micro-Operations Some of the basic micro-operations are addition, subtraction, increment and decrement. ‘Add Micro-Operation It is defined by the following statement R3 > R1+R2 ‘The above statement instructs the data or contents of register R1 to be added to data or content of register R2 and the sum should be transferred to register R3. ‘Subtract Micro-Operation Let us again take an example a R3 + R1+R2+1 In subtract micro-operation, instead of using minus operator awe! tae 1 ‘compliment and add 1 to the register which gets subtracted, ie Rl ~ R2 is equivalent twoR3>R1+R2 +1 Rio Ried R19 RI-1 Symbolic Designation RSe RI R2 RS R1-R2 ‘R2 e (RQ) R2¢ (R2) +1 RS e RI + (R241 Rie Ri+d Rie RI-1(a) Logical Shift It transfers 0 through the serial input. The sy for logical shift left and “er” is used for logical shift right | 70. Apply selective complement operation if content in A is 1010 and B is 1100, (2019) ‘Ans. The selective-complement operation complements bits in where ther are corresponding I's in B | 1010 A before 1100 B (logic operand) Aafter‘Third Semester, Digital Logic and Computer Design 98-2021 yutput of BO(EX-OR)K=B0' (Complement the operation being are there in each multiplexer. (ii) What size ow many multiplexers are there in the bust ‘tion inputs multiplexers is a technique for implementing ing attempts to keep iding incoming inst ts with diff put than Ws the added Now 2's complement subtraction for two i} pal rolex | 5 Pe | st %% | | dest ates | T —fi_oa__ FO : ae a Pipeline hazards : There are some factors that cause the pipeline to deviate its diagram. "Ans. A micro-program sequencer attached to a control memory inputs certain bits determines the next address for control memory.‘Third Semester, Digital Loic and Computer Design LP. University-{B.Tech}-Akash Books 2021-101 UNIT -IV } The sinless 7 jl. ‘is address different from physical memory Tro Addcot! vat oried to elect Qu. How is logical memory mr logical | k ee ter of the memory: is commonly referred to as physical (cone \ddresses corresponding to the logical addresses is 1e address-binding methods generate identical However, in the execution-time address-binding scheme, wrovide two address field in each sieee pee comin of Sarai | tee | Bee from the control partition ov M6 14346 ole icrenatection, Single Address Field: | ao feels” Wire is simple but it requires more bits in the microinstruction. With a simpler approach, we can havea single address feld Mapping from logical to physical addresses using memory management unit (MMU) and relocation/base register. The value in relocation/base register is added to generate corresponding physical address, base/ relocation value is 14000, then an attempt by the user is mapped to 14346. : for the next address. * Address Field. * Based on OPeode in instruction register + Next Sequential Address. between different levels of the hierarchy, is the practi As aresult, the CPU spends much of its time idling,‘Third Semester, Digital Logic and Computer Design Memory Hierarchy 102-2021 ‘The memory hierarchy in most comput + Processor registers - fastest possible access (usu: y but very large. ite asse vvogram to subtract two 8 bit numbers? Q.3. Write ass wmbly language progr! to subtract cist ‘Ans. ;2000H = 24 ; 2001H = 43 LDA 2000H ; MOVBA . LDA 2001H ; SUBB ; DAA; ‘STA 2002H ; HLT ; Q4. The memory unit of a computer has 256K words of 32 bits Coptn combster haa an instruction format with four elds: 99 OPS cove tle one dressing modes, & 1 addre a mode field, to speci ne of seven ade ie Sy aaa ‘Specit¥ processor registers, and a memory 2 its in each field if the instru) ‘Ans. To address 2 need 18 bits since 256K = 2°18 To enumerate 7 addressing modes we need 3 bits since ang = 8 wi higher number of combinations. ‘To enumerate 60 registers we need 6 bits since number of combinations nat is the 6st 2n6 = 64 what is the first higher LP. University-fBTechl-Akash Books 2021-103 its in the 82-bit word we can use for operation codes (opcodes - 18-3 - 6 = 5. So there can be 2°65 = 32 opcodes. " address” Q.5. What is cache memory? State the advantages of cache memory? (2016) ‘Ans. Cache memory is a small-sized type of volatile computer memory’ high-speed data access to a processor and stores frequently used computer programs, t stores and retains data only computer is powered up. ter data storage and access by storing an instance of vd data routinely accessed by the processor. Thus, when a processor requests .n instance in the cache memory, it does not need to go to the ‘Cache memory can be primary or secondary cache memory, where primary cache memory is directly integrated or closest to the processor. In addition to hardware-based mache, cache memory also can be a disk eache, where a reserved portion on a disk stores ind provide access to frequently accessed data/applications from the isk ‘Advantages: The advantages of cache memory are as follows: ‘* Cache memory is faster than main memory. J Ieconsumes less access time as compared to main memory, «ie stores the program that can be executed within a shert period of time ‘It stores data for temporary use. Q6.A block set associative cache memory consist of 128 blocks divided into 4 block sets. "the sain memory consists of 16,384 blocks and each blocks contains 256 eight bit words. ‘How saany bits are required for addressing the main memory? How many bits are needed to represent the TAG SET, WORD fields? (2015) cache is divided into 16 ets of 4 lines each. Therefore, 4 bits are needed set number. Main memory consists of 4K = 212 blocks. Therefore, the set plus tag lengths must be 12 bits and therefore the tag length is 8 bits. Each block contains 128 words. Therefore, 7 bits are needed to specify the word TAS set WORD. Main memory address = 8 4 7 i) Sent most bts = tag 6 middle bite = line number; 3 rightmost bts = byte number, Une, ORDsmester, Digital Logic and Computer Design ‘Third Ser 104-2021 in memory. Therefore, every ‘be copied from a storage device into are loaded in the main memeory for exeevis Sometimes :asjed into the memory, but some times 8 coriait part or routine only when itis called by the program, ‘main memory All the program: ed rove gn ac pce man emer. ening se org back to the dik ‘Contiguous Memory Allocat ai contiguous block of memory. oon entnsexaly et aed ino it.The free ich ole best ts contained in @ si fixed size partitions. Es free, a process is selected from the input quote memory are known as holes. ‘The set of holes is searched to determine w! ‘omenon by which we control is to prevent a process from rrocess from affecting other processes, operating system i soe storage violation exception being sent to the 1a process by which computer Programs a sult ried and removed from the memory. AS & Tr ot is non contiguous i.e. «ne Mens) jis phenomenon is known aS xterm! 2021-105 LP. University-1B.Tech|-Akash Books contagious. Here physi pages belonging to a certain process are loaded into available memory frames. ‘Page Table: A Page Tables the data structure used by a virtual memory system in are ‘to store the mapping between virtual address and physical supports the space of a single process into segments th physical memory. ‘Segmentation with Paging: Both paging and segmentation have their advantages and disadvantages, itis better to combine these two schemes to imprsvs savmach. The combined acheme is known as Page the Elements’. Each segment in this Scheme is divided into pages and each segment is maintained in « page table, So the logical address is divided into following 3 parts Segment numbers(S) « Page number (P) * The displacement or offset mumber(P) Q8. How many 128x8 RAM chips are required to provide = menu capacity of 2048 bytes? (2015) van. 128 x 8 RAM => 128 Bytes (Gbits) chip => Numbers of chips = 2048/ 12816 9. How many lines of the (dress be must be used to access 2048 bytes of 's sssssswill be common to all chips? (2015) ress lines => d = 11 We have 16 chips => 4 bits ines is 11-4= 7 Summary: 4 bits (MSB) to location inside the selected Ship select Number of common ac ‘the correct chip and 7 bits (LSB) to select the memory (2018) be is a signal that is sent that ines. In memory technology, the strobe) signals are used to tell a Q.10. What is strobe control? ‘Ans. In computer or memory techn‘ validates data or other signals on adi CAS (column address strobe) and RAS led a conflict miss, when two different addresses correspond 10 Even if the cache is big and contains many stale entries, it those, because the position within cache is predetermined by ‘cache, each address in main memory it can reside. Thus there are no twoLP. University-{B.Tech|~Akash Books 2021-107 Q.14. Differentiate between Unsigned notation and, sigmed notation, Py im both cases. a snester, Digital Logie and Computer Desifn ‘Third Se a hybrid between a nae ger magnitude number they ‘cause collisions Q.2. Differentiate between access ‘and cycle time of a memory. 2016) re internally represent r positive values only. Let us say the unsixn n (2 power n) igh nut 9 to ‘kes for the read/write head to is an average time since it depends on ve mininvum time interval between to rusceute sr asecttn Panes is tree" wo ESAS to-back access: reasurement of how while for signed notation range is from — ~32768 to + 32767 Q.15. Explain the need of memory hierarchy with the help of a block diagram? What is the reason for not having one large memory unit for storing all information at one place? ‘memory chip an than its access time, which measures oF s Jatency between successive memory accesses ‘me is the time, usually mes \atenc retro a, between the start of one random access memory 25528 to the time ‘then the next access can be started. ‘14 Difierentiatebetween AsynchronousDataTransfersand synchronous data transfer. (2016) "Ans. Synchronous: In synchronous data transfers, take some time to communicate before they make the exch outlines the parameter da 1e memory hierarchy is a concept used to discuss itectural design, algorithm predictions, and lower the sender and receiver time, complexity, and capacity are performance and contrlling technologies. Designing for high performance tare ceri sering the restrictions of the memory hierarchy, ie. the size and capabilities of caoescervpenent. Each ofthe various components can be viewed as part ofa hierarshy a = (mi, m2,_..mn) in which each member mi is typically smaller and faster ner ah +1 of the hierarchy. To limit waiting by higher levels, gece’ ae a tr level will respond by filling a buffer and then signaling to activate the transfer. ‘and Hold requirements of Compare Memory Hierarchy 1e server 0 another begins. They to make sure they don't drift transfer is the generation an frequency. The data is synch the known clock Synchronow respond to a message. Messages are al ‘Asynchronous: In asynchronous, or “be not establish the parameters of the inform: extra bits of data before and after each fends. It then sends the informal its clock to match the timing does not take time to commu Whereas, asynchronous data trar Me CLOCK 1 and itis sampled on any other clock, say, CLOCK 2 (Whore clock 1 £0); Mork 2 are asynchronous to each other and has no known phase and frequency relationship). Then the dat it will be a” asynchronous data transfer. that does not wait for a message from the serv Jhronously to CLOCK 2 an ‘aging involves a clientrot used whereas the memory hierar ‘saving time based of ‘a computer. For for a computer, while monitors and prin such as mod understand; the ov ‘and monitors take signals into a represent the process of reading or seeing these ction between computers and hum: emitted by hardware or ‘An interrupt alerts the processor ‘of the current code the proce to communicate that they require at fan interrupt wh is used for errors or events during program execution that are exceptional enough that they cannot be handled within the program itself. Q.17. Differentiate between “hit” and “miss” with respect to cache memory. 1015),(2017) requ ‘back object data te a cache miss regarding # storage handler will stop the in a register and load the program count given by the interrupt vector table. After processing the interrupt by the processor interrupt handler id the instruction and its configuration from the saved register, process will start its processing wher configuration and loading the ate “Locality of Reference” principle. 2017) 20. What are the different kinds of operation used in CPU design? (2017) -ro-operations in computers are classified into the following categories: mns''These micro operations are used to perform bit style on non numeric data ions: As their name suggests they are used to perform shift registers its need. Explain DMA transfer in detail with the help of suitable diagram. ‘Ans. Stands for “Direct Memory from the computer's RAM to another pat (2017),(2018) DMA is a method of transferring data DMA Transfer Types Memory To Memory Transfer: In this mode block of data address is moved to another memory address. In this modenietertairic; an enn # LP University-(B Tech}~Akash Books 202)-111 Q.22. Main memory size is 128 KB, cache size is 16 KB, block size is 2568. Using direct bit mapping what is the no of tags bits in physical address and what is the size of tag directory. Assume memory is byte addressable. (2017) Ans. [ag | index | block ‘Tag bits = address bit length ~ exponent of index- exponent of offset Index bits = logicache size'= log (16°2") = 14 4 signal which has highest priority from hardware or software 2. Software Interrupts: Softwaref inter also divided in to two types They are + Normal laterrupts:the interrupts whi are called votware instructions + Exception: unplanned interrupts while executing a program i called Exception 1 For example: while executing a program if we got a value which should be divided by zero is called a exception. j In computer architecture, the memory hierarchy separates computer storage ‘caused by the software instructions arbitrationStig SO LTO, Ce Ft Third Semester, Digital Lagic and Computer Desi on naa enema sical ‘ono weet ame mw ee? —] 2 rt] cece a = feet m0 ES hee one aw | cate — = peme fine oeneaien lang ao SR ee ee pie el Q.25. A computer uses & memory unit with 256K words of 32 bits each, A a eee binary instruction code is stored in one word of memory. =/ = — ‘The instruction has four parts: an indirect bit, an operation code, a register Oe iia Rare a code the register code part to specify one of 64 registers and an address part, nd = ae ‘} How many bits are there in the operation code, the register code part, oe — —; ‘\ ene and th» address part? —— a eae (4) Draw the instruction word format and indicate the number of bits in oe « » each part. Q.24 Differentiate between RAM and ROM chips? nom (Hi) How many bits are there in the data and address inputs ifthe memory? Ans 206K = aoe gM “ae @ Alddrens 18 ite 4 28 Reiter code 6 bite Indirect bit: 1 ite Fy 82-25 = The for opcode w 1 2 “ 1% ee a eT (Git) Data 2 bit, addreas 18 bite 2.26, For each possible addressing mode calculate the effective address and content of accumulator. Ans. The mode field of the instruction ean specify any one of a For each possible mode we calculate the effective addrean and the ‘loaded into AC In the direct address mode the effectiveLogie and Comy ito AC is 800, In the immi operand loaded i the operand loaded, ‘Addressing Mode | Effective Address | Content of AC Direct address 500 perand 201 A Indexed address Register Register indirect (2019) execution time of non-pipelined processor, wher" LP. University-1B.Tech]~Akash Books 20) ‘When the number of tasks n are significantly larger than k, that is, n >> k S=ntkn S=k where k are the number of stages in the pipeline Q.28. Difference between Isolated /O and Memory Mapped /0. Ans. Differences between memory mapped I/O and (2019) Ww - ISOLATED VO MEMORY MAPPED VO Memory and U/O have separate address Both have same address space space All address can be used by the memory | Due to addition of UO addressable ‘memory become less for mem: Separate instruction control read and write | Same instructions can control both | mn in UO and Memory and Memory s UO address are called ports Normal memory address are for both Lesser efficient nt due to separate buses ize due to more buses ‘Smaller in size It is complex due to separate separate logic | Simpler logic is used as UO is also is used to control both, treated as memory only. Q29, Explain Booth Multiplication algorithm for signed 2's complement Presentation with example. (2019) Ans. Booth algorithm gives a procedure for multiplying binary integers in signed 2's complement representation in efficient way, i, less number of additions! subtractions required. As in all multiplication schemes, booth algorithm requires examination of the multiplier bits and shifting of the partial product. Prior to the shifting, the multiplicand may be added to the partial product, subtracted from the partial product, or left unchanged according to following rules: 1. The multiplicand is subtracted from the partial product upon encountering the first least significant 1 in a string of 1's in the m: 2, The multiplicand is added to the partial product upon encountering the frst 0 (provided that there was a previous ‘I’/in a string of O's in the multiplier 3. The partial product does not change when the multiplier bit is identical to the Booth's Algorithm Flowchart: We name the register as A, B and Q, AC, BR i red to 0 and the sequence SC is set to ber n equal to the number of bits in the multiplier. The two bits of the multiplier and Q,,, are inspected. Ifthe two bits are equal to 10, it means that the first 1in a string has been encountered. This requires subtraction of the multiplicand from the partial product in AC. Ifthe 2 bits are equal to 01, it means thatthe first Oin a string of 0's has been encountered. This requires the addition of the multiplicand to the partial Droduct in AC. a hi aEP. University-(8 Teeh}-Akash Books oat-117 Memory BOs m0 * Virtual Memory: Virtual memery is the separation sf ingiea! semnery fem memory. This separation provides large virtual memary fer Sregremenars wher physical memory is availabe \s used to give programmers the iawn that they hewe « nd the ssigion Vimetoding Q_.). This is an ‘etch A eh GIR bw the right and lens the sign tat in Af MD 4. Man 4 « 1001 Ties enphamationn of Bret winp is a0 hallows GQ. A = 0, MMe Mw aa (the AC IMI, wach gras AL) = 0101 SS eeBus Grant: ivated by the CPU to inform the external DMA controller that for VO devices the buses are in pedance state and the requesting DMA can take control of the aes buses. Once the DMA has taken the control of the buses it transfers the data. ‘This transfer can take place in many ways ‘Types of DMA transfer using DMA controller: 1d from the peripherals may be done in any of the three Burst Transfer: DMA returns the bus after complete data transfer. A register is used as a byte count, being decremented for each byte transfer, and upon the byte count reaching zero, the DMAC will release the bus. When the DMAC operates in burst mode, the CPU is halted for the duration of the data transfer. 1¢ CPU. The CPU merely delays its operation smory /O transfer to “steal” one memory cycle. 2019) ‘Single-instruction, single-data (SISD) systems: An SISD computing system iiprocessor machine which is capable of executing a single instruction, operating ‘on a single data stream. In SISD, machine instructions are processed in a sequential ‘manner and computers adopting this model are popularly called sequential computers. ‘Most conventional computers have SISD architecture. All the instructions and data to bbe processed have to be stored in primary memory. LP. University-(B.Tech!-Akash Books 2021-119 ‘Third Semester, Digital Logic and Computer Design allow the peripherals removing the intervent DMA or direct memory access, During the memory buses. The DMA controll directly between the /O devices and the memory unit. ingle-instruction, multiple-data (SIMD? systems - An ‘4 multiprocessor machine capable of executing the same instruction operating on different data streams. Machines based on an. High impedance (disable) when BG is enable Bun Reaest—stoR —aus|¢—§ aves ous eus|—*» oss bin Bus Gronte—lpG. Reas wa} —e vice Fig. CPU Bus Signals for DMA Transfer Bus Request: It is used by the ler to v inguish the control of the buses. aT coo teem120-2021 Third Semester, Digital Logic and Computer Design Dominant representative SIMD systems is Cray’s vector processing machine. 3. Multiple-instruction, single-data (MISD) systems: An MISD computing system is a multiprocessor machine capable of executing different instructions on different PEs but all of them operating on the same dataset Miso Example Z = sin(x) + cos (x) + tan(x) ‘The system performs different operations on the same data set, Machines built Using the MISD model are not useful in most of the application, a few machines are 1 built, but none of them are available commercially. ¢ Multiple-instruction, multiple-data (MIMD) systems: An MIMD system isa quultiprocessor machine which is capable of executing multiple instructions on multiple data sets. Each PE in the MI ii therefore machines built using this model are cay SIMD and MISD machines, PEs in MIMD mad mitaD Instructon poot |__ broadly categorized into shared-memory MIMD and distributed-memory MIMD based on the {n the shared memory MIMD model (tightly coupled multiprocessor systems), Single global memory and they all have access to Thy takes place through the shared memory, of the-data stored in the global memory by one PE is visible to all other PEs, Dominant representative shared mem, ory MIMD systems are Silicon Graphics | P (Symmetric Multi-Processing), istributed memory MIMD. machin osely coupled multiprocessor systems) 4 local memory. The communication between PEs in this model takes interconnection network (the inter process communication channel, nnecting PEs can be configured to tree, mesh or in accordance which each PE has its own memory. nd user's requirement , distributed memory MIMD Superior to the other existing models.eee [Our Useful Solutions For GGSIPU e SOLVED PAPERS FOR B.TECH * SOLVED PAPERS FOR BBA * SOLVED PAPER FOR BCA Upcoming Solutions For GGSIPU | * SOLVED PAPERS FOR MCA e SOLVED PAPERS FOR MBA TP % AKASHBOOKS ff Sales Office: H.No.4278, Gali No. 3, Ansari Road, Darya Ganj, New Delhi-110002 Ph: 011-23281171,0-9818257423,9971086337 E-mail: [email protected] RE oe